ANALOG DEVICES AD5025

Fully Accurate, 12-/14-/16-Bit, Dual, V OUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP AD5025/AD5045/AD5065 ence buffer is provided on chip. The AD5025/AD5045/AD5065 FEATURES incorporate a power-on reset circuit that ensures the DAC output Low power dual 12-/14-/16-bit DAC, ±1 LSB INL powers up zero scale or midscale and remains there until a valid Individual voltage reference pins write takes place to the device. The AD5025/AD5045/AD5065 Rail-to-rail operation contain a power-down feature that reduces the current consump- 4.5 V to 5.5 V power supply tion of the device to typically 400 nA at 5 V and provides software Power-on reset to zero scale or midscale selectable output loads while in power-down mode. The parts are Power down to 400 nA @ 5 V put into power-down mode over the serial interface. Total unad- 3 power-down functions justed error for the parts is <2.5 mV. The parts exhibit very low Per channel power-down glitch on power-up. The outputs of all DACs can be updated Low glitch upon power-up LDAC simultaneously using the function, with the added Hardware power-down lockout capability functionality of user-selectable DAC channels to simultaneously Hardware LDAC with software LDAC override function CLR update. There is also an asynchronous that clears all DACs CLR function to programmable code to a software-selectable code—0 V, midscale, or full scale. The SDO daisy-chaining option 14-lead TSSOP parts also feature a power-down lockout pin, PDL, which can be used to prevent the DAC from entering power-down under any APPLICATIONS circumstances over the serial interface. Process controls PRODUCT HIGHLIGHTS Data acquisition systems Portable battery-powered instruments 1. Dual channel available in a 14-lead TSSOP package with Digital gain and offset adjustment individual voltage reference pins. Programmable voltage and current sources 2. 12-/14-/16-bit accurate, ±1 LSB INL. Programmable attenuators 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 50 MHz. GENERAL DESCRIPTION 5. Three power-down modes available to the user. The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit 6. Reset to known output voltage (zero scale or midscale). buffered voltage output nanoDAC® DACs offering relative accuracy 7. Power-down lockout capability. specifications of ±1 LSB INL with individual reference pins, and Table 1. Related Devices can operate from a single 4.5 V to 5.5 V supply. The AD5025/ Part No. Description AD5045/AD5065 also offer a differential accuracy specification of AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP ±1 LSB. The parts use a versatile 3-wire, low power Schmitt AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP trigger serial interface that operates at clock rates up to 50 MHz AD5062/AD5063 16-bit nanoDAC, 1 LSB INL, MSOP and is compatible with standard SPI®, QSPI™, MICROWIRE™, AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 and DSP interface standards. The reference for the AD5025/ AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, SOT-23 AD5045/AD5065 are supplied from an external pin and a refer- FUNCTIONAL BLOCK DIAGRAM V V A V B POR DD REF REF LDAC BUFFER INPUT DAC SCLK DAC A V A OUT REGISTER REGISTER SYNC INTERFACE LOGIC DIN BUFFER INPUT DAC DAC B V B OUT REGISTER REGISTER LDAC POWER-DOWN SDO LOGIC AD5025/AD5045/AD5065 PDL CLR GND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06844-001 AD5025/AD5045/AD5065 TABLE OF CONTENTS Features .............................................................................................. 1  Input Register .............................................................................. 17  Applications ....................................................................................... 1  Standalone Mode ........................................................................ 19  General Description ......................................................................... 1  SYNC Interrupt .......................................................................... 19  Product Highlights ........................................................................... 1  Daisy-Chaining ........................................................................... 19  Functional Block Diagram .............................................................. 1  Power-On Reset and Software Reset ....................................... 20  Revision History ............................................................................... 2  Power-Down Modes .................................................................. 20  Specif ica t ions ..................................................................................... 3  Clear Code Register ................................................................... 21  AC Characteristics ........................................................................ 4  LDAC Function ........................................................................... 21  Timing Characteristics ................................................................ 5  Power-Down Lockout ................................................................ 22  Absolute Maximum Ratings ............................................................ 7  Power Supply Bypassing and Grounding ................................ 22  ESD Caution .................................................................................. 7  Microprocessor Interfacing ....................................................... 23  Pin Configuration and Function Descriptions ............................. 8  Applications Information .............................................................. 24  Typical Performance Characteristics ............................................. 9  Using a Reference as a Power Supply for the AD5025/AD5045/AD5065 ....................................................... 24  Terminology .................................................................................... 15  Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24  Theory of Operation ...................................................................... 17  Using the AD5025/AD5045/AD5065 with a Digital-to-Analog Converter .................................................... 17  Galvanically Isolated Interface ................................................. 24  DAC Architecture ....................................................................... 17  Outline Dimensions ....................................................................... 25  Reference Buffer ......................................................................... 17  Ordering Guide .......................................................................... 25  Output Amplifier ........................................................................ 17  Serial Interface ............................................................................ 17  REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD5025/AD5045/AD5065 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 1, 2 B Grade A Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3 STATIC PERFORMANCE Resolution AD5065 16 16 Bits AD5045 14 AD5025 12 Relative Accuracy AD5065 ±0.4 ±1 ±0.5 ±4 LSB TA = −40°C to +105°C AD5065 +0.4 ±2 ±0.5 ±4 TA = −40°C to +125°C AD5045 ±0.1 ±0.5 LSB T = −40°C to +105°C A AD5045 ±0.1 ±1 TA = −40°C to +125°C AD5025 ±0.05 ±0.25 LSB T = −40°C to +105°C A AD5025 ±0.05 ±0.5 TA = −40°C to +125°C Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error ±0.2 ±2.5 ±0.2 ±2.5 mV V = 2.5 V; V = 5.5 V REF DD Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5065), Code 128 (AD5045), Code 32 (AD5025) loaded to DAC register 4 Offset Error Drift ±2 ±2 μV/°C Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, V < V REF DD Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR 4 Gain Temperature Coefficient ±1 ±1 ppm Of FSR/°C 4 DC Crosstalk 40 40 μV Due to single channel full-scale output change, RL = 5 kΩ to GND or VDD 40 40 μV/mA Due to load current change 40 40 μV Due to powering down (per channel) 4 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 1 1 nF R = 5 kΩ, R = 100 kΩ, and R = ∞ L L L DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 100 kΩ Output impedance tolerance ± 400 Ω 100 kΩ Network Output Connected to 1 1 kΩ Output impedance tolerance ± 20 Ω 1 kΩ Network Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero-scale, output shorted to VDD Power-Up Time 4.5 4.5 μs Time to exit power-down mode to normal mode of AD5024/AD5044/ nd AD5064, 32 clock edge to 90% of DAC midscale value, output unloaded DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, VREF < VDD REFERENCE INPUTS Reference Input Range 2.2 VDD 2.2 VDD V Reference Current 35 50 35 50 μA Per DAC channel Reference Input Impedance 120 120 kΩ Rev. 0 | Page 3 of 28 AD5025/AD5045/AD5065 1 1, 2 B Grade A Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments LOGIC INPUTS 5 Input Current ±1 ±1 μA Input Low Voltage, VINL 0.8 0.8 V Input High Voltage, V 2.2 2.2 V INH 4 Pin Capacitance 4 4 pF 3, 4 LOGIC OUTPUTS (SDO) Output Low Voltage, VOL 0.4 0.4 V ISINK = 2 mA Output High Voltage, V V − 1 V − 1 I = 2 mA OH DD DD SOURCE High Impedance Leakage ±0.002 ±1 ±0.002 ±1 μA 4 Current High Impedance Output 7 7 pF Capacitance POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DD 6 IDD DAC active, excludes load current Normal Mode 2.2 2.7 2.2 2.7 mA VIH = VDD and VIL = GND 7 All Power-Down Modes 0.4 2 0.4 2 μA T = −40°C to +105°C A 30 30 μA TA = −40°C to +125°C 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5065 only. 3 Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output unloaded. 4 Guaranteed by design and characterization; not production tested. 5 Current flowing into or out of individual digital pins. 6 Interface inactive. All DACs active. DAC outputs unloaded. 7 Both DACs powered down. AC CHARACTERISTICS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. 1 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale settling to ±1 LSB, RL = 5 kΩ single-channel update including DAC calibration sequence Output Voltage Settling Time 10.7 13 μs ¼ to ¾ scale settling to ±1 LSB, R = 5 kΩ all channel update including L DAC calibration sequence Slew Rate 1.5 V/μs 3 Digital-to-Analog Glitch Impulse 4 nV-sec 1 LSB change around major carry 3 Reference Feedthrough −90 dB V = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz REF SDO Feedthrough 0.07 nV-sec Daisy-chain mode; SDO load is 10 pF 3 Digital Feedthrough 0.1 nV-sec 3 Digital Crosstalk 1.9 nV-sec 3 Analog Crosstalk 1.2 nV-sec 3 DAC-to-DAC Crosstalk 2.1 nV-sec 3 Multiplying Bandwidth 340 kHz V = 3 V ± 0.86 V p-p REF 3 Total Harmonic Distortion −80 dB V = 3 V ± 0.86 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz 60 nV/√Hz DAC code = 0x8400, 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 Temperature range is −40°C to + 125°C, typical at 25°C. 3 See the Terminology section. Rev. 0 | Page 4 of 28 AD5025/AD5045/AD5065 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and Figure 4. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit 1 SCLK Cycle Time t1 20 ns SCLK High Time t2 10 ns SCLK Low Time t3 10 ns SYNC to SCLK Falling Edge Setup Time t 16.5 ns 4 Data Setup Time t 5 ns 5 Data Hold Time t 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t7 0 30 ns Minimum SYNC High Time (Single Channel Update) t8 2 μs Minimum SYNC High Time (All Channel Update) t 4 μs 8 SYNC Rising Edge to SCLK Fall Ignore t 17 ns 9 LDAC Pulse Width Low t 20 ns 10 SCLK Falling Edge to LDAC Rising Edge t11 20 ns CLR Pulse Width Low t12 10 ns SCLK Falling Edge to LDAC Falling Edge t13 10 ns CLR Pulse Activation Time t 10.6 μs 14 2, 3 SCLK Rising Edge to SDO Valid t 22 ns 15 2 t 5 30 ns SCLK Falling Edge to SYNC Rising Edge 16 2 SYNC Rising Edge to SCLK Rising Edge t17 8 ns 2 SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update) t18 2 μs 2 SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update) t18 4 μs PDL Minimum Pulse Width t 20 ns 19 1 Maximum SCLK frequency is 50 MHz at V = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested. DD 2 Daisy-chain mode only. 3 Measured with the load circuit of Figure 2. t determines the maximum SCLK frequency in daisy-chain mode. 15 Circuit and Timing Diagrams 2mA I OL V (MIN) + V (MAX) TO OUTPUT OH OL PIN 2 C L 50pF 2mA I OH Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications Rev. 0 | Page 5 of 28 06844-002 AD5025/AD5045/AD5065 t 1 t 9 SCLK t t 2 8 t t 3 7 t 4 SYNC t 6 t 5 DIN DB31 DB0 t 10 t 13 1 LDAC t 11 2 LDAC t 12 CLR t 14 V OUT t 19 PDL 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 3. Serial Write Operation SCLK 32 64 t 17 t t 8 4 t 16 SYNC t 5 t 6 DIN DB31 DB0 DB31 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 15 DB31 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 18 t 10 1 LDAC t 18 t 12 CLR t 18 t 19 PDL 1 IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY. Figure 4. Daisy-Chain Timing Diagram Rev. 0 | Page 6 of 28 06844-003 06844-004 AD5025/AD5045/AD5065 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND −0.3 V to +7 V DD other conditions above those indicated in the operational Digital Input Voltage to GND −0.3 V to V + 0.3 V DD section of this specification is not implied. Exposure to absolute VOUTA or VOUTB to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect VREFA or VREFB to GND −0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range, Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (T ) 150°C ESD CAUTION J MAX Power Dissipation (T − T )/θ J MAX A JA θJA Thermal Impedance 150.4°C/W Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C Rev. 0 | Page 7 of 28 AD5025/AD5045/AD5065 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 14 SCLK SYNC 2 13 DIN AD5025/ V 3 12 DD PDL AD5045/ V A 4 AD5065 11 GND REF TOP VIEW V A 5 10 V B OUT OUT (Not to Scale) POR 6 9 V B REF SDO 7 8 CLR Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC pin should update mode, as shown in Figure 3, and the LDAC pin must be brought be used in asynchronous LDAC high after pulsing. This allows all DAC outputs to simultaneously update. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the nd falling edges of the next 32 clocks. If SYNC is taken high before the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 V DD Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 VREFA DAC A Reference Input. This is the reference voltage input pin for DAC A. 5 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 6 POR Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V powers up DD the part to midscale. 7 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 8 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 9 VREFB DAC B Reference Input. This is the reference voltage input pin for DAC B. 10 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 11 GND Ground Reference Point for All Circuitry on the Part. 12 PDL The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A Logic 1 at the PLO pin causes the device to behave as normal. The user may successfully enter software power-down over the serial interface while Logic 1 is applied to the PDL pin. If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under any circumstances. If the device had previously been placed in software power-down mode, a high-to- low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to the previous code in the DAC register before the device entered software power-down. 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 SCLK Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. 0 | Page 8 of 28 06844-005 AD5025/AD5045/AD5065 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 512 16,640 32,768 48,896 65,024 512 16,640 32,768 48,896 65,024 DAC CODE DAC CODE Figure 9. AD5065 DNL Figure 6. AD5065 INL 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12,288 16,384 DAC CODE DAC CODE Figure 7. AD5045 INL Figure 10. AD5045 DNL 1.0 1.00 0.8 0.75 0.6 0.50 0.4 0.25 0.2 0 0 –0.2 –0.25 –0.4 –0.50 –0.6 –0.75 –0.8 –1.0 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12,288 16,384 DAC CODE DAC CODE Figure 8. AD5025 INL Figure 11. AD5025 DNL Rev. 0 | Page 9 of 28 INL (LSB) INL (LSB) INL (LSB) 06844-021 06844-020 06844-019 DNL (LSB) DNL (LSB) DNL (LSB) 06844-024 06844-023 06844-022 AD5025/AD5045/AD5065 0.20 1.2 T = 25°C A 1.0 0.15 0.8 0.10 0.6 0.4 0.05 MAX TUE ERROR @ V = 5.5V DD 0.2 0 0 MIN TUE ERROR @ V = 5.5V DD –0.2 –0.05 –0.4 –0.10 –0.6 –0.8 –0.15 –1.0 –0.20 –1.2 512 16,640 32,768 48,896 65,024 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DAC CODE REFERENCE VOLTAGE (V) Figure 12. Total Unadjusted Error (TUE) vs. DAC Code Figure 15. Total Unadjusted Error (TUE) vs. Reference Input Voltage 1.6 0.015 T = 25°C A 1.4 1.2 0.010 1.0 DAC A 0.8 0.6 MAX INL ERROR @ V = 5.5V DD 0.005 0.4 0.2 0 0 DAC B –0.2 –0.4 MIN INL ERROR @ V = 5.5V DD –0.005 –0.6 –0.8 –1.0 –0.010 –1.2 V = 5.5V DD –1.4 V = 4.096V REF –1.6 –0.015 –60 –40 –20 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) Figure 13. INL vs. Reference Input Voltage Figure 16. Gain Error vs. Temperature 0.6 1.6 V = 5.5V DD T = 25°C A 1.4 V = 4.096V 0.5 REF 1.2 1.0 0.4 0.8 0.3 0.6 0.4 0.2 MAX DNL ERROR @ V = 5.5V DD 0.2 DAC B 0.1 0 –0.2 0 MIN DNL ERROR @ V = 5.5V DD –0.4 –0.1 –0.6 DAC A –0.8 –0.2 –1.0 –1.2 –0.3 –1.4 –0.4 –1.6 –60 –40 –20 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (ºC) REFERENCE VOLTAGE (V) Figure 17. Offset Error vs. Temperature Figure 14. DNL vs. Reference Input Voltage Rev. 0 | Page 10 of 28 TUE (mV) DNL ERROR (LSB) INL ERROR (LSB) 06844-027 06844-026 06844-025 GAIN ERROR (%FSR) OFFSET ERROR (mV) TUE ERROR (mV) 06844-028 06844-029 06844-030 AD5025/AD5045/AD5065 0.2 5.0 4.5 4.0 0.1 3.5 V = 5V, V = 4.096V 3.0 DD REF T = 25ºC GAIN ERROR A 1/4 SCALE TO 3/4 SCALE 0 2.5 3/4 SCALE TO 1/4 SCALE OUTPUT LOADED WITH 5kΩ 2.0 AND 200pF TO GND FULL-SCALE ERROR 1.5 –0.1 1.0 0.5 –0.2 0 4.50 4.75 5.00 5.25 5.50 02 46 8 10 12 14 TIME (µs) V (V) DD Figure 21. Settling Time and Typical Output Slew Rate Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage 0.12 POR 0.09 1 0.06 V OUT 3 0.03 0 4.50 4.75 5.00 5.25 5.50 CH1 2V CH3 2V M2ms A CH1 2.52V T 20.4% V (V) DD Figure 19. Offset Error Voltage vs. Supply Voltage Figure 22. Power-On Reset to 0 V 16 14 12 10 1 8 6 3 4 2 0 0 1.0 1.1 1.2 1.3 1.4 1.5 CH1 2V CH3 2V M2ms A CH1 2.52V T 20.4% I POWER UP (mA) DD Figure 23. Power-On Reset to Midscale Figure 20. I Histogram, V = 5.0 V DD DD Rev. 0 | Page 11 of 28 OFFSET ERROR (mV) ERROR (%FSR) HITS 06844-064 06844-032 06844-031 OUTPUT VOLTAGE (V) 06844-040 06844-039 06844-038 AD5025/AD5045/AD5065 7 CH1 = SCLK V = 5V, V = 4.096V DD REF 6 T = 25°C A 5 1 4 3 2 1 CH2 = V V = 5V OUT DD POWER-UP TO MIDSCALE 0 –1 2 –2 –3 –4 CH1 5V CH2 500mV M2µs A CH2 1.2V 0 2.5 5.0 7.5 10.0 T 55% TIME (μs) Figure 27. DAC-to-DAC Crosstalk Figure 24. Exiting Power-Down to Midscale 6 V = 5V, V = 4.096V DD REF T = 25ºC 5 A DAC LOADED WITH MIDSCALE 4 3 2 1 0 –1 –2 –3 0 2.5 5.0 7.5 10.0 4s/DIV TIME (μs) Figure 25. Digital-to-Analog Glitch Impulse Figure 28. 0.1 Hz to 10 Hz Output Noise Plot 7 0 V = 5V, V = 4.096V V = 5V, DD REF DD 6 T = 25ºC –10 T = 25ºC A A DAC LOADED WITH MIDSCALE 5 V = 3.0V ± 200mV p-p –20 REF 4 –30 3 –40 2 –50 1 –60 0 –70 –1 –80 –2 –3 –90 –4 –100 0 2.5 5.0 7.5 10.0 5 10 20 30 40 50 55 TIME (μs) FREQUENCY (kHz) Figure 26. Analog Crosstalk Figure 29. Total Harmonic Distortion Rev. 0 | Page 12 of 28 GLITCH AMPLITUDE (mV) GLITCH AMPLITUDE (mV) 06844-041 06844-043 06844-042 V LEVEL (dB) GLITCH AMPLITUDE (mV) OUT 1μV/DIV 06844-045 06844-046 06844-044 AD5025/AD5045/AD5065 24 0.0010 V = 5V, V = 3.0V CODE = MIDSCALE DD REF T = 25°C V = 5V, V = 4.096V 22 DD REF A 0.0008 20 0.0006 18 0.0004 16 0.0002 14 0 12 –0.0002 V = 5.5V DD 10 –0.0004 8 –0.0006 6 –0.0008 4 012439 5 6 7 8 10 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 CAPACITANCE (nF) CURRENT (mA) Figure 30. Settling Time vs. Capacitive Load Figure 33. Typical Output Load Regulation 0.10 CODE = MIDSCALE V = 5V, V = 4.096V 0.08 DD REF 0.06 CLR 1 0.04 0.02 0 V OUT 2 –0.02 –0.04 –0.06 –0.08 –0.10 CH1 5V CH2 2V M2µs A CH1 2.5V –25 –20 –15 –10 –5 0 5 10 15 20 25 30 T 11% I (mA) OUT Figure 34. Typical Current Limiting Plot CLR Figure 31. Hardware 10 0 CH1 295mV p-p V OUT –10 –20 –30 –40 CH A CH B –50 CH C SCLK CH D 3dB POINT –60 10 100 1000 10000 CH1 50mV CH2 5V M4µs A CH2 1.2V T 8.6% FREQUENCY (kHz) Figure 32. Multiplying Bandwidth Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, No Load Rev. 0 | Page 13 of 28 ATTENUATION (dB) SETTLING TIME (μs) 06844-048 06844-047 06844-049 ΔVOLTAGE (V) ΔV (V) OUT 06844-053 06844-052 06844-051 AD5025/AD5045/AD5065 CH1 200mV p-p CH1 170mV p-p V OUT V OUT SCLK SCLK CH1 50mV CH2 5V M4µs A CH2 1.2V CH1 20mV CH2 5V M4µs A CH2 1.2V T 8.6% T 8.6% Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, 5 kΩ/200 pF Load 5 kΩ/200 pF Load 1 CH1 129mV p-p V OUT PDL VOUT 2 SCLK CH1 20mV CH2 5V M4µs A CH2 1.2V CH1 5.00V CH2 1V M1µs A CH1 2.5V T 8.6% Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No PDL Figure 39. Activation Time Load Rev. 0 | Page 14 of 28 06844-055 06844-054 06844-056 06844-068 AD5025/AD5045/AD5065 TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse For the DAC, relative accuracy, or integral nonlinearity (INL), is Digital-to-analog glitch impulse is the impulse injected into the a measure of the maximum deviation in LSBs from a straight analog output when the input code in the DAC register changes line passing through the endpoints of the DAC transfer state. It is normally specified as the area of the glitch in nanovolt- function. Figure 6, Figure 7, and Figure 8 show plots of typical seconds and is measured when the digital input code is changed INL vs. code. by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 25. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the DC Power Supply Rejection Ratio (PSRR) measured change and the ideal 1 LSB change between any two PSRR indicates how the output of the DAC is affected by changes adjacent codes. A specified differential nonlinearity of ±1 LSB in the supply voltage. PSRR is the ratio of the change in VOUT to maximum ensures monotonicity. This DAC is guaranteed mono- a change in VDD for full-scale output of the DAC. It is measured tonic by design. Figure 9, Figure 10, and Figure 11 show plots of in decibels. VREF is held at 2.5 V, and VDD is varied ±10%. typical DNL vs. code. Measured with V < V . REF DD Offset Error DC Crosstalk Offset error is a measure of the difference between the actual DC crosstalk is the dc change in the output level of one DAC in V OUT and the ideal VOUT, expressed in millivolts in the linear response to a change in the output of another DAC. It is measured region of the transfer function. Offset error is measured on the with a full-scale output change on one DAC (or soft power-down part with Code 512 (AD5065), Code 128 (AD5045), and Code 32 and power-up) while monitoring another DAC kept at midscale. (AD5025) loaded into the DAC register. It can be negative or It is expressed in microvolts. positive and is expressed in millivolts. DC crosstalk due to load current change is a measure of the Offset Error Drift impact that a change in load current on one DAC has to another Offset error drift is a measure of the change in offset error with DAC kept at midscale. It is expressed in microvolts per milliamp. a change in temperature. It is expressed in microvolts per degree Reference Feedthrough Celsius. Reference feedthrough is the ratio of the amplitude of the signal Gain Error at the DAC output to the reference input when the DAC output Gain error is a measure of the span error of the DAC. It is the is not being updated (that is, LDAC is high). It is expressed in deviation in slope of the DAC transfer characteristic from the decibels. ideal, expressed as a percentage of the full-scale range. Digital Feedthrough Gain Temperature Coefficient Digital feedthrough is a measure of the impulse injected into Gain error drift is a measure of the change in gain error with the analog output of a DAC from the digital input pins of the changes in temperature. It is expressed in parts per million of device but is measured when the DAC is not being written to full-scale range per degree Celsius. Measured with VREF < VDD. (SYNC held high). It is specified in nanovolt-seconds. It is measured with one simultaneous data and clock pulse loaded Full-Scale Error to the DAC. Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the Digital Crosstalk output should be V − 1 LSB. Full-scale error is expressed as a DD Digital crosstalk is the glitch impulse transferred to the output percentage of the full-scale range. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolt-seconds. Rev. 0 | Page 15 of 28 AD5025/AD5045/AD5065 Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC due to a change in the output of another DAC. It is multiplying bandwidth is a measure of this. A sine wave on the measured by loading one of the input registers with a full-scale reference (with full-scale code loaded to the DAC) appears on code change (all 0s to all 1s or vice versa) while keeping LDAC the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the Total Harmonic Distortion (THD) glitch is expressed in nanovolt-seconds. Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine DAC-to-DAC Crosstalk wave is used as the reference for the DAC, and the THD is a DAC-to-DAC crosstalk is the glitch impulse transferred to the measure of the harmonics present on the DAC output. It is output of one DAC due to a digital code change and subsequent measured in decibels. output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds. Rev. 0 | Page 16 of 28 AD5025/AD5045/AD5065 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER OUTPUT AMPLIFIER The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial The on-chip output buffer amplifier can generate rail-to-rail input, voltage output DACs. The parts operate from supply voltages voltages on its output, which gives an output range of 0 V to of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065 V . The amplifier is capable of driving a load of 5 kΩ in DD in a 32-bit word format via a 3-wire serial interface. The AD5025/ parallel with 200 pF to GND. The slew rate is 1.5 V/μs with a ¼ AD5045/AD5065 incorporate a power-on reset circuit that ensures to ¾ scale settling time of 13 μs. the DAC output powers up to a known output state. The devices SERIAL INTERFACE also have a software power-down mode that reduces the typical The AD5025/AD5045/AD5065 have a 3-wire serial interface current consumption to typically 400 nA. (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and Because the input coding to the DAC is straight binary, the ideal MICROWIRE interface standards as well as most DSPs. See output voltage when using an external reference is given by Figure 3 for a timing diagram of a typical write sequence. D   INPUT REGISTER V  V    OUT REFIN N  2  The AD5025/AD5045/AD5065 input register is 32 bits wide where: (see Figure 41). The first four bits are don’t cares. The next four D is the decimal equivalent of the binary code that is loaded to bits are the command bits, C3 to C0 (see Table 8), followed by the DAC register (0 to 65,535 for the 16-bit AD5065). the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally N is the DAC resolution. the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit input code, followed by eight, six, or four don’t care bits for the DAC ARCHITECTURE AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42, The DAC architecture of the AD5025/AD5045/AD5065 consists and Figure 43). These data bits are transferred to the DAC of two matched DAC sections. A simplified circuit diagram is nd register on the 32 falling edge of SCLK. shown in Figure 40. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches Table 7. Address Commands connects one of 15 matched resistors to either GND or a V REF Address (n) Selected DAC buffer output. The remaining 12 bits of the data-word drive Channel A3 A2 A1 A0 Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder 0 0 0 0 DAC A network. 0 0 1 1 DAC B V OUT 0 0 0 1 Reserved 2R 2R 2R 2R 2R 2R 2R 0 0 1 0 Reserved S0 S1 S11 E1 E2 E15 1 1 1 1 Both DACs V REF Table 8. Command Definitions Command 12-BIT R-2R LADDER FOUR MSBs DECODED INTO C3 C2 C1 C0 Description 15 EQUAL SEGMENTS 1 0 0 0 0 Write to Input Register n Figure 40. DAC Ladder Structure 1 0 0 0 1 Update DAC Register n REFERENCE BUFFER 0 0 1 0 Write to Input Register n, update all The AD5025/AD5045/AD5065 operate with an external reference. (software LDAC) 1 Each DAC has a dedicated voltage reference pin and an on-chip 0 0 1 1 Write to and update DAC Channel n reference buffer. The reference input pin has an input range of 0 1 0 0 Power down/power up DAC 2.5 V to VDD. This input voltage is then used to provide a 0 1 0 1 Load clear code register buffered reference for the DAC core. 0 1 1 0 Load LDAC register 0 1 1 1 Reset (power-on reset) 1 0 0 0 Set up DCEN register (daisy-chain enable) 1 0 0 1 Reserved 1 1 1 1 Reserved 1 See Table 7. Rev. 0 | Page 17 of 28 06844-006 AD5025/AD5045/AD5065 DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 41. AD5065 Input Register Content DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 42. AD5045 Input Register Content DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXX X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 43. AD5025 Input Register Content Rev. 0 | Page 18 of 28 06844-009 06844-008 06844-007 AD5025/AD5045/AD5065 Table 9 shows how the state of the bit corresponds to the mode STANDALONE MODE of operation of the device. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the Table 9. DCEN (Daisy-Chain Enable) Register falling edge of SCLK. The serial clock frequency can be as high DB1 DB0 Description as 50 MHz, making the AD5025/AD5045/AD5065 compatible 0 X Standalone mode (default) nd with high speed DSPs. On the 32 falling clock edge, the last 1 X DCEN mode data bit is clocked in and the programmed function is executed, The SCLK is continuously applied to the input register when that is, a change in DAC register contents and/or a change in SYNC is low. If more than 32 clock pulses are applied, the data the mode of operation. The SYNC line must be brought high nd ripples out of the input shift register and appears on the SDO within 30 ns of the 32 falling edge of SCLK. In either case, it line. This data is clocked out on the rising edge of SCLK and is must be brought high for a minimum of 1.9 μs before the next valid on the falling edge. By connecting this line to the DIN SYNC write sequence so that a falling edge of can initiate the next input on the next DAC in the chain, a multiDAC interface is SYNC write sequence. Because the buffer draws more current constructed. Each DAC in the system requires 32 clock pulses; SYNC when VIN = VDD than it does when VIN = 0 V, should be therefore, the total number of clock cycles must equal 32N, idled low between write sequences for even lower power where N is the total number of devices in the chain. operation of the part. As mentioned previously, however, SYNC If SYNC is taken high before 32N clocks are clocked into the must be brought high again just before the next write sequence. part, it is considered an invalid frame and the data is discarded. INTERRUPT SYNC SYNC When the serial transfer to all devices is complete, is SYNC In a normal write sequence, the line is kept low for at taken high. This prevents any further data from being clocked least 32 falling edges of SCLK, and the DAC is updated on the into the input register. nd 32 falling edge. However, if SYNC is brought high before the The serial clock can be continuous or a gated clock. A continuous nd 32 falling edge, this acts as an interrupt to the write sequence. SCLK source can be used only if SYNC can be held low for the The input register is reset, and the write sequence is seen as invalid. correct number of clock cycles. In gated clock mode, a burst Neither an update of the DAC register contents nor a change in clock containing the exact number of clock cycles must be used, the operating mode occurs (see Figure 44). SYNC and must be taken high after the final clock to latch the data. DAISY-CHAINING LDAC In daisy-chain mode, the pin cannot be tied permanently For systems that contain several DACs, or where the user wishes to LDAC LDAC low. The pin must be used in asynchronous update read back the DAC contents for diagnostic purposes, the SDO LDAC mode, as shown in Figure 3. The pin must be brought pin can be used to daisy-chain several devices together and high after pulsing. This allows all DAC outputs to simultaneously provide serial readback. update. The daisy-chain mode is enabled through a software executable daisy-chain enable (DCEN) command. Command 1000 is reserved for this DCEN function (see Table 8). The daisy-chain mode is enabled by setting a bit (DB1) in the DCEN register. The default setting is standalone mode, where DB1 = 0. SCLK SYNC DB31 DB0 DB31 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES ND ND SYNC HIGH BEFORE 32 FALLING EDGE ON THE 32 FALLING EDGE Figure 44. SYNC Interrupt Facility Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0 X 1 0 0 0 X X X X X 1/0 X Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register Rev. 0 | Page 19 of 28 06844-010 AD5025/AD5045/AD5065 current fall, but the output stage is also internally switched from POWER-ON RESET AND SOFTWARE RESET the output of the amplifier to a resistor network of known values. The AD5025/AD5045/AD5065 contain a power-on reset (POR) This has the advantage that the output impedance of the part is circuit that controls the output voltage during power-up. By known while the part is in power-down mode. There are three connecting the POR pin low, the AD5025/AD5045/AD5065 different options. The output is connected internally to GND output powers up to zero scale. Note that this is outside the through either a 1 kΩ or a 100 kΩ resistor, or it is left open- linear region of the DAC; by connecting the POR pin high, the circuited (three-state). The output stage is illustrated in Figure 45. AD5025/AD5045/AD5065 output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications AMPLIFIER V DAC OUT where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on POWER-DOWN reset code selected by the POR pin. Command 0111 is reserved RESISTOR CIRCUITRY NETWORK for this reset function (see Table 8). POWER-DOWN MODES Figure 45. Output Stage During Power-Down The AD5025/AD5045/AD5065 contain four separate modes The bias generator, output amplifier, resistor string, and other of operation. Command 0100 is reserved for the power-down associated linear circuitry are shut down when the power-down function (see Table 8). These modes are software-programmable mode is activated. However, the contents of the DAC register are by setting two bits, Bit DB9 and Bit DB8, in the input register (see unaffected when in power-down. The time to exit power-down Table 12). Table 11 shows how the state of the bits corresponds is typically 4.5 μs for VDD = 5 V (see Figure 24). to the mode of operation of the device. Either or both DACs (DAC A and DAC B) can be powered down Table 11. Modes of Operation to the selected mode by setting the corresponding bits (DB3 and DB9 DB8 Operating Mode DB0) to 1. See Table 12 for the contents of the input register 0 0 Normal operation, power-down modes during power-down/power-up operation. 0 1 1 kΩ to GND Any combination of DACs can be powered up by setting PD1 = 0 1 0 100 kΩ to GND and PD0 = 0 (normal operation). The output powers up to the 1 1 Three-state LDAC value in the input register ( low) or to the value in the When both Bit DB9 and Bit DB8 in the input register are set to 0, LDAC DAC register before powering down ( high). the part works normally with its normal power consumption of 2.2 mA at 5 V. However, for the three power-down modes, the supply current falls to 0.4 μV at 5 V. Not only does the supply Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function MSB LSB DB31 DB10 DB4 to to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB9 DB8 DB7 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 X DAC DAC DAC DAC A B B A Don’t Command bits (C2 to C0) Address bits (A3 to A0)—don’t Don’t Power-down Don’t Power-down/power-up channel cares cares cares mode cares selection—set bits to 1 to select Rev. 0 | Page 20 of 28 06844-011 AD5025/AD5045/AD5065 CLEAR CODE REGISTER FUNCTION LDAC The AD5025/AD5045/AD5065 have a hardware CLR pin that Hardware LDAC Pin is an asynchronous clear input. The CLR input is falling edge sensi- The outputs of all DACs can be updated simultaneously using CLR tive. Bringing the line low clears the contents of the input LDAC LDAC the hardware pin. The pin can be used in register and the DAC registers to the data contained in the user- synchronous or asynchronous mode, as shown in Figure 3. CLR configurable register, and sets the analog outputs accordingly LDAC LDAC Synchronous : is held low. After new data is read, (see Table 13). This function can be used in system calibration nd the DAC registers are updated on the falling edge of the 32 to load zero scale, midscale, or full scale to all channels together. SCLK pulse. LDAC can be permanently low or pulsed in These clear code values are user-programmable by setting two standalone mode. LDAC cannot be tied permanently low in bits, Bit DB1 and Bit DB0, in the input register (see Table 13). daisy-chain mode. The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see Table 8). LDAC LDAC Asynchronous : is held high and pulsed. The outputs are not updated at the same time that the input registers are Table 13. Clear Code Register LDAC written to. When goes low, the DAC registers are updated Clear Code Register with the contents of the input register. DB1 (CR1) DB0 (CR0) Clears to Code Software LDAC Function 0 0 0x0000 0 1 0x8000 Alternatively, the outputs of all DACs can be updated simulta- 1 0 0xFFFF LDAC neously using the software function by writing to Input 1 1 No operation Register n (see Table 7) and updating all DAC registers. nd LDAC Command 0010 is reserved for this software function. The part exits clear code mode on the 32 falling edge of the next write to the part. If CLR is activated during a write sequence, The LDAC register gives the user extra flexibility and control the write is aborted. over the hardware LDAC pin (see Table 16). Setting the LDAC CLR CLR bit register (DB0 to DB3) to 0 for a DAC channel means that The pulse activation time, the falling edge of to when LDAC the output starts to change, is typically 10.6 μs (see Figure 31). this channel update is controlled by the hardware pin. If DB0 or DB3 is set to 1, this channel updates synchronously. See Table 14 for contents of the input register during the loading clear code register operation. LDAC The part effectively sees the hardware pin as being tied LDAC low (see Table 15 for the register mode of operation). This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Table 14. 32-Bit Input Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0 X 0 1 0 1 X X X X X 1/0 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register (CR1 to CR0) Table 15. Overwrite Definitions LDAC Load DAC Register LDAC Bits (DB3 and DB0) LDAC Pin LDAC Operation 0 1, 0 Determined by LDAC pin. 1 1 X DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0. 1 X = don’t care. Table 16. 32-Bit Input Register Contents for Overwrite Function LDAC MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB4 to DB19 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC B X X DAC A Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Set LDAC bits to 1 to override LDAC pin Rev. 0 | Page 21 of 28 AD5025/AD5045/AD5065 The user is recommended to hardwire the pin to a logic high or POWER-DOWN LOCKOUT low, thereby either enabling or disabling the feature. The AD5025/AD5045/AD5065 contain a digital input pin, PDL. When activated, the power-down lockout pin (PDL) disables POWER SUPPLY BYPASSING AND GROUNDING software shutdown under any circumstances. The user should When accuracy is important in a circuit, it is helpful to carefully PDL hardwire the pin to a logic low (thus preventing subsequent consider the power supply and ground return layout on the board. software power-down) or logic high (the part can be placed in The printed circuit board (PCB) containing the AD5025/AD5045/ power-down mode over the serial interface). If the user transitions AD5065 should have separate analog and digital sections. If the the PDL pin from logic high to a logic low during a valid write AD5025/AD5045/AD5065 are in a system where other devices sequence, the device responds immediately and the current require an AGND-to-DGND connection, the connection should write sequence is aborted. Note the following PDL features. be made at one point only. This ground point should be as close as possible to the AD5025/AD5045/AD5065. During a Write Sequence PDL Bypass the power supply to the AD5025/AD5045/AD5065 with If a PDL is generated (that is, a high-to-low transition) while a 10 μF and 0.1 μF capacitors. The capacitors should physically be valid write sequence is ongoing, the write is aborted. The user as close as possible to the device, with the 0.1 μF capacitor must rewrite the current write command again. ideally right up against the device. The 10 μF capacitors are the While DACs in Power-Down Mode PDL tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and low effective series PDL If a is generated while the DAC(s) are in power-down inductance (ESI), which is typical of common ceramic types of mode, the DAC(s) come out of power-down (that is, all power- capacitors. This 0.1 μF capacitor provides a low impedance path down bits are reset to 0000) to the last voltage output correspond- to ground for high frequencies caused by transient currents due PDL ing to the last valid stored DAC value. While remains active, to internal logic switching. software power-down is disabled. The power supply line should have as large a trace as possible to PDL Low to High Transition provide a low impedance path and reduce glitch effects on the PDL After is taken from a low to a high state, all DAC channels supply line. Shield clocks and other fast switching digital signals remain in normal mode, and the user must reissue a software from other parts of the board by digital ground. Avoid crossover power-down command to the control register to power down of digital and analog signals if possible. When traces cross on the required channels. opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. PDL Transitioning from a low to a high disables the feature The best board layout technique is the microstrip technique, immediately. where the component side of the board is dedicated to the PDL CLR CLR If and are generated at the same time, the signal ground plane only and the signal traces are placed on the solder causes the DAC register to change as per the clear code register, side. However, this is not always possible with a 2-layer board. and the DACs come out of power-down. If PDL, CLR, and LDAC are generated at the same time, CLR has higher precedence over LDAC and PDL. Rev. 0 | Page 22 of 28 AD5025/AD5045/AD5065 AD5025/AD5045/AD5065 to 80C51/80L51 Interface MICROPROCESSOR INTERFACING AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Figure 48 shows a serial interface between the AD5025/AD5045/ Interface AD5065 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK Figure 46 shows a serial interface between the AD5025/AD5045/ of the AD5025/AD5045/AD5065, and RxD drives the serial AD5065 and the Blackfin® ADSP-BF53x microprocessor. The SYNC data line of the part. The signal is again derived from a ADSP-BF53x processor family incorporates two dual-channel bit-programmable pin on the port. In this case, Port Line P3.3 is synchronous serial ports, SPORT1 and SPORT0, for serial and used. When data is to be transmitted to the AD5025/AD5045/ multiprocessor communications. Using SPORT0 to connect to AD5065, P3.3 is taken low. The 80C51/80L51 transmits data in the AD5025/AD5045/AD5065, the setup for the interface is 8-bit bytes only; thus, only eight falling clock edges occur in the as follows: DT0PRI drives the DIN pin of the AD5025/AD5045/ transmit cycle. To load data to the DAC, P3.3 is lept low after SYNC AD5065, and TSCLK0 drives the SCLK of the parts. The is the first eight bits are transmitted, and a second write cycle is driven from TFS0. initiated to transmit the second byte of data. P3.3 is taken high ADSP-BF53x* AD5025/ following the completion of this cycle. The 80C51/80L51 outputs AD5045/ the serial data in LSB-first format. The AD5025/AD5045/AD5065 AD5065* TFS0 SYNC must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. DT0PRI DIN 80C51/80L51* AD5025/ TSCLK0 SCLK AD5045/ AD5065* *ADDITIONAL PINS OMITTED FOR CLARITY. P3.3 SYNC Figure 46. AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface TxD SCLK AD5025/AD5045/AD5065 to 68HC11/68L11 Interface RxD DIN Figure 47 shows a serial interface between the AD5025/AD5045/ AD5065 and the 68HC11/68L11 microcontroller. SCK of the *ADDITIONAL PINS OMITTED FOR CLARITY. 68HC11/68L11 drives the SCLK of the AD5025/AD5045/AD5065, Figure 48. AD5025/AD5045/AD5065 to 80C51/80L51 Interface and the MOSI output drives the serial data line of the DAC. AD5025/AD5045/AD5065 to MICROWIRE Interface 68HC11/68L11* AD5025/ Figure 49 shows an interface between the AD5025/AD5045/ AD5045/ AD5065* AD5065 and any MICROWIRE-compatible device. Serial data is PC7 SYNC shifted out on the falling edge of the serial clock and is clocked into the AD5025/AD5045/AD5065 on the rising edge of SCLK. SCK SCLK MICROWIRE* AD5025/ MOSI DIN AD5045/ AD5065* *ADDITIONAL PINS OMITTED FOR CLARITY. CS SYNC Figure 47. AD5025/AD5045/AD5065 to 68HC11/68L11 Interface SK DIN The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: SO SCLK The 68HC11/68L11 is configured with its CPOL bit as 0, and its *ADDITIONAL PINS OMITTED FOR CLARITY. CPHA bit as 1. When data is being transmitted to the DAC, the Figure 49. AD5025/AD5045/AD5065 to MICROWIRE Interface SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5025/AD5045/ AD5065, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. 0 | Page 23 of 28 06844-013 06844-012 06844-015 06844-014 AD5025/AD5045/AD5065 APPLICATIONS INFORMATION This is an output voltage range of ±5 V, with 0x0000 corre- USING A REFERENCE AS A POWER SUPPLY FOR sponding to a −5 V output, and 0xFFFF corresponding to a THE AD5025/AD5045/AD5065 +5 V output. Because the supply current required by the AD5025/AD5045/ R2 = 10kΩ AD5065 is extremely low, an alternative option is to use a voltage +5V reference to supply the required voltage to the parts (see Figure 50). +5V R1 = 10kΩ This is especially useful if the power supply is quite noisy or if AD820/ the system supply voltages are at some value other than 5 V or ±5V OP295 3 V, for example, 15 V. The voltage reference outputs a steady V V DD OUT 0.1µF supply voltage for the AD5025/AD5045/AD5065. If the low 10µF AD5025/ –5V AD5045/ dropout REF195 is used, it must supply 500 μA of current to AD5065 the AD5025/AD5045/AD5065 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required 3-WIRE SERIAL INTERFACE (with a 5 kΩ load on the DAC output) is Figure 51. Bipolar Operation with the AD5025/AD5045/AD5065 500 μA + (5 V/5 kΩ) = 1.5 mA USING THE AD5025/AD5045/AD5065 WITH A The load regulation of the REF195 is typically 2 ppm/mA, GALVANICALLY ISOLATED INTERFACE which results in a 3 ppm (15 μV) error for the 1.5 mA current In process control applications in industrial environments, it is drawn from it. This corresponds to a 0.196 LSB error. often necessary to use a galvanically isolated interface to protect 15V and isolate the controlling circuitry from any hazardous common- 5V REF195 mode voltages that can occur in the area where the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. The AD5025/AD5045/AD5065 use a 3-wire serial logic interface, V DD SYNC so the ADuM1300 three-channel digital isolator provides the 3-WIRE x = 0V TO 5V AD5025/ V OUT SERIAL SCLK AD5045/ required isolation (see Figure 52). The power supply to the part INTERFACE DIN AD5065 also needs to be isolated, which is achieved by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5025/AD5045/AD5065. Figure 50. REF195 as Power Supply to the AD5025/AD5045/AD5065 5V REGULATOR BIPOLAR OPERATION USING THE POWER 10µF 0.1µF AD5025/AD5045/AD5065 The AD5025/AD5045/AD5065 is designed for single-supply operation, but a bipolar output range is also possible using the V circuit in Figure 51. The circuit gives an output voltage range of DD SCLK V V SCLK IA OA ±5 V. Rail-to-rail operation at the amplifier output is achievable AD5025/ using an AD820 or an OP295 as the output amplifier. AD5045/ ADuM1300 AD5065 The output voltage for any input code can be calculated as SDI V V SYNC V x IB OUT OB follows:  D R1 R2 R2        V DATA V DIN OC V  V    V  IC      DD DD  O 65,536 R1 R1       GND   where D represents the input code in decimal (0 to 65,535). Figure 52. AD5025/AD5045/AD5065 with a Galvanically Isolated Interface With VDD = 5 V, R1 = R2 = 10 kΩ, 10 D   V   5 V O 65,536   Rev. 0 | Page 24 of 28 06844-016 06844-018 06844-017 AD5025/AD5045/AD5065 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Package Model Temperature Range Package Description Option Accuracy Resolution 1 AD5025BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits 1 AD5025BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits 1 AD5045BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits 1 AD5045BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits 1 AD5065ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits 1 AD5065ARUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits 1 AD5065BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits 1 AD5065BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits 1 Z = RoHS Compliant Part. Rev. 0 | Page 25 of 28 061908-A AD5025/AD5045/AD5065 NOTES Rev. 0 | Page 26 of 28 AD5025/AD5045/AD5065 NOTES Rev. 0 | Page 27 of 28 AD5025/AD5045/AD5065 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06844-0-10/08(0) Rev. 0 | Page 28 of 28