ANALOG DEVICES AD5024

Fully Accurate, 12-/14-/16-Bit V nanoDAC, Quad, OUT SPI Interface, 4.5 V to 5.5 V in TSSOP AD5024/AD5044/AD5064 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V DD REFIN Low power quad 12-/14-/16-bit DAC, ±1 LSB INL AD5064-1 Pin compatible and performance upgrade to AD5666 LDAC BUFFER INPUT DAC DAC A V A OUT Individual and common voltage reference pin options REGISTER REGISTER SCLK BUFFER DAC Rail-to-rail operation INPUT DAC B V B OUT REGISTER REGISTER INTERFACE SYNC LOGIC AND 4.5 V to 5.5 V power supply SHIFT BUFFER INPUT DAC V C REGISTER DAC C OUT REGISTER REGISTER DIN Power-on reset to zero scale or midscale BUFFER INPUT DAC DAC D V D OUT REGISTER REGISTER 3 power-down functions and per-channel power-down SDO POWER-ON POWER-DOWN RESET LOGIC Hardware LDAC with software LDAC override function POR GND CLR function to programmable code LDAC CLR Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666 SDO daisy-chaining option V V A V B 14-/16-lead TSSOP DD REF REF AD5024/ Internal reference buffer and internal output amplifier AD5044/ AD5064 LDAC BUFFER INPUT DAC V A DAC A OUT REGISTER REGISTER APPLICATIONS SCLK BUFFER INPUT DAC DAC B V B INTERFACE OUT REGISTER REGISTER Process control LOGIC AND SYNC SHIFT BUFFER REGISTER INPUT DAC DAC C V C Data acquisition systems OUT REGISTER REGISTER DIN BUFFER Portable battery-powered instruments INPUT DAC DAC D V D OUT REGISTER REGISTER Digital gain and offset adjustment POWER-ON POWER-DOWN RESET LOGIC Programmable voltage and current sources POR GND V C V D LDAC CLR REF REF Programmable attenuators Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5024/AD5044/AD5064/AD5064-1 are low power, quad 1. Quad channel available in 14-/16-lead TSSOP packages. 12-/14-/16-bit buffered voltage output nanoDAC® converters 2. 16-bit accurate, 1 LSB INL. that offer relative accuracy specifications of 1 LSB INL and 1 LSB 3. High speed serial interface with clock speeds up to 50 MHz. DNL with the AD5024/AD5044/AD5064 individual reference 4. Reset to known output voltage (zero scale or midscale). pin and the AD5064-1 common reference pin options. The Table 1. Related Devices AD5024/AD5044/AD5064/AD5064-1 can operate from a single Part No. Description 4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1 AD5666 Quad,16-bit buffered DAC, also offer a differential accuracy specification of ±1 LSB. The 16 LSB INL, TSSOP parts use a versatile 3-wire, low power Schmitt trigger serial AD5025/AD5045/AD5065 Dual, 16-bit buffered DACs, interface that operates at clock rates up to 50 MHz and is compati- 1 LSB INL, TSSOP ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface AD5062, AD5063 16-bit nanoDAC, 1 LSB INL, SOT-23, standards. Integrated reference buffers and output amplifiers are MSOP also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1 AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 incorporate a power-on reset circuit that ensures the DAC AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, output powers up to zero scale or midscale and remains there SOT-23 until a valid write takes place to the device. The AD5024/AD5044/ AD5064/AD5064-1 contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in power- down mode. Total unadjusted error for the parts is <2 mV. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06803-001 06803-064 AD5024/AD5044/AD5064 TABLE OF CONTENTS Features .............................................................................................. 1  Output Amplifier........................................................................ 19  Applications....................................................................................... 1  Serial Interface ............................................................................ 19  Functional Block Diagrams............................................................. 1  Shift Register............................................................................... 19  General Description ......................................................................... 1  Modes of Operation ................................................................... 21  Product Highlights ........................................................................... 1  Power-On Reset.......................................................................... 22  Revision History ............................................................................... 2  Power-Down Modes .................................................................. 22  Specifications..................................................................................... 3  Clear Code Register ................................................................... 23  AC Characteristics........................................................................ 4  LDAC Function .......................................................................... 23  Timing Characteristics ................................................................ 5  Power Supply Bypassing and Grounding................................ 24  Absolute Maximum Ratings............................................................ 7  Microprocessor Interfacing....................................................... 25  ESD Caution.................................................................................. 7  Applications Information .............................................................. 26  Pin Configurations and Function Descriptions ........................... 8  Using a Reference as a Power Supply....................................... 26  Typical Performance Characteristics ........................................... 10  Bipolar Operation....................................................................... 26  Terminology .................................................................................... 17  Using the AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface ................................................. 26  Theory of Operation ...................................................................... 19  Outline Dimensions....................................................................... 27  Digital-to-Analog Converter .................................................... 19  Ordering Guide .......................................................................... 28  DAC Architecture....................................................................... 19  Reference Buffer ......................................................................... 19  REVISION HISTORY 5/11—Rev. D to Rev. E Changes to Figure 4...........................................................................6 Changes to Table 4............................................................................ 5 Added Figure 6...................................................................................8 Changes to Figure 4 and Figure 5................................................... 6 Added Table 6; Renumbered Sequentially .....................................8 Changed Input Shift Register to Shift Register Throughout .......8 8/10—Rev. C to Rev. D Changes to Table 7.............................................................................9 Change to Minimum High Time (Single Channel Changes to Typical Performance Characteristics Section ........ 10 SYNC Changes to Terminology Section ................................................. 17 Update) Parameter, Table 4 ............................................................. 5 Changes to Digital-to-Analog Converter Section, Reference Buffer Section, Output Amplifier Section, Serial Interface 5/10—Rev. B to Rev. C Section, Shift Register Section, and Table 8................................ 19 Changes to Power-On Reset Section............................................ 22 Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20 Added Modes of Operation Section, Daisy-Chaining Section, 6/09—Rev. A to Rev. B Table 10, and Table 11.................................................................... 21 Changes to Figure 1.......................................................................... 1 Changes to Table 13 and Power-Down Mode Section .............. 22 Changes to Table 16 ....................................................................... 24 3/09—Rev. 0 to Rev. A Changes to Figure 52 to Figure 55................................................ 25 Added 14-Lead TSSOP ......................................................Universal Changes to Bipolar Operation Section and Figure 56 to Added Figure 1; Renumbered Sequentially .................................. 1 Figure 58 .......................................................................................... 26 Changes to Features Section, General Description Section, Added Figure 59 ............................................................................. 27 Product Highlights Section, Figure 2, and Table 1....................... 1 Updated Outline Dimensions....................................................... 27 Changes to Table 2............................................................................ 3 Changes to Ordering Guide .......................................................... 28 Changes to Timing Characteristics Section and Table 4............. 5 Added Circuit and Timing Diagrams Section and Figure 3....... 5 8/08—Revision 0: Initial Version Added Figure 5.................................................................................. 6 Rev. E | Page 2 of 28 AD5024/AD5044/AD5064 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 1, 2 B Grade A Grade Parameter Unit Conditions/Comments Min Typ Max Min Typ Max 3 STATIC PERFORMANCE Resolution 16 16 Bits AD5064/AD5064-1 14 Bits AD5044 12 Bits AD5024 4 Relative Accuracy (INL) ±0.5 ±1 ±0.5 ±4 LSB AD5064/AD5064-1; T = −40°C to A +105°C ±0.5 ±2 ±0.5 ±4 LSB AD5064/AD5064-1; T = −40°C to A +125°C ±0.25 ±1 LSB AD5044 ±0.12 ±0.5 LSB AD5024 4 Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error ±2 ±2 mV VREF = 2.5 V, VDD = 5.5 V 4, 5 Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Offset Error Temperature ±2 ±2 μV/°C 4, 6 Coefficient 4 Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, VREF < VDD 4 Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR V < V REF DD 4, 6 Gain Temperature Coefficient ±1 ±1 ppm FSR/°C 4, 6 DC Crosstalk 40 40 μV Due to single-channel, full-scale output change, RL = 5 kΩ to GND or VDD 40 40 μV/mA Due to load current change 40 40 μV Due to powering down (per channel) 6 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 1 1 nF RL = 5 kΩ, RL =100 kΩ, and RL = ∞ DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 100 kΩ Output impedance tolerance ± 20 kΩ 100 kΩ Network Output Connected to 1 1 kΩ Output impedance tolerance ± 400 Ω 1 kΩ Network Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero scale, output shorted to V DD 7 Power-Up Time 4.5 4.5 μs DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, VREF < VDD REFERENCE INPUTS Reference Input Range 2.2 VDD 2.2 VDD V Reference Current 35 50 35 50 μA Per DAC channel; individual reference option 140 160 140 160 μA Single reference option Reference Input Impedance 120 120 kΩ Individual reference option 32 32 kΩ Single reference option LOGIC INPUTS 8 Input Current ±1 ±1 μA Input Low Voltage, V 0.8 0.8 V INL Input High Voltage, VINH 2.2 2.2 V 6 Pin Capacitance 4 4 pF Rev. E | Page 3 of 28 AD5024/AD5044/AD5064 1 1, 2 B Grade A Grade Parameter Unit Conditions/Comments Min Typ Max Min Typ Max 9 LOGIC OUTPUTS (SDO) Output Low Voltage, V 0.4 0.4 V I = 2 mA OL SINK Output High Voltage, V V − 1 V − 1 I = 2 mA OH DD DD SOURCE High Impedance Leakage ±0.002 ±1 ±0.002 ±1 μA Current High Impedance Output 7 7 pF 6 Capacitance POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V DAC active, excludes load current 10 I V = V , V = GND, Code = midscale DD IH DD IL Normal Mode 4 6 4 6 mA 11 All Power-Down Modes 0.4 2 0.4 2 μA TA = −40°C to +105°C 30 30 μA T = −40°C to +125°C A 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5064 only. 3 Linearity and total unadjusted error are calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded. 4 See the Terminology section. 5 Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded 6 Guaranteed by design and characterization; not production tested. 7 nd Time to exit power-down mode to normal mode; 32 clock edge to 90% of DAC midscale value, output unloaded. 8 Current flowing into individual digital pins. V = 5.5 V; V = 4.096 V; Code = midscale. DD REF 9 AD5064-1 only. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All four DACs powered down. AC CHARACTERISTICS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V . All specifications T to T , unless otherwise DD L L REFIN DD MIN MAX noted. Table 3. 1, 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, single-channel update 10.7 13 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, R = 5 kΩ, all channel L update Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry Reference Feedthrough −90 dB VREF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz Digital Feedthrough 0.1 nV-sec Digital Crosstalk 1.9 nV-sec Analog Crosstalk 2 nV-sec DAC-to-DAC Crosstalk 3.5 nV-sec AC Crosstalk 6 nV-sec Multiplying Bandwidth 340 kHz V = 3 V ± 0.86 V p-p REF Total Harmonic Distortion −80 dB V = 3 V ± 0.2 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, frequency = 1 kHz 60 nV/√Hz DAC code = 0x8400, frequency = 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +125°C, typical at 25°C. Rev. E | Page 4 of 28 AD5024/AD5044/AD5064 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter Symbol Min Typ Max Unit SCLK Cycle Time t1 20 ns SCLK High Time t2 10 ns SCLK Low Time t3 10 ns SYNC to SCLK Falling Edge Setup Time t 17 ns 4 Data Setup Time t 5 ns 5 Data Hold Time t 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t7 5 30 ns Minimum SYNC High Time (Single Channel Update) t8 3 μs Minimum SYNC High Time (All Channel Update) t 8 μs 8 SYNC Rising Edge to SCLK Fall Ignore t 17 ns 9 LDAC Pulse Width Low t 20 ns 10 SCLK Falling Edge to LDAC Rising Edge t11 20 ns CLR Minimum Pulse Width Low t12 10 ns SCLK Falling Edge to LDAC Falling Edge t13 10 ns CLR Pulse Activation Time t 10.6 μs 14 2, 3 SCLK Rising Edge to SDO Valid t 22 ns 15 2 t 5 ns SCLK Falling Edge to SYNC Rising Edge 16 2 SYNC Rising Edge to SCLK Rising Edge t17 8 ns 2 SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update) t18 2 μs 2 SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update) t18 8 μs 4 Power-up Time 4.5 μs 1 Maximum SCLK frequency is 50 MHz at V = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested. DD 2 Daisy-chain mode only. 3 Measured with the load circuit of Figure 3. t determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only. 15 4 nd Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32 clock edge to 90% of DAC midscale value, with output unloaded. Circuit and Timing Diagrams 2mA I OL V (MIN) + V (MAX) OH OL TO OUTPUT 2 PIN C L 50pF 2mA I OH Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications Rev. E | Page 5 of 28 06803-002 AD5024/AD5044/AD5064 t 1 t 9 SCLK t 2 t 8 t t 3 7 t 4 SYNC t 6 t 5 DIN DB31 DB0 t 10 t 13 1 LDAC t 11 2 LDAC t 12 CLR t V 14 OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 4. Serial Write Operation SCLK 32 64 t 17 t t 8 4 t 16 SYNC t 5 t 6 DB31 DB0 DB31 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 15 DB31 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 18 t 10 1 LDAC t 18 t 12 CLR 1 IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY. Figure 5. Daisy-Chain Timing Diagram Rev. E | Page 6 of 28 06803-003 06803-004 AD5024/AD5044/AD5064 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect VOUT to GND −0.3 V to VDD + 0.3 V device reliability. VREF to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial −40°C to +125°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T ) 150°C J MAX TSSOP Package Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 113°C/W Reflow Soldering Peak Temperature Pb-Free 260°C Rev. E | Page 7 of 28 AD5024/AD5044/AD5064 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 14 SCLK LDAC SYNC 2 13 DIN V 3 12 GND DD AD5064-1 V A V B 4 11 OUT OUT TOP VIEW V C V D 5 10 OUT OUT (Not to Scale) 9 POR 6 CLR V 8 7 SDO REFIN Figure 6. 14-Lead TSSOP (RU-14) Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought high after pulsing. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the nd falling edges of the next 32 clocks. If SYNC is taken high before the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 VDD Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 5 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 6 POR Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V DD powers up all four DACs to midscale. 7 VREFIN This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D. 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 9 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 10 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 11 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 GND Ground Reference Point for All Circuitry on the Part. 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the falling edge of the serial clock input. 14 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. E | Page 8 of 28 06803-065 AD5024/AD5044/AD5064 LDAC 1 16 SCLK SYNC 2 15 DIN V 3 14 GND DD AD5024/ AD5044/ V B 4 13 OUT V B REF AD5064 V D 5 12 V A OUT REF TOP VIEW V D V A 6 (Not to Scale) 11 REF OUT 7 10 V C CLR OUT 8 9 V C POR REF Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the nd falling edges of the next 32 clocks. If SYNC is taken high before the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 VDD Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V B DAC B Reference Input. This is the reference voltage input pin for DAC B. REF 5 V A DAC A Reference Input. This is the reference voltage input pin for DAC A. REF 6 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 7 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 8 POR Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to V powers up the DD part to midscale. 9 V C DAC C Reference Input. This is the reference voltage input pin for DAC C. REF 10 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V D DAC D Reference Input. This is the reference voltage input pin for DAC D. REF 12 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 13 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the falling edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. E | Page 9 of 28 06803-005 AD5024/AD5044/AD5064 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 V = 5V V = 5V DD DD V = 4.096V V = 4.096V REF REF 0.8 0.8 T = 25°C T = 25°C A A 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 512 16,640 32,768 48,896 65,024 512 16,640 32,768 48,896 65,024 DAC CODE DAC CODE Figure 11. AD5064/AD5064-1 DNL Figure 8. AD5064/AD5064-1 INL 1.0 1.0 V = 5V V = 5V DD DD V = 4.096V V = 4.096V 0.8 REF 0.8 REF T = 25°C T = 25°C A A 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 4096 8192 12,288 16,384 0 512 1024 1536 2048 2560 3072 3584 4096 DAC CODE DAC CODE Figure 12. AD5044 DNL Figure 9. AD5044 INL 1.0 1.00 V = 5V V = 5V DD DD V = 4.096V V = 4.096V REF 0.8 REF 0.75 T = 25°C T = 25°C A A 0.6 0.50 0.4 0.25 0.2 0 0 –0.2 –0.25 –0.4 –0.50 –0.6 –0.75 –0.8 –1.0 –1.00 0 4096 8192 12,288 16,384 0 512 1024 1536 2048 2560 3072 3584 4096 DAC CODE DAC CODE Figure 13. AD5024 DNL Figure 10. AD5024 INL Rev. E | Page 10 of 28 INL (LSB) INL (LSB) INL (LSB) 06803-021 06803-020 06803-019 DNL (LSB) DNL (LSB) DNL (LSB) 06803-024 06803-023 06803-022 AD5024/AD5044/AD5064 0.20 1.2 V = 5V T = 25°C DD A 1.0 V = 4.096V REF 0.15 T = 25°C A 0.8 0.10 0.6 0.4 0.05 0.2 MAX TUE @ V = 5.5V DD 0 0 MIN TUE @ V = 5.5V DD –0.2 –0.05 –0.4 –0.10 –0.6 –0.8 –0.15 –1.0 –0.20 –1.2 512 16,640 32,768 48,896 65,024 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DAC CODE REFERENCE VOLTAGE (V) Figure 14. Total Unadjusted Error (TUE) Figure 17. TUE vs. Reference Input Voltage 1.6 0.015 T = 25°C A 1.4 1.2 0.010 1.0 DAC A 0.8 0.6 MAX INL ERROR @ V = 5.5V DD 0.005 0.4 0.2 DAC B 0 0 DAC D –0.2 –0.4 MIN INL ERROR @ V = 5.5V DD DAC C –0.005 –0.6 –0.8 –1.0 –0.010 –1.2 V = 5.5V DD –1.4 V = 4.096V REF –1.6 –0.015 120 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –60 –40 –20 0 20 40 60 80 100 140 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 15. INL vs. Reference Input Voltage Figure 18. Gain Error vs. Temperature 1.6 0.6 V = 5.5V T = 25°C A DD 1.4 V = 4.096V 0.5 REF 1.2 DAC C 1.0 0.4 0.8 0.3 0.6 0.4 0.2 MAX DNL ERROR @ V = 5.5V DD 0.2 DAC D 0 0.1 –0.2 0 MIN DNL ERROR @ V = 5.5V –0.4 DD –0.6 –0.1 DAC A –0.8 –0.2 –1.0 DAC B –1.2 –0.3 –1.4 –1.6 –0.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –60 –40 –20 0 20 40 60 80 100 120 140 REFERENCE VOLTAGE (V) TEMPERATURE (ºC) Figure 16. DNL vs. Reference Input Voltage Figure 19. Offset Error vs. Temperature Rev. E | Page 11 of 28 TUE (mV) DNL ERROR (LSB) INL ERROR (LSB) 06803-025 06803-027 06803-026 OFFSET ERROR (mV) GAIN ERROR (%FSR) TUE (mV) 06803-028 06803-030 06803-029 AD5024/AD5044/AD5064 0.2 10 V = 5.5V V = 4.096V REF DD V = 4.096 T = 25°C REF A T = 25°C A 8 0.1 6 GAIN ERROR 0 4 FULL-SCALE ERROR –0.1 2 0 –0.2 4.50 4.75 5.00 5.25 5.50 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 V (V) DD DAC CODE Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage Figure 23. Supply Current vs. Code 0.12 10 V = 5.5V V = 4.096V DD REF V = 4.096 T = 25°C REF A CODE = MIDSCALE 8 0.09 6 0.06 4 0.03 2 0 0 –40 –20 0 20 40 60 80 100 120 4.50 4.75 5.00 5.25 5.50 V (V) DD TEMPERATURE (°C) Figure 21. Offset Error Voltage vs. Supply Voltage Figure 24. Supply Current vs. Temperature 40 10 MEAN: 4.11699 V = 5.5V DD SD: 0.0544403 V = 4.096 REF 35 LIMITS: LOW: 3 HIGH: 4.3 T = 25°C A CPk: LOW: 6.84 HIGH: 1.12 8 V = 4.096V REF 30 T = 25°C A CODE = MIDSCALE 25 6 20 4 15 10 2 5 0 0 3.9 4.0 4.1 4.2 4.3 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 I (mA) SUPPLY VOLTAGE (V) DD POWER-UP Figure 25. Supply Current vs. Supply Voltage Figure 22. IDD Histogram, VDD = 5.0 V Rev. E | Page 12 of 28 HITS OFFSET ERROR (mV) ERROR (%FSR) 06803-032 06803-031 06803-033 I (mA) DD I (mA) DD I (mA) DD 06803-035 06803-036 06803-034 AD5024/AD5044/AD5064 10 V = 4.096V V = 5.5V REF DD T = 25°C V = 4.096 A REF OUTPUT UNLOADED T = 25°C A V DD 8 6 1 DAC A 4 3 2 0 0123 45 CH1 2V CH3 2V M2ms A CH1 2.52V T 20.4% DIGITAL INPUT VOLTAGE (V) Figure 26. Supply Current vs. Digital Input Voltage Figure 29. Power-On Reset to Midscale 5.0 CH1 = SCLK 4.5 4.0 1 3.5 3.0 V = 5V, V = 4.096V DD REF T = 25ºC A 1/4 SCALE TO 3/4 SCALE 2.5 3/4 SCALE TO 1/4 SCALE CH2 = V V = 5V OUT DD OUTPUT LOADED WITH 5kΩ 2.0 POWER-UP TO MIDSCALE AND 200pF TO GND OUTPUT UNLOADED 1.5 2 1.0 0.5 0 02468 10 12 14 CH1 5V CH2 500mV M2µs A CH2 1.2V T 55% TIME (µs) Figure 30. Exiting Power-Down to Midscale Figure 27. Settling Time 6 VDD = 5V V = 4.096V REF V = 4.096V T = 25°C REF A 5 T = 25°C V A DD CODE = 0x8000 TO 0x7FFF 4 OUTPUT UNLOADED WITH 5kΩ AND 200pF 3 2 1 1 0 DAC A 3 –1 –2 –3 0 2.5 5.0 7.5 10.0 CH1 2V CH3 2V M2ms A CH1 2.52V T 20.4% TIME (μs) Figure 31. Digital-to-Analog Glitch Impulse Figure 28. Power-On Reset to 0 V Rev. E | Page 13 of 28 OUTPUT VOLTAGE (V) I (mA) DD 06803-039 06803-038 06803-037 GLITCH AMPLITUDE (mV) 06803-041 06803-040 06803-042 AD5024/AD5044/AD5064 0 7 V = 5V, V = 4.096V V = 5V, DD REF DD 6 T = 25ºC –10 T = 25ºC A A DAC LOADED WITH MIDSCALE 5 V = 3.0V ± 200mV p-p –20 REF 4 –30 3 –40 2 –50 1 –60 0 –70 –1 –80 –2 –3 –90 –4 –100 0 2.5 5.0 7.5 10.0 5 10 20 30 40 50 55 TIME (μs) FREQUENCY (kHz) Figure 32. Analog Crosstalk Figure 35. Total Harmonic Distortion 7 24 V = 5V, V = 3.0V V = 5V, V = 4.096V DD REF DD REF 6 T = 25°C T = 25°C A 22 A 1/4 SCALE TO 3/4 SCALE 5 WITHIN ±1LSB 20 4 18 3 16 2 14 1 12 0 10 –1 –2 8 –3 6 –4 4 0 2.5 5.0 7.5 10.0 012439 5 6 7 8 10 TIME (μs) CAPACITANCE (nF) Figure 33. DAC-to-DAC Crosstalk Figure 36. Settling Time vs. Capacitive Load V = 5V, V = 4.096V DD REF T = 25ºC A DAC LOADED WITH MIDSCALE CLR 1 DAC A 2 V = 5V DD V = 4.096V REF T = 25ºC A 4s/DIV CH1 5V CH2 2V M2µs A CH1 2.5V T 11% Figure 34. 0.1 Hz to 10 Hz Output Noise Plot CLR Figure 37. Hardware Rev. E | Page 14 of 28 GLITCH AMPLITUDE (mV) GLITCH AMPLITUDE (mV) 1μV/DIV 06803-045 06803-044 06803-043 V LEVEL (dB) SETTLING TIME (μs) OUT 06803-048 06803-047 06803-046 AD5024/AD5044/AD5064 10 0.10 CODE = MIDSCALE V = 5V, V = 4.096V 0.08 DD REF 0 0.06 –10 0.04 0.02 –20 0 –30 –0.02 –0.04 –40 CH A –0.06 CH B –50 CH C CH D –0.08 3dB POINT –60 –0.10 10 100 1000 10000 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 FREQUENCY (kHz) I (mA) OUT Figure 38. Multiplying Bandwidth Figure 41. Typical Current Limiting Plot 5.0 T = 25°C A V = 5V, V = 4.096V DD REF 4.5 DAC A 295mV p-p 4.0 3.5 3.0 V = 5V, V = 4.096V DD REF T = 25°C A 2.5 1/4 SCALE TO 3/4 SCALE 3/4 SCALE TO 1/4 SCALE 2.0 OUTPUT LOADED WITH 5kΩ AND 200pF TO GND 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 CH1 50mV CH2 5V M4µs A CH2 1.2V TIME (µs) T 8.6% Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Figure 39. Typical Output Slew Rate No Load 0.0010 T = 25°C A CODE = MIDSCALE V = 5V, V = 4.096V DD REF V = 5V, V = 4.096V DD REF 0.0008 DAC A 200mV p-p 0.0006 0.0004 0.0002 0 –0.0002 –0.0004 SCLK –0.0006 –0.0008 CH1 50mV CH2 5V M4µs A CH2 1.2V –25 –20 –15 –10 –5 0 5 10 15 20 25 30 T 8.6% CURRENT (mA) Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Figure 40. Typical Output Load Regulation 5 kΩ/200 pF Load Rev. E | Page 15 of 28 ∆VOLTAGE (V) ATTENUATION (dB) OUTPUT VOLTAGE (V) 06803-050 06803-049 06803-051 ∆V (V) OUT 06803-054 06803-053 06803-052 AD5024/AD5044/AD5064 V = 5V,V = 4.096V T = 25°C DD REF A T = 25°C A V = 5V, V = 4.096V DD REF DAC A 170mV p-p DAC A 129mV p-p SCLK SCLK CH1 20mV CH2 5V M4µs A CH2 1.2V CH1 20mV CH2 5V M4µs A CH2 1.2V T 8.6% T 8.6% Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load 5 kΩ/200 pF Load Rev. E | Page 16 of 28 06803-055 06803-056 AD5024/AD5044/AD5064 TERMINOLOGY Relative Accuracy (INL) DC Power Supply Rejection Ratio (PSRR) For the DAC, relative accuracy, or integral nonlinearity (INL), PSRR indicates how the output of the DAC is affected by changes is a measure of the maximum deviation in LSBs from a straight in the supply voltage. PSRR is the ratio of the change in VOUT to line passing through the endpoints of the DAC transfer function. a change in VDD for full-scale output of the DAC. It is measured Figure 8, Figure 9, and Figure 10 show plots of typical INL vs. in decibels. V is held at 2.5 V, and V is varied by ±10%. REF DD code. Measured with V < V . REF DD Differential Nonlinearity (DNL) DC Crosstalk DNL is the difference between the measured change and the DC crosstalk is the dc change in the output level of one DAC in ideal 1 LSB change between any two adjacent codes. A specified response to a change in the output of another DAC. It is measured differential nonlinearity of ±1 LSB maximum ensures monoto- with a full-scale output change on one DAC (or soft power-down nicity. This DAC is guaranteed monotonic by design. Figure 11, and power-up) while monitoring another DAC kept at midscale. Figure 12, and Figure 13 show plots of typical DNL vs. code. It is expressed in microvolts. Offset Error DC crosstalk due to load current change is a measure of the Offset error is a measure of the difference between the actual impact that a change in load current on one DAC has to another V and the ideal V , expressed in millivolts in the linear DAC kept at midscale. It is expressed in microvolts per milliamp. OUT OUT region of the transfer function. Offset error is calculated using Reference Feedthrough a reduced code range—AD5064/AD5604-1: Code 512 to Code Reference feedthrough is the ratio of the amplitude of the signal 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to at the DAC output to the reference input when the DAC output Code 4064, with output unloaded. Offset error can be negative or is not being updated (that is, LDAC is high). It is expressed in positive and is expressed in millivolts. decibels. Gain Error Digital Feedthrough Gain error is a measure of the span error of the DAC. It is the Digital feedthrough is a measure of the impulse injected into deviation in slope of the DAC transfer characteristic from the the analog output of a DAC from the digital input pins of the ideal, expressed as a percentage of the full-scale range. device, but it is measured when the DAC is not being written Offset Error Temperature Coefficient to (SYNC held high). It is specified in nanovolt-seconds and Offset error temperature coefficient is a measure of the change measured with one simultaneous data and clock pulse loaded in offset error with a change in temperature. It is expressed in to the DAC. microvolts per degree Celsius. Digital Crosstalk Gain Temperature Coefficient Digital crosstalk is the glitch impulse transferred to the output Gain error drift is a measure of the change in gain error with of one DAC at midscale in response to a full-scale code change changes in temperature. It is expressed in parts per million of (all 0s to all 1s or vice versa) in the input register of another full-scale range per degree Celsius. DAC. It is measured in standalone mode and is expressed in nanovolt-seconds. Full-Scale Error Full-scale error is a measure of the output error when full-scale Analog Crosstalk code (0xFFFF) is loaded into the DAC register. Ideally, the Analog crosstalk is the glitch impulse transferred to the output output should be V − 1 LSB. Full-scale error is expressed as a REF of one DAC due to a change in the output of another DAC. It is percentage of the full-scale range. Measured with V < V . REF DD measured by loading one of the input registers with a full-scale LDAC code change (all 0s to all 1s or vice versa) while keeping Digital-to-Analog Glitch Impulse high, and then pulsing LDAC low and monitoring the output of Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes the DAC whose digital code has not changed. The area of the state. It is normally specified as the area of the glitch in nanovolt- glitch is expressed in nanovolt-seconds. seconds and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Rev. E | Page 17 of 28 AD5024/AD5044/AD5064 DAC-to-DAC Crosstalk The multiplying bandwidth, expressed in kilohertz, is the DAC-to-DAC crosstalk is the glitch impulse transferred to the frequency at which the output amplitude falls to 3 dB below output of one DAC due to a digital code change and subsequent the input. output change of another DAC. This includes both digital and Total Harmonic Distortion (THD) analog crosstalk. It is measured by loading one of the DACs Total harmonic distortion is the difference between an ideal with a full-scale code change (all 0s to all 1s or vice versa) with sine wave and its attenuated version using the DAC. The sine LDAC low and monitoring the output of another DAC. The wave is used as the reference for the DAC, and the THD is a energy of the glitch is expressed in nanovolt-seconds. measure of the harmonics present on the DAC output. It is measured in decibels. Multiplying Bandwidth The multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the DAC. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. Rev. E | Page 18 of 28 AD5024/AD5044/AD5064 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER OUTPUT AMPLIFIER The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/ The output buffer amplifier can generate rail-to-rail voltages 16-bit, serial input, voltage output DACs with an individual on its output, which gives an output range of 0 V to V . The DD reference pin. The AD5064-1 model (see the Ordering Guide) amplifier is capable of driving a load of 5 kΩ in parallel with is a 16-bit, serial input, voltage output DAC that is identical to 200 pF to GND. The slew rate is 1.5 V/μs with a ¼ to ¾ scale other AD5064 models but with a single reference pin for all settling time of 5.8 μs. DACs. The parts operate from supply voltages of 4.5 V to 5.5 V. SERIAL INTERFACE Data is written to the AD5024/AD5044/AD5064/AD5064-1 in a The AD5024/AD5044/AD5064/AD5064-1 have a 3-wire serial 32-bit word format via a 3-wire serial interface. The AD5024/ interface (SYNC, SCLK, and DIN) that is compatible with SPI, AD5044/AD5064/AD5064-1 incorporate a power-on reset circuit QSPI, and MICROWIRE interface standards as well as most that ensures that the DAC output powers up to a known output DSPs. See Figure 4 for a timing diagram of a typical write state. The devices also have a software power-down mode that sequence. The AD5064-1 model contains an SDO pin to allow reduces the typical current consumption to typically 400 nA. the user to daisy-chain multiple devices together (see the Daisy- Because the input coding to the DAC is straight binary, the ideal Chaining section). output voltage when using an external reference is given by SHIFT REGISTER D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN The AD5024/AD5044/AD5064/AD5064-1 shift register is 32 bits N ⎝ 2 ⎠ wide. The first four bits are don’t cares. The next four bits are the where: command bits, C3 to C0 (see Table 8), followed by the 4-bit D is the decimal equivalent of the binary code that is loaded to DAC address bits, A3 to A0 (see Table 9), and finally the bit the DAC register (0 to 65,535 for the 16-bit AD5064). data-word. The data-word comprises 12-bit, 14-bit, or 16-bit input N is the DAC resolution. code, followed by eight, six, or four don’t care bits for the AD5024, AD5044, and AD5064/AD5064-1, respectively (see Figure 47, DAC ARCHITECTURE Figure 48, and Figure 49). These data bits are transferred to the The DAC architecture of the AD5064 consists of two matched nd DAC register on the 32 falling edge of SCLK. Commands can be DAC sections. A simplified circuit diagram is shown in Figure 46. executed on individually selected DAC channels or on all DACs. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of Table 8. Command Definitions 15 matched resistors to either GND or the VREF buffer output. Command The remaining 12 bits of the data-word drive the S0 to S11 C3 C2 C1 C0 Description switches of a 12-bit voltage mode R-2R ladder network. 0 0 0 0 Write to Input Register n V OUT 0 0 0 1 Update DAC Register n 2R 2R 2R 2R 2R 2R 2R 0 0 1 0 Write to Input Register n, update all (software LDAC) E15 S0 S1 S11 E1 E2 0 0 1 1 Write to and update DAC Channel n V REF 0 1 0 0 Power down/power up DAC 0 1 0 1 Load clear code register 12-BIT R-2R LADDER FOUR MSBs DECODED INTO 0 1 1 0 Load LDAC register 15 EQUAL SEGMENTS 0 1 1 1 Reset (power-on reset) Figure 46. DAC Ladder Structure 1 1 0 0 0 Set up DCEN register (daisy-chain enable) 1 0 0 1 Reserved REFERENCE BUFFER 1 1 1 1 Reserved The AD5024/AD5044/AD5064/AD5064-1 operate with an exter- nal reference. For most models, each DAC has a dedicated voltage 1 Available in the AD5064-1 14-lead TSSOP package only. reference pin. The AD5064-1 model has a single voltage reference Table 9. Address Commands pin for all DACs. The reference input pin has an input range of Address (n) 2.2 V to VDD. This input voltage is then buffered internally to Selected DAC Channel A3 A2 A1 A0 provide a reference for the DAC core. 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 1 1 1 1 All DACs Rev. E | Page 19 of 28 06803-006 AD5024/AD5044/AD5064 DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX X X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 47. AD5024 Shift Register Content DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 48. AD5044 Shift Register Content DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 49. AD5064/AD5064-1 Shift Register Content SCLK SYNC DB31 DB0 DB31 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES ND ND SYNC HIGH BEFORE 32 FALLING EDGE ON THE 32 FALLING EDGE Figure 50. SYNC Interrupt Facility Rev. E | Page 20 of 28 06803-010 06803-009 06803-007 06803-008 AD5024/AD5044/AD5064 reserved for this DCEN function (see Table 8). The daisy-chain MODES OF OPERATION mode is enabled by setting Bit DB1 in the DCEN register. The There are three main modes of operation: standalone mode default setting is standalone mode, where DB1 = 0. where a single device is used, daisy-chain mode for a system that contains several DACs, and power-down mode when the Table 10 shows how the state of the bit corresponds to the mode supply current falls to 0.4 μA at 5 V. of operation of the device. Standalone Mode Table 10. DCEN (Daisy-Chain Enable) Register The write sequence begins by bringing the SYNC line low. Data DB1 DB0 Description from the DIN line is clocked into the 32-bit shift register on the 0 X Standalone mode (default) falling edge of SCLK. The serial clock frequency can be as high 1 X DCEN mode as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1 The SCLK is continuously applied to the shift register when nd compatible with high speed DSPs. On the 32 falling clock edge, SYNC is low. If more than 32 clock pulses are applied, the data the last data bit is clocked in and the programmed function is ripples out of the shift register and appears on the SDO line. LDAC executed, that is, an -dependent change in DAC register This data is clocked out on the rising edge of SCLK and is valid contents and/or a change in the mode of operation. At this on the falling edge. By connecting this line to the DIN input on stage, the SYNC line can be kept low or be brought high. In the next DAC in the chain, a daisy-chain interface is constructed. either case, it must be brought high for a minimum of 2 μs Each DAC in the system requires 32 clock pulses; therefore, the (single channel, see Table 4, t8 parameter) before the next write total number of clock cycles must equal 32N, where N is the SYNC sequence so that a falling edge of can initiate the next SYNC total number of devices that are updated. If is taken high SYNC write sequence. should be idled at rails between write at a clock that is not a multiple of 32, it is considered an invalid sequences for even lower power operation of the part. frame and the data is discarded. SYNC Interrupt When the serial transfer to all devices is complete, SYNC is In a normal write sequence, the SYNC line is kept low for at taken high. This prevents any further data from being clocked into the shift register. least 32 falling edges of SCLK, and the DAC is updated on the nd SYNC 32 falling edge. However, if is brought high before the In daisy-chain mode, the LDAC pin cannot be tied permanently nd 32 falling edge, this acts as an interrupt to the write sequence. LDAC LDAC low. The pin must be used in asynchronous update The write sequence is seen as invalid. Neither an update of the LDAC mode, as shown in Figure 5. The pin must be brought DAC register contents nor a change in the operating mode high after pulsing. This allows all DAC outputs to simulta- occurs (see Figure 50). neously update. Daisy-Chaining The serial clock can be continuous or a gated clock. A continuous For systems that contain several DACs the SDO pin can be SCLK source can be used only if SYNC can be held low for the used to daisy-chain several devices together and provide serial correct number of clock cycles. In gated clock mode, a burst readback. clock containing the exact number of clock cycles must be used, SYNC and must be taken high after the final clock to latch the data. The daisy-chain mode is enabled through a software executable daisy-chain enable (DCEN) command. Command 1000 is Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 1 0 0 0 X X X X X 1/0 X Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register Rev. E | Page 21 of 28 AD5024/AD5044/AD5064 POWER-ON RESET Any or all DACs (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, The AD5024/AD5044/AD5064/AD5064-1 contain a power-on DB2, DB1, DB0) to 1. See Table 13 for the contents of the shift reset circuit that initializes the registers to their default values register during power-down/power-up operation. and controls the output voltage during power-up. By connecting the POR pin low, the AD5024/AD5044/AD5064/AD5064-1 When both Bit DB9 and Bit D8 in the shift register are set to 0, output powers up to zero scale. Note that this is outside the the part works normally with its normal power consumption of linear region of the DAC; by connecting the POR pin high, the 4 mA at 5 V. However, for the three power-down modes, the AD5024/AD5044/AD5064/AD5064-1 output powers up to supply current falls to 0.4 μA at 5 V. Not only does the supply midscale. The output remains powered up at this level until a current fall, but the output stage is also internally switched from valid write sequence is made to the DAC. This is useful in the output of the amplifier to a resistor network of known values. applications where it is important to know the state of the This has the advantage that the output impedance of the part is output of the DAC while it is in the process of powering up. known while the part is in power-down mode. There are three There is also a software executable reset function that resets the different power-down options. The output is connected inter- DAC to the power-on reset code. Command 0111 is designated nally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is LDAC for this reset function (see Table 8). Any events on or left open-circuited (three-state). The output stage is illustrated in CLR during power-on reset are ignored. The power-on reset Figure 51. circuit is triggered when VDD passes 2.6 V approximately and takes 50 μs to complete. No writes to the AD5024/AD5044/ AMPLIFIER DAC V AD5064/AD5064-1 should take place during this time. For OUT applications which have a slow V ramp time (for example, DD more than 2 ms to 3ms), it is recommended that a software reset command is written when the power supplies have POWER-DOWN RESISTOR reached their final value. CIRCUITRY NETWORK POWER-DOWN MODES Figure 51. Output Stage During Power-Down The AD5024/AD5044/AD5064/AD5064-1 contain three The bias generator, output amplifier, resistor string, and other separate power-down modes. Command 0100 is designated for associated linear circuitry are shut down when the power-down the power-down function (see Table 8). These power-down mode is activated. However, the contents of the DAC register modes are software-programmable by setting two bits, Bit DB9 are unaffected when in power-down. The DAC register can be and Bit DB8, in the shift register. Table 12 shows how the state of updated while the device is in power-down mode. The time to the bits corresponds to the mode of operation of the device. exit power-down is typically 4.5 μs for V = 5 V (see Figure 30). DD Table 12. Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes: 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function MSB LSB DB31 DB19 DB7 to to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10 DB9 DB8 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 X DAC D DAC C DAC B DAC A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Power- Don’t Power-down/power-up channel cares don’t cares cares down mode cares selection—set bit to 1 to select Rev. E | Page 22 of 28 06803-011 AD5024/AD5044/AD5064 LDAC CLEAR CODE REGISTER Synchronous : After new data is read, the DAC registers nd are updated on the falling edge of the 32 SCLK pulse, provided The AD5024/AD5044/AD5064/AD5064-1 have a hardware LDAC is held low. CLR pin that is an asynchronous clear input. The CLR input is CLR falling edge sensitive. Bringing the line low clears the Asynchronous LDAC: The outputs are not updated at the same contents of the input register and the DAC registers to the data time that the input registers are written to. When LDAC is CLR contained in the user-configurable register and sets the pulsed low, the DAC registers are updated with the contents of analog outputs accordingly (see Table 14). This function can be the input registers. used in system calibration or reset to load zero scale, midscale, LDAC Software Function or full scale to all channels together. Note that zero scale and full Alternatively, the outputs of all DACs can be updated simulta- scale are outside the linear region of the DAC. These clear code neously or individually using the software LDAC function by values are user-programmable by setting two bits, Bit DB1 and writing to Input Register n and updating all DAC registers. Bit DB0, in the shift register (see Table 14). The default setting Command 0010 is reserved for this software LDAC function. clears the outputs to 0 V. Command 0101 is designated for Writing to the DAC using Command 0110 loads the 4-bit loading the clear code register (see Table 8). LDAC register (DB3 to DB0). The default for each channel Table 14. Clear Code Register LDAC is 0; that is, the pin works normally. Setting the bits to 1 DB1 (CR1) DB0 (CR0) Clears to Code updates the DAC channel regardless of the state of the hardware 0 0 0x0000 LDAC LDAC pin, so that it effectively sees the hardware pin as 0 1 0x8000 being tied low (see Table 15 for the LDAC register mode of 1 0 0xFFFF operation.) This flexibility is useful in applications where the 1 1 No operation user wants to simultaneously update select channels while the nd The part exits clear code mode on the 32 falling edge of the remainder of the channels are synchronously updating. CLR next write to the part. If hardware pin is activated during a LDAC Table 15. Overwrite Definition write sequence, the write is aborted. Load LDAC Register The CLR pulse activation time, which is the falling edge of CLR LDAC Bits to when the output starts to change, is typically 10.6 μs. See LDAC Pin LDAC Operation (DB3 to DB0) Table 16 for contents of the shift register while loading the clear 0 1 or 0 Determined by the LDAC pin. code register. 1 1 X DAC channels update, overrides LDAC FUNCTION the LDAC pin. DAC channels see LDAC as 0. Hardware LDAC Pin 1 X = don’t care. The outputs of all DACs can be updated simultaneously using The LDAC register gives the user extra flexibility and control LDAC LDAC the hardware pin, as shown in Figure 4. can be over the hardware LDAC pin (see Table 17). Setting the LDAC permanently low or pulsed. There are two methods of using the bits (DB0 to DB3) to 0 for a DAC channel means that this LDAC hardware pin, synchronously and asynchronously. LDAC pin. channel’s update is controlled by the hardware Table 16. 32-Bit Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X 1/0 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register (CR1 to CR0) Table 17. 32-Bit Shift Register Contents for LDAC Overwrite Function MSB LSB DB31 to DB19 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB4 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC D DAC C DAC B DAC A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Setting LDAC bits to 1 overrides LDAC pin cares don’t cares cares Rev. E | Page 23 of 28 AD5024/AD5044/AD5064 low effective series inductance (ESI), such as is typical of common POWER SUPPLY BYPASSING AND GROUNDING ceramic types of capacitors. This 0.1 μF capacitor provides a low When accuracy is important in a circuit, it is helpful to carefully impedance path to ground for high frequencies caused by consider the power supply and ground return layout on the board. transient currents due to internal logic switching. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have separate analog and digital The power supply line should have as large a trace as possible to sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a provide a low impedance path and reduce glitch effects on the system where other devices require an AGND-to-DGND supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid connection, the connection should be made at one point only. crossover of digital and analog signals, if possible. When traces This ground point should be as close as possible to the cross on opposite sides of the board, ensure that they run at right AD5024/AD5044/AD5064/AD5064-1. angles to each other to reduce feedthrough effects through the The power supply to the AD5024/AD5044/AD5064/AD5064-1 board. The best board layout technique is the microstrip tech- should be bypassed with 10 μF and 0.1 μF capacitors. The capaci- nique, where the component side of the board is dedicated to the tors should be as physically close as possible to the device, with ground plane only and the signal traces are placed on the solder the 0.1 μF capacitor ideally right up against the device. The 10 μF side. However, this is not always possible with a 2-layer board. capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and Rev. E | Page 24 of 28 AD5024/AD5044/AD5064 AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51 MICROPROCESSOR INTERFACING Interface AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP- Figure 54 shows a serial interface between the AD5024/AD5044/ BF53x Interface AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The Figure 52 shows a serial interface between the AD5024/AD5044/ setup for the interface is as follows: TxD of the 80C51/80L51 AD5064/AD5064-1 and the Blackfin® ADSP-BF53x microproces- drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and sor. The ADSP-BF53x processor family incorporates two dual- SYNC RxD drives the serial data line of the part. The signal is channel synchronous serial ports, SPORT1 and SPORT0, for again derived from a bit-programmable pin on the port. In this serial and multiprocessor communications. Using SPORT0 to case, Port Line P3.3 is used. When data is to be transmitted to the connect to the AD5024/AD5044/AD5064/AD5064-1, the setup AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The for the interface is as follows: DT0PRI drives the DIN pin of the 80C51/80L51 transmit data in 8-bit bytes only; thus, only eight AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the falling clock edges occur in the transmit cycle. To load data to SCLK of the parts. The SYNC pin is driven from TFS0. the DAC, P3.3 is left low after the first eight bits are transmitted, ADSP-BF53x* and a second write cycle is initiated to transmit the second byte of AD5024/ AD5044/ data. P3.3 is taken high following the completion of this cycle. AD5064/ AD5064-1* The 80C51/80L51 output the serial data in a format that has the TFS0 SYNC LSB first. The AD5024/AD5044/AD5064/AD5064-1 must DT0PRI DIN receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. TSCLK0 SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. 80C51/80L51* AD5024/ AD5044/ Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x AD5064/ Interface AD5064-1* P3.3 SYNC AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface TxD SCLK RxD DIN Figure 53 shows a serial interface between the AD5024/AD5044/ AD5064/AD5064-1 and the 68HC11/68L11 microcontroller. *ADDITIONAL PINS OMITTED FOR CLARITY. SCK of the 68HC11/68L11 drives the SCLK of the AD5024/ Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface AD5044/AD5064/AD5064-1, and the MOSI output drives the AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE serial data line of the DAC. Interface 68HC11/68L11* AD5024/ Figure 55 shows an interface between the AD5024/AD5044/ AD5044/ AD5064/AD5064-1 and any MICROWIRE-compatible device. AD5064/ AD5064-1* Serial data is shifted out on the falling edge of the serial clock and is PC7 SYNC clocked into the AD5024/AD5044/AD5064/AD5064-1 on the SCK SCLK rising edge of the SCLK. MOSI DIN MICROWIRE* AD5024/ *ADDITIONAL PINS OMITTED FOR CLARITY. AD5044/ AD5064/ Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface AD5064-1* SYNC CS SYNC The signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: SK DIN The 68HC11/68L11 is configured with its CPOL bit as 0, and its SO SCLK CPHA bit as 1. When data is being transmitted to the DAC, the *ADDITIONAL PINS OMITTED FOR CLARITY. SYNC line is taken low (PC7). When the 68HC11/68L11 is Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5024/AD5044/ AD5064, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. E | Page 25 of 28 06803-013 06803-012 06803-015 06803-014 AD5024/AD5044/AD5064 APPLICATIONS INFORMATION This is an output voltage range of ±5 V, with 0x0000 corre- USING A REFERENCE AS A POWER SUPPLY sponding to a −5 V output, and 0xFFFF corresponding to a Because the supply current required by the AD5024/AD5044/ +5 V output. AD5064/AD5064-1 is extremely low, an alternative option is to R2 = 10kΩ use a voltage reference to supply the required voltage to the parts +5V (see Figure 56). This is especially useful if the power supply is +5V R1 = 10kΩ quite noisy or if the system supply voltages are at some value other than 5 V (for example, 15 V). The voltage reference outputs AD8638/ 5V ±5V V V REF REFA AD8639 a steady supply voltage for the AD5024/AD5044/AD5064/ V V DD OUTA AD5064-1. If the low dropout REF195 is used, it must supply 0.1µF 10µF AD5024/ –5V 3 mA of current to the AD5024/AD5044/AD5064/AD5064-1, AD5044/ AD5064/ with no load on the output of the DAC. When the DAC output is AD5064-1 loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 3-WIRE 3 mA + (5 V/5 kΩ) = 4 mA SERIAL INTERFACE Figure 57. Bipolar Operation The load regulation of the REF195 is typically 2 ppm/mA, which results in a 3 ppm (15 μV) error for the 4 mA current USING THE AD5024/AD5044/AD5064/AD5064-1 drawn from it. This corresponds to a 0.196 LSB error. WITH A GALVANICALLY ISOLATED INTERFACE 15V In process control applications in industrial environments, it 5V is often necessary to use a galvanically isolated interface to REF195 protect and isolate the controlling circuitry from any hazardous common-mode voltages that can occur in the area where the V DD SYNC DAC is functioning. iCoupler® provides isolation in excess of AD5024/ 3-WIRE V = 0V TO 5V OUT SERIAL SCLK AD5044/ 2.5 kV. The AD5024/AD5044/AD5064/AD5064-1 use a 3-wire INTERFACE AD5064/ DIN serial logic interface, so the ADuM1300 three-channel digital AD5064-1 isolator provides the required isolation (see Figure 58). The power supply to the part also needs to be isolated, which is done Figure 56. REF195 as Power Supply to the AD5024/AD5044/AD5064/AD5064-1 by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5024/ BIPOLAR OPERATION AD5044/AD5064/AD5064-1. The AD5024/AD5044/AD5064/AD5064-1 have been designed 5V for single-supply operation, but a bipolar output range is also REGULATOR POWER 10µF 0.1µF possible using the circuit shown in Figure 57. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD8638 or an AD8639 as the output amplifier. V DD Assuming V = V , the output voltage for any input code can SCLK V V SCLK DD REF IA OA AD5024/ be calculated as follows: AD5044/ ADuM1300 AD5064/ AD5064-1 ⎡ D R1+ R2 R2 ⎤ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞ SDI V V x V SYNC IB OB OUT V = V ×⎜ ⎟× − V × ⎜ ⎟ ⎜ ⎟ ⎢ DD DD ⎥ OUT 65,536 R1 R1 ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦ where D represents the input code in decimal (0 to 65,535). DATA V V OC DIN IC With V = 5 V, R1 = R2 = 10 kΩ, DD GND 10× D ⎛ ⎞ V =⎜ ⎟− 5 V OUT 65,536 ⎝ ⎠ Figure 58. AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface Rev. E | Page 26 of 28 06803-016 06803-018 06803-017 AD5024/AD5044/AD5064 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0° 0.65 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. E | Page 27 of 28 061908-A AD5024/AD5044/AD5064 ORDERING GUIDE 1 Model Temperature Range Accuracy Resolution Package Description Package Option AD5064ARUZ-1 −40°C to +125°C ±4 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064ARUZ-1REEL7 −40°C to +125°C ±4 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ-1 −40°C to +125°C ±1 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ-1REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ −40°C to +125°C ±1 LSB INL 16 Bits 16-Lead TSSOP RU-16 AD5064BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 16-Lead TSSOP RU-16 AD5044BRUZ −40°C to +125°C ±1 LSB INL 14 Bits 16-Lead TSSOP RU-16 AD5044BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 14 Bits 16-Lead TSSOP RU-16 AD5024BRUZ −40°C to +125°C ±0.5 LSB INL 12 Bits 16-Lead TSSOP RU-16 AD5024BRUZ-REEL7 −40°C to +125°C ±0.5 LSB INL 12 Bits 16-Lead TSSOP RU-16 EVAL-AD5064-1EBZ 14-Lead TSSOP Evaluation Board EVAL-AD5064EBZ 16-Lead TSSOP Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06803-0-5/11(E) Rev. E | Page 28 of 28