14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 70.6 dBFS at 185 MHz A and 250 MSPS IN SFDR = 85 dBc at 185 MHz A and 250 MSPS IN VIN+A −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A and PIPELINE IN D0± 14-BIT 14 . 250 MSPS VIN–A ADC . . Total power consumption: 785 mW at 250 MSPS PARALLEL VCM AD9643 . DDR LVDS . 1.8 V supply voltages VIN+B PIPELINE AND D13± 14-BIT 14 LVDS (ANSI-644 levels) outputs DRIVERS ADC VIN–B Integer 1-to-8 input clock divider (625 MHz maximum input) DCO± Sample rates of up to 250 MSPS REFERENCE IF sampling frequencies of up to 400 MHz OR± Internal ADC voltage reference 1TO 8 SERIAL PORT Flexible analog input range CLOCK OEB DIVIDER 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) PDWN ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk SCLK SDIO CSB CLK+ CLK– SYNC NOTES Serial port control 1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A Energy saving power-down modes AND CHANNEL B LVDS OUTPUT DATA. User-configurable, built-in self-test (BIST) capability Figure 1. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications Programming for setup and control are accomplished using a GENERAL DESCRIPTION 3-wire SPI-compatible serial interface. The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) The AD9643 is available in a 64-lead LFCSP and is specified over with sampling speeds of up to 250 MSPS. The AD9643 is designed the industrial temperature range of −40°C to +85°C. This to support communications applications, where low cost, small product is protected by a U.S. patent. size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined PRODUCT HIGHLIGHTS architecture with integrated output error correction logic. Each 1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. ADC features wide bandwidth inputs supporting a variety of 2. Operation from a single 1.8 V supply and a separate digital user-selectable input ranges. An integrated voltage reference output driver supply accommodating LVDS outputs. eases design considerations. A duty cycle stabilizer is provided 3. Proprietary differential input maintains excellent SNR to compensate for variations in the ADC clock duty cycle, performance for input frequencies of up to 400 MHz. allowing the converters to maintain excellent performance. 4. SYNC input allows synchronization of multiple devices. The ADC output data is routed directly to the two external 5. 3-pin, 1.8 V SPI port for register programming and register 14-bit LVDS output ports and formatted as either interleaved or readback. channel multiplexed. 6. Pin compatibility with the AD9613, allowing a simple migration down from 14 bits to 12 bits. This part is also pin Flexible power-down options allow significant power savings, compatible with the AD6649 and the AD6643. when desired. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09636-001 AD9643 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Analog Input Considerations ................................................... 23  Applications....................................................................................... 1  Voltage Reference ....................................................................... 25  Functional Block Diagram .............................................................. 1  Clock Input Considerations...................................................... 25  General Description ......................................................................... 1  Power Dissipation and Standby Mode .................................... 26  Product Highlights ........................................................................... 1  Digital Outputs ........................................................................... 27  Revision History ............................................................................... 2  ADC Overrange (OR)................................................................ 27  Specifications..................................................................................... 3  Channel/Chip Synchronization.................................................... 28  ADC DC Specifications............................................................... 3  Serial Port Interface (SPI).............................................................. 29  ADC AC Specifications ............................................................... 4  Configuration Using the SPI..................................................... 29  Digital Specifications ................................................................... 6  Hardware Interface..................................................................... 29  Switching Specifications .............................................................. 8  SPI Accessible Features.............................................................. 30  Timing Specifications .................................................................. 9  Memory Map .................................................................................. 31  Absolute Maximum Ratings.......................................................... 11  Reading the Memory Map Register Table............................... 31  Thermal Characteristics ............................................................ 11  Memory Map Register Table..................................................... 32  ESD Caution................................................................................ 11  Memory Map Register Description ......................................... 34  Pin Configurations and Function Descriptions ......................... 12  Applications Information .............................................................. 35  Typical Performance Characteristics ........................................... 16  Design Guidelines ...................................................................... 35  Equivalent Circuits ......................................................................... 22  Outline Dimensions....................................................................... 36  Theory of Operation ...................................................................... 23  Ordering Guide .......................................................................... 36  ADC Architecture ...................................................................... 23  REVISION HISTORY 9/11—Rev. A to Rev. B Changes to Table 1............................................................................ 3 Changes to Table 2, .......................................................................... 4 Changes to Table 3............................................................................ 6 Changes to Table 4............................................................................ 8 Changes to Table 8.......................................................................... 12 Changes to Table 9.......................................................................... 14 Changes to Typical Performance Characterisitics Section........ 16 Added ADC Overrange (OR) Section ......................................... 27 Changes to Channel/Chip Synchronization Section ................. 28 Changes to Reading the Memory Map Register Table Section.............................................................................................. 31 Changes to Table 14........................................................................ 32 Changes to Memory Map Resgister Description Section ......... 34 5/11—Rev. 0 to Rev. A Changes to Table 2, Worst Other (Harmonic or Spur) Max Values......................................................................................... 4 4/11—Revision 0: Initial Version Rev. B | Page 2 of 36 Data Sheet AD9643 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, unless otherwise noted. Table 1. AD9643-170 AD9643-210 AD9643-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±10 ±10 ±10 mV Gain Error Full +2/−6 +3/−5 ±4 %FSR Differential Nonlinearity (DNL) Full ±0.75 ±0.75 ±0.75 LSB 25°C ±0.25 ±0.25 ±0.25 LSB 1 Integral Nonlinearity (INL) Full ±1.8 ±2 ±3.5 LSB 25°C ±1.5 ±1.5 ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full ±13 ±13 ±13 mV Gain Error Full ±2.5/ −2/ −2.5/ %FSR +3.5 +3.5 +3.5 TEMPERATURE DRIFT Offset Error Full ±5 ±5 ±5 ppm/°C Gain Error Full ±70 ±80 ±100 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.33 1.33 1.33 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p 2 Input Capacitance Full 2.5 2.5 2.5 pF 3 Input Resistance Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current 1 IAVDD Full 196 250 217 265 256 275 mA 1 I Full 145 160 160 185 180 210 mA DRVDD POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 614 680 785 mW 4 Standby Power Full 90 90 90 mW Power-Down Power Full 10 10 10 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. B | Page 3 of 36 AD9643 Data Sheet ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. AD9643-170 AD9643-210 AD9643-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 30 MHz 25°C 72.2 72.2 72.0 dBFS fIN = 90 MHz 25°C 72.0 72.0 71.7 dBFS Full 70.4 69.9 dBFS 25°C 71.8 71.6 71.4 dBFS fIN = 140 MHz 25°C 71.4 71.2 70.9 dBFS f = 185 MHz IN Full 68.8 dBFS f = 220 MHz 25°C 71.1 70.9 70.5 dBFS IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 71.2 71.2 71.0 dBFS fIN = 90 MHz 25°C 71.0 71.0 70.7 dBFS Full 70.4 69.9 dBFS fIN = 140 MHz 25°C 70.8 70.6 70.4 dBFS 25°C 70.4 70.2 69.9 dBFS fIN = 185 MHz Full 67.5 dBFS f = 220 MHz 25°C 70.1 69.9 69.5 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 11.5 11.5 11.5 Bits fIN = 90 MHz 25°C 11.5 11.5 11.5 Bits fIN = 140 MHz 25°C 11.5 11.5 11.4 Bits 25°C 11.4 11.4 11.3 Bits fIN = 185 MHz fIN = 220 MHz 25°C 11.4 11.3 11.3 Bits WORST SECOND OR THIRD HARMONIC f = 30 MHz 25°C −95 −90 −90 dBc IN fIN = 90 MHz 25°C −92 −90 −88 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −88 −88 −86 dBc fIN = 185 MHz 25°C −83 −87 −85 dBc Full −80 dBc fIN = 220 MHz 25°C −83 −85 −85 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 30 MHz 25°C 95 90 90 dBc IN f = 90 MHz 25°C 92 90 88 dBc IN Full 78 80 dBc fIN = 140 MHz 25°C 88 88 86 dBc fIN = 185 MHz 25°C 83 87 85 dBc Full 80 dBc fIN = 220 MHz 25°C 83 85 85 dBc WORST OTHER (HARMONIC OR SPUR) f = 30 MHz 25°C −98 −95 −94 dBc IN f = 90 MHz 25°C −97 −95 −93 dBc IN Full −78 −80 dBc f = 140 MHz 25°C −97 −93 −92 dBc IN fIN = 185 MHz 25°C −96 −92 −92 dBc Full −80 dBc fIN = 220 MHz 25°C −94 −90 −88 dBc TWO-TONE SFDR f = 184.12 MHz (−7 dBFS ), 187.12 25°C 88 88 88 dBc IN MHz (−7 dBFS ) Rev. B | Page 4 of 36 Data Sheet AD9643 AD9643-170 AD9643-210 AD9643-250 1 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit 2 CROSSTALK Full 95 95 95 dB 3 FULL POWER BANDWIDTH 25°C 400 400 400 MHz 4 NOISE BANDWIDTH 25°C 1000 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. 4 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally. Rev. B | Page 5 of 36 AD9643 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +22 μA Low Level Input Current Full −22 −10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −5 +5 μA Low Level Input Current Full −5 +5 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −5 +5 μA Low Level Input Current Full −80 −45 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 1 LOGIC INPUTS (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 2 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 μA Low Level Input Current Full −5 +5 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF Rev. B | Page 6 of 36 Data Sheet AD9643 Parameter Temp Min Typ Max Unit DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), Full 1.15 1.22 1.35 V ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Full 1.15 1.22 1.35 V Reduced Swing Mode 1 Pull-up. 2 Pull-down. Rev. B | Page 7 of 36 AD9643 Data Sheet SWITCHING SPECIFICATIONS Table 4. AD9643-170 AD9643-210 AD9643-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 40 170 40 210 40 250 MSPS CLK Period—Divide-by-1 Mode (t) Full 5.8 4.8 4 ns CLK CLK Pulse Width High (t) CH Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Full 0.8 0.8 0.8 ns Divide-by-8 Mode Aperture Delay (t) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (t) Full 4.8 4.8 4.8 ns PD DCO Propagation Delay (tDCO) Full 5.5 5.5 5.5 ns DCO-to-Data Skew (tSKEW) Full 0.3 0.7 1.1 0.3 0.7 1.1 0.3 0.7 1.1 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (t) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power-Down) Full 250 250 250 μs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider. Rev. B | Page 8 of 36 Data Sheet AD9643 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time 0.3 ns SSYNC tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns DS tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns t Hold time between CSB and SCLK 2 ns H t Minimum period that SCLK should be in a logic high state 10 ns HIGH t Minimum period that SCLK should be in a logic low state 10 ns LOW tEN_SDIO Time required for the SDIO pin to switch from an input to an output 10 ns relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an input 10 ns relative to the SCLK rising edge Rev. B | Page 9 of 36 AD9643 Data Sheet Timing Diagrams t A N – 1 N + 4 N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCO– DCO+ t SKEW t PD PARALLEL INTERLEAVED D0± CH A CH B CH A CH B CH A CH B CH A CH B CH A (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . CHANNEL A AND . CHANNEL B . D13± CH A CH B CH A CH B CH A CH B CH A CH B CH A (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 CHANNEL MULTIPLEXED D0±/D1± CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 (EVEN/ODD) MODE (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . . CHANNEL A . D12±/D13± CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 CHANNEL MULTIPLEXED D0±/D1± CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 (EVEN/ODD) MODE (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 . . CHANNEL B . D12±/D13± CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH B12 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 Figure 2. LVDS Modes for Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Timing Inputs Rev. B | Page 10 of 36 09636-003 09636-002 Data Sheet AD9643 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating The exposed paddle must be soldered to the ground plane for Electrical AVDD to AGND −0.3 V to +2.0 V the LFCSP package. This increases the reliability of the solder DRVDD to AGND −0.3 V to +2.0 V joints, maximizing the thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Airflow SYNC to AGND −0.3 V to AVDD + 0.2 V Velocity VCM to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 Package Type (m/sec) θ θ θ Unit JA JC JB CSB to AGND −0.3 V to DRVDD + 0.3 V 64-Lead LFCSP 0 26.8 1.14 10.4 °C/W SCLK to AGND −0.3 V to DRVDD + 0.3 V 9 mm × 9 mm 1.0 21.6 °C/W SDIO to AGND −0.3 V to DRVDD + 0.3 V (CP-64-4) 2.0 20.2 °C/W OEB to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. PDWN to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). D0−/D0+ Through D13−/D13+ −0.3 V to DRVDD + 0.3 V to AGND DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V Typical θJA is specified for a 4-layer PCB with a solid ground Environmental plane. As shown in Table 7, airflow increases heat dissipation, Operating Temperature Range −40°C to +85°C which reduces θ . In addition, metal in direct contact with the JA (Ambient) package leads from metal traces, through holes, ground, and Maximum Junction Temperature 150°C power planes, reduces the θ . JA Under Bias Storage Temperature Range −65°C to +125°C (Ambient) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 11 of 36 AD9643 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR CLK+ 1 48 PDWN CLK– 2 47 OEB SYNC 3 46 CSB DNC 4 45 SCLK 5 44 SDIO DNC 43 OR+ DNC 6 AD9643 DNC 7 42 OR– PARALLEL LVDS (LSB) D0– 8 41 D13+ (MSB) TOP VIEW (LSB) D0+ 9 40 D13– (MSB) (Not to Scale) DRVDD 10 39 D12+ D1– 11 38 D12– D1+ 12 37 DRVDD D2– 13 36 D11+ D2+ 14 35 D11– D3– 15 34 D10+ D3+ 16 33 D10– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 8. Pin Function Descriptions for Interleaved Parallel LVDS Mode Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4, 5, 6, 7, 55, 56, 58 DNC Do Not Connect. Do not connect to this pin. 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of the Exposed Paddle package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 9 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 8 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 18 D4+ Output Channel A/Channel B LVDS Output Data 4—True. Rev. B | Page 12 of 36 D4– 17 64 AVDD D4+ 18 63 AVDD DRVDD 19 62 VIN+B D5– 20 61 VIN–B D5+ 21 60 AVDD D6– 22 59 AVDD D6+ 23 58 DNC DCO– 57 VCM 24 56 DNC DCO+ 25 D7– 26 55 DNC D7+ 27 54 AVDD DRVDD 28 53 AVDD D8– 29 52 VIN–A D8+ 30 51 VIN+A D9– 31 50 AVDD D9+ 32 49 AVDD 09636-004 Data Sheet AD9643 Pin No. Mnemonic Type Description 17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 21 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 23 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 27 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 30 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 29 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 32 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 34 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 36 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 39 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True. 40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data I/O. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power- Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev. B | Page 13 of 36 AD9643 Data Sheet PIN 1 INDICATOR CLK+ 1 48 PDWN CLK– 2 47 OEB SYNC 3 46 CSB DNC 4 45 SCLK DNC 5 44 SDIO AD9643 DNC 6 43 OR+ CHANNEL DNC 7 42 OR– MULTIPLEXED (LSB) B D0–/D1– 8 41 A D12+/D13+ (MSB) (EVEN/ODD) (LSB) B D0+/D1+ 9 40 A D12–/D13– (MSB) LVDS DRVDD 10 39 A D10+/D11+ TOP VIEW B D2–/D3– 11 38 A D10–/D11– (Not to Scale) B D2+/D3+ 37 DRVDD 12 A D8+/D9+ B D4–/D5– 13 36 B D4+/D5+ 14 35 A D8–/D9– B D6–/D7– 15 34 A D6+/D7+ B D6+/D7+ 16 33 A D6–/D7– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 5. LFCSP Channel Multiplexed (Even/Odd) LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions for Channel Multiplexed (Even/Odd) LVDS Mode Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4, 5 DNC Do Not Connect. Do not connect to this pin. 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of Exposed Paddle the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 DNC Do Not Connect. Do not connect to this pin. 56 DNC Do Not Connect. Do not connect to this pin. 58 DNC Do Not Connect. Do not connect to this pin. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. B | Page 14 of 36 B D8–/D9– 17 64 AVDD B D8+/D9+ 18 63 AVDD DRVDD 19 62 VIN+B B D10–/D11– 20 61 VIN–B B D10+/D11+ 21 60 AVDD 59 AVDD (MSB) B D12–/D13– 22 (MSB) B D12+/D13+ 23 58 DNC DCO– 24 57 VCM DCO+ 25 56 DNC (LSB) A D0–/D1– 26 55 DNC (LSB) A D0+/D1+ 27 54 AVDD DRVDD 28 53 AVDD A D2–/D3– 29 52 VIN–A A D2+/D3+ 30 51 VIN+A A D4–/D5– 31 50 AVDD A D4+/D5+ 32 49 AVDD 09636-005 Data Sheet AD9643 Pin No. Mnemonic Type Description Digital Outputs 7 ORB+ Output Channel B LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 6 ORB− Output Channel B LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. 8 B D0−/D1− (LSB) Output Channel B LVDS Output Data 0/Data 1—Complement. 9 B D0+/D1+ (LSB) Output Channel B LVDS Output Data 0/Data 1—True. 11 B D2−/D3− Output Channel B LVDS Output Data 2/Data 3—Complement. 12 B D2+/D3+ Output Channel B LVDS Output Data 2/Data 3—True. 13 B D4−/D5− Output Channel B LVDS Output Data 4/Data 5—Complement. 14 B D4+/D5+ Output Channel B LVDS Output Data 4/Data 5—True. 15 B D6−/D7− Output Channel B LVDS Output Data 6/Data 7—Complement. 16 B D6+/D7+ Output Channel B LVDS Output Data 6/Data 7—True. 17 B D8−/D9− Output Channel B LVDS Output Data 8/Data 9—Complement. 18 B D8+/D9+ Output Channel B LVDS Output Data 8/Data 9—True. 20 B D10−/D11− Output Channel B LVDS Output Data 10/Data 11—Complement. 21 B D10+/D11+ Output Channel B LVDS Output Data 10/Data 11—True. 22 B D12−/D13− (MSB) Output Channel B LVDS Output Data 12/Data 13—Complement. 23 B D12+/D13+ (MSB) Output Channel B LVDS Output Data 12/Data 13—True. 26 A D0−/D1− (LSB) Output Channel A LVDS Output Data 0/Data 1—Complement. 27 A D0+/D1+ (LSB) Output Channel A LVDS Output Data 0/Data 1—True. 29 A D2−/D3− Output Channel A LVDS Output Data 2/Data 3—Complement. 30 A D2+/D3+ Output Channel A LVDS Output Data 2/Data 3—True. 31 A D4−/D5− Output Channel A LVDS Output Data 4/Data 5—Complement. 32 A D4+/D5+ Output Channel A LVDS Output Data 4/Data 5—True. 33 A D6−/D7− Output Channel A LVDS Output Data 6/Data 7—Complement. 34 A D6+/D7+ Output Channel A LVDS Output Data 6/Data 7—True. 35 A D8−/D9− Output Channel A LVDS Output Data 8/Data 9—Complement. 36 A D8+/D9+ Output Channel A LVDS Output Data 8/Data 9—True. 38 A D10−/D11− Output Channel A LVDS Output Data 10/Data 11—Complement. 39 A D10+/D11+ Output Channel A LVDS Output Data 10/Data 11—True. 40 A D12−/D13− (MSB) Output Channel A LVDS Output Data 12/Data 13—Complement. 41 A D12+/D13+ (MSB) Output Channel A LVDS Output Data 12/Data 13—True. 43 ORA+ Output Channel A LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 42 ORA− Output Channel A LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output— Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data Input/Output. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power- Down 47 OEB Input Output Enable Bar Input (Active Low). 48 PDWN Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power- down or standby (see Table 14). Rev. B | Page 15 of 36 AD9643 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted. 0 120 170MSPS SFDR (dBFS) 90.1MHz @ –1dBFS –20 SNR = 70.8dB (71.8dBFS) 100 SFDR = 88dBc –40 80 SNR (dBFS) –60 60 SFDR (dBc) –80 SECOND HARMONIC THIRD HARMONIC 40 –100 SNR (dBc) 20 –120 –140 0 0 10 203040 50 60 70 80 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 9. AD9643-170 Single-Tone SNR/SFDR vs. Input Amplitude (A ) with Figure 6. AD9643-170 Single-Tone FFT with fIN = 90.1 MHz IN f = 90.1 MHz IN 0 100 170MSPS SFDR (dBc) 185.1MHz @ –1dBFS 95 –20 SNR = 69.8dB (70.8dBFS) SFDR = 85dBc 90 –40 85 –60 THIRD HARMONIC 80 SECOND HARMONIC –80 75 SNR (dBFS) –100 70 –120 65 60 –140 0 10 20 30 405060 70 80 60 90 120 150 180 210 240 270 300 330 360 390 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. AD9643-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN) Figure 7. AD9643-170 Single-Tone FFT with fIN = 185.1 MHz 0 0 170MSPS 305.1MHz @ –1dBFS –20 SNR = 68.3dB (69.3dBFS) –20 SFDR = 79dBc SFDR (dBc) –40 –40 SECOND HARMONIC IMD3 (dBc) –60 THIRD HARMONIC –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 02 100304050607080 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 8. AD9643-170 Single-Tone FFT with f = 305.1 MHz IN Figure 11. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 170 MSPS Rev. B | Page 16 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09636-015 09636-014 09636-013 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09636-017 09636-016 09636-018 Data Sheet AD9643 100 0 95 –20 SFDR (dBc) –40 90 IMD3 (dBc) 85 –60 SFDR, CHANNEL B SNR, CHANNEL B –80 80 SFDR, CHANNEL A SNR, CHANNEL A SFDR (dBFS) 75 –100 IMD3 (dBFS) –120 70 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 40 50 60 70 80 90 100 110 120 130 140 150 160 170 INPUT AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 12. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) with Figure 15. AD9643-170 Single-Tone SNR/SFDR vs. Sample Rate (f ) IN S f = 184.12, f = 187.12 MHz, f = 170 MSPS with f = 90.1 MHz IN1 IN2 S IN 0 6000 170MSPS 1.34LSB rms 89.12MHz @ –7dBFS 16,379 TOTAL HITS –20 92.12MHz @ –7dBFS 5000 SFDR = 89dBc (96dBFS) –40 4000 –60 3000 –80 2000 –100 1000 –120 –140 0 02 100304050607080 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 FREQUENCY (MHz) OUTPUT CODE Figure 13. AD9643-170 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz, Figure 16. AD9643-170 Grounded Input Histogram fS = 170 MSPS 0 0 170MSPS 210MSPS 184.12MHz @ –7dBFS 90.1MHz @ –1dBFS –20 –20 187.12MHz @ –7dBFS SNR = 70.6dB (71.6dBFS) SFDR = 84dBc (91dBFS) SFDR = 88dBc –40 –40 –60 –60 SECOND HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 02 100304050607080 02 100304050607080 90 100 FREQUENCY (MHz) FREQUENCY (Hz) Figure 14. AD9643-170 Two-Tone FFT with f = 184.12, f = 187.12 MHz, Figure 17. AD9643-210 Single-Tone FFT with f = 90.1 MHz IN1 IN2 IN f = 170 MSPS S Rev. B | Page 17 of 36 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09636-021 09636-020 09636-019 AMPLITUDE (dBFS) NUMBER OF HITS SNR/SFDR (dBc AND dBFS) 09636-024 09636-023 09636-022 AD9643 Data Sheet 0 100 210MSPS 185.1MHz @ –1dBFS 95 –20 SNR = 70.3dB (71.3dBFS) SFDR (dBc) SFDR = 86dBc 90 –40 85 –60 SECOND HARMONIC 80 THIRD HARMONIC –80 75 SNR (dBFS) –100 70 –120 65 –140 60 0 10 20 30 40 50 607080 60 90 120 150 180 210 240 270 300 330 360 390 90 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD9643-210 Single-Tone FFT with fIN = 185.1 MHz Figure 21. AD9643-210 Single-Tone SNR/SFDR vs. Input Frequency (f ) IN 0 0 210MSPS 305.1MHz @ –1dBFS –20 SNR = 67.3dB (68.3dBFS) –20 SFDR = 75dBc SFDR (dBc) –40 –40 THIRD HARMONIC –60 IMD3 (dBc) SECOND HARMONIC –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –120 –140 02 100304050607080 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 90 100 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 22. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 19. AD9643-210 Single-Tone FFT with fIN = 305.1 MHz IN with f = 89.12, f = 92.12 MHz, f = 210 MSPS IN1 IN2 S 120 0 SFDR (dBFS) 100 –20 SFDR (dBc) 80 –40 SNR (dBFS) IMD3 (dBc) 60 –60 SFDR (dBc) 40 –80 SFDR (dBFS) SNR (dBc) 20 –100 IMD3 (dBFS) –120 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 20. AD9643-210 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) Figure 23. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN = 90.1 MHz with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 210 MSPS Rev. B | Page 18 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09636-027 09636-026 09636-025 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09636-028 09636-030 09636-029 Data Sheet AD9643 0 5000 210MSPS 1.44LSB rms 4500 89.12MHz @ –7dBFS 16,378 TOTAL HITS –20 92.12MHz @ –7dBFS 4000 SFDR = 88dBc (95dBFS) –40 3500 3000 –60 2500 –80 2000 1500 –100 1000 –120 500 –140 0 02 100304050607080 90 100 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 FREQUENCY (MHz) OUTPUT CODE Figure 24. AD9643-210 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz, Figure 27. AD9643-210 Grounded Input Histogram fS = 210 MSPS 0 0 210MSPS 250MSPS 184.12MHz @ –7dBFS 90.1MHz @ –1dBFS –20 –20 187.12MHz @ –7dBFS SNR = 70.6dB (71.6dBFS) SFDR = 88dBc (95dBFS) SFDR = 88dBc –40 –40 –60 –60 THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 –140 –140 02 100304050607080 90 100 0 10 203040 5060 7080 90 100110120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. AD9643-210 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz, Figure 28. AD9643-250 Single-Tone FFT with f = 90.1 MHz IN fS = 210 MSPS 100 0 250MSPS 185.1MHz @ –1dBFS –20 SNR = 70.6dB (71.6dBFS) 95 SFDR = 85dBc –40 90 –60 THIRD HARMONIC 85 SECOND HARMONIC –80 SNR, CHANNEL B SFDR, CHANNEL B 80 SNR, CHANNEL A –100 SFDR, CHANNEL A 75 –120 70 –140 40 60 80 100 120 140 160 180 200 0 10 20 30 40 5060 70 8090 100110 120 SAMPLE RATE (MSPS) FREQUENCY (MHz) Figure 26. AD9643-210 Single-Tone SNR/SFDR vs. Sample Rate (fS) Figure 29. AD9643-250 Single-Tone FFT with fIN = 185.1 MHz with fIN = 90.1 MHz Rev. B | Page 19 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09636-033 09636-032 09636-031 AMPLITUDE (dBFS) AMPLITUDE (dBFS) NUMBER OF HITS 09636-036 09636-035 09636-034 AD9643 Data Sheet 0 0 250MSPS 305.1MHz @ –1dBFS –20 SNR = 68.6dB (71.6dBFS) –20 SFDR = 83dBc SFDR (dBc) –40 –40 –60 IMD3 (dBc) SECOND HARMONIC –60 THIRD HARMONIC –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –120 0 10 20 30 40 5060 70 8090 100110 120 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 30. AD9643-250 Single-Tone FFT with fIN = 305.1 MHz Figure 33. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN with f = 89.12, f = 92.12 MHz, f = 250 MSPS IN1 IN2 S 120 0 SFDR (dBFS) 100 –20 SFDR (dBc) 80 –40 SNR (dBFS) IMD3 (dBc) 60 –60 SFDR (dBc) 40 –80 SFDR (dBFS) SNR (dBc) 20 –100 IMD3 (dBFS) 0 –120 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –7.0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 31. AD9643-250 Single-Tone SNR/SFDR vs. Input Amplitude (A ) Figure 34. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN IN with f = 185.1 MHz with f = 184.12, f = 187.12 MHz, f = 250 MSPS IN IN1 IN2 S 100 0 250MSPS 89.12MHz @ –7dBFS 95 –20 92.12MHz @ –7dBFS SFDR = 87dBc (94dBFS) SFDR (dBc) 90 –40 85 –60 80 –80 75 SNR (dBFS) –100 70 –120 65 60 –140 60 80 100 120 140 160 180 200 220 240 260 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 35. AD9643-250 Two-Tone FFT with f = 89.12, f = 92.12 MHz, Figure 32. AD9643-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) IN1 IN2 f = 250 MSPS S Rev. B | Page 20 of 36 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 09636-039 09636-038 09636-037 SFDR/IMD3 (dBc AND dBFS) SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) 09636-042 09636-041 09636-040 Data Sheet AD9643 0 5000 250MSPS 1.33LSB rms 4500 184.12MHz @ –7dBFS 16,378 TOTAL HITS –20 187.12MHz @ –7dBFS 4000 SFDR = 87dBc (94dBFS) –40 3500 3000 –60 2500 –80 2000 1500 –100 1000 –120 500 –140 0 0 10 20 30 40 50 60 70 80 90 100 110 120 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 FREQUENCY (MHz) OUTPUT CODE Figure 36. AD9643-250 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz, Figure 38. AD9643-250 Grounded Input Histogram fS = 250 MSPS 100 95 90 85 SNR, CHANNEL B SFDR, CHANNEL B 80 SNR, CHANNEL A SFDR, CHANNEL A 75 70 40 60 80 100 120 140 160 180 200 220 240 SAMPLE RATE (MSPS) Figure 37. AD9643-250 Single-Tone SNR/SFDR vs. Sample Rate (f ) S with f = 90.1 MHz IN Rev. B | Page 21 of 36 AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) 09636-044 09636-043 NUMBER OF HITS 09636-045 AD9643 Data Sheet EQUIVALENT CIRCUITS AVDD 350Ω SCLK, PDWN, OR OEB 26kΩ VIN Figure 39. Equivalent Analog Input Circuit Figure 43. Equivalent SCLK, PDWN, or OEB Input Circuit AVDD AVDD AVDD AVDD 26kΩ 0.9V CSB 350Ω OR 15kΩ 15kΩ OEB CLK+ CLK– Figure 40. Equivalent Clock lnput Circuit Figure 44. Equivalent CSB Input Circuit DRVDD AVDD AVDD V+ V– DATAOUT– DATAOUT+ SYNC 0.9V V– V+ 16kΩ 0.9V Figure 41. Equivalent LVDS Output Circuit Figure 45. Equivalent SYNC Input Circuit DRVDD 350Ω SDIO 26kΩ Figure 42. Equivalent SDIO Circuit Rev. B | Page 22 of 36 09636-006 09636-063 09636-009 09636-007 09636-012 09636-011 09636-010 Data Sheet AD9643 THEORY OF OPERATION A small resistor in series with each input can help reduce the The AD9643 has two analog input channels and two digital peak transient current required from the output stage of the output channels. The intermediate frequency (IF) signal passes driving source. A shunt capacitor can be placed across the through several stages before appearing at the output port(s). inputs to provide dynamic charging currents. This passive The dual ADC design can be used for diversity reception of signals, network creates a low-pass filter at the ADC input; therefore, where the ADCs operate identically on the same carrier but from the precise values are dependent on the application. two separate antennae. The ADCs can also be operated with In intermediate frequency (IF) undersampling applications, the independent analog inputs. The user can sample frequencies shunt capacitors should be reduced. In combination with the from dc to 300 MHz using appropriate low-pass or band-pass driving source impedance, the shunt capacitors limit the input filtering at the ADC inputs with little loss in ADC performance. bandwidth. Refer to the AN-742 Application Note, Frequency Operation to 400 MHz analog input is permitted but occurs at Domain Response of Switched-Capacitor ADCs; the AN-827 the expense of increased ADC noise and distortion. Application Note, A Resonant Approach to Interfacing Amplifiers to Synchronization capability is provided to allow synchronized Switched-Capacitor ADCs; and the Analog Dialogue article, timing between multiple devices. “Transformer-Coupled Front-End for Wideband A/D Converters,” Programming and control of the AD9643 are accomplished for more information on this subject. using a 3-pin, SPI-compatible serial interface. BIAS S ADC ARCHITECTURE S C C S FB The AD9643 architecture consists of a dual front-end sample- VIN+ and-hold circuit, followed by a pipelined switched-capacitor C C PAR1 PAR2 ADC. The quantized outputs from each stage are combined into S H S a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input C S sample and the remaining stages to operate on the preceding VIN– C C PAR1 C FB PAR2 S samples. Sampling occurs on the rising edge of the clock. S BIAS Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digital- Figure 46. Switched-Capacitor Input to-analog converter (DAC) and an interstage residue amplifier For best dynamic performance, the source impedances driving (MDAC). The MDAC magnifies the difference between the recon- VIN+ and VIN− should be matched, and the inputs should be structed DAC output and the flash input for the next stage in differentially balanced. the pipeline. One bit of redundancy is used in each stage to Input Common Mode facilitate digital correction of flash errors. The last stage simply The analog inputs of the AD9643 are not internally dc biased. consists of a flash ADC. In ac-coupled applications, the user must provide this bias The input stage of each channel contains a differential sampling externally. Setting the device so that V = 0.5 × AVDD (or CM circuit that can be ac- or dc-coupled in differential or single- 0.9 V) is recommended for optimum performance. An on-board ended modes. The output staging block aligns the data, corrects common-mode voltage reference is included in the design and is errors, and passes the data to the output buffers. The output buffers available from the VCM pin. Using the VCM output to set the are powered from a separate supply, allowing digital output noise to input common mode is recommended. Optimum performance be separated from the analog core. During power-down, the is achieved when the common-mode voltage of the analog input output buffers go into a high impedance state. is set by the VCM pin voltage (typically 0.5 × AVDD). The ANALOG INPUT CONSIDERATIONS VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. This The analog input to the AD9643 is a differential switched- decoupling capacitor should be placed close to the pin to capacitor circuit that has been designed for optimum performance minimize the series resistance and inductance between the part while processing a differential input signal. and this capacitor. The clock signal alternatively switches the input between sample Differential Input Configurations mode and hold mode (see the configuration shown in Figure 46). When the input is switched into sample mode, the signal source Optimum performance is achieved while driving the AD9643 must be capable of charging the sampling capacitors and settling in a differential input configuration. For baseband applications, within 1/2 clock cycle. the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 Rev. B | Page 23 of 36 09636-050 AD9643 Data Sheet differential drivers provide excellent performance and a flexible the recommended input configuration (see Figure 50). In this interface to the ADC. configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω resistor. These resistors The output common-mode voltage of the ADA4930-2 is easily compensate for losses in the input baluns to provide a 50 Ω set with the VCM pin of the AD9643 (see Figure 47), and the impedance to the driver. driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre- 15pF quency and source impedance. Based on these parameters, the 200Ω value of the input resistors and capacitors may need to be adjusted 33Ω 15Ω 90Ω VIN– AVDD VIN 76.8Ω or some components may need to be removed. Table 10 displays 5pF recommended values to set the RC network for different input ADA4930-2 ADC 0.1µF frequency ranges. However, these values are dependent on the 33Ω 15Ω VCM VIN+ 120Ω input signal and bandwidth and should be used only as a 15pF starting guide. Note that the values given in Table 10 are for each 200Ω R1, R2, C2, and R3 component shown in Figure 48 and Figure 50. 33Ω 0.1µF Table 10. Example RC Network Figure 47. Differential Input Configuration Using the ADA4930-2 Frequency R1 C1 R2 C2 R3 Range Series Differential Series Shunt Shunt For baseband applications where SNR is a key parameter, (MHz) (Ω) (pF) (Ω) (pF) (Ω) differential transformer coupling is the recommended input 0 to 100 33 8.2 0 15 49.9 configuration. An example is shown in Figure 48. To bias the 100 to 300 15 3.9 0 8.2 49.9 analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. An alternative to using a transformer-coupled input at frequencies C2 in the second Nyquist zone is to use an amplifier with variable R3 R2 gain. The AD8375 or AD8376 digital variable gain amplifier VIN+ (DVGAs) provides good performance for driving the AD9643. R1 2V p-p 49.9Ω Figure 49 shows an example of the AD8376 driving the AD9643 C1 ADC through a band-pass antialiasing filter. R1 R2 VCM VIN– 1000pF 180nH 220nH 0.1µF 33Ω R3 0.1µF 1µH 165Ω 15pF C2 VPOS AD9643 AD8376 5.1pF 3.9pF VCM 2.5kΩ║2pF Figure 48. Differential Transformer-Coupled Configuration 1nF 301Ω 165Ω 1µH 1nF 68nH The signal characteristics must be considered when selecting 180nH 220nH 1000pF a transformer. Most RF transformers saturate at frequencies NOTES ® 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE below a few megahertz. Excessive signal power can also cause EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS). core saturation, which leads to distortion. 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. At input frequencies in the second Nyquist zone and above, the Figure 49. Differential Input Configuration Using the AD8376 noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9643. For applications where SNR is a key parameter, differential double balun coupling is C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– R3 33Ω 0.1µF C2 Figure 50. Differential Double Balun Input Configuration Rev. B | Page 24 of 36 09636-052 09636-051 09636-053 09636-054 Data Sheet AD9643 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9643. 25Ω ADC 390pF 390pF CLOCK The full-scale input range can be adjusted by varying the CLK+ INPUT reference voltage via SPI. The input span of the ADC tracks 390pF reference voltage changes linearly. CLK– SCHOTTKY 25Ω DIODES: CLOCK INPUT CONSIDERATIONS HSMS2822 For optimum performance, the AD9643 sample clock inputs, Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ and CLK−, should be clocked with a differential signal. If a low jitter clock source is not available, another option is to The signal is typically ac-coupled into the CLK+ and CLK− pins ac-couple a differential PECL signal to the sample clock input via a transformer or via capacitors. These pins are biased internally pins as shown in Figure 54. The AD9510, AD9511, AD9512, (see Figure 51) and require no external bias. If the inputs are AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, floated, the CLK− pin is pulled low to prevent spurious clocking. AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ AVDD ADCLK925 clock drivers offer excellent jitter performance. 0.9V ADC 0.1µF 0.1µF CLOCK CLK+ CLK+ CLK– INPUT AD95xx 100Ω PECL DRIVER 4pF 4pF 0.1µF 0.1µF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 51. Simplified Equivalent Clock Input Circuit Figure 54. Differential PECL Sample Clock (Up to 625 MHz) Clock Input Options A third option is to ac-couple a differential LVDS signal to the The AD9643 has a very flexible clock input structure. Clock sample clock input pins, as shown in Figure 55. The AD9510, input can be a CMOS, LVDS, LVPECL, or sine wave signal. AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, Regardless of the type of signal being used, clock source jitter AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers is of the most concern, as described in the Jitter Considerations offer excellent jitter performance. section. Figure 52 and Figure 53 show two preferable methods for ADC 0.1µF 0.1µF CLOCK CLK+ clocking the AD9643 (at clock rates of up to 625 MHz). A low INPUT AD95xx jitter clock source is converted from a single-ended signal to a 100Ω LVDS DRIVER 0.1µF 0.1µF differential signal using an RF balun or RF transformer. CLOCK CLK– INPUT 50kΩ 50kΩ The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- Figure 55. Differential LVDS Sample Clock (Up to 625 MHz) mended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer secondary Input Clock Divider limit clock excursions into the AD9643 to approximately 0.8 V p-p The AD9643 contains an input clock divider with the ability to differential. This limit helps prevent the large voltage swings of divide the input clock by integer values between 1 and 8. The the clock from feeding through to other portions of the AD9643 duty cycle stabilizer (DCS) is enabled by default on power-up. while preserving the fast rise and fall times of the signal, which The AD9643 clock divider can be synchronized using the external are critical to low jitter performance. SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on ® Mini-Circuits ADT1-1WT, 1:1Z the first SYNC signal after the register is written. A valid SYNC ADC 390pF 390pF XFMR CLOCK causes the clock divider to reset to its initial state. This synchro- CLK+ INPUT 100Ω 50Ω nization feature allows multiple parts to have their clock dividers 390pF aligned to guarantee simultaneous input sampling. CLK– SCHOTTKY DIODES: HSMS2822 Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz) Rev. B | Page 25 of 36 09636-055 09636-056 09637-057 09636-059 09636-058 AD9643 Data Sheet Clock Duty Cycle Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal Typical high speed ADCs use both clock edges to generate a with digital noise. Low jitter, crystal controlled oscillators make variety of internal timing signals and, as a result, may be sensitive to the best clock sources. If the clock is generated from another type clock duty cycle. Commonly, a ±5% tolerance is required on the of source (by gating, dividing, or another method), it should be clock duty cycle to maintain dynamic performance characteristics. retimed by the original clock at the last step. The AD9643 contains a duty cycle stabilizer (DCS) that retimes Refer to the AN-501 Application Note, Aperture Uncertainty and the nonsampling (falling) edge, providing an internal clock ADC System Performance, and the AN-756 Application Note, signal with a nominal 50% duty cycle. This allows the user to Sampled Systems and the Effects of Clock Phase Noise and Jitter, for provide a wide range of clock input duty cycles without affecting more information about jitter performance as it relates to ADCs. the performance of the AD9643. POWER DISSIPATION AND STANDBY MODE Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. The duty As shown in Figure 57, the power dissipated by the AD9643 is cycle control loop does not function for clock rates less than proportional to its sample rate. The data in Figure 57 was taken 40 MHz nominally. The loop has a time constant associated using the same operating conditions as those used for the Typical with it that must be considered when the clock rate can change Performance Characteristics section. dynamically. A wait time of 1.5 μs to 5 μs is required after a 0.8 0.5 dynamic clock frequency increase or decrease before the DCS TOTAL POWER 0.7 loop is relocked to the input signal. During the time period that 0.4 the loop is not locked, the DCS loop is bypassed, and internal 0.6 device timing is dependent on the duty cycle of the input clock 0.5 0.3 signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS 0.4 I AVDD circuit is recommended to maximize ac performance. 0.2 0.3 I Jitter Considerations DRVDD 0.2 High speed, high resolution ADCs are sensitive to the quality of 0.1 0.1 the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by 0 0 40 60 80 100 120 140 160 180 200 220 240 2 (−SNR /10) LF SNRHF = −10 log[(2π × fIN × tJRMS) + 10 ] ENCODE FREQUENCY (MSPS) Figure 57. AD9643-250 Power and Current vs. Sample Rate In the equation, the rms aperture jitter represents the root- mean-square of all jitter sources, which include the clock input, By asserting PDWN (either through the SPI port or by asserting the analog input signal, and the ADC aperture jitter specification. the PDWN pin high), the AD9643 is placed in power-down IF undersampling applications are particularly sensitive to jitter, mode. In this state, the ADC typically dissipates 10 mW. During as shown in Figure 56. power-down, the output drivers are placed in a high impedance 80 state. Asserting the PDWN pin low returns the AD9643 to its normal operating mode. Note that PDWN is referenced to the 75 digital output driver supply (DRVDD) and should not exceed that supply voltage. 70 Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, 65 and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning 60 0.05ps to normal operation. As a result, wake-up time is related to the 0.2ps 0.5ps time spent in power-down mode, and shorter power-down 1ps 55 1.5ps cycles result in proportionally shorter wake-up times. MEASURED 50 When using the SPI port interface, the user can place the ADC 1 10 100 1000 in power-down mode or standby mode. Standby mode allows INPUT FREQUENCY (MHz) the user to keep the internal reference circuitry powered when Figure 56. AD9643-250 SNR vs. Input Frequency and Jitter faster wake-up times are required. See the Memory Map Register The clock input should be treated as an analog signal in cases Description section and the AN-877 Application Note, Interfacing where aperture jitter may affect the dynamic range of the AD9643. to High Speed ADCs via SPI, for additional details. Rev. B | Page 26 of 36 SNR (dBc) 09636-060 TOTAL POWER (W) 09636-061 SUPPLY CURRENT (A) Data Sheet AD9643 Timing DIGITAL OUTPUTS The AD9643 provides latched data with a pipeline delay of 10 input The AD9643 output drivers can be configured for either ANSI sample clock cycles. Data outputs are available one propagation LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. delay (tPD) after the rising edge of the clock signal. As detailed in the AN-877 Application Note, Interfacing to High The length of the output data lines and loads placed on them Speed ADCs via SPI, the data format can be selected for offset should be minimized to reduce transients within the AD9643. binary, twos complement, or gray code when using the SPI These transients can degrade converter dynamic performance. control. The lowest typical conversion rate of the AD9643 is 40 MSPS. At Digital Output Enable Function (OEB) clock rates below 40 MSPS, dynamic performance may degrade. The AD9643 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin Data Clock Output (DCO) or through the SPI interface. If the OEB pin is low, the output The AD9643 also provides data clock output (DCO) intended data drivers are enabled. If the OEB pin is high, the output data for capturing the data in an external register. Figure 2 shows a drivers are placed in a high impedance state. This OEB function graphical timing diagram of the AD9643 output modes. is not intended for rapid access to the data bus. Note that OEB ADC OVERRANGE (OR) is referenced to the digital output driver supply (DRVDD) and The ADC overrange indicator is asserted when an overrange is should not exceed that supply voltage. detected on the input of the ADC. The overrange condition is When using the SPI interface, the data outputs of each channel determined at the output of the ADC pipeline and, therefore, is can be independently three-stated by using the output enable subject to a latency of 10 ADC clocks. An overrange at the input is bar bit (Bit 4) in Register 0x14. Because the output data is indicated by this bit, 10 clock cycles after it occurs. interleaved, if only one of the two channels is disabled, the output data of the remaining channel is repeated in both the rising and falling output clock cycles. Table 11. Output Data Format VIN+ − VIN−, Input (V) Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR VIN+ − VIN− <–0.875 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− –0.875 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− +0.875 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− >+0.875 11 1111 1111 1111 01 1111 1111 1111 1 Rev. B | Page 27 of 36 AD9643 Data Sheet CHANNEL/CHIP SYNCHRONIZATION The AD9643 has a SYNC input that allows the user flexible The SYNC input is internally synchronized to the sample clock. synchronization options for synchronizing the internal blocks. However, to ensure that there is no timing uncertainty between The SYNC feature is useful for guaranteeing synchronized multiple parts, the SYNC input signal should be synchronized operation across multiple ADCs. The input clock divider can be to the input clock signal. The SYNC input should be driven synchronized using the SYNC input. The divider can be enabled using a single-ended CMOS type signal. to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. Rev. B | Page 28 of 36 Data Sheet AD9643 SERIAL PORT INTERFACE (SPI) The AD9643 serial port interface (SPI) allows the user to configure All data is composed of 8-bit words. The first bit of each individual the converter for specific functions or operations through a byte of serial data indicates whether a read or write command is structured register space provided inside the ADC. The SPI issued. This allows the serial data input/output (SDIO) pin to gives the user added flexibility and customization, depending on change direction from an input to an output. the application. Addresses are accessed via the serial port and In addition to word length, the instruction phase determines can be written to or read from via the port. Memory is organized whether the serial frame is a read or write operation, allowing into bytes that can be further divided into fields. These fields are the serial port to be used both to program the chip and to read documented in the Memory Map section. For detailed operational the contents of the on-chip memory. If the instruction is a readback information, see the AN-877 Application Note, Interfacing to operation, performing a readback causes the serial data input/ High Speed ADCs via SPI. output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin is port configuration register. For more information about this used to synchronize the read and write data presented from/to the and other features, see the AN-877 Application Note, Interfacing ADC. The SDIO (serial data input/output) pin is a dual-purpose to High Speed ADCs via SPI. pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active HARDWARE INTERFACE low control that enables or disables the read and write cycles. The pins described in Table 12 comprise the physical interface Table 12. Serial Port Interface Pins between the user programming device and the serial port of the Pin Function AD9643. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, SCLK Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. functioning as an input during write phases and as an output SDIO Serial Data Input/Output. A dual-purpose pin that during readback. typically serves as an input or an output, depending on The SPI interface is flexible enough to be controlled by either the instruction being sent and the relative position in the timing frame. FPGAs or microcontrollers. One method for SPI configuration CSB Chip Select Bar. An active low control that gates the read is described in detail in the AN-812 Application Note, Micro- and write cycles. controller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full The falling edge of CSB, in conjunction with the rising edge of dynamic performance of the converter is required. Because the SCLK, determines the start of the framing. An example of the SCLK signal, the CSB signal, and the SDIO signal are typically serial timing and its definitions can be found in Figure 58 and asynchronous to the ADC clock, noise from these signals can Table 5. degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between Other modes involving the CSB are available. The CSB can be this bus and the AD9643 to prevent these signals from transi- held low indefinitely, which permanently enables the device; tioning at the converter inputs during critical sampling periods. this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and the W1 bits. Rev. B | Page 29 of 36 AD9643 Data Sheet SPI ACCESSIBLE FEATURES Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9643 part-specific features are described in the Memory Map Register Description section. Table 13. Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power-down mode or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. B | Page 30 of 36 09636-062 Data Sheet AD9643 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip • “Bit is set” is synonymous with “bit is set to Logic 1” or configuration registers (Address 0x00 to Address 0x02); the “writing Logic 1 for the bit.” channel index and transfer registers (Address 0x05 and • “Clear a bit” is synonymous with “bit is set to Logic 0” or Address 0xFF); and the ADC functions registers, including setup, “writing Logic 0 for the bit.” control, and test (Address 0x08 to Address 0x3A). Transfer Register Map The memory map register table (see Table 14) documents the Address 0x08 to Address 0x20 and Address 0x3A are shadowed. default hexadecimal value for each hexadecimal address shown. Writes to these addresses do not affect part operation until a The column with the heading Bit 7 (MSB) is the start of the transfer command is issued by writing 0x01 to Address 0xFF, default hexadecimal value given. For example, Address 0x14, setting the transfer bit. This allows these registers to be updated the output mode register, has a hexadecimal default value of internally and simultaneously when the transfer bit is set. The 0x05. This means that Bit 0 = 1 and Bit 2 = 1, and the remaining internal update takes place when the transfer bit is set, and then bits are 0s. This setting is the default output format value, which the bit autoclears. is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Channel-Specific Registers Speed ADCs via SPI. This document details the functions Some channel setup functions, such as the signal monitor controlled by Register 0x00 to Register 0x25. The remaining thresholds, can be programmed to a different value for each registers, Register 0x3A, is documented in the Memory Map channel. In these cases, channel address locations are internally Register Description section. duplicated for each channel. These registers and bits are designated Open and Reserved Locations in Table 14 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in All address and bit locations that are not included in Table 14 Register 0x05. If both bits are set, the subsequent write affects are not currently supported for this device. Unused bits of a the registers of both channels. In a read cycle, only Channel A valid address location should be written with 0s. Writing to these or Channel B should be set to read one of the two registers. If locations is required only when part of an address location is both bits are set during an SPI read cycle, the part returns the open (for example, Address 0x18). If the entire address location value for Channel A. Registers and bits designated as global in is open (for example, Address 0x13), this address location should Table 14 affect the entire part and the channel features for which not be written. independent settings are not allowed between channels. The Default Values settings in Register 0x05 do not affect the global registers and bits. After the AD9643 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 14. Rev. B | Page 31 of 36 AD9643 Data Sheet MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are mirrored 1 (global) so that LSB first mode or MSB first mode registers correctly, regardless of shift mode. 0x01 0x82 Read only. Chip ID 8-bit chip ID[7:0] (global) (AD9643 = 0x82) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed (global) 00 = 250 MSPS grade ID used to 01 = 210 MSPS differentiate 11 = 170 MSPS devices; read only. Channel Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are (global) (default) (default) set to determine which device on the chip receives the next write command; applies to local registers only. 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchro- (global) nously transfers data from the master shift register to the slave. ADC Functions 0x08 Power modes Open Open External Open Open Open Internal power-down mode 0x00 Determines (local) power- (local) various down pin generic 00 = normal operation function modes of 01 = full power-down (local) chip 10 = standby operation. 0 = power- 11 = reserved down 1 = standby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 (global) stabilizer (default) 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock (global) divide 000 = no delay 000 = divide by 1 values 001 = 1 input clock cycle 001 = divide by 2 other than 010 = 2 input clock cycles 010 = divide by 3 000 auto- 011 = 3 input clock cycles 011 = divide by 4 matically 100 = 4 input clock cycles 100 = divide by 5 cause the 101 = 5 input clock cycles 101 = divide by 6 duty cycle 110 = 6 input clock cycles 110 = divide by 7 stabilizer to 111 = 7 input clock cycles 111 = divide by 8 become active. Rev. B | Page 32 of 36 Data Sheet AD9643 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0D Test mode User test Open Reset PN Reset PN Output test mode 0x00 When this (local) mode long gen short gen register is 0000 = off (default) control set, the test 0001 = midscale short data is 0 = con- 0010 = positive FS placed on tinuous/ 0011 = negative FS the output repeat 0100 = alternating checkerboard pins in pattern 0101 = PN long sequence place of 1 = single 0110 = PN short sequence normal data. pattern, 0111 = one/zero word toggle then 0s 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 (local) sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (local) (twos complement format) 0x14 Output mode Open Open Open Output Open Output Output format 0x05 Configures enable bar invert (local) the outputs 00 = offset binary (local) and the 1 = normal 01 = twos complement format of (default) (default) the data. 0 = inverted 10 = gray code 11 = reserved (local) 0x15 Output Adjust Open Open Open Open LVDS output drive current adjust 0x01 (Global) 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved 0x16 Clock phase Invert Open Open Open Open Open Open 0x00 Even/odd control DCO clock mode (global) output enable 0 = disabled 1 = enabled 0x17 DCO output Enable Open Open DCO clock delay 0x00 delay DCO [delay = (3100 ps × register value/31 +100)] (global) clock 00000 = 100 ps delay 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps 0x18 Open Open Open Full-scale input voltage selection 0x00 Input Span Full-scale select input 01111 = 2.087 V p-p (global) adjustment … in 0.022 V 00001 = 1.772 V p-p steps. 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1[7:0] 0x00 Pattern 1 LSB (global) 0x1A User Test User Test Pattern 1[15:8] 0x00 Pattern 1 MSB (global) 0x1B User Test User Test Pattern 2[7:0] 0x00 Pattern 2 LSB (global) 0x1C User Test User Test Pattern 2[15:8] 0x00 Pattern 2 MSB (global) Rev. B | Page 33 of 36 AD9643 Data Sheet Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x1D User Test User Test Pattern 3[7:0] 0x00 Pattern 3 LSB (global) 0x1E User Test User Test Pattern 3[15:8] 0x00 Pattern 3 MSB (global) 0x1F User Test User Test Pattern 4[7:0] 0x00 Pattern 4 LSB (global) 0x20 User Test User Test Pattern 4[15:8] 0x00 Pattern 4 MSB (global) 0x24 BIST signature BIST signature[7:0] 0x00 Read only. LSB (local) 0x25 BIST signature BIST signature[15:8] 0x00 Read only. MSB (local) 0x3A Sync control Open Open Open Open Open Clock Clock Master sync 0x00 (global) divider divider buffer enable next sync sync only enable 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. MEMORY MAP REGISTER DESCRIPTION Bit 1—Clock Divider Sync Enable For more information on functions controlled in Register 0x00 Bit 1 gates the sync pulse to the clock divider. The sync signal is to Register 0x25, see the AN-877 Application Note, Interfacing enabled when Bit 1 is high and Bit 0 is high. This is continuous to High Speed ADCs via SPI. sync mode. Sync Control (Register 0x3A) Bit 0—Master Sync Buffer Enable Bits[7:3]—Reserved Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to Bit 2—Clock Divider Next Sync Only conserve power. If the master sync buffer enable bit (Address 0x3A, Bit 0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Rev. B | Page 34 of 36 Data Sheet AD9643 APPLICATIONS INFORMATION VCM DESIGN GUIDELINES The VCM pin should be decoupled to ground with a 0.1 μF Before starting system level design and layout of the AD9643, capacitor, as shown in Figure 48. For optimal channel-to-channel it is recommended that the designer become familiar with these isolation, a 33 Ω resistor should be included between the AD9643 guidelines, which discuss the special circuit connections and VCM pin and the Channel A analog input network connection, layout requirements needed for certain pins. as well as between the AD9643 VCM pin and the Channel B Power and Ground Recommendations analog input network connection. When connecting power to the AD9643, it is recommended SPI Port that two separate 1.8 V supplies be used: one supply should be The SPI port should not be active during periods when the full used for analog (AVDD), and a separate supply should be used dynamic performance of the converter is required. Because the for the digital outputs (DRVDD). The designer can employ SCLK, CSB, and SDIO signals are typically asynchronous to the several different decoupling capacitors to cover both high and ADC clock, noise from these signals can degrade converter low frequencies. These capacitors should be located close to the performance. If the on-board SPI bus is used for other devices, point of entry at the PC board level and close to the pins of the it may be necessary to provide buffers between this bus and the part with minimal trace length. AD9643 to keep these signals from transitioning at the converter A single PCB ground plane should be sufficient when using the input pins during critical sampling periods. AD9643. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9643 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about the packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Rev. B | Page 35 of 36 AD9643 Data Sheet OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9643BCPZ-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZ-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZ-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643-170EBZ −40°C to +85°C Evaluation Board with AD9643-170 AD9643-210EBZ −40°C to +85°C Evaluation Board with AD9643-210 AD9643-250EBZ −40°C to +85°C Evaluation Board with AD9643-250 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09636-0-9/11(B) Rev. B | Page 36 of 36 091707-C