Isolated Sigma-Delta Modulator AD7401A FEATURES GENERAL DESCRIPTION 1 20 MHz maximum external clock rate The AD7401A is a second-order, sigma-delta (Σ-Δ) modulator Second-order modulator that converts an analog input signal into a high speed, 1-bit data 16 bits, no missing codes stream with on-chip digital isolation based on Analog Devices, ±2 LSB INL typical at 16 bits Inc., iCoupler® technology. The AD7401A operates from a 5 V 1 μV/°C typical offset drift power supply and accepts a differential input signal of ±250 mV On-board digital isolator (±320 mV full scale). The analog input is continuously sampled On-board reference by the analog modulator, eliminating the need for external ±250 mV analog input range sample-and-hold circuitry. The input information is contained Low power operation: 17 mA typical at 5.5 V in the output stream as a density of ones with a data rate up to −40°C to +125°C operating range 20 MHz. The original information can be reconstructed with 16-lead SOIC package an appropriate digital filter. The serial I/O can use a 5 V or a 3 V Internal clock version: AD7400A supply (VDD2). Safety and regulatory approvals The serial interface is digitally isolated. High speed CMOS, UL recognition combined with Analog Devices, Inc., iCoupler® technology , 5000 V rms for 1 minute per UL 1577 means the on-chip isolation provides outstanding performance CSA Component Acceptance Notice #5A characteristics, superior to alternatives such as optocoupler VDE Certificate of Conformity devices. The part contains an on-chip reference. The AD7401A DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 is offered in a 16-lead SOIC and has an operating temperature V = 891 V peak IORM range of −40°C to +125°C. APPLICATIONS AC motor controls Shunt current monitoring Data acquisition systems Analog-to-digital and opto-isolator replacements FUNCTIONAL BLOCK DIAGRAM V V DD1 DD2 AD7401A V + IN Σ-∆ ADC V – IN UPDATE WATCHDOG ENCODE DECODE MDAT REF CONTROL LOGIC WATCHDOG UPDATE DECODE MCLKIN ENCODE GND GND 1 2 Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. 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T/H BUF 07332-001 AD7401A TABLE OF CONTENTS Features .............................................................................................. 1  Terminology.................................................................................... 13  Applications....................................................................................... 1  Theory of Operation ...................................................................... 14  General Description ......................................................................... 1  Circuit Information.................................................................... 14  Functional Block Diagram .............................................................. 1  Analog Input ............................................................................... 14  Revision History ............................................................................... 2  Differential Inputs...................................................................... 15  Specifications..................................................................................... 3  Current Sensing Applications................................................... 15  Timing Specifications .................................................................. 5  Voltage Sensing Applications.................................................... 15  Insulation and Safety-Related Specifications............................ 6  Digital Filter ................................................................................ 16  Regulatory Information............................................................... 6  Applications Information .............................................................. 18  DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Grounding and Layout .............................................................. 18  Characteristics .............................................................................. 7  Evaluating the AD7401A Performance ................................... 18  Absolute Maximum Ratings............................................................ 8  Insulation Lifetime..................................................................... 18  ESD Caution.................................................................................. 8  Outline Dimensions....................................................................... 19  Pin Configuration and Function Descriptions............................. 9  Ordering Guide .......................................................................... 19  Typical Performance Characteristics ........................................... 10  REVISION HISTORY 7/11—Rev. B to Rev. C 1/11—Rev. 0 to Rev. A Changes to Minimum External Air Gap (Clearance) Parameter, Change to Features, UL Recognition Value ...................................1 Table 3 and Minimum External Tracking (Creepage) Parameter, Change to Table 3, Input-to-Output Momentary Withstand Table 3 ................................................................................................ 6 Voltage Value...............................................................................................6 Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7 Changes to Table 4, Isolation Voltage Value, and Endnote 1.......6 Description, Table 8.......................................................................... 9 7/08—Revision 0: Initial Version 3/11—Rev. A to Rev. B Change to General Description Section ........................................ 1 Changes to Table 1............................................................................ 3 Rev. C | Page 2 of 20 AD7401A SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, fMCLKIN = 1 16 MHz maximum, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. 1, 2 Y Version Parameter Unit Test Conditions/Comments Min Typ Max STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits 3 1 Integral Nonlinearity (INL) ±1.5 ±7 LSB V + = ±200 mV, T = −40°C to +85°C, f = 20 MHz max IN A MCLKIN 1 ±2 ±13 LSB V + = ±250 mV, T = −40°C to +85°C, f = 20 MHz max IN A MCLKIN 1 ±1.5 ±11 LSB VIN+ = ±200 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max 1 ±2 ±46 LSB VIN+ = ±250 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max 3 Differential Nonlinearity (DNL) ±0.9 LSB Guaranteed no missed codes to 16 bits, 1 fMCLKIN = 20 MHz max, VIN+ = −250 mV to +250 mV 3 1 ±.025 ±0.5 mV Offset Error fMCLKIN = 20 MHz max, VIN+ = −250 mV to +250 mV 3 Offset Drift vs. Temperature 1 3.5 μV/°C 3 Offset Drift vs. V 120 μV/V DD1 3 Gain Error 0.07 ±1.5 mV 1 ±1 mV f = 20 MHz max, V + = −250 mV to +250 mV MCLKIN IN 3 23 μV/°C Gain Error Drift vs. Temperature 3 110 μV/V Gain Error Drift vs. VDD1 ANALOG INPUT Input Voltage Range ±200 ±250 mV For specified performance; full range ±320 mV 1 Dynamic Input Current ±13 ±18 μA VIN+ = 500 mV, VIN− = 0 V, fMCLKIN = 20 MHz max 1 ±10 ±15 μA VIN+ = 400 mV, VIN− = 0 V, fMCLKIN = 20 MHz max 1 0.08 μA V + = 0 V, V − = 0 V, f = 20 MHz max IN IN MCLKIN DC Leakage Current ±0.01 ±0.6 μA Input Capacitance 10 pF DYNAMIC SPECIFICATIONS VIN+ = 5 kHz 3 76 82 dB V + = ±200 mV, T = −40°C to +85°C, Signal-to-(Noise + Distortion) Ratio (SINAD) IN A 1 f = 5 MHz to 20 MHz MCLKIN 71 82 dB V + = ±250 mV, T = −40°C to +85°C, IN A 1 fMCLKIN = 5 MHz to 20 MHz 72 82 dB VIN+ = ±200 mV, TA = −40°C to +125°C, 1 fMCLKIN = 5 MHz to 20 MHz 82 dB VIN+ = ±250 mV, TA = −40°C to +125°C, 1 fMCLKIN = 5 MHz to 20 MHz 3 81 83 dB V + = ±250 mV, T = −40°C to +125°C, Signal-to-Noise Ratio (SNR) IN A 1 f = 5 MHz to 20 MHz MCLKIN 80 82 dB V + = ±200 mV, T = −40°C to +125°C, IN A 1 f = 5 MHz to 20 MHz MCLKIN 3 1 Total Harmonic Distortion (THD) −90 dB f = 20 MHz max , V + = −250 mV to +250 mV MCLKIN IN 3 −92 dB Peak Harmonic or Spurious Noise (SFDR) 3 12.3 13.3 Bits Effective Number of Bits (ENOB) 3 Isolation Transient Immunity 25 30 kV/μs LOGIC INPUTS Input High Voltage, VIH 0.8 × VDD2 V Input Low Voltage, V 0.2 × V V IL DD2 Input Current, I ±0.5 μA IN Floating State Leakage Current 1 μA 4 Input Capacitance, C 10 pF IN Rev. C | Page 3 of 20 AD7401A 1, 2 Y Version Parameter Unit Test Conditions/Comments Min Typ Max LOGIC OUTPUTS Output High Voltage, V V − 0.1 V I = −200 μA OH DD2 O Output Low Voltage, V 0.4 V I = +200 μA OL O POWER REQUIREMENTS VDD1 4.5 5.5 V V 3 5.5 V DD2 5 IDD1 10 12 mA VDD1 = 5.5 V 6 IDD2 7 9 mA VDD2 = 5.5 V 3 4 mA V = 3.3 V DD2 93.5 MW V = V = 5.5 V POWER DISSIPATION (SEE Figure 17) DD1 DD2 1 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C. 2 All voltages are relative to their respective ground. 3 See the Terminology section. 4 Sample tested during initial release to ensure compliance. 5 See Figure 15. 6 See Figure 17. Rev. C | Page 4 of 20 AD7401A TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Table 2. 1 Parameter Limit at TMIN, TMAX Unit Description 2, 3 f 20 MHz max Master clock input frequency MCLKIN 5 MHz min Master clock input frequency 4 t1 25 ns max Data access time after MCLKIN rising edge 4 t2 15 ns min Data hold time after MCLKIN rising edge t 0.4 × t ns min Master clock low time 3 MCLKIN t 0.4 × t ns min Master clock high time 4 MCLKIN 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN ≤ 16 MHz and 48/52 to 52/48 for 16 MHz < fMCLKIN < 20 MHz. 3 V = V = 5 V ± 5% for f > 16 MHz to 20 MHz. DD1 DD2 MCLKIN 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA I OL TO OUTPUT 1.6V PIN C L 25pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications t 4 MCLKIN t t t 1 2 3 MDAT Figure 3. Data Timing Rev. C | Page 5 of 20 07332-002 07332-003 AD7401A INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Symbol Value Unit Conditions Input-to-Output Momentary Withstand Voltage V 5000 min V 1-minute duration ISO Minimum External Air Gap (Clearance) L(I01) 8.1 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.46 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I) REGULATORY INFORMATION Table 4. 1 2 UL CSA VDE Recognized Under 1577 Approved under CSA Component Certified according to DIN V VDE V 0884-10 1 2 Component Recognition Program Acceptance Notice #5A (VDE V 0884-10):2006-12 5000 V rms Isolation Voltage Reinforced insulation per Reinforced insulation per DIN V VDE V 0884-10 (VDE V CSA 60950-1-03 and IEC 60950-1, 0884-10):2006-12, 891 V peak 630 V rms maximum working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each AD7401A is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 μA). 2 In accordance with DIN V VDE V 0884-10, each AD7401A is proof tested by applying an insulation test voltage ≥1671V peak for 1 sec (partial discharge detection limit = 5 pC). Rev. C | Page 6 of 20 AD7401A DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Description Symbol Characteristic Unit INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 450 V rms I to II For Rated Mains Voltage ≤ 600 V rms I to II CLIMATIC CLASSIFICATION 40/105/21 POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2 MAXIMUM WORKING INSULATION VOLTAGE V 891 V peak IORM INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 V × 1.875 = V , 100% Production Test, t = 1 sec, Partial Discharge < 5 pC V 1671 V peak IORM PR m PR INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR After Environmental Test Subgroup 1 1426 V peak V × 1.6 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 1069 V peak V × 1.2 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, t = 10 sec) V 6000 V peak TR TR SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 4) Case Temperature TS 150 °C Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 9 INSULATION RESISTANCE AT TS, VIO = 500 V RS >10 Ω 350 300 250 SIDE #2 200 150 SIDE #1 100 50 0 0 50 100 150 200 CASE TEMPERATURE (°C) Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. C | Page 7 of 20 SAFETY-LIMITING CURRENT (mA) 07332-004 AD7401A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to Stresses above those listed under Absolute Maximum Ratings their respective ground. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 6. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +6.5 V DD1 1 maximum rating conditions for extended periods may affect VDD2 to GND2 −0.3 V to +6.5 V device reliability. Analog Input Voltage to GND1 −0.3 V to VDD1 + 0.3 V 1 Digital Input Voltage to GND2 −0.3 V to VDD1 + 0.5 V Table 7. Maximum Continuous Working Voltage Output Voltage to GND −0.3 V to V + 0.3 V 2 DD2 Parameter Max Unit Constraint 1 Input Current to Any Pin Except Supplies ±10 mA AC Voltage, Bipolar 565 V peak 50-year minimum Operating Temperature Range −40°C to +125°C Waveform lifetime Storage Temperature Range −65°C to +150°C AC Voltage, Unipolar 891 V peak Maximum CSA/VDE Junction Temperature 150°C Waveform approved working voltage SOIC Package 2 DC Voltage 891 V Maximum CSA/VDE θJA Thermal Impedance 89.2°C/W approved working 2 θJC Thermal Impedance 55.6°C/W voltage 12 Resistance (Input to Output), R 10 Ω I-O 1 Refers to continuous voltage magnitude imposed across the isolation 3 Capacitance (Input to Output), C 1.7 pF typ I-O barrier. See the Insulation Lifetime section for more details. Pb-Free Temperature, Soldering Reflow 260°C ESD CAUTION ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR to latch up. 2 EDEC 2S2P standard board. 3 f = 1 MHz. Rev. C | Page 8 of 20 AD7401A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 16 GND DD1 2 V + 2 15 NC IN V – 3 14 V IN DD2 AD7401A NC 4 13 MCLKIN TOP VIEW (Not to Scale) NC 5 12 NC NC 6 11 MDAT V /NC 7 10 NC DD1 GND 8 9 GND 1 2 NC = NO CONNECT Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7401A and is relative to GND . DD1 1 2 V + Positive Analog Input. Specified range of ±250 mV. IN 3 VIN− Negative Analog Input. Normally connected to GND1. 4 to 6, 10, NC No Connect. 12, 15 7 V /NC Supply Voltage. 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7401A and is relative to DD1 1 GND . No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7401A will operate normally provided that the supply voltage is applied to Pin 1. 8 GND1 Ground 1. This is the ground reference point for all circuitry on the isolated side. 9, 16 GND2 Ground 2. This is the ground reference point for all circuitry on the nonisolated side. 11 MDAT Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge. 13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN. 14 VDD2 Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Rev. C | Page 9 of 20 07332-005 AD7401A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using 25 kHz brick-wall filter, unless otherwise noted. 100 –90 V = V = 5V DD1 DD2 90 –85 MCLKIN = 10MHz 80 MCLKIN = 16MHz –80 70 MCLKIN = 16MHz –75 60 50 –70 MCLKIN = 5MHz MCLKIN = 10MHz 40 –65 30 –60 20 200mV p-p SINE WAVE ON V DD1 NO DECOUPLING –55 10 V = V = 5V DD1 DD2 1MHz CUTOFF FILTER 0 –50 0 100 200 300 400 500 600 700 800 900 1000 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33 SUPPLY RIPPLE FREQUENCY (kHz) ± INPUT AMPLITUDE (V) Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 9. SINAD vs. V IN –90 0.4 V = V = 5 V V = V DD1 DD2 = 5V DD1 DD2 0.3 –85 MCLKIN = 16MHz 0.2 –80 0.1 –75 0 MCLKIN = 10MHz –70 –0.1 –65 MCLKIN = 5MHz –0.2 –60 –0.3 –55 –0.4 V + = –200mV TO +200mV IN V – = 0V IN –50 –0.5 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 0 10k 20k 30k 40k 50k 60k INPUT FREQUENCY (Hz) CODE Figure 7. SINAD vs. Analog Input Frequency Figure 10. Typical DNL (±200 mV Range) 20 0.8 4096 POINT FFT V + = –200mV TO +200mV IN f = 5kHz 0 V – = 0V IN IN SINAD = 81.984dB 0.6 THD = –96.311dB –20 DECIMATION BY 256 –40 0.4 –60 –80 0.2 –100 0 –120 –140 –0.2 –160 –180 –0.4 03 5 101520250 06 10k 20k 30k 40k 50k0k FREQUENCY (kHz) CODE Figure 8. Typical FFT (±200 mV Range) Figure 11. Typical INL (±200 mV Range) Rev. C | Page 10 of 20 PSRR (dB) SINAD (dB) (dB) 07332-008 07332-007 07332-006 DNL ERROR (LSB) INL ERROR (LSB) SINAD (dB) 07332-011 07332-009 07332-010 AD7401A 250 0.0105 V = V = 5V DD1 DD2 V = V = 4.5V V = V = 4.5V MCLKIN = 16MHz DD1 DD2 DD1 DD2 200 0.0100 MCLKIN = 16MHz MCLKIN = 10MHz T = +85°C A MCLKIN = 16MHz MCLKIN = 16MHz V = V = 4.5V V = V = 5V DD1 DD2 DD1 DD2 T = –40°C T = +105°C A A 150 0.0095 MCLKIN = 5MHz MCLKIN = 5MHz V = V = 5V DD1 DD2 100 0.0090 MCLKIN = 16MHz MCLKIN = 10MHz MCLKIN = 10MHz 50 T = –40°C T = +105°C 0.0085 A A 0 0.0080 –50 MCLKIN = 10MHz T = +85°C A 0.0075 –100 V = V = 5.25V V = V = 5.25V DD1 DD2 DD1 DD2 MCLKIN = 16MHz MCLKIN = 10MHz 0.0070 –150 MCLKIN = 5MHz V = V = 5V V = V = 5.25V DD1 DD2 DD1 DD2 T = –40°C A MCLKIN = 5MHz MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 5MHz 0.0065 –200 T = +85°C T = +105°C A A 0.0060 –250 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 TEMPERATURE (°C) V DC INPUT VOLTAGE (V) IN Figure 12. Offset Drift vs. Temperature for Various Supply Voltages Figure 15. IDD1 vs. VIN at Various Temperatures 200.5 0.0070 V = V = 4.5V V = V = 4.5V V = V = 5V DD1 DD2 DD1 DD2 DD1 DD2 MCLKIN = 16MHz MCLKIN = 10MHz MCLKIN = 16MHz T = 25°C 200.4 0.0065 A V = V = 4.5V V = V = 5V DD1 DD2 DD1 DD2 200.3 MCLKIN = 5MHz MCLKIN = 5MHz 0.0060 V = V = 5V V = V = 5.25V DD1 DD2 DD1 DD2 200.2 0.0055 MCLKIN = 16MHz MCLKIN = 10MHz V = V = 5.25V V = V = 5.25V DD1 DD2 DD1 DD2 200.1 0.0050 MCLKIN = 16MHz MCLKIN = 5MHz MCLKIN = 10MHz 200.0 V = V = 5V 0.0045 DD1 DD2 MCLKIN = 10MHz 199.9 0.0040 199.8 0.0035 MCLKIN = 5MHz 199.7 0.0030 199.6 0.0025 199.5 0.0020 –0.225 –0.125 –0.025 0.075 0.175 0.275 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 TEMPERATURE (°C) V DC INPUT VOLTAGE (V) IN Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages Figure 16. I vs. V DC Input Voltage DD2 IN 0.0105 0.0070 V = V = 5V V = V = 5V DD1 DD2 DD1 DD2 T = 25°C A 0.0065 0.0100 MCLKIN = 16MHz 0.0060 T = +105°C 0.0095 MCLKIN = 16MHz A MCLKIN = 16MHz MCLKIN = 16MHz 0.0055 T = –40°C T = +85°C A A 0.0090 MCLKIN = 10MHz MCLKIN = 10MHz 0.0050 T = –40°C T = +105°C A A 0.0085 0.0045 MCLKIN = 10MHz 0.0040 MCLKIN = 10MHz 0.0080 T = +85°C A MCLKIN = 5MHz 0.0035 T = –40°C A 0.0075 MCLKIN = 5MHz 0.0030 0.0070 0.0025 MCLKIN = 5MHz MCLKIN = 5MHz T = +105°C T = +85°C A A 0.0065 0.0020 –0.225 –0.125 –0.025 0.075 0.175 0.275 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 V DC INPUT VOLTAGE (V) V DC INPUT VOLTAGE (V) IN IN Figure 14. I vs. V DC Input Voltage Figure 17. IDD2 vs. VIN at Various Temperatures DD1 IN Rev. C | Page 11 of 20 I (A) DD1 GAIN (mV) OFFSET (µV) 07332-012 07332-013 07332-014 I (A) I (A) DD2 DD2 I (A) DD1 07332-015 07332-017 07332-016 AD7401A 8 1.0 V = V = 4.5V TO 5.25V DD1 DD2 V = V = 5V DD1 DD2 50kHz BRICK-WALL FILTER 6 MCLKIN = 16MHz 0.8 MCLKIN = 10MHz 4 2 0.6 0 MCLKIN = 5MHz 0.4 –2 MCLKIN = 5MHz –4 0.2 –6 MCLKIN = 16MHz MCLKIN = 10MHz –8 0 V DC INPUT (V) V – DC INPUT (V) IN IN Figure 20. RMS Noise Voltage vs. V DC Input Figure 18. IIN vs. VIN− DC Input IN 0 V = V = 5 V DD1 DD2 V = V = 5V DD1 DD2 –20 –40 MCLKIN = 5MHz –60 MCLKIN = 10MHz –80 MCLKIN = 16MHz –100 –120 0.1 1 10 100 1000 RIPPLE FREQUENCY (kHz) Figure 19. CMRR vs. Common-Mode Ripple Frequency Rev. C | Page 12 of 20 CMRR (dB) I (µA) IN –0.35 –0.30 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 07332-018 07332-019 NOISE (mV) –0.30 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 07332-020 AD7401A TERMINOLOGY Total Harmonic Distortion (THD) Differential Nonlinearity (DNL) THD is the ratio of the rms sum of harmonics to the DNL is the difference between the measured and the ideal 1 fundamental. For the AD7401A, it is defined as LSB change between any two adjacent codes 2 2 2 2 2 in the ADC. + + + + V V V V V 2 3 4 5 6 THD(dB)= 20log V Integral Nonlinearity (INL) 1 INL is the maximum deviation from a straight line passing where: through the endpoints of the ADC transfer function. The V1 is the rms amplitude of the fundamental. endpoints of the transfer function are specified negative full V2, V3, V4, V5, and V6 are the rms amplitudes of the second scale, −250 mV (VIN+ − VIN−), Code 7169 for the 16-bit level, through the sixth harmonics. and specified positive full scale, +250 mV (VIN+ − VIN−), Code Peak Harmonic or Spurious Noise 58366 for the 16-bit level. Peak harmonic or spurious noise is defined as the ratio of the Offset Error rms value of the next largest component in the ADC output Offset error is the deviation of the midscale code (32768 for the spectrum (up to fS/2, excluding dc) to the rms value of the 16-bit level) from the ideal V + − V − (that is, 0 V). IN IN fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but Gain Error for ADCs where the harmonics are buried in the noise floor, The gain error includes both positive full-scale gain error and it is a noise peak. negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58366 for the Common-Mode Rejection Ratio (CMRR) 16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the CMRR is defined as the ratio of the power in the ADC output offset error is adjusted out. Negative full-scale gain error is the at ±250 mV frequency, f, to the power of a 250 mV p-p sine deviation of the specified negative full-scale code (7169 for the wave applied to the common-mode voltage of VIN+ and VIN− 16-bit level) from the ideal V + − V − (−250 mV) after the IN IN of frequency, fS, as offset error is adjusted out. Gain error includes reference error. CMRR (dB) = 10 .log(Pf/PfS) Signal-to-(Noise and Distortion) Ratio (SINAD) where: SINAD is the measured ratio of signal-to-noise and distortion Pf is the power at frequency, f, in the ADC output. at the output of the ADC. The signal is the rms amplitude of the Pf is the power at frequency, f , in the ADC output. S S fundamental. Noise is the sum of all nonfundamental signals up Power Supply Rejection Ratio (PSRR) to half the sampling frequency (f /2), excluding dc. The ratio is S Variations in power supply affect the full-scale transition but dependent on the number of quantization levels in the digitization not the converter’s linearity. PSRR is the maximum change in process; the more levels, the smaller the quantization noise. The the specified full-scale (±250 mV) transition point due to a theoretical signal-to-(noise and distortion) ratio for an ideal change in power supply voltage from the nominal value (see N-bit converter with a sine wave input is given by Figure 6). Signal-to-(Noise and Distortion) = (6.02N + 1.76) dB Isolation Transient Immunity Therefore, for a 12-bit converter, this is 74 dB. The isolation transient immunity specifies the rate of rise/fall of Effective Number of Bits (ENOB) a transient pulse applied across the isolation boundary beyond ENOB is defined by which clock or data is corrupted. The AD7401A was tested using a transient pulse frequency of 100 kHz. ENOB = (SINAD − 1.76)/6.02 bits Rev. C | Page 13 of 20 AD7401A THEORY OF OPERATION A differential input of 320 mV results in a stream of, ideally, all CIRCUIT INFORMATION 1s. This is the absolute full-scale range of the AD7401A, and The AD7401A isolated Σ-Δ modulator converts an analog input 200 mV is the specified full-scale range, as shown in Table 9. signal into a high speed (20 MHz maximum), single-bit data stream; the time average single-bit data from the modulators Table 9. Analog Input Range is directly proportional to the input signal. Figure 23 shows a Analog Input Voltage Input typical application circuit where the AD7401A is used to provide Full-Scale Range +640 mV isolation between the analog input, a current sensing resistor, Positive Full Scale +320 mV and the digital output, which is then processed by a digital filter Positive Typical Input Range +250 mV to provide an N-bit word. Positive Specified Input Range +200 mV Zero 0 mV ANALOG INPUT Negative Specified Input Range −200 mV The differential analog input of the AD7401A is implemented Negative Typical Input Range −250 mV with a switched capacitor circuit. This circuit implements a Negative Full Scale −320 mV second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKIN) To reconstruct the original information, this output needs to be provides the clock signal for the conversion process as well as digitally filtered and decimated. A sinc3 filter is recommended the output data-framing clock. This clock source is external because this is one order higher than that of the AD7401A modu- on the AD7401A. The analog input signal is continuously lator. If a 256 decimation rate is used, the resulting 16-bit word sampled by the modulator and compared to an internal rate is 62.5 kHz, assuming a 16 MHz external clock frequency. voltage reference. A digital stream that accurately represents Figure 22 shows the transfer function of the AD7401A relative the analog input over time appears at the output of the to the 16-bit output. converter (see Figure 21). MODULATOR OUTPUT 65535 +FS ANALOG INPUT 53248 –FS ANALOG INPUT SPECIFIED RANGE ANALOG INPUT Figure 21. Analog Input vs. Modulator Output A differential signal of 0 V results (ideally) in a stream of alter- 12288 nating 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time (for a +250 mV input, the output stream is high 89.06% of 0 the time). A differential input of −200 mV produces a stream of –320mV –200mV +200mV +320mV 1s and 0s that are high 18.75% of the time (for a −250 mV ANALOG INPUT input, the output stream is high 10.94% of the time). Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED NONISOLATED 5V 5V/3V AD7401A V V V DD1 DD2 DD SINC3 FILTER* Σ-∆ CS MOD/ V + MDAT MDAT IN ENCODER DECODER + SCLK INPUT CURRENT MCLKIN MCLK V – IN SDAT R SHUNT DECODER ENCODER GND GND GND 1 2 *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP. Figure 23. Typical Application Circuit Rev. C | Page 14 of 20 07332-021 ADC CODE 07332-023 07332-022 AD7401A DIFFERENTIAL INPUTS CURRENT SENSING APPLICATIONS The analog input to the modulator is a switched capacitor The AD7401A is ideally suited for current sensing applications design. The analog signal is converted into charge by highly where the voltage across a shunt resistor is monitored. The load linear sampling capacitors. A simplified equivalent circuit current flowing through an external shunt resistor produces a diagram of the analog input is shown in Figure 24. A signal voltage at the input terminals of the AD7401A. The AD7401A source driving the analog input must be able to provide the provides isolation between the analog input from the current charge onto the sampling capacitors every half MCLKIN cycle sensing resistor and the digital outputs. By selecting the appro- and settle to the required accuracy within the next half cycle. priate shunt resistor value, a variety of current ranges can be monitored. φA Choosing R SHUNT 1kΩ φB V + IN 2pF The shunt resistor values used in conjunction with the AD7401A are determined by the specific application requirements in 2pF φA terms of voltage, current, and power. Small resistors minimize 1kΩ φB V – IN power dissipation, while low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce φA φB φA φB current variations. The final values chosen are a compromise MCLKIN between low power dissipation and good accuracy. Low value Figure 24. Analog Input Equivalent Circuit resistors have less power dissipated in them, but higher value Because the AD7401A samples the differential voltage across resistors may be required to utilize the full input range of the its analog inputs, low noise performance is attained with an ADC, thus achieving maximum SNR performance. input circuit that provides low common-mode noise at each When the peak sense current is known, the voltage range of the input. The amplifiers used to drive the analog inputs play a AD7401A (±200 mV) is divided by the maximum sense current critical role in attaining the high performance available from the to yield a suitable shunt value. If the power dissipation in the AD7401A. shunt resistor is too large, the shunt resistor can be reduced When a capacitive load is switched onto the output of an op and less of the ADC input range is used. Using less of the ADC amp, the amplitude momentarily drops. The op amp tries to input range results in performance that is more susceptible to correct the situation and, in the process, hits its slew rate limit. noise and offset errors because offset errors are fixed and are This nonlinear response, which can cause excessive ringing, thus more significant when smaller input ranges are used. can lead to distortion. To remedy the situation, a low-pass RC RSHUNT must be able to dissipate the I2R power losses. If the filter can be connected between the amplifier and the input power dissipation rating of the resistor is exceeded, its value to the AD7401A. The external capacitor at each input aids may drift or the resistor may be damaged, resulting in an open in supplying the current spikes created during the sampling circuit. This can result in a differential voltage across the ter- process, and the resistor isolates the op amp from the transient minals of the AD401A in excess of the absolute maximum nature of the load. ratings. If I has a large high frequency component, take SENSE The recommended circuit configuration for driving the care to choose a resistor with low inductance. differential inputs to achieve best performance is shown in VOLTAGE SENSING APPLICATIONS Figure 25. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one The AD7401A can also be used for isolated voltage monitoring. input to be effectively supplied by the other input. The series For example, in motor control applications, it can be used to resistor again isolates any op amp from the current spikes sense bus voltage. In applications where the voltage being moni- created during the sampling process. Recommended values for tored exceeds the specified analog input range of the AD7401A, the resistors and capacitor are 22 Ω and 47 pF, respectively. a voltage divider network can be used to reduce the voltage to R be monitored to the required range. V + IN C AD7401A R V – IN Figure 25. Differential Input RC Network Rev. C | Page 15 of 20 07332-025 07332-024 AD7401A /*`Data is read on negative clk edge*/ DIGITAL FILTER module DEC256SINC24B(mdata1, mclk1, reset, The overall system resolution and throughput rate is determined DATA); by the filter selected and the decimation rate used. The higher input mclk1; /*used to clk filter*/ the decimation rate, the greater the system accuracy, as illus- input reset; /*used to reset filter*/ trated in Figure 26. However, there is a tradeoff between accuracy input mdata1; /*ip data to be filtered*/ and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. Note that for a given output [15:0] DATA; /*filtered op*/ bandwidth requirement, a higher MCLKIN frequency can allow integer location; for higher decimation rates to be used, resulting in higher SNR integer info_file; performance. reg [23:0] ip_data1; reg [23:0] acc1; 90 reg [23:0] acc2; SINC3 80 reg [23:0] acc3; 70 reg [23:0] acc3_d1; SINC2 reg [23:0] acc3_d2; 60 reg [23:0] diff1; 50 reg [23:0] diff2; 40 reg [23:0] diff3; SINC1 30 reg [23:0] diff1_d; 20 reg [23:0] diff2_d; 10 reg [15:0] DATA; 0 reg [7:0] word_count; 1 10 100 1k reg word_clk; DECIMATION RATE reg init; Figure 26. SNR vs. Decimation Rate for Different Filter Types A sinc3 filter is recommended for use with the AD7401A. This /*Perform the Sinc ACTION*/ filter can be implemented on an FPGA or a DSP. always @ (mdata1) 3 DR ⎛( )⎞ 1− Z if(mdata1==0) ⎜ ⎟ H(z)= ⎜ −1 ⎟ ip_data1 <= 0; /* change from a 0 () 1− Z ⎝ ⎠ to a -1 for 2's comp */ else where DR is the decimation rate. ip_data1 <= 1; The following Verilog code provides an example of a sinc3 filter /*ACCUMULATOR (INTEGRATOR) implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code Perform the accumulation (IIR) at the speed can possibly be compiled for another FPGA, such as an Altera® of the modulator. device. Note that the data is read on the negative clock edge in this case, although it can be read on the positive edge, if MCLKIN preferred. ACC1+ ACC2+ ACC3+ IP_DATA1 Z Z Z + + + Figure 27. Accumulator Rev. C | Page 16 of 20 SNR (dB) 07332-026 07332-027 AD7401A Z = one sample delay Z = one sample delay MCLKOUT = modulators conversion bit rate WORD_CLK = output word rate */ */ always @ (posedge mclk1 or posedge reset) if (reset) always @ (posedge word_clk or posedge reset) begin if(reset) /*initialize acc registers on reset*/ begin acc1 <= 0; acc3_d2 <= 0; acc2 <= 0; diff1_d <= 0; acc3 <= 0; diff2_d <= 0; end diff1 <= 0; else diff2 <= 0; begin diff3 <= 0; /*perform accumulation process*/ end acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; else acc3 <= acc3 + acc2; begin end diff1 <= acc3 - acc3_d2; /*DECIMATION STAGE (MCLKOUT/ WORD_CLK) diff2 <= diff1 - diff1_d; */ diff3 <= diff2 - diff2_d; always @ (negedge mclk1 or posedge reset) acc3_d2 <= acc3; if (reset) diff1_d <= diff1; word_count <= 0; diff2_d <= diff2; else end word_count <= word_count + 1; /* Clock the Sinc output into an output always @ (word_count) register word_clk <= word_count[7]; /*DIFFERENTIATOR ( including decimation WORD_CLK stage) Perform the differentiation stage (FIR) at a DIFF3 DATA lower speed. Figure 29. Clocking Sinc Output into an Output Register DIFF1 DIFF2 DIFF3 + + + ACC3 WORD_CLK = output word rate – – – – –1 –1 –1 Z Z Z */ always @ (posedge word_clk) WORD_CLK begin Figure 28. Differentiator DATA[15] <= diff3[23]; DATA[14] <= diff3[22]; DATA[13] <= diff3[21]; DATA[12] <= diff3[20]; DATA[11] <= diff3[19]; DATA[10] <= diff3[18]; DATA[9] <= diff3[17]; DATA[8] <= diff3[16]; DATA[7] <= diff3[15]; DATA[6] <= diff3[14]; DATA[5] <= diff3[13]; DATA[4] <= diff3[12]; DATA[3] <= diff3[11]; DATA[2] <= diff3[10]; DATA[1] <= diff3[9]; DATA[0] <= diff3[8]; end endmodule Rev. C | Page 17 of 20 07332-028 07332-029 AD7401A APPLICATIONS INFORMATION These tests subjected devices to continuous cross-isolation GROUNDING AND LAYOUT voltages. To accelerate the occurrence of failures, the selected Supply decoupling with a value of 100 nF is recommended on test voltages were values exceeding those of normal use. The both V and V . In applications involving high common- DD1 DD2 time-to-failure values of these units were recorded and used mode transients, care should be taken to ensure that board to calculate acceleration factors. These factors were then used coupling across the isolation barrier is minimized. Further- to calculate the time-to-failure under normal operating more, the board layout should be designed so that any coupling conditions. The values shown in Table 7 are the lesser of the that occurs equally affects all pins on a given component side. following two values: Failure to ensure this may cause voltage differentials between • The value that ensures at least a 50-year lifetime of pins to exceed the absolute maximum ratings of the device, continuous use. thereby leading to latch-up or permanent damage. Any decoupling • The maximum CSA/VDE approved working voltage. used should be placed as close to the supply pins as possible. Series resistance in the analog inputs should be minimized to It should also be noted that the lifetime of the AD7401A varies avoid any distortion effects, especially at high temperatures. If according to the waveform type imposed across the isolation possible, equalize the source impedance on each analog input to barrier. The iCoupler insulation structure is stressed differently minimize offset. Beware of mismatch and thermocouple effects depending on whether the waveform is bipolar ac, unipolar ac, on the analog input PCB tracks to reduce offset drift. or dc. Figure 30, Figure 31, and Figure 32 illustrate the different isolation voltage waveforms. EVALUATING THE AD7401A PERFORMANCE An AD7401A evaluation board is available with split ground RATED PEAK VOLTAGE planes and a board split beneath the AD7401A package to ensure isolation. This board allows access to each pin on the 0V device for evaluation purposes. The evaluation board package includes a fully assembled and Figure 30. Bipolar AC Waveform tested evaluation board, documentation, and software for controlling the board from the PC via the EVAL-CED1Z. The RATED PEAK VOLTAGE software also includes a sinc3 filter implemented on an FPGA. The evaluation board is used in conjunction with the EVAL- CED1Z board and can also be used as a standalone board. The 0V software allows the user to perform ac (fast Fourier transform) Figure 31. Unipolar AC Waveform and dc (histogram of codes) tests on the AD7401A. The soft- ware and documentation are on a CD that is shipped with the evaluation board. RATED PEAK VOLTAGE INSULATION LIFETIME All insulation structures, subjected to sufficient time and/or 0V voltage, are vulnerable to breakdown. In addition to the testing Figure 32. DC Waveform performed by the regulatory agencies, Analog Devices has carried out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7401A. Rev. C | Page 18 of 20 07332-032 07332-031 07332-030 AD7401A OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 8 10.00 (0.3937) 1.27 (0.0500) 45° BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7401AYRWZ −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16 AD7401AYRWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16 EVAL-AD7401AEDZ Evaluation Board EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part. Rev. C | Page 19 of 20 5 (0.029 0.7 5) 0 .0098) .25 (0 03-27-2007-B AD7401A NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07332-0-7/11(C) Rev. C | Page 20 of 20