Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module • Up to 4 Million Equivalent System Gates or 500 k Equivalent Redundancy (TMR) ASIC Gates – Immune to Single-Event Upsets (SEU) to LET > 37 MeV- • Up to 20,160 SEU-Hardened Flip-Flops TH 2 cm /mg • Up to 840 I/Os with SEU-Protected Input, Output, and Enable -10 – SEU Rate < 10 Errors/Bit-Day (worst case GEO) Registers -10 • SRAM Upset Rate of <10 Errors/Bit-Day with Use of Error • Up to 540 kbits Embedded SRAM Detection and Correction (EDAC) IP (included) with Integrated • Manufactured on 0.15 µm CMOS Antifuse Process Technology, SRAM Scrubber 7 Layers of Metal – Single-Bit Correction, Double-Bit Detection • Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883, – Variable-Rate Background Refreshing TM3015) • Total Ionizing Dose Up to 300 krad (Si, Functional) Embedded Multiply/Accumulate Blocks • Single-Event Latch-Up Immunity (SEL) to LET > 117 MeV- TH 2 cm /mg (RTAX-DSP Only) • TM1019 Test Data Available • Up to 120 Multiply/Accumulate Blocks • Fully SEU- and SET-Hardened Processing Flows • 125 MHz Performance throughout Military Temperature Range • B-Flow – MIL-STD-883B • Flexible, Cascadable Accumulate Function • E-Flow – Extended Flow • EV-Flow – Class V Equivalent Flow Processing Consistent with Features MIL-PRF 38535 • Single-Chip, Nonvolatile Solution • 1.5 V Core Voltage for Low Power Prototyping Options ® • Flexible, Multi-Standard I/Os: • Commercial Axcelerator Devices for Functional Verification – 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation (RTAX™-S/SL only) – Bank-Selectable I/Os – 8 Banks per Chip • RTAX-S PROTO and RTAX-DSP PROTO Devices with Same – Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI Functional and Timing Characteristics as Flight Unit in a Non- – JTAG Boundary Scan Testing (as per IEEE 1149.1) Hermetic Package – Differential I/O Standards: LVPECL and LVDS ® • Low-Priced Reprogrammable ProASIC 3 Option for Functional – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, Verification (RTAX-S/SL only) SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 RTAX-SL Low Power Option – Hot-Swap with Cold-Sparing Support (Except PCI) • Embedded Memory with Variable Aspect Ratio: • Offers Up To 80% Saving of Static Current Compared to – Independent, Width-Configurable Read and Write Ports Standard RTAX-S Device at Worst-Case Conditions – Programmable Embedded FIFO Control Logic Leading-Edge Performance – ROM Emulation Capability • Deterministic, User-Controllable Timing • High-Performance Embedded FIFOs • Unique In-System Diagnostic and Debug Capability • 350+ MHz System Performance • 500+ MHz Internal Performance • 700 Mb/s LVDS Capable I/Os Table 1 • RTAX Family Product Profile Device RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL Capacity Equivalent System Gates 250,000 1,000,000 2,000,000 4,000,000 2,000,000 4,000,000 ASIC Gates 125,000 250,000 500,000 250,000 500,000 30,000 Modules Register (R-cells) 1,408 6,048 10,752 20,160 9,856 18,480 Combinatorial (C-cells) 2,816 12,096 21,504 40,320 19,712 36,960 Embedded RAM/FIFO (w/o EDAC) Core RAM Blocks 12 36 64 120 64 120 Core RAM Bits (K = 1,024) 54 k 162 k 288 k 540 k 288 k 540 k Embedded Multiply/Accumulate – – – – 64 120 Blocks Clocks (segmentable) Hardwired 4 4 4 4 4 4 Routed 4 4 4 4 4 4 I/Os I/O Banks 8 8 8 8 8 8 User I/Os (maximum) 198 418 684 840 684 840 I/O Registers 744 1,548 2,052 2,520 2,052 2,520 Package CCGA/LGA* 624 624 624, 1152 1272 1272 1272 CQFP 208, 352 352 256, 352 352 352 352 Note: *The body size of the 1272-pin CCGA and LGA packages used on the RTAX-DSP devices is slightly larger than the body size of the 1272- pin CCGA and LGA used on the RTAX4000S/SL devices. October 2011 i © 2011 Microsemi Corporation Ordering Information _ RTAX2000S 1 CGS 624 B Screening Level B = MIL-STD 883 Class B E = E-Flow (Microsemi Space-Level Flow) EV = Class V Equivalent Flow Processing Consistent with MIL-PRF-38535 = PROTO Prototype Unit; not for Space Flight or Qualification of Space-Flight Hardware Package Lead Count Package Type CQ = Ceramic Quad Flat Pack CG = Ceramic Column Grid Array (RTAX-S/SL) = CGD Ceramic Column Grid Array (RTAX-DSP) = LG Land Grid Array (RTAX-S/SL) = LGD Land Grid Array (RTAX-DSP) S = Six Sigma Column Speed Grade Blank = Standard Speed = 1 Approximately 15% Faster than Standard (applies to RTAX250S/SL, RTAX1000S/SL. RTAX2000S/SL, RTAX2000D/DL FPGA Logic) = 1 Approximately 10% Faster than Standard (applies to RTAX4000S/SL, RTAX4000D/DL FPGA Logic) Part Number S = Standard Device SL = Low-Power Option = D DSP Device = DL Low-Power Option for DSP Device RTAX250S/SL = 250,000 Equivalent System Gates RTAX1000S/SL = 1,000,000 Equivalent System Gates RTAX2000S/SL = 2,000,000 Equivalent System Gates RTAX4000S/SL = 4,000,000 Equivalent System Gates RTAX2000D/DL = 2,000,000 Equivalent System Gates RTAX4000D/DL = 4,000,000 Equivalent System Gates Note: All parts in Column Grid Array packages are now supplied with only Six Sigma solder columns. Screening Levels Package RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL CQ208 B, E, EV, PROTO – – – – – CQ256 – – B, E, EV, PROTO – – – CQ352 B, E, EV, PROTO B, E, EV, PROTO B, E, EV, PROTO B, E, EV, PROTO B, E, EV, PROTO B, E, EV, PROTO CG624/LG624 B, E, EV, PROTO B, E, EV, PROTO B, E, EV, PROTO – – – CG1152/LG1152 – – B, E, EV, PROTO – – – CG1272/LG1272 – – – B, E, EV, PROTO – – CGD1272/LGD1272 – – – – B, E, EV, PROTO B, E, EV, PROTO Note: B = MIL-STD-883 Class B E = E-Flow (Space-Level Flow) EV = "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535) PROTO = Prototype unit; not for space flight or qualification of space-flight hardware. ii Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs RTAX-S/SL and RTAX-DSP Device Status RTAX-S/SL or RTAX-DSP Device Status RTAX250S Production RTAX250SL Production RTAX1000S Production RTAX1000SL Production RTAX2000S Production RTAX2000SL Production RTAX4000S Production RTAX4000SL Production RTAX2000D Production RTAX4000D Production RTAX2000DL Production RTAX4000DL Production Speed Grade and Temperature Grade Matrix Temperature RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL STD ✓✓ ✓ ✓ ✓ ✓ –1 ✓✓ ✓ ✓ ✓ ✓ Notes: 1. Data applies to B, E, EV, and PROTO flow devices. 2. Contact your Microsemi representative for availability. Device Resources User I/Os (Including Clock Buffers) Device RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL CQ208 115 – – – – – CQ256 –– 136 – – – 1 1 CQ352 198 198 198 166 166 166 CG624/LG624 232 418 418 – – – CG1152/LG1152 –– 684 – – – CG1272/LG1272 – – – 840 – – 2 CGD1272/LGD1272 –– – – 684 840 CQ = Ceramic Quad Flat Pack, CG= Ceramic Column Grid Array, and LG = Land Grid Array Notes: 1. RTAX2000S/SL and RTAX2000D/DL are not pin compatible in the CQ352 package type. 2. The package overhang for RTAX4000D/DL is slightly larger than RTAX4000S/SL, but they are pin compatible. Revision 14 iii I/Os per Package Adjacent Non-Adjacent 1 2 3 Package Device Single-Ended Differential Pairs Differential Pairs Total I/Os CQ208 RTAX250S 7 41 13 115 CQ256 RTAX2000S 4 66 0 136 CQ352 RTAX250S 2 98 0 198 RTAX1000S 2 98 0 198 RTAX2000S 2 98 0 198 RTAX4000S 4 81 0 166 RTAX2000D 4 81 0 166 RTAX4000D 4 81 0 166 CG624 / LG624 RTAX250S 0 124 0 248 RTAX1000S 68 170 5 418 RTAX2000S 52 178 5 418 CG1152 / LG1152 RTAX2000S 0 342 0 684 CG1272/ LG1272 RTAX4000S 0 420 0 840 CGD1272 / LGD1272 RTAX2000D 0 342 0 684 RTAX4000D 0 420 0 840 Notes: 1. Single-ended I/Os can implement only single ended I/O standards. 2. Adjacent differential pairs are pairs of I/Os that are physically adjacent and can implement differential I/O standards as well as single-ended I/O standards. 3. Non-adjacent differential pairs are pairs of I/Os that can implement differential I/O standards as well as single-ended I/O standards but are not physically adjacent. 4. The total number of I/Os is calculated by adding the single-ended I/Os, double the number of adjacent differential pairs, and double the number of non-adjacent differential pairs. iv Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs MIL-STD-883 Class B Product Flow 1, 2 Table 2 • MIL-STD-883 Class B Product Flow for RTAX-S/SL and RTAX-DSP Step Screen Method Requirement 1 Internal Visual 2010, Condition B 100% 2 Serialization 100% 3 Temperature Cycling 1010, Condition C, 10 cycles minimum 100% 4 Constant Acceleration 2001, Y1 Orientation Only 100% Condition B for CQ256, CQ352, LG624, LG1152 Condition D for CQ208 3 Condition A for LG1272, LGD1272, CQ352 5 Particle Impact Noise Detection 2020, Condition A 100% 6 Seal (Fine & Gross Leak Test) 1014 100% 7 Pre-Burn-In Electrical Parameters In accordance with applicable Microsemi device 100% specification 8 Dynamic Burn-In 1015, Condition D, 100% 160 hours at 125°C or 80 hours at 150°C minimum 9 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device 100% specification 10 Percent Defective Allowable (PDA) Calculation 5% All Lots 2 11 Final Electrical Test In accordance with applicable Microsemi device 100% specification, which includes a, b, and c: a. Static Tests 5005, Table 1, Subgroup 1 (1) 25°C 5005, Table 1, Subgroup 2, 3 (2) –55°C and +125°C b. Functional Tests 5005, Table 1, Subgroup 7 (1) 25°C 5005, Table 1, Subgroup 8a, 8b (2) –55°C and +125°C 5005, Table 1, Subgroup 9 c. Switching Tests at 25°C 12 External Visual 2009 100% Notes: 1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 2. RTAX-S and RTAX-SL devices, as well as RTAX-D and RTAX-DL devices, have the same silicon and are distinguished by screening the ICCA current limits at 125°C final electrical test. 3. Condition A applies to RTAX4000S/SL, RTAX2000D/DL, and RTAX4000D/DL packages only. Revision 14 v Extended Flow 1, 2, 3, 4 Table 3 • Extended Flow for RTAX-S/SL and RTAX-DSP Step Screen Method Requirement 5 1 Destructive Bond Pull 2011, Condition D Extended Sample 2 Internal Visual 2010, Condition A 100% 3 Serialization 100% 4 Temperature Cycling 1010, Condition C, 10 cycles minimum 100% 5 Constant Acceleration 2001, Y1 Orientation Only Condition B for CQ256, CQ352, LG624, LG1152 Condition D for CQ208 5 Condition A for LG1272, LGD1272, CQ352 6 Particle Impact Noise Detection 2020, Condition A 100% 7 Radiographic (X-Ray) 2012, One View (Y1 Orientation) Only 100% 8 Pre-Burn-In Electrical Parameters In accordance with applicable Microsemi device specification 9 Dynamic Burn-In 1015, Condition D, 100% 240 hours at 125°C or 120 hours at 150°C minimum 10 Interim (Post-Dynamic-Burn-In) Electrical In accordance with applicable Microsemi device 100% Parameters specification 11 Static Burn-In 1015, Condition C, 72 hours at 150°C or 144 hours at 125°C 100% minimum 12 Interim (Post-Static-Burn-In) Electrical Parameters In accordance with applicable Microsemi device 100% specification 13 Percent Defective Allowable (PDA) Calculation 5% Overall, 3% Functional Parameters at 25°C All Lots 4 14 Final Electrical Test In accordance with applicable Microsemi device 100% specification, which includes a, b, and c: a. Static Tests 5005, Table 1, Subgroup 1 (1) 25°C 5005, Table 1, Subgroup 2, 3 (2) –55°C and +125°C b. Functional Tests 5005, Table 1, Subgroup 7 (1) 25°C 5005, Table 1, Subgroup 8a, 8b (2) –55°C and +125°C 5005, Table 1, Subgroup 9 c. Switching Tests at 25°C 15 Seal (Fine & Gross Leak Test) 1014 100% 16 External Visual 2009 100% Notes: 1. Microsemi offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Microsemi is offering this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. 2. The Quality Conformance Inspection (QCI) for Extended Flow devices still comply to MIL-STD-833, Class B requirement. 3. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 4. RTAX-S and RTAX-SL devices, as well as RTAX-D and RTAX-DL devices, have the same silicon and are distinguished by screening the ICCA current limits at 125°C final electrical test. 5. Condition A applies to RTAX4000S/SL, RTAX2000D/DL, and RTAX4000D/DL packages only. 6. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis. vi Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs "EV" Flow (Class V Flow Equivalent Processing) 1, 2, 3 Table 4 • "EV" Flow (Class V Equivalent Flow Processing) for RTAX-S/SL and RTAX-DSP Step Screen Method Requirement 4 1 Destructive Bond Pull 2011, Condition D Extended Sample 2 Internal Visual 2010, Condition A 100% 3 Serialization 100% 4 Temperature Cycling 1010, Condition C, 50 cycles minimum 100% 5 Constant Acceleration 2001, Y1 Orientation Only 100% Condition B for CQ256, CQ352, LG624, LG1152 Condition D for CQ208 5 Condition A for LG1272, LGD1272, CQ352 6 Particle Impact Noise Detection 2020, Condition A 100% 7 Radiographic (X-Ray) 2012, One View (Y1 Orientation) Only 100% 8 Pre-Burn-In Electrical Parameters In accordance with applicable Microsemi device 100% specification 9 Dynamic Burn-In 1015, Condition D, 100% 240 hours at 125°C or 120 hours at 150°C minimum 10 Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance with applicable Microsemi device 100% specification 11 Static Burn-In 1015, Condition C, 72 hours at 150°C or 144 hours at 100% 125°C minimum 12 Interim (Post-Static-Burn-In) Electrical Parameters In accordance with applicable Microsemi device 100% specification 13 Percent Defective Allowable (PDA) Calculation 5% Overall, 3% Functional Parameters at 25°C All Lots 3 14 Final Electrical Test In accordance with applicable Microsemi device 100% specification, which includes a, b, and c: a. Static Tests 5005, Table 1, Subgroup 1 (1) 25°C 5005, Table 1, Subgroup 2, 3 (2) –55°C and +125°C b. Functional Tests 5005, Table 1, Subgroup 7 (1) 25°C 5005, Table 1, Subgroup 8a, 8b (2) –55°C and +125°C 5005, Table 1, Subgroup 9 c. Switching Tests at 25°C 15 Seal (Fine & Gross Leak Test) 1014 100% 16 External Visual 2009 100% 17 Wafer Lot Specific Life Test (Group C) MIL-PRF-38535, Appendix B, sec. B.4.2.c All Wafer Lots Notes: 1. Microsemi offers "EV" flow for users requiring full compliance to MIL-PRF-38535 class V requirement. The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow devices) with the intention to be in full compliance to MIL-PRF-38535 Table IA and Appendix B requirement, but without the official class V certification from DSCC. 2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 3. RTAX-S and RTAX-SL devices, as well as RTAX-D and RTAX-DL devices have the same silicon and are distinguished by screening the I CCA current limits at 125°C final electrical test. 4. Condition A applies to RTAX4000S/SL, RTAX2000D/DL, and RTAX4000D/DL packages only. 5. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis Revision 14 vii RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Mathblock Multiply-Accumulate Function (RTAX-DSP only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 RTAX-DSP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Low-Cost Prototyping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Detailed Specifications Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Mathblock Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-136 Package Pin Assignments CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 CQ352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 CG624/LG624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 CG1152/LG1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 CG1272/LG1272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Related Documents Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 User’s Guides and Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 White Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Revision 14 ix 1 – General Description RTAX-S/SL and RTAX-DSP FPGAs offer high performance at densities of up to four million equivalent ® system gates for space-based applications. Based upon the Microsemi commercial Axcelerator family, RTAX-S/SL and RTAX-DSP have several system-level features such as embedded SRAM (with built-in FIFO control logic), segmentable clocks, chip-wide highway routing, and carry logic. Featuring SEU-hardened flip-flops that offer the benefits of user-implemented Triple Module Redundancy (TMR) without the associated overhead, the RTAX-S/SL and RTAX-DSP families are the second generation of Microsemi’s products for space applications. RTAX-S/SL and RTAX-DSP devices are manufactured using a 0.15 µm technology at a UMC facility in Taiwan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. Device Architecture RTAX-S/SL architecture, derived from the highly-successful A54SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike traditional FPGAs, the entire floor of the RTAX-S/SL or RTAX-DSP device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element The RTAX-S/SL and RTAX-DSP families use a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, low-impedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the RTAX architecture abundant routing resources. Routing Switch Matrix Logic Block Sea-of-Modules Architecture Traditional FPGA Architecture Logic Modules Figure 1-1 • Sea-of-Modules Comparison Revision 14 1-1 General Description Figure 1-2 • RTAX Interconnect Elements The very nature of nonvolatile antifuse technology provides excellent protection against design pirating ® and cloning (FuseLock technology). Typical cloning attempts are impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see the "Security" section on page 2-135). Microsemi's RTAX architecture provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The RTAX C-cell can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). The C-cell contains carry logic for even more efficient implementation of arithmetic functions. With its small size, the C-cell structure is extremely synthesis- friendly, simplifying the overall design as well as reducing design time. While each SEU-hardened R-cell appears as a single D-Type flip-flop to the user, each is implemented in 2 silicon using triple redundancy to achieve a LET threshold of greater than 60 MeV-mg/cm . Each TMR R- cell consist of three master-slave latch pairs, each with asynchronous self-correcting feedback paths. The output of each latch on the master or slave side votes with the outputs of the other two latches on that side. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents that change from feeding back and permanently latching. Care was also taken in the layout to ensure that a single ion strike could not affect more than one latch (see the "R-Cell" section on page 2-87 for more details). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure1-3 on page1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual- data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. Two C-cells, a single R-cell, and two Transmit (TX) and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4 on page 1-3). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and- route tool, minimizing system delays while improving logic utilization. The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by- side, giving a C–C–R – C–C–R pattern to the SuperCluster. This C–C–R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). 1-2 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs The RTAX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. FCI A[0:1] D Q PRE B[0:1] E C-cell D[0:3] Y CLK CLR DB CFN (Positive Edge Triggered) FCO C-Cell R-Cell Figure 1-3 • RTAX C-Cell and R-Cell TX TX TX TX C C R C C R RX RX B RX RX Figure 1-4 • RTAX SuperCluster FCI DCOUT C-Cell C-Cell Y Y Carry Logic FCO Figure 1-5 • RTAX Two-Bit Carry Logic Revision 14 1-3 General Description At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the RTAX1000S/SL is composed of a 3×3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the RTAX250S/SL). The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6). SuperCluster TX TX TX TX C C R C C R RX RX B RX RX RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC 4k RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAM/ RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC FIFO RAMC SC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC 4k RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAM/ SC SC SC SC SC SC RD RAMC SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC FIFO RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC 4k RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC Chip Layout RAM/ RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC FIFO RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC Core T SC SC ile SC SC SC 4k RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAM/ RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC FIFO RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC I/O Structure Figure 1-6 • RTAX Device Architecture (RTAX1000S/SL shown) Table 1-1 • Number of Core Tiles per Device Device Number of Core Tiles RTAX250S/SL 4 smaller tiles RTAX1000S/SL 9 regular tiles RTAX2000S/SL, RTAX2000D 16 regular tiles RTAX4000S/SL, RTAX4000D 30 regular tiles 1-4 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. The FIFO control unit was not implemented with SEU-hardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. Also, the pipeline register in each of the memory blocks is not hardened and is susceptible to single event-upsets. Microsemi has enhanced the SEU tolerance of the embedded SRAM within RTAX-S/SL and RTAX-DSP FPGAs by employing the use of two upset-mitigation techniques: • Microsemi has developed Error Detection and Correction (EDAC) IP for use with RTAX-S/SL and RTAX-DSP. EDAC can be accomplished by the use of SmartGen-generated Error Correcting Codes (ECC) IP, which employs the use of shortened Hamming Codes • A background memory-refresher, or scrubber circuitry, which has been embedded into the EDAC IP. The embedded scrubber circuitry periodically refreshes memory in the background to ensure that no data corruption occurs while the memory is not in use. The use of EDAC IP combined with the embedded memory scrubber circuitry, gives RTAX-S/SL and -10 RTAX-DSP FPGAs an SEU radiation performance level of better than 10 errors/bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. Revision 14 1-5 General Description I/O Logic The RTAX-S/SL and RTAX-DSP families of FPGAs feature a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5 V, 1.8 V, 2.5 V, and 3.3 V. In all, RTAX-S/SL and RTAX-DSP FPGAs support at least 14 different I/O standards (single-ended, differential, voltage- referenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see the "User I/Os" section on page 2-16 for more information). All I/O standards are available in each bank. Hot-swap and cold-sparing are supported for all I/O standards except PCI. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. By design, all user flip-flops in the RTAX FPGAs are immune to SEUs including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. I/O Module InReg OutReg EnReg I 4k O RAM/ FIFO B TX TX I/O I/O A I/O Cluster Module Module N RX RX B RX RX 4k K RAM/ FIFO 4k RAM/ FIFO CoreTile 4k RAM/ FIFO Figure 1-7 • I/O Cluster Arrangement 1-6 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Mathblock Multiply-Accumulate Function (RTAX-DSP only) The flexible elements of the RTAX-DSP Mathblocks enable easy integration into many different signal processing topologies, such as Fast Fourier Transforms, Inverse Fast Fourier Transforms, Finite Impulse Response Filters, Infinite Impulse Response Filters, and Discrete Cosine Transforms. The hardwired Mathblocks also enable acceleration of high precision single and double floating point multiplications. Figure 1-8 shows a basic functional diagram of a Mathblock. ADD_SUB OVFL A[17:0] D +/- X SN[40:0] EN B[17:0] >>17 SHIFT17 MUX2 SEL_CONST CONST[40:0] MUX1 SEL_CASC SN-1[40:0] Figure 1-8 • RTAX-DSP Mathblock The Mathblocks comprise the following elements: 1. Multiplier The multiplier operates on two signed 18-bit factors, A[17:0] and B[17:0] (Figure 1-9). The multiplier produces a signed 36-bit output, which is provided as an input to the add/subtract function. The output of the multiplier can optionally bypass the add/subtract function. A[17:0] P[35:0] X B[17:0] Figure 1-9 • RTAX-DSP Mathblock Multiplier Configured as Signed 18x18 The multiplier can be fractured to implement two instances of signed 9x9 multiplication (Figure 1- 10). A1[8:0] P1[17:0] X B1[8:0] A2[8:0] P2[17:0] X B2[8:0] Figure 1-10 • Mathblock Configured with Two Independent Signed 9x9 multipliers Revision 14 1-7 General Description 2. Adder/Subtractor plus MUX Control • The adder/subtractor can perform the following functions: – Accumulate using feedback. – Create higher precision multipliers using the S input and the 17-bit shift function. N-1 – Create complex DSP functions, such as FIR filters, by cascading Mathblocks together using the S input. N-1 – The initial value of the accumulate function can be set using the value defined on the CONST bus. Overflow or underflow of the add/subtract function is indicated by the OVFL output. Figure 1-11 shows the Mathblock configured to perform multiply and accumulate functions. fabric resources can be used to extend the accumulate width. ADD_SUB A[17:0] OVFL +/- X SN[40:0] B[17:0] SEL_CONST CONST[40:0] Figure 1-11 • Mathblock Configured to Perform Multiply and Accumulate Functions 3. Output Register The output of the adder/subtractor block is presented to a 41-bit output register. The register has a clock input, an enable input, a set or reset input, and provides a 41-bit output S [40:0] to the N exterior of the Mathblock. Signals S [40:0] are also fed back within the Mathblock to the N accumulator multiplexer stack to enable various accumulation functions. 4. Cascading Mathblocks Mathblocks may be cascaded together to form complex DSP structures such as FIR filters and FFTs. Figure 1-12 shows the configuration of Mathblocks cascaded together. Next Mathblock A[17:0] X+/- CDOUT2[40:0] B[17:0] Cascade CASC_CTL MUX A[17:0] CDOUT1[40:0] X+/- B[17:0] Cascade MUX Previous Mathblock Figure 1-12 • Mathblocks Cascaded Together as Part of a Complex DSP Function 1-8 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs RTAX-DSP Architecture The overall RTAX-DSP device architecture is shown in Figure 1-13 on page 1-10. In each core tile, there are four Mathblocks, which are located adjacent to the SRAM/FIFO blocks. The Mathblocks are evenly distributed across the device, to help achieve uniform performance of DSP functions. Routing The RTAX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-14 on page 1-10). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R- cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the carry- logic FCO output of one C-cell pair to the carry-logic FCI input of the C-cell pair of the SuperCluster below. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. Global Resources Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). Both these clocks can be segmented, allowing significantly more than eight clock domains to be implemented in the devices. The RTAX1000S/SL, RTAX2000S/SL, RTAX4000S/SL, RTAX2000D, and RTAX4000D devices have 12 HCLK segments per tile and 28 RCLK segments per tile. The RTAX250S/SL has 8 HCLK segments per tile and 22 RCLK segments per tile. Revision 14 1-9 General Description Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. SuperCluster TX TX TX TX C C R C C R RX RX B RX RX Core Tile RAMC DSP I/F SC SC SC SC SC C SC SC SC SC SC S SC SC RD RD R RD SC SC SC SC SC C SC SC SC C SC SC C SC RAMC DSP I/F SC SC C SC SC SC SC SC SC SC SC SC SC RD R RD SC SC SC SC SC SC SC SC SC C SC SC RAMC DSP I/F SC SC SC S SC SC SC S RD RD RD D SC SC SC SC SC SC SC SC SC SC RAMC DSP I/F SC C C C SC SC SC SC S RD RD RD RD SC SC SC SC SC SC SC RAMC DSP I/F SC SC C C C SC SC SC SC C SC SC C R RD SC SC SC SC SC RAMC DSP I/F S SC SC SC C C C C C C C C C C C C C C C C C C C C C SC SC SC SC SC SC SC SC SC SC S SC S SC SC C SC RD SC SC SC SC SC RAMC DSP I/F S S SC SC C C C C C C C C C C C C SC SC SC C SC SC RD SC SC SC SC SC Chip Layout RAMC DSP I/F SC SC SC SC SC SC SC SC SC SC SC SC SC S S S S S SC S S S S S S S S S SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC RD SC SC SC SC SC DSP I/F RAMC DSP I/F SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC RD RAMC DSP I/F SC SC SC SC SC RAMC SC SC SC SC SC RD DSP I/F SC SC SC SC SC RAMC DSP I/F SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC RD SC SC SC SC SC HD HD HD HD HD HD HD HD HD HD SC SC SC SC RD SC SC SC SC SC SC SC SC S SC SC RD SC SC SC SC SC S SC C SC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC C RD RD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC R RD RD S SC SC SC SC S SC C SC SC SC S SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC SC SC S SC SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC S SC SC SC SC SC SC SC SC SC C SC SC SC SC SC SC SC R RD D S SC SC SC S SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC SC SC SC C RD RD D SC SC SC SC SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC S SC SC SC SC SC C SC SC C RAMC SC SC SC SC SC SC SC SC SC SC RD RD S S SC SC SC SC SC RAMC SC SC SC SC SC SC SC SC SC SC SC RD RD S SC SC SC SC SC ADD_SUB RAMC D SC SC SC SC SC SC SC SC SC RD RD D S SC SC SC SC SC A[17:0] OVFL D X + – / I/O Structure S [40:0] N EN B[17:0] SHIFT17 >> 17 SEL_CONST MUX2 CONST[40:0] SEL_CASC MUX1 S [40:0] N-1 Mathblock Figure 1-13 • RTAX-DSP Device Architecture Overview Figure 1-14 • RTAX Routing Structures 1-10 Revision 14 4 k RAM/FIFO 4 k RAM/FIFO 4 k RAM/FIFO 4 k RAM/FIFO DSP Mathblock RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Design Environment ® RTAX-S/SL and RTAX-DSP FPGAs are fully supported by both Microsemi Libero Integrated Design Environment (IDE) and Designer FPGA development software. Microsemi Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Microsemi SoC Products ® ® Group website). Libero IDE includes Synplify AE from Synopsys, ViewDraw AE from Mentor ® ® Graphics , ModelSim HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from ® SynaptiCAD , and Designer software from Microsemi. Microsemi's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: • SmartTime – a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route • NetlistViewer – a design netlist schematic viewer • ChipPlanner – a graphical floorplanner viewer and editor • SmartPower – allows the designer to quickly estimate the power consumption of a design • PinEditor – a graphical application for editing pin assignments and I/O attributes • I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, the Microsemi back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, the Microsemi integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Microsemi Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI. Factory programming is available for high-volume production needs. Low-Cost Prototyping Solutions Since the enhanced radiation characteristics of radiation-tolerant devices are not required during the prototyping phase of the design, Microsemi has developed two prototyping options for RTAX-S/SL. For early design development and functional verification, Microsemi offers the commercial Axcelerator devices; for final flight design verification in hardware, Microsemi offers RTAX-S PROTO devices that have the same form, fit, and function as the flight silicon. For RTAX-DSP devices, since there are no commercial equivalent devices with embedded Mathblocks, the preferred prototyping method is to use RTAX-DSP PROTO units. Prototyping with Axcelerator Units The prototyping solution using the commercial Axcelerator devices consists of two parts: • A well-documented design flow that allows the customer to target an RTAX-S/SL design to the equivalent commercial Axcelerator device • A set of Microsemi Extender circuit boards that map the commercial device package to the appropriate RTAX-S package footprint This methodology provides the user with a cost-effective solution while maintaining the short time-to- market associated with Microsemi FPGAs. Revision 14 1-11 General Description Prototyping with RTAX-S and RTAX-DSP PROTO Units The RTAX-S and RTAX-DSP PROTO units offer a prototyping solution that can be used for final timing verification of the flight design. The PROTO prototype units have the same timing attributes as the RTAX- S/SL and RTAX-DSP flight units. Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in their part number, and "PROTO" is marked on devices to indicate that they are not intended for space flight. They also are not intended for applications which require the quality of space-flight units, such as qualification of space-flight hardware. RT-PROTO units offer no guarantee of hermeticity, and no MIL- STD-883B processing. At a minimum, users should plan on using class B level devices for all qualification activities. The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full military temperature range. The RT-PROTO units will also be offered in -1 or standard speed grades, so as to enable customers to validate the timing attributes of their space designs using actual flight silicon. Prototyping with ProASIC3E Reprogrammable Units Using Microsemi’s ProASIC3E prototyping solution offers the unique advantage of reprogrammability, resulting in cost savings while providing faster functional verification of designs in prototype stage. This methodology employs a footprint compatible adaptor board and an EDIF netlist and pinout convertor for easy migration. Please see the application note Prototyping for RTAX-S and RTAX-SL Devices for more details. In-System Diagnostic and Debug Capabilities The RTAX-S/SL family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation. Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II (Figure 1-15), the Microsemi integrated verification and logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG port (see the "Silicon Explorer II Probe Interface" section on page 2-136). In addition, Microsemi offers a Configurable Logic Analyzer Module (CLAM), which allows a real-time verification and debug capability to be embedded into IP programmed into Microsemi FPGAs. CLAM allows signals from the inside of the IP core to be routed to the exterior of the chip for verification purposes. Microsemi RTAX-S/SL and RTAX-DSP FPGAs offer enhanced capabilities beyond the successful RTSX-SU family of radiation-tolerant FPGAs, adding embedded RAM, FIFOs, and high-speed I/Os, and in the case of RTAX-DSP, adding embedded Mathblocks for enhanced signal processing. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an RTAX-S/SL or RTAX-DSP design yet still achieve high performance and efficient device utilization in an SEU-hardened device. RTAX-S/SL FPGAs 16-Pin Connection TDI* TCK* Serial TMS* Silicon Explorer II Connection TDO* PRA* PRB* 22-Pin Connection CH3/PRC* CH4/PRD* Additional 14 Channels (Logic Analyzer) Note: *Refer to the "Pin Descriptions" section on page 2-14 for more information. Figure 1-15 • Probe Setup RTAX-S/SL and RTAX-DSP 1-12 Revision 14 2 – Detailed Specifications Table 2-1 • I/O Features Comparison Clamp Hot Insertion / I/O Assignment Diode Cold Sparing 5 V Tolerance Input Buffer Output Buffer 1 1,2 3.3 V LVTTL Yes No Yes Enabled/Disabled 2 3.3 V PCI Yes No Yes Enabled/Disabled LVCMOS 2.5 V No Yes No Enabled/Disabled LVCMOS 1.8 V No Yes No Enabled/Disabled LVCMOS 1.5 V (JESD8-11) No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled 3 Differential, LVDS/LVPECL, Input No Yes No Enabled Disabled 4 Differential, LVDS/LVPECL, Output No Yes No Disabled Enabled Notes: 1. Default setting for the clamp diode is set to be PCI. The LVTTL clamp diode is not enabled by default. To allow 5 V tolerance, the LVTTL clamp diode needs to be enabled using settings in Designer. Hot-insertion and cold-sparing are not supported when the clamp diode is enabled. In other words, 5 V tolerance and hot-swapping/cold-sparing cannot coexist. 2. Can be implemented with an external resistor. 3. The OE input of the output buffer is automatically deasserted by Designer. 4. The OE input of the output buffer is automatically asserted by Designer. 5 V Tolerance 3.3 V PCI and 3.3 V LVTTL (with clamp diode enabled) I/O standards directly allow 5 V tolerance. For example, the 3.3V PCI I/O standard provides an internal clamp diode between the input pad and the VCCI pad so that the voltage at the input pin is clamped below the absolute maximum input voltage of 4.1 V (Table 2-2 on page 2-2). An example of the input pad voltage level is shown in EQ 1: V = VCCI + V = 3.3 V + 0.7 V = 4.0 V input diode EQ 1 The internal VCCI clamp diode is only enabled while the device is powered on, so the voltage at the input will not be clamped if the VCCI or VCCA are powered off. An external series resistor (~100 Ω) is required between the input pin and the 5V signal source to limit the current to less than 20 mA (Figure 2-1).The100 Ω resistor was chosen to meet the input Tr/Tf requirement (Table2-22 on page 2-26). The GND clamp diode is available for all I/O standards and always enabled. 5 V tolerance is not allowable for VCCI greater than 3.3 V or for input signals greater than 5.0 V. Non-Microsemi Part Microsemi FPGA 5 V 3.3 V 3.3 V VCCI Clamp Diode . R ext GND Clamp Diode Figure 2-1 • Use of an External Resistor for 5 V Tolerance Revision 14 2-1 Detailed Specifications Operating Conditions Absolute Maximum Conditions Stresses beyond those listed in Table 2-2 may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions in Table 2-3. Table 2-2 • Absolute Maximum Ratings Symbol Parameter Limits Units T Junction Temperature –55 to +135 °C J 1 VCCA AC Core Supply Voltage –0.3 to 1.8 V VCCA DC Core Supply Voltage –0.3 to 1.7 V 2 VCCI DC I/O Supply Voltage –0.3 to 3.75 V VREF DC I/O Reference Voltage –0.3 to 3.75 V VI Input Voltage –0.5 to 4.1 V VO Output Voltage –0.5 to 3.75 V TSTG Storage Temperature –60 to +150 °C 3 VCCDA Supply Voltage for Differential I/Os –0.3 to 3.75 V Notes: 1. The AC transient VCCA limit is for radiation-induced transients less than 10 µs duration and not intended for repetitive use. Core voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the transient does not exceed 1.8 V at any time and the total time that the transient exceeds 1.575 V does not exceed 10 µs in duration. 2. The absolute maximum ratings of VCCI are applicable to all I/O standards supported by the device. 3. VCCDA must be greater than or equal to the highest VCCI voltage Table 2-3 • RTAX-S/SL and RTAX-DSP Recommended Operating Conditions Parameter Range Military Units Junction Temperature (T ) –55 to +125 °C J 1 Ambient Temperature (T ) –55 to +125 °C A 1.5 V Core Supply Voltage 1.425 to 1.575 V 1.5 V I/O Supply Voltage 1.425 to 1.575 V 1.8 V I/O Supply Voltage 1.71 to 1.89 V 2 2.5 V I/O Supply Voltage 2.375 to 2.625 V 3.3 V I/O Supply Voltage 3.0 to 3.6 V 2 2.5 V VCCDA I/O Supply Voltage (no differential I/O used) 2.375 to 2.625 V 3 3.3 V VCCDA I/O Supply Voltage (differential or voltage-referenced I/O used) 3.0 to 3.6 V 3.3 V VPUMP Supply Voltage 3.0 to 3.6 V Notes: 1. Ambient temperature (T ) is used for commercial and industrial grades; case temperature (T ) is used for A C military grades. 2. Please see "VCCDA Supply Voltage" on page 2-14 more detail. 2-2 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Overshoot/Undershoot Limits For AC signals, the input signal may undershoot during transitions to –1.0 V for no longer than 10% of the period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. Note: The above specification does not apply to the PCI standard. The RTAX-S/SL and RTAX-DSP PCI I/Os are compliant to the PCI standard including the PCI overshoot/undershoot specifications. Power-Up/Down Sequence VCCA, VCCI, and VCCDA can be powered up or powered down in any sequence. During power-up, all RTAX-S/SL and RTAX-DSP I/Os are tristated until they reach the state defined by the design. During power-down, all RTAX-S/SL and RTAX-DSP I/Os are tristated. Refer to the Board-Level Considerations for Power-Up and Power-Down of RTAX-S/SL FPGAs application note for more information. Calculating Power Dissipation Table 2-4 • RTAX-S Standby Current 1 Device Temperature ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, IOZ (µA) RTAX4000S Typical 25ºC 75 15 15 3.13 1 125ºC 600 60 20 3.7 5 RTAX2000S Typical 25ºC 50 10 7 3.13 1 125ºC 500 35 10 2.96 5 RTAX1000S Typical 25ºC 30 10 7 3.13 1 125ºC 450 35 10 2.96 5 RTAX250S Typical 25ºC 20 5 5 3.13 1 125ºC 250 20 10 2.96 5 Notes: 1. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. 2. Above values are maximum. 3. Values in the ICCDIFFA column refer to the current (in addition to ICCDA) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins. Revision 14 2-3 Detailed Specifications Table 2-5 • RTAX-SL Standby Current 1 Device Temperature ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, IOZ (µA) RTAX4000SL Typical 25ºC 40 15 15 3.13 1 125ºC 300 60 20 3.7 5 RTAX2000SL Typical 25ºC 30 10 7 3.13 1 125ºC 150 35 10 3.7 5 RTAX1000SL Typical 25ºC 20 10 7 3.13 1 125ºC 90 35 10 3.7 5 RTAX250SL Typical 25ºC 15 5 5 3.13 1 125ºC 60 20 10 3.7 5 Notes: 1. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. 2. Above values are maximum. 3. Values in the ICCDIFFA column refer to the current (in addition to ICCDA) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins. Table 2-6 • RTAX-D Standby Current 1 Device Temperature ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, IOZ (µA) RTAX4000D Typical 25ºC 80 15 20 3.13 1 125ºC 650 60 25 3.7 5 RTAX2000D Typical 25ºC 55 10 10 3.13 1 125ºC 550 35 13 3.7 5 Notes: 1. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. 2. Above values are maximum. 3. Values in the I column refer to the current (in addition to ICCDA) flowing per pair through CCDIFFA differential amplifiers only when using differential pairs or voltage references pins. Table 2-7 • RTAX-DL Standby Current 1 Device Temperature ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, IOZ (µA) RTAX4000DL Typical 25ºC 40 15 20 3.13 1 125ºC 300 60 25 3.7 5 RTAX2000DL Typical 25ºC 30 10 10 3.13 1 125ºC 150 35 13 3.7 5 Notes: 1. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. 2. Above values are maximum. 3. Values in the I column refer to the current (in addition to ICCDA) flowing per pair through CCDIFFA differential amplifiers only when using differential pairs or voltage references pins. 2-4 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-8 • Default Cload / VCCI CLOAD (pF) VCCI (V) PLOAD (µW/MHz) P10 (µW/MHz) PI/O (µW/MHZ)* Single-Ended without VREF LVCMOS – 15 (JESD8-11) 35 1.5 78.8 49.5 128.3 LVCMOS –18 35 1.8 113.4 73.4 186.8 LVCMOS – 25 35 2.5 218.8 148.0 366.8 LVTTL 8 mA Low Slew 35 3.3 381.2 118.7 499.9 LVTTL 12 mA Low Slew 35 3.3 381.2 138.6 519.8 LVTTL 16 mA Low Slew 35 3.3 381.2 150.8 532.0 LVTTL 24 mA Low Slew 35 3.3 381.2 169.2 550.4 LVTTL 8 mA High Slew 35 3.3 381.2 130.3 511.5 LVTTL 12 mA High Slew 35 3.3 381.2 165.9 547.1 LVTTL 16 mA High Slew 35 3.3 381.2 225.1 606.3 LVTTL 24 mA High Slew 35 3.3 381.2 267.5 648.7 PCI 10 3.3 108.9 218.5 327.4 PCI-X 10 3.3 108.9 162.9 271.8 Single-Ended with VREF SSTL2-I 30 2.5 – 171.7 171.7 SSTL2-II 30 2.5 – 148.3 148.3 SSTL3-I 30 3.3 – 327.8 327.8 SSTL3-II 30 3.3 – 288.9 288.9 HSTL-I 20 1.5 – 41.4 41.4 GTLP – 33 10 3.3 – 68.5 68.5 Differential LVPECL – 33 N/A 3.3 – 260.6 260.6 LVDS – 25 N/A 2.5 – 145.8 145.8 2 Note: *P = P + C * VCCI I/O 10 load Revision 14 2-5 Detailed Specifications Table 2-9 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL/DSP Devices Device-Specific Value (in µW/MHz) Sym. Power Component RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL P1 Core tile HCLK power 85.8 227.5 378.0 700 378.0 700.0 component P2 R-cell power component 0.6 0.6 0.6 0.6 0.6 0.6 P3 HCLK signal power 7.7 23.2 31.0 50.0 31.0 50.0 dissipation P4 Core tile RCLK power 85.8 227.5 378.0 700 378.0 700.0 component P5 R-cell power component 0.9 0.9 0.9 0.9 0.9 0.9 P6 RCLK signal power 8.6 25.7 34.3 55.0 34.3 55.0 dissipation P7 Power dissipation due to 1.6 1.6 1.6 1.6 1.6 1.6 the switching activity on the R-cell P8 Power dissipation due to 1.4 1.4 1.4 1.4 1.4 1.4 the switching activity on the C-cell P9 Power component 10.0 10.0 10.0 10.0 10.0 10. associated with input voltage P10 Power component See Table 2-4 and Table 2-5 on page 2-4 for per pin contribution. associated with output voltage P11 Power component 25.0 25.0 25.0 25.0 25.0 25.0 associated with the read operation in the RAM block P12 Power component 30.0 30.0 30.0 30.0 30.0 30.0 associated with the write operation in the RAM block P13 Math Block multiplier –– – – 9 9 only P14 Math Block multiplier –– – – 15 15 with adder P15 Math Block multiplier –– – – 5.9 5.9 only – SIMD P16 Math Block multiplier – – – – 10.2 10.2 with adder – SIMD P17 Math Block clock – – – – 59.26 59.26 contribution 2-6 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs P = P + P total dc ac P =I * VCCA + ICCI * VCCI + ICCDA * VCCDA + ICCDIFFA * VCCDA * N dc CCA b_da_pairs P =P + P + P + P + P + P + P + P ac HCLK CLK R-cells C-cells inputs outputs memory mathblock N = number of differential pairs or voltage referenced pins used b_da_pairs P = (P1 + P2 * s + P3 * sqrt[s]) * Fs HCLK s = number of R-cells clocked by this clock Fs = clock frequency P = (P4 + P5 * s + P6 * sqrt[s]) * Fs CLK s = number of R-cells clocked by this clock Fs = clock frequency P = P7 * ms * Fs R-cells ms = number of R-cells switching at each Fs cycle Fs = clock frequency P = P8 * mc * Fs C-cells mc = number of C-cells switching at each Fs cycle Fs = clock frequency P = P9 * pi * F inputs pi pi = number of inputs F = average input frequency pi 2 P = (P10 + C * VCCI ) * po * F outputs load po C = output load (technology dependent) load V = output voltage (technology dependent) CCI po = number of outputs F = average output frequency po P = P11 * N * F + P12 * N * F memory block RCLK block WCLK N = number of RAM/FIFO blocks (1 block = 4 k) block F = read-clock frequency of the memory RCLK F = write-clock frequency of the memory WCLK P = N * F * ( P17 (if pipe) + P13 ) when SIMD = No and Add = No MathBlock block CLK P = N * F * ( P17 (if pipe) + P14 ) when SIMD = No and Add = Yes MathBlock block CLK P = N * F * ( P17 (if pipe) + P15 ) when SIMD = Yes and Add = No MathBlock block CLK P = N * F * ( P17 (if pipe) + P16 ) when SIMD = Yes and Add = Yes MathBlock block CLK N = Number of math blocks block F = Clock frequency CLK SIMD = Mode of the math block: fractured (SIMD = Yes) or normal (SIMD = No) Add = Configuration of the math block: multiply only (Add = No) or multiply-accumulate (Add = Yes) pipe = P17 should be added if the internal registers of the math block are used. Revision 14 2-7 Detailed Specifications Power Estimation Example This example employs an RTAX1000S/SL shift-register design with 1,080 R-cells, one C-cell, one reset input, and one output. This design also uses a single clock (HCLK) at 100 MHz and is operated under room temperature. ms = 1,080 (in a shift register 100% of R-cells are toggling at each clock cycle) Fs = 100 MHz s = 1,080 => P = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 163.8 mW HCLK and Fs = 100 MHz = P7 * ms * Fs = 172.8 mW => P R-cells mc = 1 (1 C-cell in this design) and Fs = 100 MHz = P8 * mc * Fs = 0.14 mW => P C-cells F ~ 0 MHz pi and pi= 1 (1 reset input => this is why F = 0) pi = P9 * pi * F = 0 mW => P inputs pi F = 50 MHz po C = 35 pF load VCCI= 3.3 V and po = 1 2 => P = (P10 + C * V ) * po * F = 23.6 mW outputs load CCI po No RAM/FIFO in this shift-register => P = 0 mW memory P =P + P + P + P + P + P + P = 360.4 mW ac HCLK CLK R-cells C-cells inputs outputs memory =I * V + I * V + I * V + I * V * N = 101.1 P dc CCA CCA CCI CCI CCDA CCDA CCDIFFA CCDA b_da_pairs mW =P + P = 360.4 mW + 101.1 mW = 461.5 mW P total dc ac 2-8 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Thermal Characteristics The temperature variable in Microsemi Designer software refers to the junction temperature, not the ambient, case or board temperature. This is an important distinction because dynamic and static power consumption causes the chip's junction temperature to be higher than the ambient, case or board temperature. EQ 2, EQ 3, and EQ 4 show the relationship between thermal resistance, temperature, and power. T – T j a θ = ----------------- ja P EQ 2 T – T j c θ = ----------------- jc P EQ 3 T – T j b θ = ----------------- jb P EQ 4 Where: = θ Thermal resistance from junction to air ja θ = Thermal resistance from junction to case jc θ = Thermal resistance from junction to board jb T = Junction Temperature j T = Ambient Temperature a T = Case Temperature c T = Board Temperature b P=Power Table 2-10 • Package Thermal Characteristics Product Package Type θ θ θ Units ja jc jb RTAX250S/SL CQ208 19.9 0.8 N/A C/W CQ352 16.8 0.7 N/A C/W CG624 13.7 TBD TBD C/W RTAX1000S/SL CQ352 13.3 0.4 N/A C/W CG624 10.8 5.6 4.5 C/W RTAX2000S/SL CQ256 15.8 0.25 N/A C/W CQ352 12.3 0.2 N/A C/W CG624 9.7 4.3 3.5 C/W CG1152 9.0 2.0 2.6 C/W RTAX4000S/SL CQ352 12.3 0.2 N/A C/W CG1272 8.0 2.0 2.2 C/W RTAX2000D/DL CQ352 TBD TBD N/A C/W CGD1272 TBD TBD TBD C/W RTAX4000D/DL CQ352 TBD 0.17 N/A C/W CGD1272 TBD TBD TBD C/W Notes: 1. θ are estimated at still air. ja 2. θ for CQFP packages refers to the thermal resistance between the junction and the bottom surface of the jc package. 3. θ for CCGA packages refers to the thermal resistance between the junction and the top surface of the jc package. 4. The θ values are conduction heat transfer simulation only. jb Revision 14 2-9 Detailed Specifications Calculation for Power Sample Case 1 A sample calculation of the power dissipation allowed for an RTAX1000S/SL-CG624 in still air is shown below. Assume that the maximum junction temperature is maintained at 110°C and the ambient temperature is 50°C. The maximum power allowed can be estimated using EQ 5. = 110°C T j 50°C T a = 110°C – 50°C θ == 10.8°C/W ------------------------------------ ja P EQ 5 P = 5.55 W Air Solder Columns PCB Figure 2-2 • Heat Flow when Air is Present Sample Case 2 A sample calculation of the power dissipation when there is no air in the environment is shown below. An RTAX1000S/SL-CQ352 is attached to the board with a thermal adhesive between the package body. The thermal resistance of the paste is 0.58°C/W. Since air is not present in the environment, most of the heat will be flowing through the bottom of the package, through the thermal paste, and to the board. Neglecting the heat flowing through the package leads, the maximum power allowed can be estimated as shown in EQ 6 through EQ 9. T 110°C j = θ Thermal resistance of the thermal paste from case to board (i.e., = 0.58°C/W) cb = T = 70°C b 110°C – 70°C θ = ------------------------------------ jb (Total) P EQ 6 θ = θ + θ jb (Total) jc cb EQ 7 110°C– 70°C θ + θ = ------------------------------------ jc cb P EQ 8 110°C – 70°C 0.4°C/W + 0.58°C/W = ------------------------------------ P EQ 9 P = 40.8 W 2-10 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Thermal Adhesive PCB Figure 2-3 • Heat Flow in a Vacuum The thermal resistances, shown in Table 2-10 on page 2-9, are based on the simulations done with test conditions and test boards configurations specified in JEDEC specification JESD51. Timing Characteristics RTAX-S/SL and RTAX-DSP devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-11 should be applied to all timing data contained within this datasheet. Table 2-11 • Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Military, T = 125°C, VCCA = 1.4 V) J Junction Temperature VCCA –55°C –40°C 0°C 25°C 70°C 85°C 125°C 1.4 V 0.76 0.77 0.81 0.84 0.90 0.92 1.00 1.425 V 0.75 0.76 0.80 0.83 0.89 0.92 0.99 1.5 V 0.73 0.74 0.78 0.81 0.87 0.90 0.97 1.575 V 0.72 0.73 0.77 0.79 0.86 0.88 0.96 1.6 V 0.71 0.72 0.76 0.79 0.85 0.88 0.95 Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 125°C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. All timing numbers listed in this datasheet represent sample timing characteristics of RTAX-S/SL and RTAX-DSP devices. Actual timing delay values are design-specific and can be derived from the SmartTime tool in Microsemi’s Designer software after place-and-route. Revision 14 2-11 Detailed Specifications Timing Model I/O Module (Nonregistered) Carry Chain t = 2.45 ns PY Combinatorial Combinatorial I/O Cell Cell FCO LVPECL t = 0.69 ns t = 0.75 ns I/O PDC CCY I/O Module I/O Module (Registered) (Nonregistered) t = 0.84 ns RD2 Combinatorial t = 1.83 ns Buffer DP Buffer Cell t = 3.51 ns + Module PY Module LVPECL Y LVTTL Output Drive Strength = 4 (24mA) t = 0.17 ns t = 0.95 ns t = 0.17 ns BFPD PD High Slew Rate BFPD t = 0.90 ns ICLKQ t = 0.66 ns RD1 t = 0.31 ns SUD t = 0.84 ns RD2 LVTTL t = 1.07 ns RD3 t = 1.84 ns DP Routed or Hardwired t = 3.64 ns HCKH F (external) = 350 MHz MAX Register Cell Combinatorial Register Cell I/O Module F (internal) = 649 MHz Cell MAX t = 0.90 ns t = 0.94 ns OCLKQ RCO Buffer t = 0.66 ns t = 0.31 ns RD1 t = 0.21 ns SUD t = 1.26 ns SUD Module PY I/O Module DQ DQ DQ Y GTL + 3.3V (Non- registered) t = 0.21ns BPFD t = 0.95 ns PD + t = 0.94 ns RCO LVDS t = 3.54 ns RCKL t = 3.71 ns t = 0.21 ns SUD RCKH F (external) = 350 MHz MAX t = 3.54 ns RCKL F (internal) = 649 MHz MAX t = 2.00 ns DP Routed Clock LVTTL t = 1.84 ns DP t = 3.48 ns Hardwired or Routed Clock HCKL t = 3.55 ns RCKL LVTTL t = 1.84 ns DP Note: Timing data is for the RTAX2000S/SL, –1 speed. Figure 2-4 • Timing Model 2-12 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs 1 Hardwired Clock External Setup =(t + t + t ) – t DP RD2 SUD HCKH = (1.84 + 0.84 + 0.31) – 3.64 = –0.65 Clock-to-Out (Pad-to-Pad) =t + t + t + t HCKH RCO RD1 PY = 3.64 + 0.94 + 0.66 + 3.51 = 8.75 ns Routed Clock External Setup =(t + t + t ) – t DP RD2 SUD RCKH = (1.84 + 0.84 + 0.31) – 3.54 = –0.72 ns Clock-to-Out (Pad-to-Pad) =t + t + t + t RCKH RCO RD1 PY = 3.71 + 0.94 + 0.66 + 3.51 = 8.82 ns 1. Calculations are examples of how to calculate related parameters and do not necessary match the path represented in the "Timing Model". Revision 14 2-13 Detailed Specifications I/O Specifications Pin Descriptions Supply Pins GND Ground Low supply voltage. VCCA Supply Voltage Supply voltage for array (1.5 V). VCCIBx Supply Voltage Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See "User I/Os" on page 2-16 for more information. Unused VCCIBX I/O banks may be tied to GND or can be tied to other used VCCIBX I/O banks within the same device. VCCDA Supply Voltage Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. VCCDA is either 3.3 V or 2.5 V and must use 3.3 V when voltage-referenced and/or differential is used. Additionally, VCCDA must be greater than or equal to any VCCI voltages (i.e. VCCDA ≥ VCCIBx). VPUMP Supply Voltage (External Pump) In low-power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge 2 pump when the voltage level on VPUMP reaches 3.3 V. In normal device operation, when using the internal charge pump, VPUMP can be directly tied or through a 1K resistor to GND. User-Defined Supply Pins VREF Supply Voltage Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF are not in fixed locations. There can be one or more VREF pins in an I/O bank. The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed only for input and bidirectional I/Os. Global Pins HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C, and D These pins are the clock input for sequential modules. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. HCLK pins may be used either as HCLK inputs or as user I/Os. If they are not being used for either purpose, Microsemi recommends that they are tied to ground. CLKE/F/G/H Global Clocks E, F, G, and H These pins are clock inputs for clock distribution networks. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). The clock input is buffered prior to clocking the R-cells. CLK pins may be used either as CLK inputs or as user I/Os. If they are not being used for either purpose, Microsemi recommends that they are tied to a known state. 2. When V = 3.3V, it shuts off the internal charge pump. PUMP 2-14 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs JTAG/Probe Pins 3 PRA/B/C/D Probes A, B, C, and D The dedicated probe pins are used to output data from any user-defined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins’ probe capabilities can be permanently disabled to protect programmed design confidentiality. Refer to Table2-116 on page2-133 for recommendations on pin status for flight boards. 2 TCK Test Clock Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II). 2 TDI Test Data Input Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal pull- up resistor with approximately 10 kΩ resistance. 2 TDO Test Data Output Serial output for JTAG boundary-scan testing. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal pull-up resistor with approximately 10 kΩ resistance. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a programmable pull-up resistor with approximately 10 kΩ resistance (i.e. with or without the pull-up resistor). This pin must be hardwired to ground for flight. Special Functions NC No Connection This pin is not connected to circuitry within the device, or to any other pin in the package. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. 3. Microsemi recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, and PRD). The series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe connector) during probing and reading back the checksum. With an internal setup we have seen 70- ohm termination resistor improved the signal transmission. Since the series termination depends on the setup, Microsemi recommends users to calculate the termination resistor for their own setup. Below is a guideline on how to calculate the resistor value. The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace impedance. Z0 = Rs + Zd Z0 = trace impedance (silicon explorer’s breakout cable’s resistance + PCB trace impedance), Rs = series termination, Zd = probe signal’s driver impedance. The termination resistor should be placed as close as possible to the driver. Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the driver impedances needs to be calculated from RTAX-S IBIS Models (Mixed Voltage Operation). PRA, PRB, PRC, PRD, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model. Silicon explorer’s breakout cable’s resistance is usually close to 1 ohm. Revision 14 2-15 Detailed Specifications 4 User I/Os Introduction The RTAX-S/SL and RTAX-DSP families feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-12 on page 2-17 contains the I/O standards supported by the RTAX-S/SL and RTAX-DSP families. Unused I/Os are configured as follows: • Output buffer is disabled (with tristated value of Hi-Z) • Input buffer is disabled (with tristated value of Hi-Z) • No pull-up/pull-down is programmed In Microsemi Designer Software, unused RTAX-S/SL I/Os are configured as tristate with no pull-up resistors. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. The slew rate setting is effective for both rising and falling edges. All I/O standards are 3.3 V tolerant, and I/O standards, except 3.3 V PCI, are capable of hot insertion and cold sparing. 3.3 V PCI is also 5 V tolerant with the aid of an external resistor (see "5 V Tolerance" on page 2-1). Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). By design, all user flip-flops in the RTAX-S/SL and RTAX-DSP FPGAs are immune to SEUs, including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. I/Os are organized into banks, and there are eight banks per device – two per side (Figure 2-7 on page 2-25). Each I/O bank has a common VCCI, the supply voltage for its I/Os. For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While V REF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a V . REF The location of the VREF pin should be selected according to the following rules: • Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. • I/O package locations listed as no-connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a V pin. REF • Dedicated I/O pins (GND, VCCI...) are not counted as part of the 16. • The user I/O pad immediately adjacent on either side of the VREF pin may only be used as an input. The exception is when there is a VCCI/GND pair separating the VREF pin and the user I/O pad location. The differential amplifier supply voltage VCCDA should be connected to 3.3 V. When neither voltage- referenced nor differential I/Os are used, VCCDA may be connected to 2.5 V when VCCI ≤ 2.5 V in a given I/O bank; however, it is still recommended to connect VCCDA to 3.3 V. The user can gain access to the various I/O standards in three ways: • Instantiate specific library macros that represent the desired specific standard • Use generic I/O macros and then use Microsemi Designer’s PinEditor to specify the desired I/O standards. (Please note that this is not applicable to differential standards.) • A combination of the first two methods 4. Do not use an external resistor to pull the I/O above V for a higher logic “1” voltage level. The desired higher logic “1” CCI voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI. 2-16 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Please refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library Guide for more details. Table 2-12 • I/O Standards Supported by the RTAX-S/SL and RTAX-DSP Families Input/Output Supply Input Reference Board Termination I/O Standard Voltage (VCCI) Voltage (VREF) Voltage (VTT) LVTTL 3.3 N/A N/A LVCMOS 2.5 V 2.5 N/A N/A LVCMOS 1.8 V 1.8 N/A N/A LVCMOS 1.5 V (JDEC8-11) 1.5 N/A N/A 3.3 V PCI 3.3 N/A N/A GTL+ 3.3 V 3.3 1.0 1.2 * GTL+ 2.5 V 2.5 1.0 1.2 HSTL Class 1 1.5 0.75 0.75 SSTL3 Class 1 and II 3.3 1.5 1.5 SSTL2 Class1 and II 2.5 1.25 1.25 LVDS 2.5 N/A N/A LVPECL 3.3 N/A N/A Note: * 2.5 V GTL+ is not supported across the full military temperature range. Simultaneous Switching Outputs (SSO) Microsemi defines SSOs as any outputs that transition in phase within a 1 ns window. The measurements made by Microsemi are based on the following worst-case conditions: 1. The switching outputs are adjacent to the quiet output on either side. 2. All unused I/O buffers are tristated so they do not help either ground or V . CC 3. A worst-case package was used. When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or more commonly, ground bounce. SSN becomes more of an issue in high pin count packages and when using high performance devices such as the RTAX-S/SL and RTAX-DSP families. Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more information. I/O Banks and Compatibility Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage (V ), only I/Os with compatible standards can be assigned to the same bank. CCI Table 2-13 shows the compatible I/O standards for a common VREF (for voltage-referenced standards). Similarly, Table 2-14 on page 2-18 shows compatible standards for a common VCCI. Table 2-13 • Compatible I/O Standards for Different VREF Values VREF Compatible Standards 1.5 V SSTL 3 (Class I and II) 1.25 V SSTL 2 (Class I and II) 1.0 V GTL+ (2.5 V and 3.3 V Outputs) 0.75 V HSTL (Class I) Revision 14 2-17 Detailed Specifications Table 2-14 • Compatible I/O Standards for Different VCCI Values 1 VCCI Compatible Standards VREF 3.3 V LVTTL, PCI, LVPECL, GTL+ 3.3V 1.0 3.3 V SSTL 3 (Class I and II), LVTTL, PCI, LVPECL 1.5 2 2.5 V LVCMOS 2.5V, GTL+ 2.5V, LVDS 1.0 2 2.5 V LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS 1.25 1.8 V LVCMOS 1.8V N/A 1.5 V LVCMOS 1.5V, HSTL Class I 0.75 Notes: 1. VCCI is used for both inputs and outputs. 2. Refer to Table 2-3 on page 2-2 for VCCI tolerances. Table 2-15 on page 2-19 summarizes the different combinations of voltages and I/O standards that can be used together in the same I/O bank. Note that two I/O standards are compatible if: • Their VCCI values are identical • Their VREF standards are identical (if applicable) For example, if LVTTL 3.3 V (VREF = 1.0 V) is used, then the other available (i.e., compatible) I/O standards in the same bank are GTL+ and LVPECL. Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all I/O standards used in the bank. For instance, when using LVCMOS2.5 (±5% VCCI tolerance) and LVDS (±5% VCCI tolerance) within an I/O bank, the maximum voltage tolerance of the bank will be ±5% VCCI. 2-18 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-15 • Legal I/O Usage Matrix I/O Standard LVTTL 3. 3V (VREF = 1.0 V) ✓ ––– ✓✓ –– – – – ✓ LVTTL 3. 3V(VREF = 1.5 V) ✓ ––– ✓ –– – – ✓ – ✓ LVCMOS 2.5 V (VREF = 1.0 V) – ✓ –––– ✓ –– – ✓ – LVCMOS 2.5 V (VREF = 1.25 V) – ✓ –––– –– ✓ – ✓ – LVCMOS1.8 V – – ✓ ––– –– – – – – LVCMOS1.5 V (VREF = 1.75 V) (JESD8-11) – – – ✓ –– – ✓ –– – – 3.3 V PCI (VREF=1.0 V) ✓ ––– ✓✓ –– – – – ✓ 3.3 V PCI (VREF=1.5 V) ✓ ––– ✓ –– – – ✓ – ✓ GTL+ (3.3 V) ✓ ––– ✓✓ –– – – – ✓ GTL+ (2.5 V) – ✓ –––– ✓ –– – – – HSTL Class I – – – ✓ –– – ✓ –– – – SSTL2 Class I & II – ✓ –––– –– ✓ – ✓ – SSTL3 Class I & II ✓ ––– ✓ –– – – ✓ – ✓ LVDS (VREF=1.0 V) – ✓ –––– ✓ –– – ✓ – LVDS (VREF=1.25 V) – ✓ –––– –– ✓ – ✓ – LVPECL (VREF=1.0 V) ✓ ––– ✓✓ –– – – – ✓ LVPECL (VREF=1.5 V) ✓ ––– ✓ –– – – ✓ – ✓ Notes: 1. Note that GTL+2.5 V is not supported across the full military temperature range. 2. A "✓" indicates whether standards can be used within a bank at the same time. Examples: a) LVTTL can be used with 3.3 V PCI and GTL+ (3.3 V), when VREF = 1.0 V (GTL+ requirement). b) LVTTL can be used with 3.3 V PCI and SSTL3 Class I and II, when VREF = 1.5 V (SSTL3 requirement). c) LVDS VCCI = 2.5 V ±5%. Revision 14 2-19 LVTTL 3.3 V LVCMOS 2.5 V LVCMOS1.8 V LVCMOS1.5 V (JESD8-11) 3.3 V PCI GTL + (3.3 V) GTL + (2.5 V) HSTL Class I (1.5 V) SSTL2 Class I & II (2.5 V) SSTL3 Class I & II (3.3 V) LVDS (2.5 V ±5%) LVPECL (3.3 V) Detailed Specifications I/O Clusters Each I/O cluster incorporates two I/O modules, four RX modules and two TX modules, and a buffer module. In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg) (Figure 2-5). I/O CLUSTER P PAD EnReg Routed Input Track OEP Routed Input Track DIN YOUT OutREg Routed Input Track Routed Input Track UOP DIN YOUT I/O Slew Rate Drive Strength InReg Output Track UIP Output Track Y DCIN V REF HCLK or RCLK N PAD EnReg Routed Input Track OEN Routed Input Track DIN YOUT UON Routed Input Track OutREg Routed Input Track DIN YOUT I/O Slew Rate Drive Strength InReg Output Track Output Track UIN Y DCIN V REF Figure 2-5 • I/O Cluster Interface Using an I/O Register To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os. Usage of each I/O register (register combining) is individually controlled and can be selected/deselected using the PinEditor tool in Microsemi's Designer software. I/O register combining can also be controlled at the device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any 5 given design. In addition, Designer software provides a global option to enable/disable the usage of registers in the I/Os. This option is design specific. The setting for each individual I/O overrides this global option. Furthermore, the Global Set Fuse option in the Designer software, when checked, causes all I/O registers to output logic HIGH at device power-up. Using the Weak Pull-Up and Pull-Down Circuits Each RTAX-S/SL/DSP I/O comes with a weak pull-up/-down circuit (refer to Table 2-21 on page 2-26). These are weak transistors with the gates tied on, so the on resistance of the transistor emulates a resistor. The weak pull-up and pull-down is active only when the device is powered up, and they must be biased to be on. When the rails are coming up, they are not biased fully, so they do not behave as resistors until the voltage is at sufficient levels to bias the transistors. The key is they really are transistors; they are not traces of poly silicon, which is another way to do an on-chip resistor (those take much more room). I/O macros are provided for combinations of pull-up/-down for LVTTL, LVCMOS (2.5 V, 1.8 V, and 1.5 V) standards. These macros can be instantiated if a keeper circuit for any input buffer is required. 5. Please note that register combining for multi fanout nets is not supported. 2-20 Revision 14 FPGA LOGIC CORE BSR BSR RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Customizing the I/O • A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (Table 2-16). It is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the I/O). When the input buffer drives a register within the I/O, the delay element is activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer. • The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. • The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values – 8 mA, 12 mA, 16 mA, or 24 mA – that can be specified in 6 Designer. Table 2-16 • Bank Wide Delay Values –1 Std. Bit Setting Delay (ns) 00.88 1.03 11.10 1.29 21.21 1.42 31.44 1.69 41.53 1.80 51.75 2.06 61.86 2.19 72.09 2.46 82.16 2.54 92.38 2.80 10 2.49 2.93 11 2.72 3.20 12 2.81 3.30 13 3.04 3.57 14 3.15 3.70 15 3.37 3.96 16 3.39 3.98 17 3.61 4.25 18 3.72 4.38 19 3.95 4.64 20 4.04 4.75 21 4.27 5.01 22 4.38 5.14 23 4.60 5.41 24 4.67 5.49 25 4.90 5.76 26 5.01 5.89 27 5.23 6.15 28 5.32 6.26 29 5.55 6.52 30 5.66 6.65 31 5.88 6.92 Note: Data shown in the table above was measured at VCCA = 1.425 and 125°C. 6. These values are minimum drive strengths. Revision 14 2-21 Detailed Specifications Using the Differential I/O Standards Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Note that there are no tristated or bidirectional I/O buffers for differential standards. Using the Voltage-Referenced I/O Standards Using these I/O standards is similar to that of single-ended I/O standards. Their settings can be changed in Designer. Using DDR (Double Data Rate) In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very high-speed systems. To implement a DDR, users must do the following: 1. Instantiate an input buffer (with the required I/O standard). 2. Instantiate the DDR_REG macro (Figure 2-6 on page 2-22). 3. Connect the output from the Input buffer to the input of the DDR macro. 4. DDR supports all I/O standards. 5. The DDR macro in SmartGen can be used to implement DDR. 6. Bit width and I/O standard can be chosen in SmartGen. PRE DQR QF E CLK CLR Figure 2-6 • DDR Register Macros for Specific I/O Standards There are different macro types for any I/O standard or feature that determine the required V and CCI V voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and REF 24 mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals. Most of the macro symbols represent variations of the six generic symbol types: • CLKBUF: Clock Buffer • HCLKBUF: Hardwired Clock Buffer • INBUF: Input Buffer • OUTBUF: Output Buffer • TRIBUFF: Tristate Buffer • BIBUF: Bidirectional Buffer Other macros include the following: • Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). • Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUFF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. 2-22 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs • DDR_REG macro. It can be connected to any I/O standard input buffers (i.e., INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module. Table 2-17, Table 2-18 on page 2-24, and Table 2-19 on page 2-24 list all the available macro names differentiated by I/O standard, type, slew rate, and drive strength. Table 2-17 • Macros for Single-Ended I/O Standards Standard VCCI Macro Names LVTTL 3.3 V CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_F_8, OUTBUF_F_12, OUTBUF_F_16, OUTBUF_F_24, TRIBUFF, TRIBUFF_S_8, TRIBUFF_S_12, TRIBUFF_S_16, TRIBUFF_S_24, TRIBUFF_F_8, TRIBUFF_F_12, TRIBUFF_F_16, TRIBUFF_F_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_F_8, BIBUF_F_12, BIBUF_F_16, BIBUF_F_24, 3.3V PCI 3.3 V CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUFF_PCI, BIBUF_PCI LVCMOS25 2.5 V CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUFF_LVCMOS25, BIBUF_LVCMOS25 LVCMOS18 1.8 V CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUFF_LVCMOS18, BIBUF_LVCMOS18 LVCMOS15 1.5 V CLKBUF_LVCMOS15, (JESD8-11) HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUFF_LVCMOS15, BIBUF_LVCMOS15 Revision 14 2-23 Detailed Specifications Table 2-18 • I/O Macros for Differential I/O Standards Standard VCCI Macro Names LVPECL 3.3 V CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL LVDS 2.5 V CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS Table 2-19 • I/O Macros for Voltage-Referenced I/O Standards Standard VCCI VREF Macro Names GTL+ 3.3 V 1.0 V CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUFF_GTP33, BIBUF_GTP33 GTL+ 2.5 V 1.0 V CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUFF_GTP25, BIBUF_GTP25 SSTL2 Class I 2.5 V 1.25 V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUFF_SSTL2_I, BIBUF_SSTL2_I, INBUF_SSTL2_I, OUTBUF_SSTL2_I SSTL2 Class II 2.5 V 1.25 V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUFF_SSTL2_II, BIBUF_SSTL2_II, INBUF_SSTL2_II, OUTBUF_SSTL2_II SSTL3 Class I 3.3 V 1.5 V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUFF_SSTL3_I, BIBUF_SSTL3_I, INBUF_SSTL3_I, OUTBUF_SSTL3_I SSTL3 Class II 3.3 V 1.5 V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUFF_SSTL3_II, BIBUF_SSTL3_II, INBUF_SSTL3_II, OUTBUF_SSTL3_II HSTL Class I 1.5 V 0.75 V CLKBUF_HSTL_I, BIBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, TRIBUFF_HSTL_I 2-24 Revision 14 GND VCCDA GND VCCDA VPUMP 4 1 VCCI VCCI GND GND VCCA VCCA GND GND VCCDA PRC GND PRD GND PRB VCCDA PRA 0 VCCI 5 VCCI GND GND VCCA VCCA GND GND TDO VCCDA TDI I/O BANK 7 I/O BANK 6 GND TCK TMS TRST RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs User I/O Naming Conventions Due to the complex and flexible nature of the RTAX-S/SL family’s user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7). GND GND VCCDA VCCDA Corner1 I/O BANK 0 I/O BANK 1 Corner2 7 VCCI 2 VCCI GND GND VCCA VCCA GND GND VCCDA GND RTAX-S/SL/DSP GND VCCDA 3 6 VCCI VCCI GND GND VCCA GND VCCA GND GND GND Corner4 I/O BANK 5 I/O BANK 4 Corner3 VCCDA VCCDA Figure 2-7 • I/O Bank and Dedicated Pin Layout IOxxXBxFx Examples: IO12PB1F1 Is the positive pin of the thirteenth pair of the Pair number in the first I/O bank (IOB NE). IO12PB1 combined bank, starting at 00, clockwise from IOB NW with IO12NB1 form a differential pair. For those I/Os that can be employed P - Positive Pin/ N- Negative Pin either as a user I/O or as a special Bank I/D 0 through 7, function, the following nomenclature clockwise from IOB NW is used: IOxxXBxFx/special_function_name Fx refers to an unimplemented feature IOxxPB1Fx/CLKx This pin can be configured as a clock and can be ignored input or as a user I/O Figure 2-8 • General Naming Schemes Revision 14 2-25 I/O BANK 3 I/O BANK 2 Detailed Specifications I/O Standard Electrical Specifications Table 2-20 • Input Capacitance Symbol Parameter Conditions Min. Max. Units C Input capacitance VIN = 0, f =1.0 MHz 10 pF IN C Input capacitance on HCLK and RCLK pin VIN = 0, f =1.0 MHz 10 pF INCLK 1 Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances 1 2 R (kΩ) R (kΩ) WEAK PULL-UP WEAK PULL-DOWN I/O Configuration (VCCI) Min. Max. Min. Max. 3.3 V 35 65 30 60 2.5 V 50 75 40 85 1.8 V 80 140 70 130 1.5 V 100 210 90 180 Notes: 1. R (VCCImax – VOHspec) I ) (WEAK PULL-UP-MAX) = / WEAK PULL-UP-MIN 2. R (VOLspec) I (WEAK PULL-DOWN-MAX) = / WEAK PULL-DOWN-MIN) Table 2-22 • I/O Input Rise Time and Fall Time* Input Buffer Input Rise/Fall Time (Min) Input Rise/Fall Time (Max) LVTTL No Requirement 50 ns LVCMOS 2.5 V No Requirement 50 ns LVCMOS 1.8 V No Requirement 50 ns LVCMOS 1.5 V No Requirement 50 ns PCI No Requirement 50 ns PCIX No Requirement 50 ns GTL+ No Requirement 50 ns HSTL No Requirement 50 ns SSTL2 No Requirement 50 ns HSTL3 No Requirement 50 ns LVDS No Requirement 50 ns LVPECL No Requirement 50 ns Note: *Input Rise/Fall time applies to all inputs, including clock or data. Inputs have to ramp up/down linearly, in a monotonic way. Glitches or a plateau may cause double-clocking. They must be avoided. For Output Rise/Fall time, refer to IBIS Models for extraction. 2-26 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs IN Y INBUF PAD Input High Vtrip Vtrip ln 0 V VCCA 50% 50% Y t t GND DP DP (Rising) (Falling) Figure 2-9 • Input Buffer Delays OUT Pad ln TRIBUF To AC test loads (shown below) En VCCA VCCA VCCA 50% 50% 50% 50% 50% 50% ln GND En GND En GND VOH VCCI/VTT VTT Out Vtrip Vtrip Vtrip VOH Out 10% 90% VOL VOL Vtrip t t PY PY VTT t t ENZH ENHZ Out (t ) (t ) DLH DHL t t GND/VTT ENZL ENLZ Figure 2-10 • Output Buffer Delays Revision 14 2-27 Detailed Specifications I/O Module Timing Characteristics Output Register DQ E OutReg Input Register PRE/CLR D Q E InReg Output Enable Register PRE/CLR DQ EnReg E PRE/CLR CLK (Routed or Hardwired) Figure 2-11 • Timing Model D t t SUD HD CLK t t CPWHL CPWLH t ICLKQ Q t t HASYN REASYN t WASYN CLR t t HASYN REASYN t t CLR PRESET t PRESET WASYN t t SUE HE E Figure 2-12 • Input Register Timing Characteristics 2-28 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs D t t SUD HD CLK t t CPWHL CPWLH t OCLKQ Q t t HASYN REASYN t WASYN CLR t t HASYN REASYN t t CLR PRESET t PRESET WASYN t t SUE HE E Figure 2-13 • Output Register Timing Characteristics D t t SUD HD CLK t t CPWHL CPWLH t OCLKQ Q t t HASYN REASYN t WASYN CLR t t HASYN REASYN t t CLR PRESET t PRESET WASYN t t HE SUE E Figure 2-14 • Output Enable Register Timing Characteristics Revision 14 2-29 Detailed Specifications 3.3 V LVTTL Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-23 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 0.8 2.0 3.6 0.4* 2.4 24 –24 Note: For RTAX250S/SL-CQ352 devices only, VOL limits are 500 mV across all operating temperatures. AC Loadings R to VCCI for t / t plz pzl R=1 k R to GND for t / t phz pzh Test Point Test Point for t for tristate pd 35 pF for t / t pzh pzl 35 pF t / t 5 pF for phz plz Figure 2-15 • AC Test Loads Table 2-24 • AC Waveforms, Measuring Points, and Capacitive Load Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load 0 3.0 1.40 N/A 35 Note: * Measuring Point = V trip 2-30 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Characteristics Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 1 (8 mA) / Low Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 16.78 15.82 18.60 ns PY t Enable to Pad delay through the 17.65 16.64 19.56 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 16.51 15.56 18.29 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 2.55 2.41 2.83 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 3.26 3.07 3.61 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-31 Detailed Specifications Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 2 (12 mA) / Low Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 14.06 13.25 15.58 ns PY t Enable to Pad delay through the 14.39 13.56 15.94 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 14.09 13.28 15.61 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 2.84 2.68 3.15 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 3.71 3.50 4.11 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-32 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 3 (16 mA) / Low Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 12.78 12.04 14.16 ns PY t Enable to Pad delay through the 13.22 12.46 14.65 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 12.79 12.05 14.17 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.06 2.88 3.39 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 4.19 3.95 4.64 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-33 Detailed Specifications Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 4 (24 mA) / Low Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 12.10 11.41 13.41 ns PY t Enable to Pad delay through the 12.28 11.58 13.61 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 12.12 11.43 13.43 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.16 2.98 3.50 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 4.30 4.06 4.77 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-34 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 1 (8 mA) / High Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 5.07 4.78 5.62 ns PY t Enable to Pad delay through the 5.37 5.06 5.95 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 4.89 4.61 5.42 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.11 2.93 3.44 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 3.36 3.17 3.72 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-35 Detailed Specifications Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 2 (12 mA) / High Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 4.10 3.87 4.54 ns PY t Enable to Pad delay through the 4.33 4.08 4.79 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 3.55 3.34 3.93 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.11 2.93 3.44 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 3.83 3.61 4.25 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-36 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 3 (16 mA) / High Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 3.89 3.66 4.31 ns PY t Enable to Pad delay through the 4.10 3.87 4.55 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 3.22 3.03 3.56 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.14 2.96 3.48 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 4.32 4.07 4.79 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-37 Detailed Specifications Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVTTL I/O Module Drive Strength = 4 (24 mA) / High Slew Rate t Input buffer 1.96 1.84 2.17 ns DP t Output buffer 3.72 3.51 4.12 ns PY t Enable to Pad delay through the 3.89 3.67 4.31 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 2.99 2.82 3.32 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.14 2.96 3.48 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 4.42 4.17 4.90 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-38 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs 2.5 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-26 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 0.7 1.7 3.6 0.40 2.0 12 –12 AC Loadings R to VCCI for t / t plz pzl R=1 k R to GND for t / t phz pzh Test Point Test Point for t for tristate pd 35 pF for t / t pzh pzl 35 pF t / t 5 pF for phz plz Figure 2-16 • AC Test Loads Table 2-27 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load 0 2.5 1.25 N/A 35 Note: *Measuring Point = V trip Revision 14 2-39 Detailed Specifications Timing Characteristics Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 1 (6 mA) / Low Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 22.98 21.66 25.46 ns PY t Enable to Pad delay through the 24.20 22.81 26.81 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 21.72 20.47 24.07 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-40 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 2 (12 mA) / Low Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 19.19 18.09 21.26 ns PY t Enable to Pad delay through the 20.21 19.05 22.39 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 18.47 17.40 20.46 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-41 Detailed Specifications Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 3 (16 mA) / Low Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 17.63 16.62 19.53 ns PY t Enable to Pad delay through the 18.56 17.50 20.57 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 16.81 15.84 18.62 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-42 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 4 (24 mA) / Low Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 16.62 15.66 18.41 ns PY t Enable to Pad delay through the 17.49 16.49 19.38 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 16.01 15.09 17.74 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-43 Detailed Specifications Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 1 (6 mA) / High Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 6.71 6.32 7.43 ns PY t Enable to Pad delay through the 5.60 5.27 6.20 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 6.71 6.32 7.43 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-44 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 2 (12 mA) / High Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 4.70 4.43 5.21 ns PY t Enable to Pad delay through the 4.34. 4.09 4.80 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 4.70 4.43 5.21 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-45 Detailed Specifications Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 3 (16 mA) / High Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 4.14 3.91 4.59 ns PY t Enable to Pad delay through the 4.09 3.86 4.53 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 4.14 3.91 4.59 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-46 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS25 I/O Module Drive Strength = 4 (24 mA) / High Slew Rate t Input buffer 2.26 2.13 2.51 ns DP t Output buffer 3.81 3.59 4.22 ns PY t Enable to Pad delay through the 3.88 3.66 4.30 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 3.81 3.59 4.22 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.13 6.72 7.90 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.19 7.72 9.07 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-47 Detailed Specifications 1.8 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-29 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 0.35* VCCI 0.65* VCCI 3.60 0.20 VCCI – 0.2 8 –8 AC Loadings R to VCCI for t / t plz pzl R=1 k R to GND for t / t phz pzh Test Point Test Point for t for tristate pd 35 pF for t / t pzh pzl 35 pF t / t 5 pF for phz plz Figure 2-17 • AC Test Loads Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ) (V) C (pF) REF load 0 1.8 0.5VCCI N/A 35.00 Note: *Measuring Point = V trip 2-48 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Characteristics Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 2 (2 mA) / Low Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 35.85 33.79 39.72 ns PY t Enable to Pad delay through the 37.75 35.58 41.82 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 28.28 26.65 31.33 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-49 Detailed Specifications Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 3 (6 mA) / Low Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 32.95 31.06 36.51 ns PY t Enable to Pad delay through the 34.70 32.70 38.44 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 25.80 24.32 28.59 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-50 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 4 (8 mA) / Low Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 31.55 29.73 34.95 ns PY t Enable to Pad delay through the 33.22 31.31 36.80 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 24.65 23.23 27.31 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-51 Detailed Specifications Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 2 (2 mA) / High Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 6.94 6.54 7.69 ns PY t Enable to Pad delay through the 5.09 4.80 5.64 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 6.94 6.54 7.69 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-52 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 3 (6 mA) / High Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 5.89 5.55 6.52 ns PY t Enable to Pad delay through the 4.74 4.47 5.25 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 5.89 5.55 6.52 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET Revision 14 2-53 Detailed Specifications Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, T = 125°C (continued) J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS18 I/O Module Drive Strength = 4 (8 mA) / High Slew Rate t Input buffer 3.78 3.56 4.19 ns DP t Output buffer 5.27 4.97 5.84 ns PY t Enable to Pad delay through the 4.40 4.15 4.88 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 5.27 4.97 5.84 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.47 7.04 8.27 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.36 7.88 9.26 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37ns PRESET 2-54 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-32 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 0.35 VCCI 0.65 VCCI 3.60 0.40 VCCI – 0.4 8 mA –8 mA AC Loadings R to VCCI for t / t plz pzl R=1 k R to GND for t / t phz pzh Test Point Test Point for t for tristate pd 35 pF for t / t pzh pzl 35 pF t / t 5 pF for phz plz Figure 2-18 • AC Test Loads Table 2-33 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load 0 1.5 0.5VCCI N/A 35.00 Note: *Measuring Point = V trip Revision 14 2-55 Detailed Specifications Timing Characteristics Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 1 (2 mA) / Low Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 64.07 60.38 70.98 ns PY t Enable to Pad delay through the 67.46 63.58 74.74 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 47.54 44.80 52.67 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-56 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 2 (4 mA) / Low Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 56.55 53.29 62.65 ns PY t Enable to Pad delay through the 59.55 56.12 65.97 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 40.20 37.88 44.53 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-57 Detailed Specifications Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 3 (6 mA) / Low Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 51.89 48.90 57.49 ns PY t Enable to Pad delay through the 54.64 51.50 60.54 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 36.96 34.84 40.95 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-58 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 8 (4 mA) / Low Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 50.09 47.20 55.49 ns PY t Enable to Pad delay through the 52.74 49.71 58.43 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 35.21 33.18 39.01 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-59 Detailed Specifications Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 1 (2 mA) / High Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 15.48 14.59 17.15 ns PY t Enable to Pad delay through the 8.89 8.38 9.85 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 15.48 14.59 17.15 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-60 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 2 (4 mA) / High Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 9.68 9.12 10.73 ns PY t Enable to Pad delay through the 6.14 5.79 6.81 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 9.68 9.12 10.73 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-61 Detailed Specifications Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 3 (6 mA) / High Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 8.09 7.62 8.96 ns PY t Enable to Pad delay through the 5.68 5.36 6.30 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 8.09 7.62 8.96 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-62 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVCMOS15 I/O Module Drive Strength = 4 (8 mA) / High Slew Rate t Input buffer 4.17 3.93 4.62 ns DP t Output buffer 7.01 6.60 7.76 ns PY t Enable to Pad delay through the 5.19 4.89 5.75 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 7.01 6.60 7.76 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 7.90 7.45 8.76 ns ENLZ Output Buffer—LOW to Z t Enable to Pad delay through the 8.61 8.12 9.54 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-63 Detailed Specifications 3.3 V PCI Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5 V tolerant with the aid of external components. The RTAX-S/SL 3.3 V PCI buffer is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-35 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 0.3 VCCI 0.5 VCCI VCCI + 0.5 (per PCI specification) AC Loadings Per PCI Specification except for tristate. Microsemi loading for tristate is in Figure 2-19. R to VCCI for t pl R = 25 R to GND for t R =1 k ph R to VCCI for t /t plz pzl R to GND for t /t phz pzh Test Point Test point for data for tristate 10 pF 35 pF for t /t pzl pzh 5 pF for t /t phz plz GND Figure 2-19 • AC Test Loads Table 2-36 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load (Per PCI Spec) N/A 10 Note: *Measuring Point = V trip 2-64 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Characteristics Table 2-37 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 3.3V PCI I/O Module Timing t Input buffer 1.82 1.72 2.02 ns DP t Output buffer 2.38 2.25 2.64 ns PY t Enable to Pad delay through the 2.51 2.36 2.78 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 2.23 2.10 2.47 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.16 2.98 3.50 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 4.37 4.12 4.84 ns ENHZ Output Buffer—High to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET Revision 14 2-65 Detailed Specifications Table 2-38 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 3.3 V PCI-X I/O Module Timing t Input buffer 1.82 1.72 2.02 ns DP t Output buffer 2.44 2.30 2.71 ns PY t Enable to Pad delay through the 2.51 2.36 2.78 ns ENZL Output Buffer—Z to Low t Enable to Pad delay through the 2.44 2.30 2.70 ns ENZH Output Buffer—Z to High t Enable to Pad delay through the 3.29 3.10 3.65 ns ENLZ Output Buffer—Low to Z t Enable to Pad delay through the 3.87 3.64 4.28 ns ENHZ Output Buffer—HIgh to Z t Sequential clock-to-Q for the input 0.95 0.90 1.05 ns IOCLKQ register t Clock-to-output Y for the I/O output 0.95 0.90 1.05 ns IOCLKY register and the enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.21 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-66 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Voltage-Referenced I/O Standards GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer and an open drain output buffer. The VCCI pin should be connected to 2.5 V or 3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range. Table 2-39 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA N/A VREF – 0.1 VREF + 0.1 N/A 0.6 NA NA NA Note: For high temperature of 125°C only, VOL limits are 700 mV, for all other temperatures 600 mV applies. AC Loadings VTT 25 Test Point 10 pF Figure 2-20 • AC Test Loads Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ) (V) C (pF) REF load VREF-0.2 VREF+0.2 VREF 1.0 10 Note: *Measuring Point = V trip Revision 14 2-67 Detailed Specifications Timing Characteristics Table 2-41 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed 'Std.' Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 3.3 V GTL+ I/O Module Timing t Input buffer 2.13 2.01 2.36 ns DP t Output buffer 1.34 1.26 1.49 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output 0.95 0.90 1.05 ns OCLKQ register and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-68 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The RTAX-S/SL devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer. Table 2-42 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V1 V VmA mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCC – 0.4 8 –8 AC Loadings VTT 50 Test Point 20 pF Figure 2-21 • AC Test Loads Table 2-43 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ) (V) C (pF) REF load VREF – 0.5 VREF + 0.5 VREF 0.75 20 Note: *Measuring Point = V trip Revision 14 2-69 Detailed Specifications Timing Characteristics Table 2-44 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 125°C –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 1.5 V HSTL Class I I/O Module Timing t Input buffer 2.24 2.12 2.49 ns DP t Output buffer 5.68 5.35 6.29 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-70 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs SSTL2 Stub Series Terminated Logic for 2.5 V is a general-purpose 2.5 V memory bus standard (JESD8-9). The RTAX-S/SL devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-45 • DC Input and Output Levels VIL V VOL VOH IOL IOH IH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.57 VREF + 0.57 7.6 –7.6 AC Loadings VTT 50 Test Point 25 30 pF Figure 2-22 • AC Test Loads Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ) (V) C (pF) REF load VREF – 0.75 VREF + 0.75 VREF 1.25 30 Note: *Measuring Point = V trip Revision 14 2-71 Detailed Specifications Timing Characteristics Table 2-47 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 2.5 V SSTL2 Class I I/O Module Timing t Input buffer 2.28 2.14 2.52 ns DP t Output buffer 2.77 2.61 3.07 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-72 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Class II Table 2-48 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 15.2 –15.2 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-23 • AC Test Loads Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load VREF – 0.75 VREF+0.75 VREF 1.25 30 Note: *Measuring Point = V trip Revision 14 2-73 Detailed Specifications Timing Characteristics Table 2-50 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 2.5 V SSTL2 Class II I/O Module Timing t Input buffer 2.36 2.22 2.61 ns DP t Output buffer 2.77 2.61 3.07 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-74 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs SSTL3 Stub Series Terminated Logic for 3.3 V is a general-purpose 3.3 V memory bus standard (JESD8-8). The RTAX-S/SL devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-51 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 VREF – 0.2 VREF + 0.2 3.6 VREF– 0.6 VREF + 0.6 8 –8 AC Loadings VTT 50 Test Point 25 30 pF Figure 2-24 • AC Test Loads Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) C (pF) load VREF-1.0 VREF+1.0 VREF 1.50 30 Note: *Measuring Point = V trip Revision 14 2-75 Detailed Specifications Timing Characteristics Table 2-53 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 3.3 V SSTL3 Class I I/O Module Timing t Input buffer 2.22 2.09 2.46 ns DP t Output buffer 2.70 2.55 2.99 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-76 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Class II Table 2-54 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min. Max. Min. Max. Max. Min. V V V V V VmA mA –0.3 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-25 • AC Test Loads Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ) (V) C (pF) REF load VREF – 1.0 VREF + 1.0 VREF 1.50 30 Note: *Measuring Point = V trip Revision 14 2-77 Detailed Specifications Timing Characteristics Table 2-56 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units 3.3 V SSTL3 Class II I/O Module Timing t Input buffer 2.30 2.16 2.55 ns DP t Output buffer 2.70 2.55 2.99 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-78 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Differential Standards Physical Implementation Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting in a single internal signal. To facilitate construction of the differential pair, a single I/O cluster contains the resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Microsemi's Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), and Enable Register (EnReg). However, there is no support for bidirectional I/Os or tristates with these standards. LVDS Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV. FPGA FPGA OUTBUF_LVDS P P 165 Ω ZO = 50 Ω INBUF_LVDS + 140 Ω 100 Ω – 165 Ω ZO = 50 Ω N N Figure 2-26 • LVDS Circuit The LVDS circuit consists of a differential driver connected to a terminated receiver through a constant- impedance transmission line. The receiver is a wide-common-mode-range differential amplifier. The common-mode range is from 0.2 V to 2.2 V for a differential input with 400 mV swing. To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the differential signals (Note that the driver is not a current-mode driver). This driver provides a nominal constant current of 3.5 mA. When this current flows through a 100 Ω termination resistor on the receiver side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is controlled by the data fed to the driver. An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV. Therefore, four external resistors are required, three for the driver and one for the receiver. Table 2-57 • DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 1 VCCI Supply voltage 2.375 2.5 2.625 V VOL Output low voltage 0.9 1.075 1.25 V VOH Output high voltage 1.25 1.425 1.6 V VI Input voltage 0 2.925 V V Differential output voltage 250 350 450 mV ODIFF V Output common mode voltage 1.125 1.25 1.375 V OCM 2 Input common mode voltage 0.2 1.25 2.2 V V ICM V Differential input voltage 100 350 mV IDIFF Notes: 1. ± 5% 2. Differential input voltage = ±400 mV. Revision 14 2-79 Detailed Specifications AC Loadings For AC test loads, see the above LVDS circuit. Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C (pF) load 1.2 – 0.125 1.2 + 0.125 1.2 N/A Note: *Measuring Point = V trip Timing Characteristics Table 2-59 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVDS I/O Module Timing t Input buffer 2.12 2.00 2.35 ns DP t Output buffer 2.70 2.54 2.99 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register and 0.95 0.90 1.05 ns OCLKQ the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-80 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. FPGA FPGA P P 100 Ω ZO = 50 Ω OUTBUF_LVPECL + INBUF_LVPECL 187 Ω 100 Ω – 100 Ω ZO = 50 Ω N N Figure 2-27 • LVPECL Circuit The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS, since the output voltage levels are different. Please note that the V levels are 200 mV below the standard OH LVPECL levels. Table 2-60 • DC Input and Output Levels DC Parameter Description Min. Max. Min. Max. Min. Max. Units VCCI Supply voltage 3.0 3.3 3.6 V VOL Output Low voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL Input Low voltages 0.86 2.125 0.86 2.125 0.86 2.125 V VIH Input High voltages 1.49 2.72 1.49 2.72 1.49 2.72 V VODIFF Differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output common mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input common mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 VIDIFF Input differential voltage 300 – 300 – 300 – mV AC Loadings For AC test loads, See the above LVPECL circuit. Table 2-61 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C (pF) load 1.6 – 0.3 1.6 + 0.3 1.6 N/A Note: *Measuring Point = V trip Revision 14 2-81 Detailed Specifications Timing Characteristics Table 2-62 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units LVPECL Output Module Timing t Input buffer 1.94 1.83 2.15 ns DP t Output buffer 2.60 2.45 2.88 ns PY t Clock-to-Q for the I/O input register 0.95 0.90 1.05 ns ICLKQ t Clock-to-Q for the I/O output register 0.95 0.90 1.05 ns OCLKQ and the I/O enable register t Data input setup 0.33 0.31 0.36 ns SUD t Enable input setup 0.36 0.34 0.40 ns SUE t Data input hold 0.00 0.00 0.00 ns HD t Enable input hold 0.00 0.00 0.00 ns HE t Clock pulse width High to Low 0.39 0.39 0.39 ns CPWHL t Clock pulse width Low to High 0.39 0.39 0.39 ns CPWLH t Asynchronous pulse width 0.37 0.37 0.37 ns WASYN t Asynchronous recovery time 0.18 0.17 0.20 ns REASYN t Asynchronous removal time 0.00 0.00 0.00 ns HASYN t Asynchronous Clear-to-Q 0.33 0.31 0.37 ns CLR t Asynchronous Preset-to-Q 0.33 0.31 0.37 ns PRESET 2-82 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Module Specifications C-Cell Introduction The C-cell is one of the two logic module types in the RTAX-S/SL/DSP architecture. It is the combinatorial logic resource in the RTAX-S/SL/DSP device. The RTAX-S/SL/DSP architecture implements a new Combinatorial Cell that is an extension of the C-cell implemented in the A54SX-A family. The main enhancement of the new C-cell is the addition of carry-chain logic. The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not required, it can be disabled. The C-cell features the following (Figure 2-28): • Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed clocks (CLKE/F/G/H). • Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell. • A carry input and a carry output. The carry input signal of the C-cell is the carry output from the C-cell directly to the north. • Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. • A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the east side of a SuperCluster with a signal propagation time of less than 0.1 ns. This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The carry-chain configuration is handled automatically for the user with the extensive Microsemi macro library. Refer to the Antifuse Macro Library Guide for a complete listing of available RTAX-S/SL macros. D1 D3 B0 B1 CFN FCI 0 1 0 1 0 1 0 1 0 1 D0 D2 DB A0 A1 FCO Y Figure 2-28 • C-Cell Revision 14 2-83 Detailed Specifications Timing Model and Waveforms VCCA 50% 50% A, B, D, FCI GND VCCA 50% 50% Y, FCO GND t , t t , t PD PDC PD PDC Y, FCO VCCA 50% 50% GND t , t t , t PD PDC PD PDC Figure 2-29 • C-Cell Timing Model and Waveforms Timing Characteristics Table 2-63 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays t Any input to output 0.99 0.93 1.10 ns PD t Any input to carry chain output 0.73 0.69 0.81 ns PDC (FCO) t Any input thorough DB when 1 input 1.55 1.46 1.72 ns PDB is used t Input carry chain (FCI) to Y 0.80 0.75 0.88 ns CCY t Input carry chain (FCI) to carry chain 0.11 0.10 0.12 ns CC output (FCO) 2-84 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Carry-Chain Logic The RTAX-S/SL/DSP dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e., carry out) for the two bits is generated in a Carry Look-ahead scheme to achieve minimum propagation delay from the FCI (i.e., carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-30. The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-5 on page 1-3 and Figure 2-31 on page 2-86). The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through the Microsemi macro library. The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns. 0 1 0 0 1 1 0 DCOUT 0 1 1 0 1 0 1 0 1 0 1 Figure 2-30 • RTAX-S/SL/DSP Two-Bit Carry Logic Revision 14 2-85 D0 D2 D1 D3 B0 B1 DB A0 0 A1 1 CFN FCI Y D0 D1 D2 D3 B0 B1 DB A0 0 A1 1 CFN FCO Y Detailed Specifications FCI 1 C-cell2 R-cell1 C-cell1 DCOUT DCIN FCO 2 FCI 3 DCOUT DCIN FCO 4 FCI 5 n-2 Clusters FCI (2n-1) R-celln C-cell C-cell2n CDIN (2n-1) DCOUT FCO 2n Note: The carry-chain sequence can end on either C-cell. Figure 2-31 • Carry-Chain Sequencing of C-Cells Timing Characteristics Refer to the C-cell timing characteristics in Table 2-63 on page 2-84 for more information on carry-chain timing. 2-86 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs R-Cell Introduction The R-cell, the sequential logic resource of the RTAX-S/SL/DSP devices, is the second logic module type in the RTAX-S/SL/DSP family architecture. The RTAX-S/SL/DSP R-cell is an enhanced version of the A54SX- A R-cell. It includes additional clock inputs for all eight global resources of the RTAX-S/SL/DSP architecture as well as global presets and clears (Figure 2-32). The main features of the R-cell include the following: • Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a connection with less than 0.1 ns of routing delay. • The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using the R-cell as a 2:1 MUXed flip-flop as well. • Provision of data enable-input (S0). • Independent active low asynchronous clear (CLR). • Independent active low asynchronous preset (PSET). If both CLR and PSET are low, CLR has higher priority. • Clock can be driven by any of the following (CKP selects clock polarity): – One of the four high performance hardwired fast clocks (HCLKs) – One of the four routed clocks (CLKs) – User signals • Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide basis. – When the Global Set Fuse option in the Designer software is unchecked (by default), GCLR = 0 and GPSET =1 at device power-up. When the option is checked, GCLR = 1 and GPSET= 0. Both pins are pulled HIGH when the device is in user mode. • S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals. • DIN and S1 can be driven by user signals. Revision 14 2-87 Detailed Specifications As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Microsemi's extensive macro library (please see the Macro Library Guide for a complete listing of available RTAX-S/SL macros). CKP DIN (user signals) DCIN SEU Enhanced D-FF HCLKA/B/C/D CLKE/F/G/H Internal Logic Y S1 S0 CKS Figure 2-32 • R-Cell 2-88 Revision 14 CLR GCLR PRE GPRE RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs SEU Hardened D Flip-Flop (DFF) 2 In order to meet the stringent SEU requirements of a LET greater than 37 MeV-cm /mg, the internal design TH of the R-cell was modified without changing the functionality of the cell. Figure 2-33 illustrates a simplified representation of how the D flip-flop in the SuperCluster is implemented in the RTAX-S/SL/DSP architecture. The flip-flop consists of a master and a slave latch gated by opposite edges of the clock. Each latch is constructed by feeding back the output to the input stage. The potential problem in a space environment is that either of the latches can change state when hit by a particle with enough energy. To achieve the SEU requirements, the D flip-flop in the RTAX-S/SL/DSP R-cell is enhanced (Figure 2-34). Both the master and slave "latches" are actually implemented with three latches. The asynchronous self-correcting feedback paths of each of the three latches is voted with the outputs of the other two latches. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch. Figure 2-35 on page 2-90 is a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip-flop. The inputs to each of the three latches are independently controllable, so the voting circuitry in the asynchronous self-correcting feedback paths can be tested exhaustively. This testing is performed on an unprogrammed array during wafer sort, final test, and post-burn-in test. This test circuitry cannot be used to test the flip-flops once the device has been programmed. D Q CLK CLK Figure 2-33 • RTAX-S/SL/DSP R-cell Implementation of D Flip-Flop Q D CLK CLK Voter Gate CLK CLK CLK CLK CLK CLK Figure 2-34 • RTAX-S/SL/DSP R-cell Implementation of D Flip-Flop Using Voter Gate Logic Revision 14 2-89 Detailed Specifications D Q Tst1 Voter Gate Tst2 Tst3 CLK Test Circuitry Figure 2-35 • RTAX-S/SL/DSP R-Cell Implementation – Test Circuitry 2-90 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Models and Waveforms D t t SUD HD CLK t t CPWHL CPWLH t RCO Q t t HASYN REASYN t CLR WASYN t t HASYN REASYN t t CLR PRESET t PRESET WASYN t t SUE HE E Figure 2-36 • R-Cell Delays Timing Characteristics Table 2-64 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units R-Cell Propagation Delays t Sequential Clock to Q 1.00 0.94 1.10 ns RCO t Asynchronous Clear to Q 0.66 0.62 0.73 ns CLR t Asynchronous Preset to Q 0.79 0.75 0.88 ns PRESET t FF Data input setup 0.22 0.21 0.25 ns SUD t FF Enable input setup 0.22 0.21 0.25 ns SUE t FF Data Hold 0.00 0.00 0.00 ns HD t FF Enable Hold time 0.00 0.00 0.00 ns HE t Asynchronous Pulse width 0.48 0.48 0.48 ns WASYN t Asynchronous Recovery time 0.00 0.00 0.00 ns REASYN t Asynchronous Removal time 0.00 0.00 0.00 ns HASYN t Clock pulse width high to low 0.35 0.35 0.35 ns CPWHL t Clock pulse width low to high 0.36 0.36 0.36 ns CPWLH Revision 14 2-91 Detailed Specifications Buffer Module Introduction An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to the RTAX-S/SL/DSP architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets. Timing Models and Waveforms IN OUT Figure 2-37 • Buffer Module Timing Model VCCA 50% 50% IN GND VCCA 50% 50% OUT GND t t BFPD BFPD Figure 2-38 • Buffer Module Waveform Timing Characteristics Table 2-65 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C J –1 Speed Std. Speed RTAX4000S/SL RTAX250/1000/2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units t Any input to output Y 0.18 0.17 0.20 ns BFPD 2-92 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Mathblock Timing Specification Mathblock Timing Characteristics Table 2-66 • Mathblock with All Registers Used Worst-Case Military Conditions VCCA = 1.425 V, T = 125°C J Std. Speed Parameter Description Min. Max. Units t A, B, control register setup vs. CLK 0.36 ns MSUR t A, B, control register hold vs. CLK 0.00 ns MHR t Carry inputs setup vs. CLK 4.40 ns MSUC t Carry inputs hold vs. CLK 0.00 ns MHC t Sequential clock to output propagation delay 3.83 ns MCQR t CLK Minimum period 8.05 ns MPMIN SUB t = 0.36 ns MSUR t = 0.00 ns MHR A CDOUT[40:0] t = 0.36 ns MSUR t = 0.00 ns MHR OVERFLOW X t = 8.05 ns MPMIN B t = 0.36 ns MSUR C P[40:0] t = 0.00 ns MHR ARSHFT17 t = 0.36 ns MSUR >> t = 0.00 ns MHR t = 3.83 ns MCQR t = 8.05 ns MPMIN SLOAD_N t = 0.36 ns MSUR t = 0.00 ns MHR SLOAD_DATA t = 4.40 ns MSUC t = 0.00 ns MHC Figure 2-39 • Timing Diagram for Mathblock with All Registers Used Revision 14 2-93 Detailed Specifications Table 2-67 • Mathblock with Output Registers Used and Input Registers Bypassed Worst-Case Military Conditions VCCA = 1.425 V, T = 125°C J Std. Speed Parameter Description Min. Max. Units 1 t Output register setup vs. CLK 5.77 ns MSUO 2 t Output register hold vs. CLK 0.00 ns MHO t Carry inputs setup vs. CLK 4.40 ns MSUC t Carry inputs hold vs. CLK 0.00 ns MHC t Sequential clock to output propagation delay 3.83 ns MCQO t CLK Minimum period 8.05 ns MPMIN Notes: 1. This parameter originally was named "A, B, control register setup vs. CLK." 2. This parameter originally was named "A, B, control register hold vs. CLK." SUB t = 5.77 ns MSUO t = 0.00 ns MHO A CDOUT[40:0] t = 5.77 ns MSUO t = 0.00 ns MHO OVERFLOW X B t = 5.77 ns MSUO C P[40:0] t = 0.00 ns MHO ARSHFT17 t = 5.77 ns >> MSUO t = 0.00 ns MHO t = 3.83 ns MCQR t = 8.05 ns MPMIN SLOAD_N t = 5.77 ns MSUO t = 0.00 ns MHO SLOAD_DATA t = 4.40 ns MSUC t = 0.00 ns MHC Figure 2-40 • Timing Diagram for Mathblock with Output Registers Used and Input Register Bypassed 2-94 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-68 • Mathblock with Output Registers Bypassed and Input Registers Used Worst-Case Military Conditions VCCA = 1.425 V, T = 125°C J Std. Speed Parameter Description Min. Max. Units t A, B, control register setup vs. CLK 0.36 ns MSUR t A, B, control register hold vs. CLK 0.00 ns MHR t Sequential clock to output propagation delay 7.97 ns MCQI t Carry inputs to any outputs propagation delay 7.43 ns MPDC SUB t = 0.36 ns MSUR t = 0.00 ns MHR A CDOUT[40:0] t = 0.36 ns MSUR t = 0.00 ns MHR OVERFLOW X t = 7.97 ns MCQI B t = 0.36 ns MSUR C P[40:0] t = 0.00 ns MHR ARSHFT17 t = 0.36 ns MSUR >> t = 0.00 ns MHR SLOAD_N t = 0.36 ns MSUR t = 0.00 ns MHR SLOAD_DATA t = 7.43 ns MPDC Figure 2-41 • Mathblock with Output Registers Bypassed and Input Registers Used Revision 14 2-95 Detailed Specifications Table 2-69 • Mathblock with All Registers Bypassed Worst-Case Military Conditions VCCA = 1.425 V, T = 125°C J Std. Speed Parameter Description Min. Max. Units t A, B, control registers to any outputs propagation delay 8.69 ns MPDB t Carry inputs to any outputs propagation delay 7.43 ns MPDC SUB t = 8.69 ns MPDB A CDOUT[40:0] t = 8.69 ns MPDB OVERFLOW X B t = 8.69 ns MPDB C P[40:0] ARSHFT17 t = 8.69 ns MPDB >> SLOAD_N t = 8.69 ns MPDB SLOAD_DATA t = 7.43 ns MPDC Figure 2-42 • Timing Diagram for Mathblock with All Registers Bypassed 2-96 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Routing Specifications Routing Resources The routing structure found in RTAX-S/SL/DSP devices enables any logic module to be connected to any other logic module while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are four primary types of routing within the RTAX-S/SL/DSP architecture: DirectConnect, CarryConnect, FastConnect and Vertical and Horizontal Routing. DirectConnect DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-43). This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. Figure 2-43 • DirectConnect and CarryConnect CarryConnect CarryConnects are used to build carry chains for arithmetic functions (Figure 2-43). The FCO output of the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster immediately below it. This pattern continues down both sides of each SuperCluster column. Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This connection has a delay of less than 0.1 ns from the FCO of one two-C-cell Cluster to the FCI of the two- C-cell Cluster immediately below it (see the "Carry-Chain Logic" on page 2-85 for more information). FastConnect For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 2-44 on page 2-98). FastConnects provide a maximum delay of 0.4 ns. The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on the Output Tracks can then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below it. Vertical and Horizontal Routing Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-45 on page 2-98). These tracks are composed of both short-distance, segmented routing and across-chip routing tracks (segmented at core tile boundaries). The short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. Revision 14 2-97 Detailed Specifications These short-distance routing tracks can be used within and between SuperClusters or between modules of non-adjacent SuperClusters. They can be connected to the Output Tracks and to any logic module input (R-cell, C-cell, Buffer, and TX module). The across-chip horizontal and vertical routing provides long-distance, routing resources. These resources interface with the rest of the routing structures through the RX and TX modules (Figure 2-45). The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output Tracks within the SuperCluster. The TX module is used to drive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. Figure 2-44 • FastConnect Routing Figure 2-45 • Horizontal and Vertical Tracks 2-98 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Characteristics Table 2-70 • RTAX250S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Unit Predicted Routing Delays t Direct connect 0.08 0.07 ns DC t Fast connect F01 0.24 0.29 ns FC t Fanout 1 0.66 0.77 ns RD1 t Fanout 2 0.84 0.99 ns RD2 t Fanout 3 1.07 1.25 ns RD3 t Fanout 4 1.38 1.62 ns RD4 t Fanout 5 1.45 1.7 ns RD5 t Fanout 6 2.08 2.44 ns RD6 t Fanout 7 2.26 2.66 ns RD7 t Fanout 8 2.44 2.87 ns RD8 t Fanout 9 2.87 3.37 ns RD9 t Fanout 10 3.3 3.88 ns RD10 Table 2-71 • RTAX1000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Unit Predicted Routing Delays t Direct connect 0.08 0.07 ns DC t Fast connect F01 0.24 0.29 ns FC t Fanout 1 0.66 0.77 ns RD1 t Fanout 2 0.84 0.99 ns RD2 t Fanout 3 1.07 1.25 ns RD3 t Fanout 4 1.38 1.62 ns RD4 t Fanout 5 1.45 1.7 ns RD5 t Fanout 6 2.08 2.44 ns RD6 t Fanout 7 2.26 2.66 ns RD7 t Fanout 8 2.44 2.87 ns RD8 t Fanout 9 2.87 3.37 ns RD9 t Fanout 10 3.3 3.88 ns RD10 Revision 14 2-99 Detailed Specifications Table 2-72 • RTAX2000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Unit Predicted Routing Delays t Direct connect 0.08 0.07 ns DC t Fast connect F01 0.24 0.29 ns FC t Fanout 1 0.66 0.77 ns RD1 t Fanout 2 0.84 0.99 ns RD2 t Fanout 3 1.07 1.25 ns RD3 t Fanout 4 1.38 1.62 ns RD4 t Fanout 5 1.45 1.70 ns RD5 t Fanout 6 2.08 2.44 ns RD6 t Fanout 7 2.26 2.66 ns RD7 t Fanout 8 2.44 2.87 ns RD8 t Fanout 9 2.87 3.37 ns RD9 t Fanout 10 3.30 3.88 ns RD10 Table 2-73 • RTAX2000D (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J Std. Speed Parameter Description Min. Max. Unit Predicted Routing Delays t Direct connect 0.07 ns DC t Fast connect F01 0.29 ns FC t Fanout 1 0.77 ns RD1 t Fanout 2 0.99 ns RD2 t Fanout 3 1.25 ns RD3 t Fanout 4 1.62 ns RD4 t Fanout 5 1.70 ns RD5 t Fanout 6 2.44 ns RD6 t Fanout 7 2.66 ns RD7 t Fanout 8 2.87 ns RD8 t Fanout 9 3.37 ns RD9 t Fanout 10 3.88 ns RD10 2-100 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-74 • RTAX4000S (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Unit Predicted Routing Delays t Direct connect 0.06 0.07 ns DC t Fast connect F01 0.26 0.29 ns FC t Fanout 1 0.69 0.77 ns RD1 t Fanout 2 0.89 0.99 ns RD2 t Fanout 3 1.13 1.25 ns RD3 t Fanout 4 1.46 1.62 ns RD4 t Fanout 5 1.53 1.7 ns RD5 t Fanout 6 2.20 2.44 ns RD6 t Fanout 7 2.39 2.66 ns RD7 t Fanout 8 2.58 2.87 ns RD8 t Fanout 9 3.03 3.37 ns RD9 t Fanout 10 3.49 3.88 ns RD10 Table 2-75 • RTAX4000D (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, T = 125°C) J Std. Speed Parameter Description Min. Max. Unit Predicted Routing Delays t Direct connect 0.07 ns DC t Fast connect F01 0.29 ns FC t Fanout 1 0.77 ns RD1 t Fanout 2 0.99 ns RD2 t Fanout 3 1.25 ns RD3 t Fanout 4 1.62 ns RD4 t Fanout 5 1.7 ns RD5 t Fanout 6 2.44 ns RD6 t Fanout 7 2.66 ns RD7 t Fanout 8 2.87 ns RD8 t Fanout 9 3.37 ns RD9 t Fanout 10 3.88 ns RD10 Revision 14 2-101 Detailed Specifications Global Resources One of the most important aspects of any FPGA architecture is its global resources or clocks. The RTAX- S/SL family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures. In addition, these global resources have been hardened to improve SEU performance. The RTAX-S/SL architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed clock). Every RTAX-S/SL device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density. Hardwired Clocks The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip. Timing Characteristics Table 2-76 • RTAX250S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 2.75 3.23 ns HCKL t Input High to Low 2.94 3.45 ns HCKH Table 2-77 • RTAX250S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 0.77 0.77 ns HPWH t Minimum Pulse width Low 0.26 0.26 ns HPWL 1 f Maximum frequency 649 649 MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL Table 2-78 • RTAX1000S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 3.64 4.28 ns HCKL t Input High to Low 3.47 4.08 ns HCKH Table 2-79 • RTAX1000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 0.86 0.86 ns HPWH t Minimum Pulse width Low 0.31 0.31 ns HPWL 1 f Maximum frequency 581 581 MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL 2-102 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-80 • RTAX2000S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 3.64 4.28 ns HCKL t Input High to Low 3.47 4.08 ns HCKH Table 2-81 • RTAX2000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 0.77 0.77 ns HPWH t Minimum Pulse width Low 0.26 0.26 ns HPWL 1 f Maximum frequency 649 649 MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL Table 2-82 • RTAX4000S (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 5.67 6.28 ns HCKL t Input High to Low 5.47 6.06 ns HCKH Table 2-83 • RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High TBD TBD ns HPWH t Minimum Pulse width Low TBD TBD ns HPWL 1 f Maximum frequency TBD TBD MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL Table 2-84 • RTAX4000D Worst-Case Military Conditions (VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) 'Std.' Speed Parameter Description Min. Max. Units t Input Low to High TBD ns HCKL t Input High to Low TBD ns HCKH f Maximum skew TBD ns HCKSW Table 2-85 • RTAX2000D Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J Std. Speed Parameter Description Min. Max. Units t Minimum Pulse width High TBD ns HPWH t Minimum Pulse width Low TBD ns HPWL 1 f Maximum frequency TBD MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL Revision 14 2-103 Detailed Specifications Table 2-86 • RTAX4000D Worst-Case Military Conditions (VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) Std. Speed Parameter Description Min. Max. Units t Input Low to High TBD ns HCKL t Input High to Low TBD ns HCKH f Maximum skew TBD ns HCKSW Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL Table 2-87 • RTAX4000D Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J Std. Speed Parameter Description Min. Max. Units t Minimum Pulse width High TBD ns HPWH t Minimum Pulse width Low TBD ns HPWL 1 f Maximum frequency TBD MHz HMAX Note: *f = 1000 / (2*(MAX(t ,t ))) HMAX HPWH HPWL 2-104 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Routed Clocks The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip. Timing Characteristics Timing characteristics are shown in Table 2-88 through Table 2-95. Table 2-88 • RTAX250S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 2.77 3.25 ns RCKL t Input High to Low 2.91 3.42 ns RCKH t Maximum skew – 16 Loads 1.40 1.64 ns RCKSW Maximum skew – 24 Loads 1.80 2.12 ns Table 2-89 • RTAX250S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 0.79 0.79 ns RPWH t Minimum Pulse width Low 0.27 0.27 ns RPWL 1 f Maximum frequency 633 633 MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Table 2-90 • RTAX1000S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 3.71 4.36 ns RCKL t Input High to Low 3.53 4.14 ns RCKH t Maximum skew – 16 Loads 1.39 1.63 ns RCKSW Maximum skew – 24 Loads 1.80 2.11 ns Maximum skew – 36 Loads 1.86 2.19 ns = 125°C) Table 2-91 • RTAX1000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 1.04 1.04 ns RPWH t Minimum Pulse width Low 0.33 0.33 ns RPWL 1 f Maximum frequency 481 481 MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Revision 14 2-105 Detailed Specifications Table 2-92 • RTAX2000S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C) –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 3.71 4.36 ns RCKL t Input High to Low 3.53 4.14 ns RCKH t Maximum skew – 16 Loads 1.39 1.63 ns RCKSW Maximum skew – 24 Loads 1.80 2.11 ns Maximum skew – 36 Loads 2.11 2.48 ns Table 2-93 • RTAX2000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High 0.79 0.79 ns RPWH t Minimum Pulse width Low 0.27 0.27 ns RPWL 1 f Maximum frequency 633 633 MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Table 2-94 • RTAX4000S (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Input Low to High 5.77 6.39 ns RCKL t Input High to Low 5.56 6.16 ns RCKH t Maximum skew – 16 Loads 1.47 1.62 ns RCKSW Maximum skew – 24 Loads 1.90 2.10 ns Maximum skew – 36 Loads 1.94 2.15 ns Table 2-95 • RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J –1 Speed Std. Speed Parameter Description Min. Max. Min. Max. Units t Minimum Pulse width High TBD TBD ns RPWH t Minimum Pulse width Low TBD TBD ns RPWL 1 f Maximum frequency TBD TBD MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Table 2-96 • RTAX2000D (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) Std. Speed Parameter Description Min. Max. Units t Input Low to High TBD ns RCKL t Input High to Low TBD ns RCKH t Maximum skew – 16 Loads TBD ns RCKSW Maximum skew – 24 Loads TBD ns Maximum skew – 36 Loads TBD ns 2-106 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-97 • RTAX2000D Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J Std. Speed Parameter Description Min. Max. Units t Minimum Pulse width High TBD ns RPWH t Minimum Pulse width Low TBD ns RPWL 1 f Maximum frequency TBD MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Table 2-98 • RTAX4000D (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = J 125°C) 'Std.' Speed Parameter Description Min. Max. Units t Input Low to High TBD ns RCKL t Input High to Low TBD ns RCKH t Maximum skew – 16 Loads TBD ns RCKSW Maximum skew – 24 Loads TBD ns Maximum skew – 36 Loads TBD ns Table 2-99 • RTAX4000D Worst-Case MPW (VCCA = 1.575 V, V = 3.6 V, T = 125°C) CCI J Std. Speed Parameter Description Min. Max. Units t Minimum Pulse width High TBD ns RPWH t Minimum Pulse width Low TBD ns RPWL 1 f Maximum frequency TBD MHz RMAX Note: *f = 1000 / (2*(MAX(t ,t ))) RMAX RPWH RPWL Revision 14 2-107 Detailed Specifications Global Resource Distribution At the root of each global resource is a ClockDistBuffer (CDB). There are two groups of four CDBs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-46). Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 2-47). PN P N P N P N CDB Cluster HCLKA HCLKB HCLKC HCLKD CLKE CLKF CLKG CLKH CDB Cluster PN P N P N P N Figure 2-46 • ClockDistBuffer Group HCLK CLK CDB Cluster ClockTileDist Cluster 4 4 CDB Cluster Figure 2-47 • Example of HCLK and CLK Distributions on the RTAX2000S/SL 2-108 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK branches propagate vertically through the center of the core tile to CLKRowDist (RD) modules in every SuperCluster row. Together, the HCLK and CLK branches provide for a low-skew global fanout within the core tile (Figure 2-48 and Figure 2-49). Figure 2-48 • CTD, CD, and HD Module Layout Figure 2-49 • HCLK and CLK Distribution within a Core Tile Revision 14 2-109 Detailed Specifications The HM and CM modules can select between: • The HCLK or CLK source • A local signal routed on generic routing resources This allows each core tile to have eight clocks independent of the other core tiles in the device. Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. Like the HM and CM modules, the HD and RD modules can select between: • The HCLK or CLK source from the HM or CM module, respectively • A local signal routed on generic routing resources Again, an unused input can be tied to ground for power savings. The RTAX-S/SL architecture is capable of supporting a large number of local clocks. Refer to the RTAX-S/SL Clocking Resource and Implementation application note for more information. Microsemi Designer software’s place-and-route takes advantage of the segmented clock structure found in RTAX-S/SL devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption. Future releases of Designer will give the user greater control over these individual clock segments. Global Resource Access Macros Global resources can be driven by one of three sources: external pad(s) or an internal net. These connections can be made by using one of two types of macros: CLKBUF and CLKINT. CLKBUF and HCLKBUF CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g., CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-50). P Clock Network CLKBUF N HCLKBUF Figure 2-50 • CLKBUF and HCLKBUF Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the P- pad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals. CLKINT and HCLKINT CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-51). Clock Logic Network CLKINT HCLKINT Figure 2-51 • CLKINT and HCLKINT 2-110 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Embedded Memory The RTAX-S/SL architecture provides extensive, high-speed memory resources to the user. Each 4,608- bit block of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either RAM or FIFO. To meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write operations. However, the read and write clocks are completely independent, and each may operate beyond 500 MHz. No additional core logic resources are required to cascade the address and data buses when cascading different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading. The RTAX-S/SL memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A block diagram of the memory module is illustrated in Figure 2-52. During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion. RA [K:0] RD [(N-1):0] REN RCLK WD [(M-1):0] WA [J:0] WEN WCLK PIPE RW [2:0] WW [2:0] Figure 2-52 • RTAX-S/SL Memory Module RAM Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion (Table 2-100). Each block has independent read and write ports, which enable simultaneous read and write operations. Simultaneous read and write operations to the same address is not supported. Revision 14 2-111 Detailed Specifications Table 2-100 • Memory Block WxD Options Data-Word (in bits) Depth Address Bus Data Bus 1 4,096 RA/WA[11:0] RD/WD[0] 2 2,048 RA/WA[10:0] RD/WD[1:0] 4 1,024 RA/WA[9:0] RD/WD[3:0] 9 512 RA/WA[8:0] RD/WD[8:0] 18 256 RA/WA[7:0] RD/WD[17:0] 36 128 RA/WA[6:0] RD/WD[35:0] Clocks The RCLK and the WCLK have independent source polarity selection and can be sourced by any global or local signal. RAM Configurations The RTAX-S/SL architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins. The available DxW configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2, and 4kx1. The allowable RW and WW values are shown in Table 2-102. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine- bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four- bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. Note that the RAM blocks employ little-endian byte order for read and write operations. Table 2-101 • RAM Signal Description Signal Direction Description WCLK Input Write clock (can be active on either edge). WA[J:0] Input Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. WD[M-1:0] Input Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. RCLK Input Read clock (can be active on either edge). RA[K:0] Input Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. REN Input Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. WEN Input Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. RW[2:0] Input Width of the read operation dataword. WW[2:0] Input Width of the write operation dataword. Pipe Input Sets the pipeline option to be on or off. 2-112 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-102 • Allowable RW and WW Values RW(2:0) WW(2:0) D x W 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101 101 128x36 11x 11x reserved Modes of Operation There are two read modes and one write mode: 1. Read Nonpipelined (synchronous – one clock edge): In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read-port active-clock edge and data appears at read-data after the RAM access time. Setting PIPE to OFF enables this mode. 2. Read Pipelined (synchronous – two clock edges): The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode. 3. Write (synchronous – one clock edge): On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements beginning in "Timing Characteristics" on page 2-115. Enhancing SEU Performance SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. To allow users to achieve high levels of SEU performance, Microsemi has developed an intellectual property (IP) core to enhance the SEU tolerance of the embedded SRAM within RTAX-S/SL. This IP employs two upset-mitigation techniques: • Error Detection and Correction (EDAC) • A background memory-refresher, or scrubber The EDAC IP employs the use of shortened Hamming Codes to provide the user with single-error correction/double-error detection (SEC/DED) capabilities. These shortened Hamming Codes provide the user with an implementation that has a reduced number of logic levels and less complexity than traditional Hamming Codes. The SmartGen-generated EDAC IP supports RAM widths of 8, 16, and 32 bits, with a variable RAM depth from 256 to 4k words. The memory scrubber circuitry has also been embedded in the EDAC IP as an optional block. The scrubber circuitry periodically refreshes memory in the background to ensure that no corruption of its contents has taken place while the memory was not in use. The refresh rate can be set by the user. The use of EDAC IP combined with the embedded memory scrubber circuitry, gives the RTAX-S/SL an -10 SEU radiation performance level of better than 10 errors/bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. Revision 14 2-113 Detailed Specifications Timing Model and Waveforms WD RD WA RA WCLK RCLK WEN REN Figure 2-53 • SRAM Model t t t WCKP WCKH WCKL WCLK t t WxxSU WxxHD WA<11:0>, WD<35:0>, WEN<4:0> Figure 2-54 • RAM Write Timing Waveforms t t t RCKH RCKL RCKP RCLK t t RxxSU RxxHD RA<11:0>, REN<4:0> t t RCK2RD2 RCK2RD1 RD <35:0> Figure 2-55 • RAM Read Timing Waveforms 2-114 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Timing Characteristics Table 2-103 • One RAM Block* (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode t Write Data Setup vs. WCLK 1.51 1.42 1.67 ns WDASU t Write Data Hold vs. WCLK 0.31 0.29 0.34 ns WDAHD t Write Address Setup vs. WCLK 1.51 1.42 1.67 ns WADSU t Write Address Hold vs. WCLK 0.00 0.00 0.00 ns WADHD t Write Enable Setup vs. WCLK 1.51 1.42 1.67 ns WENSU t Write Enable Hold vs. WCLK 0.31 0.29 0.34 ns WENHD t WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns WCKH t WCLK Minimum Low Pulse Width 0.88 0.88 0.88 ns WCLKL t WCLK Minimum Period 1.63 1.63 1.63 ns WCKP Read Mode t Read Address Setup vs. RCLK 1.13 1.06 1.25 ns RADSU t Read Address Hold vs. RCLK 0.00 0.00 0.00 ns RADHD t Read Enable Setup vs. RCLK 1.13 1.06 1.25 ns RENSU t Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns RENHD t RCLK-To-OUT (Pipelined) 1.85 1.74 2.05 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.02 2.85 3.35 ns RCK2RD2 t RCLK Minimum High Pulse Width 0.77 0.77 0.77 ns RCLKH t RCLK Minimum Low Pulse Width 0.93 0.93 0.93 ns RCLKL t RCLK Minimum Period 1.70 1.70 1.70 ns RCKP Note: *Timing data for this single block RAM has a depth of 4,096. For all other combinations, use Microsemi's SmartTime tool. Revision 14 2-115 Detailed Specifications Table 2-104 • Two RAM Blocks* Are Cascaded (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode t Write Data Setup vs. WCLK 1.95 1.83 2.16 ns WDASU t Write Data Hold vs. WCLK 0.00 0.00 0.00 ns WDAHD t Write Address Setup vs. WCLK 1.95 1.83 2.16 ns WADSU t Write Address Hold vs. WCLK 0.00 0.00 0.00 ns WADHD t Write Enable Setup vs. WCLK 1.95 1.83 2.16 ns WENSU t Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns WENHD t WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns WCKH t WCLK Minimum Low Pulse Width 1.76 1.76 1.76 ns WCLKL t WCLK Minimum Period 2.51 2.51 2.51 ns WCKP Read Mode t Read Address Setup vs. RCLK 2.38 2.24 2.64 ns RADSU t Read Address Hold vs. RCLK 0.00 0.00 0.00 ns RADHD t Read Enable Setup vs. RCLK 2.38 2.24 2.64 ns RENSU t Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns RENHD t RCLK-To-OUT (Pipelined) 2.00 1.89 2.22 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.16 2.98 3.50 ns RCK2RD2 t RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns RCLKH t RCLK Minimum Low Pulse Width 1.89 1.89 1.89 ns RCLKL t RCLK Minimum Period 2.62 2.62 2.62 ns RCKP Note: *Timing data for two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use Microsemi's SmartTime tool. 2-116 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-105 • Four RAM Blocks* Are Cascaded (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode t Write Data Setup vs. WCLK 3.31 3.12 3.67 ns WDASU t Write Data Hold vs. WCLK 0.00 0.00 0.00 ns WDAHD t Write Address Setup vs. WCLK 3.31 3.12 3.67 ns WADSU t Write Address Hold vs. WCLK 0.00 0.00 0.00 ns WADHD t Write Enable Setup vs. WCLK 3.31 3.12 3.67 ns WENSU t Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns WENHD t WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns WCKH t WCLK Minimum Low Pulse Width 2.51 2.51 2.51 ns WCLKL t WCLK Minimum Period 3.26 3.26 3.26 ns WCKP Read Mode t Read Address Setup vs. RCLK 4.31 4.06 4.77 ns RADSU t Read Address Hold vs. RCLK 0.00 0.00 0.00 ns RADHD t Read Enable Setup vs. RCLK 4.31 4.06 4.77 ns RENSU t Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns RENHD t RCLK-To-OUT (Pipelined) 3.30 3.11 3.66 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.96 3.73 4.38 ns RCK2RD2 t RCLK Minimum High Pulse Width 2.96 0.73 0.73 ns RCLKH t RCLK Minimum Low Pulse Width 3.69 2.96 2.96 ns RCLKL t RCLK Minimum Period 3.69 3.69 ns RCKP Note: *Timing data for four cascaded RAM blocks uses a depth of 16,384. For all other combinations, use Microsemi's SmartTime tool. Revision 14 2-117 Detailed Specifications Table 2-106 • Eight RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode t Write Data Setup vs. WCLK 8.07 7.61 8.94 ns WDASU t Write Data Hold vs. WCLK 0.00 0.00 0.00 ns WDAHD t Write Address Setup vs. WCLK 8.07 7.61 8.94 ns WADSU t Write Address Hold vs. WCLK 0.00 0.00 0.00 ns WADHD t Write Enable Setup vs. WCLK 8.07 7.61 8.94 ns WENSU t Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns WENHD t WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns WCKH t WCLK Minimum Low Pulse Width 5.13 5.13 5.13 ns WCLKL t WCLK Minimum Period 5.88 5.88 5.88 ns WCKP Read Mode t Read Address Setup vs. RCLK 9.44 8.89 10.45 ns RADSU t Read Address Hold vs. RCLK 0.00 0.00 0.00 ns RADHD t Read Enable Setup vs. RCLK 9.44 8.89 10.45 ns RENSU t Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns RENHD t RCLK-To-OUT (Pipelined) 4.73 4.46 5.24 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 6.89 6.49 7.63 ns RCK2RD2 t RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns RCLKH t RCLK Minimum Low Pulse Width 5.77 5.77 5.77 ns RCLKL t RCLK Minimum Period 6.50 6.50 6.50 ns RCKP Note: *Timing data for eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use Microsemi's SmartTime tool. 2-118 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-107 • Sixteen RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode t Write Data Setup vs. WCLK 23.11 21.78 25.60 ns WDASU t Write Data Hold vs. WCLK 0.00 0.00 0.00 ns WDAHD t Write Address Setup vs. WCLK 23.11 21.78 25.60 ns WADSU t Write Address Hold vs. WCLK 0.00 0.00 0.00 ns WADHD t Write Enable Setup vs. WCLK 23.11 21.78 25.60 ns WENSU t Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns WENHD t WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns WCKH t WCLK Minimum Low Pulse Width 13.40 13.40 13.40 ns WCLKL t WCLK Minimum Period 14.15 14.15 14.15 ns WCKP Read Mode t Read Address Setup vs. RCLK 25.32 23.87 28.06 ns RADSU t Read Address Hold vs. RCLK 0.00 0.00 0.00 ns RADHD t Read Enable Setup vs. RCLK 25.32 23.87 28.06 ns RENSU t Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns RENHD t RCLK-To-OUT (Pipelined) 16.87 15.90 18.69 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 17.93 16.90 19.86 ns RCK2RD2 t RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns RCLKH t RCLK Minimum Low Pulse Width 14.41 14.41 14.41 ns RCLKL t RCLK Minimum Period 15.14 15.14 15.14 ns RCKP Note: Timing data for sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use Microsemi's SmartTime tool. Revision 14 2-119 Detailed Specifications FIFO Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one write port. This embedded FIFO controller uses no internal FPGA logic and features: • Glitch-free FIFO Flags • Gray-code address counters/pointers to prevent metastability problems • Overflow and underflow control Both ports are configurable in various size from 4kx1 to 128x36, similar to the RAM block size. Each port is fully synchronous. Read and write operations can be completely independent. Data on the appropriate WD pins are written to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output on the appropriate RD pins on every active RCLK edge as long as REN is asserted. The FIFO block offers programmable Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags as well as EMPTY and FULL flags (Figure 2-56): • The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full. • The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty condition. Note: Microsemi recommends that the WCLK and the RCLK are in phase with each other. For more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller. Gray code counters are used to prevent metastability problems associated with flag logic. The depth of the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are synchronous with respect to the RCLK. The FIFO block may be reset to the empty state The FIFO control unit was not implemented with SEU-hardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. 2-120 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs RD [n-1:0] RD WD WD [n-1:0] RCLK RCLK WCLK WCLK RAM RA [J:0] WA [J:0] REN WEN DEPTH[3:0] CNT 16 FREN = E FULL AFULL AFVAL > AEMPTY AEVAL > = CNT 16 FWEN E = EMPTY CLR Figure 2-56 • RTAX-S/SL RAM with Embedded FIFO Controller Revision 14 2-121 SUB 16 PIPE RW[2:0] WIDTH[2:0] WW[2:0] Detailed Specifications FIFO Flag Logic The FIFO is user configurable into various depths and widths. Figure 2-57 shows the FIFO address counter details. • Bits 11 to 5 are active for all modes. • As the data word size is reduced, more least-significant bits are added to the address. • As the number of cascaded blocks increases, the number of significant bits in the address increases. For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each RAM block, whereas bits 13 and 12 will be used to specify the RAM block. The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. Note that the effective number of threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-108). FIFO Address Counters Mode when Counter Alignment of FIFO Address Active Bits Threshold bits Cas 16 blks CNTR [15] R/W EN[3] AEVAL/AFVAL[7] activate Cas 8 blks CNTR [14] R/W EN[2] AEVAL/AFVAL[6] activate [15:W] Cas 4 blks CNTR [13] R/W EN[1] AEVAL/AFVAL[5] activate [14:W] [13:W] Cas 2 blks [12:W] CNTR [12] R/W EN[0] AEVAL/AFVAL[4] activate 4kx1 128x36 256x18 512x9 1kx4 2kx2 R/W ADD[11:8] AEVAL/AFVAL[3:0] by 36 CNTR [11:5] R/W ADD[7:5] not compared always active [11:5] [11:4] [11:3] by 18 CNTR [4] R/W ADD[4] not compared activate [11:2] by 9 CNTR [3] [11:1] R/W ADD[3] not compared [11:0] activate by 4 CNTR [2] R/W ADD[2] not compared activate by 2 CNTR [1] R/W ADD[1] not compared activate by 1 R/W ADD[0] CNTR [0] not compared activate Variable Active Address Space CNTR [15:0] >> REN [4:0], RAD [11:0] >> WEN [4:0], WAD [11:0] Note: Inactive counter bits are set to zero. Figure 2-57 • FIFO Address Counters 2-122 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-108 • FIFO Flag Logic Inactive AEVAL/AFVAL Inactive DIFF bits DIFF comparison to Mode bits (set to 0) AFVAL/AEVAL Non-cascade [7:4] [15:12] DIFF[11:8] withAE/FVAL[3:0] Cascade 2 blocks [7:5] [15:13] DIFF[12:8] withAE/FVAL[4:0] Cascade 4 blocks [7:6] [15:14] DIFF[13:8] withAE/FVAL[5:0] Cascade 8 blocks [7] [15] DIFF[14:8] withAE/FVAL[6:0] Cascade 16 blocks None None DIFF[15:8] withAE/FVAL[7:0] Figure 2-58 illustrates flag generation. The Verilog statements for flag assignment are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-109). The active- high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-126. For more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller. AEMPTY AEVAL [7:0], GND [7:0] (MSB....LSB) X Y 16 WCNTR WCLK [15:0] X>=Y (16-bit) DIFF [15:0] 16 RCNTR AFULL RCLK [15:0] X AFVAL [7:0], GND [7:0] (MSB....LSB) Y Figure 2-58 • ALMOST-EMPTY and ALMOST-FULL Logic Revision 14 2-123 Detailed Specifications Table 2-109 • Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 1 1x1 4 2 1x2 4 2 2x1 5 4 1x4 4 4 2x2 5 4 4x1 6 8 1x8 4 8 2x4 5 8 4x2 6 8 8x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 Glitch Elimination An analog filter is added to each FIFO controller to guarantee, glitch-free FIFO-flag logic. Overflow and Underflow Control The counter MSB keeps track of the difference between the read address (RA) and the write address (WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the write address is double-sampled by the read clock prior to comparison with the read address (part A in Figure 2-59). To prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part B in Figure 2-59). AB WA RA = = EMPTY FULL RCLK WCLK RA WA Figure 2-59 • Overflow and Underflow Control FIFO Configurations Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO, the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable word widths, as shown in Table 2-110. The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2, 4, 8, and 16 to be specified. Table 2-100 on page 2-112 describes the FIFO depth options for various data width and memory blocks. Interface Figure 2-60 shows a logic block diagram of the RTAX-S/SL FIFO module. 2-124 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Cascading FIFO Blocks FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be taken into account when building the FIFO blocks manually. However, when using SmartGen, the user only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically configures these blocks to optimize performance. Clock As with RAM configuration, the RCLK and WCLK pins have independent polarity selection Table 2-110 • FIFO Width Configurations WIDTH(2:0) WxD 000 1x4k 001 2x2k 010 4x1k 011 9x512 100 18x256 101 36x128 11x Reserved DEPTH [3:0] RD [35:0] WIDTH [2:0] PIPE FULL FREN EMPTY RCLK AFULL AEVAL [7:0] AEMPTY AFVAL [7:0] WD [35:0] FWEN WCLK CLR Figure 2-60 • FIFO Block Diagram Revision 14 2-125 Detailed Specifications Timing Characteristics WD RD AEMPTY EMPTY AFULL FULL FWEN FREN WCLK RCLK Clr Figure 2-61 • FIFO Model t t t WCKH WCKL WCKP WCLK t t WSU WHD WD<35:0>, FWEN t CLR2HF CLR t t WCK2xF CLR2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-62 • FIFO Write Timing 2-126 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs t t t RCKP RCKH RCKL RCLK t t RSU RHD FREN t t RCK2RD1 RCK2RD2 RD <35:0> t CLRHF CLR t t CLR2xF CK2xF EMPTY, AEMPTY, AFULL, FUL L Figure 2-63 • FIFO Read Timing Revision 14 2-127 Detailed Specifications Table 2-111 • One FIFO Block (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing t Write Setup 15.92 15.26 17.64 ns WSU t Write Hold 0.31 0.29 0.34 ns WHD t WCLK High 0.75 0.75 0.75 ns WCKH t WCLK Low 0.88 0.88 0.88 ns WCKL t Minimum WCLK Period 1.63 1.63 1.63 ns WCKP t Read Setup 16.25 15.32 18.01 ns RSU t Read Hold 0.00 0.00 0.00 ns RHD t RCLK High 0.77 0.77 0.77 ns RCKH t RCLK Low 0.93 0.93 0.93 ns RCKL t Minimum RCLK period 1.70 1.70 1.70 ns RCKP t Clear-to-flag (EMPTY/FULL) 2.68 2.52 2.97 ns CLR2FF t Clear-to-flag (AEMPTY/AFULL) 6.13 5.78 6.79 ns CLR2AF t Clock-to-flag (EMPTY/FULL) 2.97 2.80 3.29 ns CK2FF t Clock-to-flag (AEMPTY/AFULL) 7.05 6.64 7.81 ns CK2AF t RCLK-To-OUT (Pipelined) 1.85 1.74 2.05 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.02 3.50 4.12 ns RCK2RD2 Note: Timing data for this single cascaded FIFO block uses a depth of 4,096. For all other combinations, please use Microsemi's Timing software. 2-128 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-112 • Two FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing t Write Setup 19.21 18.10 21.28 ns WSU t Write Hold 0.00 0.00 0.00 ns WHD t WCLK High 0.75 0.75 0.75 ns WCKH t WCLK Low 1.76 1.76 1.76 ns WCKL t Minimum WCLK Period 2.51 2.51 2.51 ns WCKP t Read Setup 20.02 18.86 22.18 ns RSU t Read Hold 0.00 0.00 0.00 ns RHD t RCLK High 0.73 0.73 0.73 ns RCKH t RCLK Low 1.89 1.89 1.89 ns RCKL t Minimum RCLK period 2.62 2.62 2.62 ns RCKP t Clear-to-flag (EMPTY/FULL) 2.68 2.52 2.97 ns CLR2FF t Clear-to-flag (AEMPTY/AFULL) .6.13 5.78 6.79 ns CLR2AF t Clock-to-flag (EMPTY/FULL) 2.97 2.80 3.29 ns CK2FF t Clock-to-flag (AEMPTY/AFULL) 7.05 6.64 7.81 ns CK2AF t RCLK-To-OUT (Pipelined) 2.00 1.89 2.22 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.16 2.98 3.50 ns RCK2RD2 Note: Timing data for two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, please use Microsemi's Timing software. Revision 14 2-129 Detailed Specifications Table 2-113 • Four FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing t Write Setup 20.40 19.23 22.60 ns WSU t Write Hold 0.00 0.00 0.00 ns WHD t WCLK High 0.75 0.75 0.75 ns WCKH t WCLK Low 2.51 2.51 2.51 ns WCKL t Minimum WCLK Period 3.26 3.26 3.26 ns WCKP t Read Setup 21.33 20.10 23.63 ns RSU t Read Hold 0.00 0.00 0.00 ns RHD t RCLK High 0.73 0.73 0.73 ns RCKH t RCLK Low 2.96 2.96 2.96 ns RCKL t Minimum RCLK period 3.69 3.69 3.69 ns RCKP t Clear-to-flag (EMPTY/FULL) 2.68 2.52 2.97 ns CLR2FF t Clear-to-flag (AEMPTY/AFULL) 6.13 5.78 6.79 ns CLR2AF t Clock-to-flag (EMPTY/FULL) 2.97 2.80 3.29 ns CK2FF t Clock-to-flag (AEMPTY/AFULL) 7.05 6.64 7.81 ns CK2AF t RCLK-To-OUT (Pipelined) 3.30 3.11 3.66 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 3.96 3.73 4.38 ns RCK2RD2 Note: Timing data for four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, please use Microsemi's Timing software. 2-130 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Table 2-114 • Eight FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing t Write Setup 21.59 20.35 23.92 ns WSU t Write Hold 0.00 0.00 0.00 ns WHD t WCLK High 0.75 0.75 0.75 ns WCKH t WCLK Low 5.13 5.13 5.13 ns WCKL t Minimum WCLK Period 5.88 5.88 5.88 ns WCKP t Read Setup 22.66 21.35 25.10 ns RSU t Read Hold 0.00 0.00 0.00 ns RHD t RCLK High 0.73 0.73 0.73 ns RCKH t RCLK Low 5.77 5.77 5.77 ns RCKL t Minimum RCLK period 6.50 6.50 6.50 ns RCKP t Clear-to-flag (EMPTY/FULL) 2.68 2.52 2.97 ns CLR2FF t Clear-to-flag (AEMPTY/AFULL) 6.13 5.78 6.79 ns CLR2AF t Clock-to-flag (EMPTY/FULL) 2.97 2.80 3.29 ns CK2FF t Clock-to-flag (AEMPTY/AFULL) 7.05 6.64 7.81 ns CK2AF t RCLK-To-OUT (Pipelined) 4.73 4.46 5.24 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 6.89 6.49 7.63 ns RCK2RD2 Note: Timing data for eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, please use Microsemi's Timing software. Revision 14 2-131 Detailed Specifications Table 2-115 • Sixteen FIFO Blocks are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J –1 Speed Std. Speed RTAX250/1000/ RTAX4000S/SL 2000S/SL All Parameter Description Min. Max. Min. Max. Min. Max. Units FIFO Module Timing t Write Setup 22.80 21.49 25.27 ns WSU t Write Hold 0.00 0.00 0.00 ns WHD t WCLK High 0.75 0.75 0.75 ns WCKH t WCLK Low 13.40 13.40 13.40 ns WCKL t Minimum WCLK Period 14.15 14.15 14.15 ns WCKP t Read Setup 23.97 22.59 26.55 ns RSU t Read Hold 0.00 0.00 0.00 ns RHD t RCLK High 0.73 0.73 0.73 ns RCKH t RCLK Low 14.41 14.41 14.41 ns RCKL t Minimum RCLK period 15.14 15.14 15.14 ns RCKP t Clear-to-flag (EMPTY/FULL) 2.68 2.52 2.97 ns CLR2FF t Clear-to-flag (AEMPTY/AFULL) 6.13 5.78 6.79 ns CLR2AF t Clock-to-flag (EMPTY/FULL) 2.97 2.80 3.29 ns CK2FF t Clock-to-flag (AEMPTY/AFULL) 7.05 6.64 7.81 ns CK2AF t RCLK-To-OUT (Pipelined) 16.87 15.90 18.69 ns RCK2RD1 t RCLK-To-OUT (Non-Pipelined) 17.93 16.90 19.86 ns RCK2RD2 Note: Timing data for sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, please use Microsemi's Timing software. Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: • Using the SmartGen core generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (please refer to the SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide for more information). • The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. 2-132 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Other Architectural Features Charge Pump Bypass To reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in no DC current draw. The RTAX-S/SL family devices have a dedicated "V " pin that can be used to access PUMP an external charge pump device. In normal chip operation, when using the internal charge pump, V PUMP should be tied to GND. When the voltage level on V is set to 3.3 V, the internal charge pump is PUMP turned off, and the V voltage will be used as the charge pump voltage. Adequate voltage regulation PUMP (i.e., high drive, low output impedance, and good decoupling) should be used at V . PUMP JTAG RTAX-S/SL offers a JTAG interface that is compliant with the IEEE 1149.1 standard except for the device ID length which is 33 bits. The user can employ the JTAG interface for probing a design and executing any JTAG public instructions as defined in the Table 2-116. The JTAG pins and probes are configured as a LVTTL standard port. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note, which also applies to the RTAX-S/SL family of devices. The JTAG pins should not be left floating on flight systems. Table 2-116 • JTAG Instruction Code Instruction (IR4:IR0) Binary Code EXTEST 00000 PRELOAD / SAMPLE 00001 INTEST 00010 USERCODE 00011 IDCODE 00100 HIGHZ 01110 CLAMP 01111 DIAGNOSTIC 10000 Reserved All others BYPASS 11111 Interface The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up resistors. TRST TRST (Test-Logic Reset) is an active-low asynchronous reset signal to the TAP controller. The TRST input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the TRST state, it is recommended to connect TRST directly to ground for flight. There is an optional internal pull-up resistor available for the TRST input that can be set by the user at programming. Care should be exercised when using this option in combination with an external tie-off to ground. An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST," but it only occurs at power-up or during recovery from a V and/or V voltage drop. CCA CCDA Revision 14 2-133 Detailed Specifications TDO TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or "Shift_IR" state. The least significant bit of the selected register (i.e., IR or DR) is clocked out to TDO first by the falling edge of TCK. TAP Controller The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that controls the Instruction Register (IR) and the Data Registers (such as Boundary-Scan Register, IDCODE, USRCODE, BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at the rising edges of TCK. Instruction Register (IR) The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR." When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111." If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully" flag. During flight, the following configurations for all JTAG and Probe pins are recommended (Table 2-117 on page 2-134). Table 2-117 • JTAG and Probe Pin Recommendations for Flight JTAG and Probe Pins Configurations TCK • Can be hardwired to VCCDA or ground • Can be driven to VCCDA or ground • Must not be left unterminated TDO Must be left unconnected TDI • Can be hardwired or driven to VCCDA • Can be left unconnected (equipped with internal 10 k pull-up resistor) TMS • Can be hardwired or driven to VCCDA • Can be left unconnected (equipped with internal 10 k pull-up resistor) TRST Must be hardwired to ground (equipped with optional internal 10 k pull-up resistor) PRA/B/C/D May be left unconnected, or may be connected via pull-up or pull-down resistor to VCCI or GND. PRA/B/C/D are in tristate mode during normal operation. In test mode, these pins put out the logic value of the internal node they are connected to. 2-134 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Data Registers (DRs) Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data registers. Descriptions of the main registers are as follow: 1. IDCODE: The IDCODE is a hard coded JTAG Silicon Signature. It is a hardwired device ID code, which contains the Microsemi identity, part number, and version number in a specific JTAG format. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note for more information. The IDCODE is 33 bits in length in the following devices: RTAX250S/SL, RTAX1000S/SL, and RTAX2000S/SL. The IDCODE is 32 bits in length in the following devices: RTAX2000D, RTAX4000S/SL, and RTAX4000D. 2. USERCODE: The USERCODE is a programmable JTAG Silicon Signature. It is a supplementary identity code for the user to program information to distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note for more information. The USERCODE is 33 bits in length in the following devices: RTAX250S/SL, RTAX1000S/SL, and RTAX2000S/SL. The USERCODE is 32 bits in length in the following devices: RTAX2000D, RTAX4000S/SL, and RTAX4000D. 3. Boundary-Scan Register (BSR): Each I/O contains three BSR Cells. Each cell has a shift register bit, a latch, and two MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I) registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan cells are then chained serially to form the BSR. The length of the BSR is the number of I/Os in the die (not the package) multiplied by three. This excludes special function pins (TRST, TCK, TMS, TDI, TDO, PRA, PRB, PRC, PRD, and VPUMP). 4. Bypass Register (BYR): This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to only one bit per device not being tested. It is also selected for all "reserved" or unused instructions. Probing Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB," "PRC," and "PRD." Special Fuses Security Microsemi antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device during power-up, thus making device cloning impossible. In addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an RTAX-S/SL device that access or bypass these security fuses will destroy access to the rest of the device (refer to the Design Security in Nonvolatile Flash and Antifuse FPGAs white paper). Look for this symbol to ensure your valuable IP is protected by the highest level of security in the industry. FuseLock Figure 2-64 • FuseLock Logo Revision 14 2-135 Detailed Specifications To ensure maximum security in RTAX-S/SL devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. For more information, refer to the Implementation of Security in Actel Antifuse FPGAs application note. Global Set Fuse The Global Set Fuse determines if all R-cells and I/O Registers (InReg, OutReg, and EnReg) are either cleared or preset by driving the GCLR and GPSET inputs of all R-cells and I/O Registers ("R-Cell" on page 2-88). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and GPSET= 0). A local CLR or PRESET will take precedence overt this setting. Both pins are pulled HIGH during normal device operation. For use details, see Libero IDE online help. Silicon Explorer II Probe Interface Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is operating in a prototype or a production system. The user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. Highlighted nets in Designer’s ChipPlanner can be accessed using Silicon Explorer II in order to observe their real time values. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route program cycles the integrity of the design is maintained throughout the debug process. Each member of the RTAX-S/SL family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four probe signals from the RTAX-S/SL device. Each core tile can has up to two probe signals. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on page 2-135 for more information). Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-15 on page 1-12). Once the design has been placed-and-routed, and the RTAX-S/SL device has been programmed, Silicon Explorer II can be connected and the Explorer software can be launched. Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. Programming Device programming is supported through the Silicon Sculptor 3, a single-site, robust and compact device programmer for the PC. Up to four Silicon Sculptor 3s can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor 3 is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Sculptor 3 programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor 3 to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor 3 also provides a self-test to test its own hardware extensively. Programming an RTAX-S/SL device using Silicon Sculptor 3 is similar to programming any other antifuse device. The procedure is as follows: 1. Load the AFM file. 2. Select the device to be programmed. 2-136 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs 3. Begin programming. When the design is ready to go to production, Microsemi offers device volume-programming services either through distribution partners or via our In-House Programming Center. For more details on programming the RTAX-S/SL devices, please refer to the Silicon Sculptor User’s Guide. Table 2-118 • FIFO Signal Description Signal Direction Description WCLK Input Write clock (active either edge). FWEN Input FIFO write enable. When this signal is asserted, the WD bus data is latched into the FIFO, and the internal write counters are incremented. WD[N-1:0] Input Write data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. FULL Output Active high signal indicating that the FIFO is FULL. When this signal is set, additional write requests are ignored. AFULL Output Active high signal indicating that the FIFO is AFULL. AFVAL Input 8-bit input defining the AFULL value of the FIFO. RCLK Input Read clock (active either edge). FREN Input FIFO read enable. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. EMPTY Output Empty flag indicating that the FIFO is EMPTY. When this signal is asserted, attempts to read the FIFO will be ignored. AEMPTY Output Active high signal indicating that the FIFO is AEMPTY. AEVAL Input 8-bit input defining the almost-empty value of the FIFO. PIPE Input Sets the pipe option on or off. CLR Input Active high clear input. DEPTH Input Determines the depth of the FIFO and the number of FIFOs to be cascaded. WIDTH Input Determines the width of the dataword / width of the FIFO, and the number of the FIFOs to be cascaded. Revision 14 2-137 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs 3 – Package Pin Assignments CQ208 1 156 Pin 1 2 155 3 154 4 153 Ceramic Tie Bar 208-Pin CQFP 49 108 50 107 51 106 52 105 Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 14 3-1 158 103 53 208 54 207 55 206 56 205 101 160 102 159 157 104 Package Pin Assignments CQ208 CQ208 CQ208 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number Bank 0 IO43PB2F2 134 IO76PB5F5/CLKGP 77 IO44NB2F2 131 IO77NB5F5/CLKHN 70 IO02NB0F0 197 IO03NB0F0 198 IO44PB2F2 133 IO77PB5F5/CLKHP 71 IO03PB0F0 199 Bank 3 IO78NB5F5 66 IO12NB0F0/HCLKAN 191 IO45NB3F3 127 IO78PB5F5 67 IO12PB0F0/HCLKAP 192 IO45PB3F3 129 IO86NB5F5 62 IO13NB0F0/HCLKBN 185 IO46NB3F3 126 IO87NB5F5 60 IO13PB0F0/HCLKBP 186 IO46PB3F3 128 IO87PB5F5 61 Bank 1 IO48NB3F3 122 IO88NB5F5 56 IO14NB1F1/HCLKCN 180 IO48PB3F3 123 IO88PB5F5 57 IO14PB1F1/HCLKCP 181 IO50NB3F3 120 IO89NB5F5 54 IO15NB1F1/HCLKDN 174 IO50PB3F3 121 IO89PB5F5 55 IO15PB1F1/HCLKDP 175 IO55NB3F3 116 Bank 6 IO16NB1F1 170 IO55PB3F3 117 IO91NB6F6 47 IO16PB1F1 171 IO57NB3F3 114 IO91PB6F6 49 IO24NB1F1 165 IO57PB3F3 115 IO92NB6F6 48 IO24PB1F1 166 IO59NB3F3 110 IO92PB6F6 50 IO26NB1F1 161 IO59PB3F3 111 IO93NB6F6 42 IO26PB1F1 162 IO60NB3F3 108 IO93PB6F6 43 IO27NB1F1 159 IO60PB3F3 109 IO94PB6F6 44 IO27PB1F1 160 IO61NB3F3 106 IO96NB6F6 40 Bank 2 IO61PB3F3 107 IO96PB6F6 41 IO29NB2F2 151 Bank 4 IO101NB6F6 35 IO29PB2F2 153 IO62NB4F4 100 IO101PB6F6 36 IO30NB2F2 152 IO62PB4F4 103 IO102PB6F6 37 IO30PB2F2 154 IO63NB4F4 101 IO103NB6F6 33 IO31PB2F2 148 IO63PB4F4 102 IO103PB6F6 34 IO32NB2F2 146 IO64NB4F4 96 IO105NB6F6 28 IO32PB2F2 147 IO64PB4F4 97 IO105PB6F6 30 IO34NB2F2 144 IO72NB4F4 91 IO106NB6F6 27 IO34PB2F2 145 IO72PB4F4 92 IO106PB6F6 29 IO39NB2F2 139 IO74NB4F4/CLKEN 87 Bank 7 IO39PB2F2 140 IO74PB4F4/CLKEP 88 IO107NB7F7 23 IO40PB2F2 141 IO75NB4F4/CLKFN 81 IO107PB7F7 25 IO41NB2F2 137 IO75PB4F4/CLKFP 82 IO108NB7F7 22 IO41PB2F2 138 Bank 5 IO108PB7F7 24 IO43NB2F2 132 IO76NB5F5/CLKGN 76 IO110NB7F7 18 3-2 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ208 CQ208 CQ208 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number IO110PB7F7 19 GND 194 VCCA 156 IO112NB7F7 16 GND 196 VCCA 168 IO112PB7F7 17 GND 201 VCCA 195 IO117NB7F7 12 GND 208 VCCDA 1 IO117PB7F7 13 NC 72 VCCDA 26 IO119NB7F7 10 NC 73 VCCDA 53 IO119PB7F7 11 NC 74 VCCDA 63 IO121PB7F7 7 NC 75 VCCDA 78 IO122NB7F7 5 NC 83 VCCDA 95 IO122PB7F7 6 NC 84 VCCDA 105 IO123NB7F7 3 NC 85 VCCDA 130 IO123PB7F7 4 NC 86 VCCDA 157 Dedicated I/O NC 176 VCCDA 167 GND 9 NC 177 VCCDA 182 GND 15 NC 178 VCCDA 202 GND 21 NC 179 VCCIB0 193 GND 32 NC 187 VCCIB0 200 GND 39 NC 188 VCCIB1 163 GND 46 NC 189 VCCIB1 172 GND 51 NC 190 VCCIB2 135 GND 59 PRA 184 VCCIB2 149 GND 65 PRB 183 VCCIB3 112 GND 69 PRC 80 VCCIB3 124 GND 90 PRD 79 VCCIB4 89 GND 94 TCK 205 VCCIB4 98 GND 99 TDI 204 VCCIB5 58 GND 104 TDO 203 VCCIB5 68 GND 113 TMS 206 VCCIB6 31 GND 119 TRST 207 VCCIB6 45 GND 125 VCCA 2 VCCIB7 8 GND 136 VCCA 14 VCCIB7 20 GND 143 VCCA 38 VPUMP 158 GND 150 VCCA 52 GND 155 VCCA 64 GND 164 VCCA 93 GND 169 VCCA 118 GND 173 VCCA 142 Revision 14 3-3 Package Pin Assignments CQ256 1 192 Pin 1 2 191 3 190 4 189 Ceramic Tie Bar 256-Pin CQFP 61 132 62 131 63 130 64 129 Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 3-4 Revision 14 194 127 65 256 66 255 67 254 68 253 125 196 126 195 193 128 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ256 CQ256 CQ256 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number Bank 0 Bank 2 IO167PB3F15 134 IO107NB2F10 184 Bank 4 IO01NB0F0 248 IO01PB0F0 249 IO107PB2F10 185 IO181NB4F17 124 IO04NB0F0 246 IO110NB2F10 180 IO181PB4F17 125 IO04PB0F0 247 IO110PB2F10 181 IO182NB4F17 122 IO05NB0F0 242 IO111NB2F10 178 IO182PB4F17 123 IO05PB0F0 243 IO111PB2F10 179 IO183NB4F17 118 IO08NB0F0 240 IO112NB2F10 174 IO183PB4F17 119 IO08PB0F0 241 IO112PB2F10 175 IO184NB4F17 116 Bank 0 IO113NB2F10 172 IO184PB4F17 117 IO37NB0F3 234 IO113PB2F10 173 IO190NB4F17 112 IO37PB0F3 235 IO114NB2F10 168 IO190PB4F17 113 IO41NB0F3/HCLKAN 232 IO114PB2F10 169 IO192NB4F17 110 IO41PB0F3/HCLKAP 233 IO115NB2F10 166 IO192PB4F17 111 IO42NB0F3/HCLKBN 228 IO115PB2F10 167 Bank 4 IO42PB0F3/HCLKBP 229 IO117NB2F10 162 IO212NB4F19/CLKEN 104 Bank 1 - IO117PB2F10 163 IO212PB4F19/CLKEP 105 IO43NB1F4/HCLKCN 220 Bank 3 IO213NB4F19/CLKFN 100 IO43PB1F4/HCLKCP 221 IO139NB3F13 158 IO213PB4F19/CLKFP 101 IO44NB1F4/HCLKDN 216 IO139PB3F13 159 Bank 5 IO44PB1F4/HCLKDP 217 IO141NB3F13 154 IO214NB5F20/CLKGN 92 Bank 1 IO141PB3F13 155 IO214PB5F20/CLKGP 93 IO65NB1F6 210 IO142NB3F13 152 IO215NB5F20/CLKHN 88 IO65PB1F6 211 IO142PB3F13 153 IO215PB5F20/CLKHP 89 IO69NB1F6 208 IO145NB3F13 148 Bank 5 IO69PB1F6 209 IO145PB3F13 149 IO236NB5F22 82 IO70NB1F6 199 IO146NB3F13 146 IO236PB5F22 83 IO71NB1F6 204 IO146PB3F13 147 IO238NB5F22 80 IO71PB1F6 205 IO147NB3F13 140 IO238PB5F22 81 IO73NB1F6 202 IO147PB3F13 141 IO240NB5F22 76 IO73PB1F6 203 IO148NB3F13 142 IO240PB5F22 77 IO74NB1F6 197 IO148PB3F13 143 IO242NB5F22 74 IO74PB1F6 198 IO149NB3F13 136 IO242PB5F22 75 Bank 2 IO149PB3F13 137 IO243NB5F22 70 IO87NB2F8 187 Bank 3 IO243PB5F22 71 IO87PB2F8 188 IO165NB3F15 135 IO244NB5F22 68 IO89PB2F8 186 IO167NB3F15 133 IO244PB5F22 69 Revision 14 3-5 Package Pin Assignments CQ256 CQ256 CQ256 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number Bank 6 IO320PB7F29 9 GND 171 IO257PB6F24 60 Bank 7 GND 177 IO258NB6F24 58 IO341NB7F31 6 GND 183 IO258PB6F24 59 IO341PB7F31 7 GND 190 Bank 6 Dedicated I/O GND 192 IO279NB6F26 56 GND 1 GND 193 IO279PB6F26 57 GND 5 GND 201 IO280NB6F26 52 GND 11 GND 207 IO280PB6F26 53 GND 17 GND 213 IO281NB6F26 50 GND 23 GND 219 IO281PB6F26 51 GND 29 GND 225 IO282NB6F26 46 GND 33 GND 231 IO282PB6F26 47 GND 37 GND 239 IO284NB6F26 44 GND 43 GND 245 IO284PB6F26 45 GND 49 GND 256 IO285NB6F26 40 GND 55 PRA 227 IO285PB6F26 41 GND 62 PRB 226 IO286NB6F26 38 GND 64 PRC 99 IO286PB6F26 39 GND 65 PRD 98 IO287NB6F26 34 GND 73 TCK 253 IO287PB6F26 35 GND 79 TDI 252 Bank 7 9 GND 85 TDO 250 IO310NB7F29 30 GND 91 TMS 254 IO310PB7F29 31 GND 97 TRST 255 IO311NB7F29 26 GND 103 VCCA 3 IO311PB7F29 27 GND 109 VCCA 4 IO312NB7F29 24 GND 115 VCCA 22 IO312PB7F29 25 GND 121 VCCA 42 IO315NB7F29 20 GND 128 VCCA 61 IO315PB7F29 21 GND 129 VCCA 63 IO316NB7F29 18 GND 132 VCCA 84 IO316PB7F29 19 GND 139 VCCA 108 IO317NB7F29 14 GND 145 VCCA 127 IO317PB7F29 15 GND 151 VCCA 131 IO318NB7F29 12 GND 157 VCCA 150 IO318PB7F29 13 GND 161 VCCA 170 IO320NB7F29 8 GND 165 VCCA 189 3-6 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ256 CQ256 Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number VCCA 191 VCCIB3 156 VCCA 212 VCCIB4 102 VCCA 238 VCCIB4 114 VCCDA 2 VCCIB4 120 VCCDA 32 VCCIB5 72 VCCDA 66 VCCIB5 78 VCCDA 67 VCCIB5 90 VCCDA 86 VCCIB6 36 VCCDA 87 VCCIB6 48 VCCDA 94 VCCIB6 54 VCCDA 95 VCCIB7 10 VCCDA 96 VCCIB7 16 VCCDA 106 VCCIB7 28 VCCDA 107 VPUMP 195 VCCDA 126 VCCDA 130 VCCDA 160 VCCDA 194 VCCDA 196 VCCDA 214 VCCDA 215 VCCDA 222 VCCDA 223 VCCDA 224 VCCDA 236 VCCDA 237 VCCDA 251 VCCIB0 230 VCCIB0 244 VCCIB1 200 VCCIB1 206 VCCIB1 218 VCCIB2 164 VCCIB2 176 VCCIB2 182 VCCIB3 138 VCCIB3 144 Revision 14 3-7 Package Pin Assignments CQ352 1 264 Pin 1 2 263 3 262 4 261 Ceramic Tie Bar 223 41 42 222 221 43 220 44 45 352-Pin CQFP 219 218 46 217 47 216 48 49 215 85 180 86 179 87 178 88 177 3-8 Revision 14 266 175 89 352 90 351 91 350 92 349 127 339 128 338 129 337 130 336 131 335 132 334 133 333 134 332 135 331 173 268 174 267 176 265 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Note: The 352-pin CQFP pin assignments for RTAX250S/SL, RTAX1000S/SL and RTAX2000S/SL are compatible except for the following pins. RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX250S/SL N/A 117, 148, 294, 327, 91, 117, 130, 131, 148, Not pin compatible 328 174, 268, 294, 307, 308, 327, 328 RTAX1000S/SL 117, 148, 294, 327, N/A 91,130, 131, 174, 268, Not pin compatible 328 307, 308 RTAX2000S/SL 91, 117, 130, 131, 148, 91,130, 131, 174, 268, NA Not pin compatible 174, 268, 294, 307, 307, 308 308, 327, 328 Where exceptions occur, the smaller density devices have those pins designated as No Connects (NC). Customers are therefore recommended to layout their board targeting the larger density device, in order to preserve interchangeability between the two devices. Note: RTAX4000S is not pin compatible with any of the smaller density devices. For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 14 3-9 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number Bank 0 IO24NB1F1 275 Bank 3 IO00NB0F0 341 IO24PB1F1 276 IO45NB3F3 217 IO00PB0F0 342 IO25NB1F1 271 IO45PB3F3 218 IO01NB0F0 343 IO25PB1F1 272 IO46NB3F3 219 IO02NB0F0 337 IO27NB1F1 269 IO46PB3F3 220 IO02PB0F0 338 IO27PB1F1 270 IO47NB3F3 213 IO04NB0F0 335 Bank 2 IO47PB3F3 214 IO04PB0F0 336 IO29NB2F2 261 IO48NB3F3 211 IO06NB0F0 331 IO29PB2F2 262 IO48PB3F3 212 IO06PB0F0 332 IO30NB2F2 259 IO49NB3F3 207 IO08NB0F0 325 IO30PB2F2 260 IO49PB3F3 208 IO08PB0F0 326 IO31NB2F2 255 IO51NB3F3 205 IO10NB0F0 323 IO31PB2F2 256 IO51PB3F3 206 IO10PB0F0 324 IO33NB2F2 249 IO52NB3F3 201 IO12NB0F0/HCLKAN 319 IO33PB2F2 250 IO52PB3F3 202 IO12PB0F0/HCLKAP 320 IO34NB2F2 253 IO53NB3F3 199 IO13NB0F0/HCLKBN 313 IO34PB2F2 254 IO53PB3F3 200 IO13PB0F0/HCLKBP 314 IO35NB2F2 247 IO54NB3F3 195 Bank 1 IO35PB2F2 248 IO54PB3F3 196 IO14NB1F1/HCLKCN 305 IO36NB2F2 243 IO55NB3F3 193 IO14PB1F1/HCLKCP 306 IO36PB2F2 244 IO55PB3F3 194 IO15NB1F1/HCLKDN 299 IO37NB2F2 241 IO56NB3F3 187 IO15PB1F1/HCLKDP 300 IO37PB2F2 242 IO56PB3F3 188 IO16NB1F1 289 IO38NB2F2 237 IO57NB3F3 189 IO16PB1F1 290 IO38PB2F2 238 IO57PB3F3 190 IO17NB1F1 295 IO39NB2F2 235 IO59NB3F3 183 IO17PB1F1 296 IO39PB2F2 236 IO59PB3F3 184 IO18NB1F1 287 IO41NB2F2 231 IO60NB3F3 181 IO18PB1F1 288 IO41PB2F2 232 IO60PB3F3 182 IO20NB1F1 283 IO42NB2F2 229 IO61NB3F3 179 IO20PB1F1 284 IO42PB2F2 230 IO61PB3F3 180 IO22NB1F1 277 IO43NB2F2 225 Bank 4 IO22PB1F1 278 IO43PB2F2 226 IO62NB4F4 172 IO23NB1F1 281 IO44NB2F2 223 IO62PB4F4 173 IO23PB1F1 282 IO44PB2F2 224 IO64NB4F4 166 3-10 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number IO64PB4F4 167 IO85PB5F5 105 IO106NB6F6 46 IO65NB4F4 170 IO86NB5F5 98 IO106PB6F6 47 IO65PB4F4 171 IO86PB5F5 99 Bank 7 IO66NB4F4 164 IO87NB5F5 94 IO107NB7F7 40 IO66PB4F4 165 IO87PB5F5 95 IO107PB7F7 41 IO67NB4F4 160 IO89NB5F5 92 IO108NB7F7 42 IO67PB4F4 161 IO89PB5F5 93 IO108PB7F7 43 IO68NB4F4 158 Bank 6 IO109NB7F7 36 IO68PB4F4 159 IO90PB6F6 86 IO109PB7F7 37 IO70NB4F4 154 IO91NB6F6 84 IO110NB7F7 34 IO70PB4F4 155 IO91PB6F6 85 IO110PB7F7 35 IO72NB4F4 152 IO92NB6F6 78 IO111NB7F7 30 IO72PB4F4 153 IO92PB6F6 79 IO111PB7F7 31 IO73NB4F4 146 IO93NB6F6 82 IO113NB7F7 28 IO73PB4F4 147 IO93PB6F6 83 IO113PB7F7 29 IO74NB4F4/CLKEN 142 IO95NB6F6 76 IO114NB7F7 24 IO74PB4F4/CLKEP 143 IO95PB6F6 77 IO114PB7F7 25 IO75NB4F4/CLKFN 136 IO96NB6F6 72 IO115NB7F7 22 IO75PB4F4/CLKFP 137 IO96PB6F6 73 IO115PB7F7 23 Bank 5 IO97NB6F6 70 IO116NB7F7 18 IO76NB5F5/CLKGN 128 IO97PB6F6 71 IO116PB7F7 19 IO76PB5F5/CLKGP 129 IO98NB6F6 66 IO117NB7F7 16 IO77NB5F5/CLKHN 122 IO98PB6F6 67 IO117PB7F7 17 IO77PB5F5/CLKHP 123 IO99NB6F6 64 IO118NB7F7 12 IO78NB5F5 112 IO99PB6F6 65 IO118PB7F7 13 IO78PB5F5 113 IO100NB6F6 60 IO119NB7F7 10 IO79NB5F5 118 IO100PB6F6 61 IO119PB7F7 11 IO79PB5F5 119 IO101NB6F6 58 IO121NB7F7 6 IO80NB5F5 110 IO101PB6F6 59 IO121PB7F7 7 IO80PB5F5 111 IO103NB6F6 54 IO123NB7F7 4 IO82NB5F5 106 IO103PB6F6 55 IO123PB7F7 5 IO82PB5F5 107 IO104NB6F6 52 Dedicated I/O IO84NB5F5 100 IO104PB6F6 53 GND 1 IO84PB5F5 101 IO105NB6F6 48 GND 9 IO85NB5F5 104 IO105PB6F6 49 GND 15 Revision 14 3-11 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number GND 21 GND 240 NC 302 GND 27 GND 246 NC 303 GND 33 GND 252 NC 304 GND 39 GND 258 NC 307 GND 45 GND 264 NC 308 GND 51 GND 265 NC 315 GND 57 GND 274 NC 316 GND 63 GND 280 NC 317 GND 69 GND 286 NC 318 GND 75 GND 292 NC 327 GND 81 GND 298 NC 328 GND 88 GND 310 PRA 312 GND 89 GND 322 PRB 311 GND 97 GND 330 PRC 135 GND 103 GND 334 PRD 134 GND 109 GND 340 TCK 349 GND 115 GND 345 TDI 348 GND 121 GND 352 TDO 347 GND 133 NC 91 TMS 350 GND 145 NC 117 TRST 351 GND 151 NC 124 VCCA 3 GND 157 NC 125 VCCA 14 GND 163 NC 126 VCCA 32 GND 169 NC 127 VCCA 56 GND 176 NC 130 VCCA 74 GND 177 NC 131 VCCA 87 GND 186 NC 138 VCCA 102 GND 192 NC 139 VCCA 114 GND 198 NC 140 VCCA 150 GND 204 NC 141 VCCA 162 GND 210 NC 148 VCCA 175 GND 216 NC 174 VCCA 191 GND 222 NC 268 VCCA 209 GND 228 NC 294 VCCA 233 GND 234 NC 301 VCCA 251 3-12 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number VCCA 263 VCCIB5 108 VCCA 279 VCCIB5 120 VCCA 291 VCCIB6 50 VCCA 329 VCCIB6 62 VCCA 339 VCCIB6 68 VCCDA 2 VCCIB6 80 VCCDA 44 VCCIB7 8 VCCDA 90 VCCIB7 20 VCCDA 116 VCCIB7 26 VCCDA 132 VCCIB7 38 VCCDA 149 VPUMP 267 VCCDA 178 VCCDA 221 VCCDA 266 VCCDA 293 VCCDA 309 VCCDA 346 VCCIB0 321 VCCIB0 333 VCCIB0 344 VCCIB1 273 VCCIB1 285 VCCIB1 297 VCCIB2 227 VCCIB2 239 VCCIB2 245 VCCIB2 257 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 Revision 14 3-13 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number Bank 0 IO60NB1F5 275 Bank 3 IO02NB0F0 341 IO60PB1F5 276 IO96NB3F9 217 IO02PB0F0 342 IO61NB1F5 271 IO96PB3F9 218 IO03PB0F0 343 IO61PB1F5 272 IO97NB3F9 219 IO04NB0F0 337 IO63NB1F5 269 IO97PB3F9 220 IO04PB0F0 338 IO63PB1F5 270 IO99NB3F9 213 IO08NB0F0 331 Bank 2 IO99PB3F9 214 IO08PB0F0 332 IO64NB2F6 259 IO108NB3F10 211 IO09NB0F0 335 IO64PB2F6 260 IO108PB3F10 212 IO09PB0F0 336 IO67NB2F6 261 IO109NB3F10 207 IO24NB0F2 325 IO67PB2F6 262 IO109PB3F10 208 IO24PB0F2 326 IO68NB2F6 255 IO111NB3F10 205 IO25NB0F2 323 IO68PB2F6 256 IO111PB3F10 206 IO25PB0F2 324 IO69NB2F6 253 IO112NB3F10 199 IO30NB0F2/HCLKAN 319 IO69PB2F6 254 IO112PB3F10 200 IO30PB0F2/HCLKAP 320 IO74NB2F7 249 IO113NB3F10 201 IO31NB0F2/HCLKBN 313 IO74PB2F7 250 IO113PB3F10 202 IO31PB0F2/HCLKBP 314 IO75NB2F7 247 IO115NB3F10 195 Bank 1 IO75PB2F7 248 IO115PB3F10 196 IO32NB1F3/HCLKCN 305 IO76NB2F7 243 IO116NB3F10 193 IO32PB1F3/HCLKCP 306 IO76PB2F7 244 IO116PB3F10 194 IO33NB1F3/HCLKDN 299 IO77NB2F7 241 IO117NB3F10 189 IO33PB1F3/HCLKDP 300 IO77PB2F7 242 IO117PB3F10 190 IO38NB1F3 295 IO78NB2F7 237 IO124NB3F11 183 IO38PB1F3 296 IO78PB2F7 238 IO124PB3F11 184 IO54NB1F5 287 IO79NB2F7 235 IO125NB3F11 187 IO54PB1F5 288 IO79PB2F7 236 IO125PB3F11 188 IO55NB1F5 289 IO82NB2F7 231 IO127NB3F11 181 IO55PB1F5 290 IO82PB2F7 232 IO127PB3F11 182 IO56NB1F5 281 IO83NB2F7 229 IO128NB3F11 179 IO56PB1F5 282 IO83PB2F7 230 IO128PB3F11 180 IO57NB1F5 283 IO94NB2F8 225 Bank 4 IO57PB1F5 284 IO94PB2F8 226 IO130NB4F12 172 IO59NB1F5 277 IO95NB2F8 223 IO130PB4F12 173 IO59PB1F5 278 IO95PB2F8 224 IO131NB4F12 170 3-14 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number IO131PB4F12 171 IO187PB5F17 99 IO224NB6F20 46 IO132NB4F12 166 IO188NB5F17 100 IO224PB6F20 47 IO132PB4F12 167 IO188PB5F17 101 Bank 7 IO133NB4F12 164 IO190NB5F17 94 IO225NB7F21 40 IO133PB4F12 165 IO190PB5F17 95 IO225PB7F21 41 IO134NB4F12 160 IO192NB5F17 92 IO226NB7F21 42 IO134PB4F12 161 IO192PB5F17 93 IO226PB7F21 43 IO136NB4F12 158 Bank 6 IO237NB7F22 34 IO136PB4F12 159 IO193PB6F18 86 IO237PB7F22 35 IO137NB4F12 154 IO194NB6F18 84 IO238NB7F22 36 IO137PB4F12 155 IO194PB6F18 85 IO238PB7F22 37 IO138NB4F12 152 IO196NB6F18 78 IO240NB7F22 30 IO138PB4F12 153 IO196PB6F18 79 IO240PB7F22 31 IO153NB4F14 146 IO197NB6F18 82 IO241NB7F22 28 IO153PB4F14 147 IO197PB6F18 83 IO241PB7F22 29 IO159NB4F14/CLKEN 142 IO198NB6F18 76 IO242NB7F22 24 IO159PB4F14/CLKEP 143 IO198PB6F18 77 IO242PB7F22 25 IO160NB4F14/CLKFN 136 IO203NB6F19 72 IO244NB7F22 22 IO160PB4F14/CLKFP 137 IO203PB6F19 73 IO244PB7F22 23 Bank 5 IO204NB6F19 70 IO245NB7F22 18 IO161NB5F15/CLKGN 128 IO204PB6F19 71 IO245PB7F22 19 IO161PB5F15/CLKGP 129 IO205NB6F19 66 IO246NB7F22 16 IO162NB5F15/CLKHN 122 IO205PB6F19 67 IO246PB7F22 17 IO162PB5F15/CLKHP 123 IO206NB6F19 64 IO249NB7F23 12 IO167NB5F15 118 IO206PB6F19 65 IO249PB7F23 13 IO167PB5F15 119 IO207NB6F19 60 IO250NB7F23 10 IO183NB5F17 110 IO207PB6F19 61 IO250PB7F23 11 IO183PB5F17 111 IO208NB6F19 58 IO256NB7F23 4 IO184NB5F17 112 IO208PB6F19 59 IO256PB7F23 5 IO184PB5F17 113 IO211NB6F19 54 IO257NB7F23 6 IO185NB5F17 104 IO211PB6F19 55 IO257PB7F23 7 IO185PB5F17 105 IO212NB6F19 52 Dedicated I/O IO186NB5F17 106 IO212PB6F19 53 GND 1 IO186PB5F17 107 IO223NB6F20 48 GND 9 IO187NB5F17 98 IO223PB6F20 49 GND 15 Revision 14 3-15 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number GND 21 GND 240 NC 307 GND 27 GND 246 NC 308 GND 33 GND 252 NC 315 GND 39 GND 258 NC 316 GND 45 GND 264 NC 317 GND 51 GND 265 NC 318 GND 57 GND 274 PRA 312 GND 63 GND 280 PRB 311 GND 69 GND 286 PRC 135 GND 75 GND 292 PRD 134 GND 81 GND 298 TCK 349 GND 88 GND 310 TDI 348 GND 89 GND 322 TDO 347 GND 97 GND 330 TMS 350 GND 103 GND 334 TRST 351 GND 109 GND 340 VCCA 3 GND 115 GND 345 VCCA 14 GND 121 GND 352 VCCA 32 GND 133 NC 91 VCCA 56 GND 145 NC 124 VCCA 74 GND 151 NC 125 VCCA 87 GND 157 NC 126 VCCA 102 GND 163 NC 127 VCCA 114 GND 169 NC 130 VCCA 150 GND 176 NC 131 VCCA 162 GND 177 NC 138 VCCA 175 GND 186 NC 139 VCCA 191 GND 192 NC 140 VCCA 209 GND 198 NC 141 VCCA 233 GND 204 NC 174 VCCA 251 GND 210 NC 268 VCCA 263 GND 216 NC 301 VCCA 279 GND 222 NC 302 VCCA 291 GND 228 NC 303 VCCA 329 GND 234 NC 304 VCCA 339 3-16 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number VCCDA 2 VCCIB5 108 VCCDA 44 VCCIB5 120 VCCDA 90 VCCIB6 50 VCCDA 116 VCCIB6 62 VCCDA 117 VCCIB6 68 VCCDA 132 VCCIB6 80 VCCDA 148 VCCIB7 8 VCCDA 149 VCCIB7 20 VCCDA 178 VCCIB7 26 VCCDA 221 VCCIB7 38 VCCDA 266 VPUMP 267 VCCDA 293 VCCDA 294 VCCDA 309 VCCDA 327 VCCDA 328 VCCDA 346 VCCIB0 321 VCCIB0 333 VCCIB0 344 VCCIB1 273 VCCIB1 285 VCCIB1 297 VCCIB2 227 VCCIB2 239 VCCIB2 245 VCCIB2 257 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 Revision 14 3-17 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number Bank 0 IO71NB1F6 277 Bank 3 IO01NB0F0 341 IO71PB1F6 278 IO129NB3F12 219 IO01PB0F0 342 IO73NB1F6 269 IO129PB3F12 220 IO02PB0F0 343 IO73PB1F6 270 IO132NB3F12 217 IO04NB0F0 337 IO74NB1F6 271 IO132PB3F12 218 IO04PB0F0 338 IO74PB1F6 272 IO137NB3F12 213 IO05NB0F0 335 Bank 2 IO137PB3F12 214 IO05PB0F0 336 IO87NB2F8 261 IO139NB3F13 211 IO08NB0F0 331 IO87PB2F8 262 IO139PB3F13 212 IO08PB0F0 332 IO88NB2F8 255 IO141NB3F13 205 IO37NB0F3 325 IO88PB2F8 256 IO141PB3F13 206 IO37PB0F3 326 IO89NB2F8 259 IO142NB3F13 207 IO38NB0F3 323 IO89PB2F8 260 IO142PB3F13 208 IO38PB0F3 324 IO91NB2F8 253 IO145NB3F13 199 IO41NB0F3/HCLKAN 319 IO91PB2F8 254 IO145PB3F13 200 IO41PB0F3/HCLKAP 320 IO99NB2F9 249 IO146NB3F13 201 IO42NB0F3/HCLKBN 313 IO99PB2F9 250 IO146PB3F13 202 IO42PB0F3/HCLKBP 314 IO100NB2F9 247 IO147NB3F13 193 Bank 1 IO100PB2F9 248 IO147PB3F13 194 IO43NB1F4/HCLKCN 305 IO107NB2F10 243 IO148NB3F13 195 IO43PB1F4/HCLKCP 306 IO107PB2F10 244 IO148PB3F13 196 IO44NB1F4/HCLKDN 299 IO110NB2F10 241 IO149NB3F13 189 IO44PB1F4/HCLKDP 300 IO110PB2F10 242 IO149PB3F13 190 IO48NB1F4 295 IO111NB2F10 237 IO161NB3F15 183 IO48PB1F4 296 IO111PB2F10 238 IO161PB3F15 184 IO65NB1F6 283 IO112NB2F10 235 IO163NB3F15 187 IO65PB1F6 284 IO112PB2F10 236 IO163PB3F15 188 IO66NB1F6 289 IO113NB2F10 231 IO165NB3F15 181 IO66PB1F6 290 IO113PB2F10 232 IO165PB3F15 182 IO68NB1F6 287 IO114NB2F10 229 IO167NB3F15 179 IO68PB1F6 288 IO114PB2F10 230 IO167PB3F15 180 IO69NB1F6 275 IO115NB2F10 225 Bank 4 IO69PB1F6 276 IO115PB2F10 226 IO181NB4F17 172 IO70NB1F6 281 IO117NB2F10 223 IO181PB4F17 173 IO70PB1F6 282 IO117PB2F10 224 IO182NB4F17 170 3-18 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO182PB4F17 171 IO240PB5F22 101 IO296NB6F27 46 IO183NB4F17 166 IO242NB5F22 94 IO296PB6F27 47 IO183PB4F17 167 IO242PB5F22 95 Bank 7 IO184NB4F17 164 IO243NB5F22 98 IO300NB7F28 42 IO184PB4F17 165 IO243PB5F22 99 IO300PB7F28 43 IO185NB4F17 160 IO244NB5F22 92 IO303NB7F28 40 IO185PB4F17 161 IO244PB5F22 93 IO303PB7F28 41 IO190NB4F17 158 Bank 6 IO310NB7F29 34 IO190PB4F17 159 IO257PB6F24 86 IO310PB7F29 35 IO191NB4F17 154 IO258NB6F24 84 IO311NB7F29 36 IO191PB4F17 155 IO258PB6F24 85 IO311PB7F29 37 IO192NB4F17 152 IO261NB6F24 82 IO312NB7F29 28 IO192PB4F17 153 IO261PB6F24 83 IO312PB7F29 29 IO207NB4F19 146 IO262NB6F24 78 IO315NB7F29 30 IO207PB4F19 147 IO262PB6F24 79 IO315PB7F29 31 IO212NB4F19/CLKEN 142 IO265NB6F24 76 IO316NB7F29 22 IO212PB4F19/CLKEP 143 IO265PB6F24 77 IO316PB7F29 23 IO213NB4F19/CLKFN 136 IO279NB6F26 72 IO317NB7F29 24 IO213PB4F19/CLKFP 137 IO279PB6F26 73 IO317PB7F29 25 Bank 5 IO280NB6F26 70 IO318NB7F29 18 IO214NB5F20/CLKGN 128 IO280PB6F26 71 IO318PB7F29 19 IO214PB5F20/CLKGP 129 IO281NB6F26 66 IO320NB7F29 16 IO215NB5F20/CLKHN 122 IO281PB6F26 67 IO320PB7F29 17 IO215PB5F20/CLKHP 123 IO282NB6F26 64 IO334NB7F31 10 IO217NB5F20 118 IO282PB6F26 65 IO334PB7F31 11 IO217PB5F20 119 IO284NB6F26 60 IO335NB7F31 12 IO236NB5F22 110 IO284PB6F26 61 IO335PB7F31 13 IO236PB5F22 111 IO285NB6F26 58 IO338NB7F31 6 IO237NB5F22 112 IO285PB6F26 59 IO338PB7F31 7 IO237PB5F22 113 IO286NB6F26 54 IO341NB7F31 4 IO238NB5F22 104 IO286PB6F26 55 IO341PB7F31 5 IO238PB5F22 105 IO287NB6F26 52 Dedicated I/O IO239NB5F22 106 IO287PB6F26 53 GND 1 IO239PB5F22 107 IO294NB6F27 48 GND 9 IO240NB5F22 100 IO294PB6F27 49 GND 15 Revision 14 3-19 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number GND 21 GND 240 PRB 311 GND 27 GND 246 PRC 135 GND 33 GND 252 PRD 134 GND 39 GND 258 TCK 349 GND 45 GND 264 TDI 348 GND 51 GND 265 TDO 347 GND 57 GND 274 TMS 350 GND 63 GND 280 TRST 351 GND 69 GND 286 VCCA 3 GND 75 GND 292 VCCA 14 GND 81 GND 298 VCCA 32 GND 88 GND 310 VCCA 56 GND 89 GND 322 VCCA 74 GND 97 GND 330 VCCA 87 GND 103 GND 334 VCCA 102 GND 109 GND 340 VCCA 114 GND 115 GND 345 VCCA 150 GND 121 GND 352 VCCA 162 GND 133 NC 124 VCCA 175 GND 145 NC 125 VCCA 191 GND 151 NC 126 VCCA 209 GND 157 NC 127 VCCA 233 GND 163 NC 138 VCCA 251 GND 169 NC 139 VCCA 263 GND 176 NC 140 VCCA 279 GND 177 NC 141 VCCA 291 GND 186 NC 301 VCCA 329 GND 192 NC 302 VCCA 339 GND 198 NC 303 VCCDA 2 GND 204 NC 304 VCCDA 44 GND 210 NC 315 VCCDA 90 GND 216 NC 316 VCCDA 91 GND 222 NC 317 VCCDA 116 GND 228 NC 318 VCCDA 117 GND 234 PRA 312 VCCDA 130 3-20 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number VCCDA 131 VCCIB5 108 VCCDA 132 VCCIB5 120 VCCDA 148 VCCIB6 50 VCCDA 149 VCCIB6 62 VCCDA 174 VCCIB6 68 VCCDA 178 VCCIB6 80 VCCDA 221 VCCIB7 8 VCCDA 266 VCCIB7 20 VCCDA 268 VCCIB7 26 VCCDA 293 VCCIB7 38 VCCDA 294 VPUMP 267 VCCDA 307 VCCDA 308 VCCDA 309 VCCDA 327 VCCDA 328 VCCDA 346 VCCIB0 321 VCCIB0 333 VCCIB0 344 VCCIB1 273 VCCIB1 285 VCCIB1 297 VCCIB2 227 VCCIB2 239 VCCIB2 245 VCCIB2 257 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 Revision 14 3-21 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number Bank 0 Bank 2 IO179PB3F20 206 IO02NB0F0 341 IO104NB2F12 259 IO181NB3F20 201 IO02PB0F0 342 IO104PB2F12 260 IO181PB3F20 202 IO03PB0F0 343 IO106NB2F12 253 IO182NB3F20 199 IO05NB0F0 337 IO106PB2F12 254 IO182PB3F20 200 IO05PB0F0 338 IO107NB2F12 257 IO183NB3F20 195 IO06NB0F0 335 IO107PB2F12 258 IO183PB3F20 196 IO06PB0F0 336 IO111NB2F12 251 IO203NB3F23 189 IO07NB0F0 331 IO111PB2F12 252 IO203PB3F23 190 IO07PB0F0 332 IO139NB2F16 241 IO204NB3F23 183 IO11NB0F0 329 IO139PB2F16 242 IO204PB3F23 184 IO11PB0F0 330 IO140NB2F16 245 IO206NB3F23 187 IO50NB0F4/HCLKAN 317 IO140PB2F16 246 IO206PB3F23 188 IO50PB0F4/HCLKAP 318 IO141NB2F16 235 IO209NB3F23 181 IO51NB0F4/HCLKBN 313 IO141PB2F16 236 IO209PB3F23 182 IO51PB0F4/HCLKBP 314 IO142NB2F16 239 Bank 4 Bank 1 IO142PB2F16 240 IO210NB4F24 167 IO52NB1F6/HCLKCN 303 IO143NB2F16 229 IO210PB4F24 168 IO52PB1F6/HCLKCP 304 IO143PB2F16 230 IO211NB4F24 173 IO53NB1F6/HCLKDN 299 IO144NB2F16 233 IO213NB4F24 171 IO53PB1F6/HCLKDP 300 IO144PB2F16 234 IO213PB4F24 172 IO94NB1F10 287 IO145NB2F16 223 IO214NB4F24 161 IO94PB1F10 288 IO145PB2F16 224 IO214PB4F24 162 IO97NB1F10 281 IO146NB2F16 227 IO215NB4F24 165 IO97PB1F10 282 IO146PB2F16 228 IO215PB4F24 166 IO98NB1F10 285 Bank 3 IO216NB4F24 155 IO98PB1F10 286 IO175NB3F20 213 IO216PB4F24 156 IO99NB1F10 275 IO175PB3F20 214 IO217NB4F24 159 IO99PB1F10 276 IO176NB3F20 217 IO217PB4F24 160 IO100NB1F10 279 IO176PB3F20 218 IO219NB4F24 153 IO100PB1F10 280 IO177NB3F20 207 IO219PB4F24 154 IO102NB1F10 273 IO177PB3F20 208 IO260NB4F28/CLKEN 141 IO102PB1F10 274 IO178NB3F20 211 IO260PB4F28/CLKEP 142 IO103NB1F10 269 IO178PB3F20 212 IO261NB4F28/CLKFN 137 IO103PB1F10 270 IO179NB3F20 205 IO261PB4F28/CLKFP 138 3-22 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number Bank 5 IO352PB6F40 65 GND 1 IO262NB5F30/CLKGN 127 IO353NB6F40 54 GND 5 IO262PB5F30/CLKGP 128 IO353PB6F40 55 GND 11 IO263NB5F30/CLKHN 123 IO354NB6F40 58 GND 17 IO263PB5F30/CLKHP 124 IO354PB6F40 59 GND 19 IO304NB5F34 111 IO355NB6F40 48 GND 23 IO304PB5F34 112 IO355PB6F40 49 GND 29 IO305NB5F34 109 IO356NB6F40 52 GND 35 IO305PB5F34 110 IO356PB6F40 53 GND 41 IO307NB5F34 103 Bank 7 GND 45 IO307PB5F34 104 IO385NB7F44 42 GND 47 IO308NB5F34 105 IO385PB7F44 43 GND 51 IO308PB5F34 106 IO386NB7F44 38 GND 57 IO309NB5F34 97 IO386PB7F44 39 GND 63 IO309PB5F34 98 IO387NB7F44 36 GND 69 IO310NB5F34 99 IO387PB7F44 37 GND 73 IO310PB5F34 100 IO388NB7F44 32 GND 75 IO312NB5F34 93 IO388PB7F44 33 GND 81 IO312PB5F34 94 IO389NB7F44 30 GND 86 IO313NB5F34 92 IO389PB7F44 31 GND 88 Bank 6 IO391NB7F44 26 GND 89 IO314PB6F36 84 IO391PB7F44 27 GND 96 IO316NB6F36 82 IO392NB7F44 24 GND 102 IO316PB6F36 83 IO392PB7F44 25 GND 108 IO317NB6F36 78 IO393NB7F44 20 GND 117 IO317PB6F36 79 IO393PB7F44 21 GND 119 IO319NB6F36 76 IO413NB7F47 14 GND 126 IO319PB6F36 77 IO413PB7F47 15 GND 132 IO349NB6F40 66 IO414NB7F47 8 GND 134 IO349PB6F40 67 IO414PB7F47 9 GND 140 IO350NB6F40 70 IO416NB7F47 12 GND 147 IO350PB6F40 71 IO416PB7F47 13 GND 149 IO351NB6F40 60 IO419NB7F47 6 GND 158 IO351PB6F40 61 IO419PB7F47 7 GND 164 IO352NB6F40 64 Dedicated I/O GND 170 Revision 14 3-23 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number GND 176 GND 345 VCCA 277 GND 177 GND 352 VCCA 292 GND 180 PRA 312 VCCA 305 GND 186 PRB 311 VCCA 307 GND 192 PRC 136 VCCA 324 GND 194 PRD 135 VCCA 339 GND 198 TCK 349 VCCDA 2 GND 204 TDI 348 VCCDA 16 GND 210 TDO 347 VCCDA 46 GND 216 TMS 350 VCCDA 74 GND 220 TRST 351 VCCDA 90 GND 222 VCCA 3 VCCDA 91 GND 226 VCCA 4 VCCDA 113 GND 232 VCCA 18 VCCDA 114 GND 238 VCCA 34 VCCDA 115 GND 244 VCCA 44 VCCDA 118 GND 248 VCCA 56 VCCDA 120 GND 250 VCCA 72 VCCDA 121 GND 256 VCCA 85 VCCDA 122 GND 262 VCCA 87 VCCDA 130 GND 264 VCCA 101 VCCDA 133 GND 265 VCCA 116 VCCDA 143 GND 272 VCCA 129 VCCDA 144 GND 278 VCCA 131 VCCDA 145 GND 284 VCCA 148 VCCDA 146 GND 293 VCCA 163 VCCDA 150 GND 295 VCCA 175 VCCDA 151 GND 302 VCCA 179 VCCDA 152 GND 308 VCCA 193 VCCDA 174 GND 310 VCCA 209 VCCDA 178 GND 316 VCCA 219 VCCDA 191 GND 323 VCCA 231 VCCDA 221 GND 325 VCCA 247 VCCDA 249 GND 334 VCCA 261 VCCDA 266 GND 340 VCCA 263 VCCDA 268 3-24 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number VCCDA 289 VCCIB5 107 VCCDA 290 VCCIB5 125 VCCDA 291 VCCIB6 50 VCCDA 294 VCCIB6 62 VCCDA 296 VCCIB6 68 VCCDA 297 VCCIB6 80 VCCDA 298 VCCIB7 10 VCCDA 306 VCCIB7 22 VCCDA 309 VCCIB7 28 VCCDA 319 VCCIB7 40 VCCDA 320 VPUMP 267 VCCDA 321 VCCDA 322 VCCDA 326 VCCDA 327 VCCDA 328 VCCDA 346 VCCIB0 315 VCCIB0 333 VCCIB0 344 VCCIB1 271 VCCIB1 283 VCCIB1 301 VCCIB2 225 VCCIB2 237 VCCIB2 243 VCCIB2 255 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 139 VCCIB4 157 VCCIB4 169 VCCIB5 95 Revision 14 3-25 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000D Function Number RTAX2000D Function Number RTAX2000D Function Number Bank 0 Bank 2 IO143PB3F13 206 IO01PB0F0 343 IO87NB2F8 259 IO147NB3F13 201 IO05NB0F0 341 IO87PB2F8 260 IO147PB3F13 202 IO05PB0F0 342 IO91NB2F8 257 IO151NB3F14 199 IO13NB0F1 337 IO91PB2F8 258 IO151PB3F14 200 IO13PB0F1 338 IO95NB2F8 253 IO155NB3F14 195 IO17NB0F1 335 IO95PB2F8 254 IO155PB3F14 196 IO17PB0F1 336 IO99NB2F9 251 IO159NB3F14 189 IO25NB0F2 331 IO99PB2F9 252 IO159PB3F14 190 IO25PB0F2 332 IO103NB2F9 245 IO163NB3F15 187 IO29NB0F2 329 IO103PB2F9 246 IO163PB3F15 188 IO29PB0F2 330 IO107NB2F10 241 IO167NB3F15 183 IO41NB0F3/HCLKAN 317 IO107PB2F10 242 IO167PB3F15 184 IO41PB0F3/HCLKAP 318 IO111NB2F10 239 IO170NB3F15 181 IO42NB0F3/HCLKBN 313 IO111PB2F10 240 IO170PB3F15 182 IO42PB0F3/HCLKBP 314 IO115NB2F10 235 Bank 4 Bank 1 IO115PB2F10 236 IO172NB4F16 173 IO43NB1F4/HCLKCN 303 IO119NB2F11 233 IO176NB4F16 171 IO43PB1F4/HCLKCP 304 IO119PB2F11 234 IO176PB4F16 172 IO44NB1F4/HCLKDN 299 IO121NB2F11 229 IO184NB4F17 167 IO44PB1F4/HCLKDP 300 IO121PB2F11 230 IO184PB4F17 168 IO53NB1F4 287 IO123NB2F11 227 IO188NB4F17 165 IO53PB1F4 288 IO123PB2F11 228 IO188PB4F17 166 IO57NB1F5 285 IO127NB2F11 223 IO192NB4F17 161 IO57PB1F5 286 IO127PB2F11 224 IO192PB4F17 162 IO61NB1F5 281 Bank 3 IO196NB4F18 159 IO61PB1F5 282 IO131NB3F12 217 IO196PB4F18 160 IO65NB1F6 279 IO131PB3F12 218 IO200NB4F18 155 IO65PB1F6 280 IO135NB3F12 213 IO200PB4F18 156 IO69NB1F6 275 IO135PB3F12 214 IO208NB4F19 153 IO69PB1F6 276 IO137NB3F12 211 IO208PB4F19 154 IO77NB1F7 273 IO137PB3F12 212 IO212NB4F19/CLKEN 141 IO77PB1F7 274 IO139NB3F13 207 IO212PB4F19/CLKEP 142 IO81NB1F7 269 IO139PB3F13 208 IO213NB4F19/CLKFN 137 IO81PB1F7 270 IO143NB3F13 205 IO213PB4F19/CLKFP 138 3-26 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000D Function Number RTAX2000D Function Number RTAX2000D Function Number Bank 5 IO282PB6F26 61 GND 1 IO214NB5F20/CLKGN 127 IO286NB6F26 58 GND 5 IO214PB5F20/CLKGP 128 IO286PB6F26 59 GND 11 IO215NB5F20/CLKHN 123 IO290NB6F27 54 GND 19 IO215PB5F20/CLKHP 124 IO290PB6F27 55 GND 23 IO218NB5F20 111 IO294NB6F27 52 GND 29 IO218PB5F20 112 IO294PB6F27 53 GND 35 IO228NB5F21 109 IO298NB6F27 48 GND 41 IO228PB5F21 110 IO298PB6F27 49 GND 47 IO232NB5F21 105 Bank 7 GND 51 IO232PB5F21 106 IO302NB7F28 42 GND 57 IO236NB5F22 103 IO302PB7F28 43 GND 63 IO236PB5F22 104 IO306NB7F28 38 GND 69 IO240NB5F22 99 IO306PB7F28 39 GND 73 IO240PB5F22 100 IO308NB7F28 32 GND 81 IO246NB5F23 97 IO308PB7F28 33 GND 86 IO246PB5F23 98 IO310NB7F29 36 GND 88 IO248NB5F23 92 IO310PB7F29 37 GND 89 IO252NB5F23 93 IO314NB7F29 30 GND 96 IO252PB5F23 94 IO314PB7F29 31 GND 102 Bank 6 IO318NB7F29 26 GND 108 IO257PB6F24 84 IO318PB7F29 27 GND 117 IO258NB6F24 82 IO322NB7F30 24 GND 126 IO258PB6F24 83 IO322PB7F30 25 GND 132 IO262NB6F24 78 IO326NB7F30 20 GND 134 IO262PB6F24 79 IO326PB7F30 21 GND 140 IO266NB6F24 76 IO330NB7F30 14 GND 149 IO266PB6F24 77 IO330PB7F30 15 GND 158 IO270NB6F25 70 IO334NB7F31 12 GND 164 IO270PB6F25 71 IO334PB7F31 13 GND 170 IO274NB6F25 66 IO338NB7F31 8 GND 176 IO274PB6F25 67 IO338PB7F31 9 GND 177 IO278NB6F26 64 IO341NB7F31 6 GND 180 IO278PB6F26 65 IO341PB7F31 7 GND 186 IO282NB6F26 60 Dedicated I/O GND 194 Revision 14 3-27 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX2000D Function Number RTAX2000D Function Number RTAX2000D Function Number GND 198 NC 119 TMS 350 GND 204 NC 120 TRST 351 GND 210 NC 122 VCCA 3 GND 216 NC 129 VCCA 87 GND 222 NC 143 VCCA 175 GND 226 NC 144 VCCA 263 GND 232 NC 146 VCCA 4 GND 238 NC 147 VCCA 18 GND 244 NC 151 VCCA 34 GND 248 NC 152 VCCA 56 GND 256 NC 191 VCCA 72 GND 262 NC 192 VCCA 85 GND 264 NC 219 VCCA 101 GND 265 NC 220 VCCA 116 GND 272 NC 249 VCCA 131 GND 278 NC 250 VCCA 148 GND 284 NC 289 VCCA 163 GND 293 NC 294 VCCA 179 GND 302 NC 295 VCCA 193 GND 308 NC 296 VCCA 209 GND 310 NC 298 VCCA 231 GND 316 NC 305 VCCA 247 GND 325 NC 319 VCCA 261 GND 334 NC 320 VCCA 277 GND 340 NC 322 VCCA 292 GND 345 NC 323 VCCA 307 GND 352 NC 327 VCCA 324 NC 16 NC 328 VCCA 339 NC 17 PRA 312 VCCDA 2 NC 44 PRB 311 VCCDA 46 NC 45 PRC 136 VCCDA 90 NC 74 PRD 135 VCCDA 91 NC 75 TCK 349 VCCDA 114 NC 113 TDI 348 VCCDA 115 NC 118 TDO 347 VCCDA 121 3-28 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX2000D Function Number RTAX2000D Function Number VCCDA 130 VCCIB5 107 VCCDA 133 VCCIB5 125 VCCDA 145 VCCIB6 50 VCCDA 150 VCCIB6 62 VCCDA 174 VCCIB6 68 VCCDA 178 VCCIB6 80 VCCDA 221 VCCIB7 10 VCCDA 266 VCCIB7 22 VCCDA 268 VCCIB7 28 VCCDA 290 VCCIB7 40 VCCDA 291 VPUMP 267 VCCDA 297 VCCDA 306 VCCDA 309 VCCDA 321 VCCDA 326 VCCDA 346 VCCIB0 315 VCCIB0 333 VCCIB0 344 VCCIB1 271 VCCIB1 283 VCCIB1 301 VCCIB2 225 VCCIB2 237 VCCIB2 243 VCCIB2 255 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 139 VCCIB4 157 VCCIB4 169 VCCIB5 95 Revision 14 3-29 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000D Function Number RTAX4000D Function Number RTAX4000D Function Number Bank 0 Bank 2 IO179PB3F20 206 IO02NB0F0 341 IO104NB2F12 259 IO181NB3F20 201 IO02PB0F0 342 IO104PB2F12 260 IO181PB3F20 202 IO03PB0F0 343 IO106NB2F12 253 IO182NB3F20 199 IO05NB0F0 337 IO106PB2F12 254 IO182PB3F20 200 IO05PB0F0 338 IO107NB2F12 257 IO183NB3F20 195 IO06NB0F0 335 IO107PB2F12 258 IO183PB3F20 196 IO06PB0F0 336 IO111NB2F12 251 IO203NB3F23 189 IO07NB0F0 331 IO111PB2F12 252 IO203PB3F23 190 IO07PB0F0 332 IO139NB2F16 241 IO204NB3F23 183 IO11NB0F0 329 IO139PB2F16 242 IO204PB3F23 184 IO11PB0F0 330 IO140NB2F16 245 IO206NB3F23 187 IO50NB0F4/HCLKAN 317 IO140PB2F16 246 IO206PB3F23 188 IO50PB0F4/HCLKAP 318 IO141NB2F16 235 IO209NB3F23 181 IO51NB0F4/HCLKBN 313 IO141PB2F16 236 IO209PB3F23 182 IO51PB0F4/HCLKBP 314 IO142NB2F16 239 Bank 4 Bank 1 IO142PB2F16 240 IO210NB4F24 167 IO52NB1F6/HCLKCN 303 IO143NB2F16 229 IO210PB4F24 168 IO52PB1F6/HCLKCP 304 IO143PB2F16 230 IO211NB4F24 173 IO53NB1F6/HCLKDN 299 IO144NB2F16 233 IO213NB4F24 171 IO53PB1F6/HCLKDP 300 IO144PB2F16 234 IO213PB4F24 172 IO94NB1F10 287 IO145NB2F16 223 IO214NB4F24 161 IO94PB1F10 288 IO145PB2F16 224 IO214PB4F24 162 IO97NB1F10 281 IO146NB2F16 227 IO215NB4F24 165 IO97PB1F10 282 IO146PB2F16 228 IO215PB4F24 166 IO98NB1F10 285 Bank 3 IO216NB4F24 155 IO98PB1F10 286 IO175NB3F20 213 IO216PB4F24 156 IO99NB1F10 275 IO175PB3F20 214 IO217NB4F24 159 IO99PB1F10 276 IO176NB3F20 217 IO217PB4F24 160 IO100NB1F10 279 IO176PB3F20 218 IO219NB4F24 153 IO100PB1F10 280 IO177NB3F20 207 IO219PB4F24 154 IO102NB1F10 273 IO177PB3F20 208 IO260NB4F28/CLKEN 141 IO102PB1F10 274 IO178NB3F20 211 IO260PB4F28/CLKEP 142 IO103NB1F10 269 IO178PB3F20 212 IO261NB4F28/CLKFN 137 IO103PB1F10 270 IO179NB3F20 205 IO261PB4F28/CLKFP 138 3-30 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000D Function Number RTAX4000D Function Number RTAX4000D Function Number Bank 5 IO352PB6F40 65 GND 1 IO262NB5F30/CLKGN 127 IO353NB6F40 54 GND 5 IO262PB5F30/CLKGP 128 IO353PB6F40 55 GND 11 IO263NB5F30/CLKHN 123 IO354NB6F40 58 GND 17 IO263PB5F30/CLKHP 124 IO354PB6F40 59 GND 19 IO304NB5F34 111 IO355NB6F40 48 GND 23 IO304PB5F34 112 IO355PB6F40 49 GND 29 IO305NB5F34 109 IO356NB6F40 52 GND 35 IO305PB5F34 110 IO356PB6F40 53 GND 41 IO307NB5F34 103 Bank 7 GND 45 IO307PB5F34 104 IO385NB7F44 42 GND 47 IO308NB5F34 105 IO385PB7F44 43 GND 51 IO308PB5F34 106 IO386NB7F44 38 GND 57 IO309NB5F34 97 IO386PB7F44 39 GND 63 IO309PB5F34 98 IO387NB7F44 36 GND 69 IO310NB5F34 99 IO387PB7F44 37 GND 73 IO310PB5F34 100 IO388NB7F44 32 GND 75 IO312NB5F34 93 IO388PB7F44 33 GND 81 IO312PB5F34 94 IO389NB7F44 30 GND 86 IO313NB5F34 92 IO389PB7F44 31 GND 88 Bank 6 IO391NB7F44 26 GND 89 IO314PB6F36 84 IO391PB7F44 27 GND 96 IO316NB6F36 82 IO392NB7F44 24 GND 102 IO316PB6F36 83 IO392PB7F44 25 GND 108 IO317NB6F36 78 IO393NB7F44 20 GND 117 IO317PB6F36 79 IO393PB7F44 21 GND 119 IO319NB6F36 76 IO413NB7F47 14 GND 126 IO319PB6F36 77 IO413PB7F47 15 GND 132 IO349NB6F40 66 IO414NB7F47 8 GND 134 IO349PB6F40 67 IO414PB7F47 9 GND 140 IO350NB6F40 70 IO416NB7F47 12 GND 147 IO350PB6F40 71 IO416PB7F47 13 GND 149 IO351NB6F40 60 IO419NB7F47 6 GND 158 IO351PB6F40 61 IO419PB7F47 7 GND 164 IO352NB6F40 64 Dedicated I/O GND 170 Revision 14 3-31 Package Pin Assignments CQ352 CQ352 CQ352 Pin Pin Pin RTAX4000D Function Number RTAX4000D Function Number RTAX4000D Function Number GND 176 GND 345 VCCA 261 GND 177 GND 352 VCCA 277 GND 180 PRA 312 VCCA 292 GND 186 PRB 311 VCCA 307 GND 192 PRC 136 VCCA 324 GND 194 PRD 135 VCCA 339 GND 198 TCK 349 VCCDA 2 GND 204 TDI 348 VCCDA 16 GND 210 TDO 347 VCCDA 46 GND 216 TMS 350 VCCDA 74 GND 220 TRST 351 VCCDA 90 GND 222 VCCA 3 VCCDA 91 GND 226 VCCA 44 VCCDA 113 GND 232 VCCA 87 VCCDA 114 GND 238 VCCA 129 VCCDA 115 GND 244 VCCA 175 VCCDA 118 GND 248 VCCA 219 VCCDA 120 GND 250 VCCA 263 VCCDA 121 GND 256 VCCA 305 VCCDA 122 GND 262 VCCA 4 VCCDA 130 GND 264 VCCA 18 VCCDA 133 GND 265 VCCA 34 VCCDA 143 GND 272 VCCA 56 VCCDA 144 GND 278 VCCA 72 VCCDA 145 GND 284 VCCA 85 VCCDA 146 GND 293 VCCA 101 VCCDA 150 GND 295 VCCA 116 VCCDA 151 GND 302 VCCA 131 VCCDA 152 GND 308 VCCA 148 VCCDA 174 GND 310 VCCA 163 VCCDA 178 GND 316 VCCA 179 VCCDA 191 GND 323 VCCA 193 VCCDA 221 GND 325 VCCA 209 VCCDA 249 GND 334 VCCA 231 VCCDA 266 GND 340 VCCA 247 VCCDA 268 3-32 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CQ352 CQ352 Pin Pin RTAX4000D Function Number RTAX4000D Function Number VCCDA 289 VCCIB5 107 VCCDA 290 VCCIB5 125 VCCDA 291 VCCIB6 50 VCCDA 294 VCCIB6 62 VCCDA 296 VCCIB6 68 VCCDA 297 VCCIB6 80 VCCDA 298 VCCIB7 10 VCCDA 306 VCCIB7 22 VCCDA 309 VCCIB7 28 VCCDA 319 VCCIB7 40 VCCDA 320 VPUMP 267 VCCDA 321 VCCDA 322 VCCDA 326 VCCDA 327 VCCDA 328 VCCDA 346 VCCIB0 315 VCCIB0 333 VCCIB0 344 VCCIB1 271 VCCIB1 283 VCCIB1 301 VCCIB2 225 VCCIB2 237 VCCIB2 243 VCCIB2 255 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 139 VCCIB4 157 VCCIB4 169 VCCIB5 95 Revision 14 3-33 Package Pin Assignments CG624/LG624 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Note: The 624-pin CCGA pin assignments for RTAX250S/SL, RTAX1000S/SL and RTAX2000S/SL are compatible except for the following pins. Table 1 • Compatibility Table for the CGA/LGA 624 Package RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX250S/SL NA A12, AD11, AE17, B15, D13 A12, A14, AA20, AB13, AD11, AD4, AE12, B15, D13, F21, G10 RTAX1000S/SL A12, AD11, AE17, B15, D13 NA A14, AA20, AB13, AD4, AE12, F21, G10 RTAX2000S/SL A12, A14, AA20, AB13, A14, AA20, AB13, AD4, NA AD11, AD4, AE12, B15, AE12, F21, G10 D13, F21, G10 Where exceptions occur, the smaller density devices have those pins designated as No Connects (NC). Customers are therefore recommended to layout their board targeting the larger density device, in order to preserve interchangeability between the two devices. Note: RTAX4000S is not pin compatible with any of the smaller density devices. For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 3-34 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number Bank 0 IO21PB1F1 A19 IO37PB2F2 K24 IO22NB1F1 D18 IO38NB2F2 J24 IO00NB0F0 C9 IO00PB0F0 C8 IO22PB1F1 D17 IO38PB2F2 H24 IO01NB0F0 B5 IO23NB1F1 A22 IO39NB2F2 N22 IO01PB0F0 B4 IO23PB1F1 A21 IO39PB2F2 M22 IO02NB0F0 D10 IO24NB1F1 G17 IO40NB2F2 N24 IO02PB0F0 D9 IO24PB1F1 H17 IO40PB2F2 M24 IO03NB0F0 A5 IO25NB1F1 C21 IO41NB2F2 N19 IO03PB0F0 A4 IO25PB1F1 C20 IO41PB2F2 N18 IO04NB0F0 H8 IO26NB1F1 C19 IO42NB2F2 L25 IO04PB0F0 H7 IO26PB1F1 C18 IO42PB2F2 K25 IO05NB0F0 A7 IO27NB1F1 D20 IO43NB2F2 N23 IO05PB0F0 A6 IO27PB1F1 D19 IO43PB2F2 M23 IO06NB0F0 H10 IO14NB1F1/HCLKCN G15 IO44NB2F2 N25 IO06PB0F0 H9 IO14PB1F1/HCLKCP G14 IO44PB2F2 M25 IO07NB0F0 B11 IO15NB1F1/HCLKDN B14 Bank 3 IO07PB0F0 B10 IO15PB1F1/HCLKDP B13 IO45NB3F3 R22 IO08NB0F0 J8 Bank 2 IO45PB3F3 P22 IO08PB0F0 J7 IO28NB2F2 J22 IO46NB3F3 R25 IO09NB0F0 A9 IO28PB2F2 H22 IO46PB3F3 P25 IO09PB0F0 B9 IO29NB2F2 L18 IO47NB3F3 R23 IO12NB0F0/HCLKAN G13 IO29PB2F2 K18 IO47PB3F3 P23 IO12PB0F0/HCLKAP G12 IO30NB2F2 F23 IO48NB3F3 Y25 IO13NB0F0/HCLKBN C13 IO30PB2F2 E23 IO48PB3F3 W25 IO13PB0F0/HCLKBP C12 IO31NB2F2 J21 IO49NB3F3 U24 Bank 1 IO31PB2F2 J20 IO49PB3F3 U23 IO16NB1F1 D14 IO32NB2F2 E25 IO50NB3F3 T24 IO16PB1F1 C14 IO32PB2F2 D25 IO50PB3F3 R24 IO17NB1F1 A16 IO33NB2F2 M19 IO51NB3F3 Y23 IO17PB1F1 A15 IO33PB2F2 M18 IO51PB3F3 AA23 IO18NB1F1 H20 IO34NB2F2 H23 IO52NB3F3 V23 IO18PB1F1 H19 IO34PB2F2 G23 IO52PB3F3 V24 IO19NB1F1 B17 IO35NB2F2 L22 IO53NB3F3 P20 IO19PB1F1 B16 IO35PB2F2 K22 IO53PB3F3 P19 IO20NB1F1 D16 IO36NB2F2 G25 IO54NB3F3 U25 IO20PB1F1 D15 IO36PB2F2 F25 IO54PB3F3 T25 IO21NB1F1 A20 IO37NB2F2 L24 IO55NB3F3 V22 Revision 14 3-35 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number IO55PB3F3 U22 IO73PB4F4 AE16 IO91NB6F6 U4 IO56NB3F3 AA24 IO74NB4F4/CLKEN W14 IO91PB6F6 V4 IO56PB3F3 Y24 IO74PB4F4/CLKEP W15 IO92NB6F6 AA1 IO57NB3F3 V20 IO75NB4F4/CLKFN AC13 IO92PB6F6 AB1 IO57PB3F3 U20 IO75PB4F4/CLKFP AD13 IO93NB6F6 W2 IO58NB3F3 AB25 Bank 5 IO93PB6F6 Y2 IO58PB3F3 AA25 IO78NB5F5 AE10 IO94NB6F6 V3 IO59NB3F3 Y22 IO78PB5F5 AE11 IO94PB6F6 W3 IO59PB3F3 Y21 IO79NB5F5 AD9 IO95NB6F6 R4 IO60NB3F3 W22 IO79PB5F5 AD10 IO95PB6F6 T4 IO60PB3F3 W23 IO80NB5F5 V9 IO96NB6F6 W1 IO61NB3F3 T18 IO80PB5F5 V10 IO96PB6F6 Y1 IO61PB3F3 R18 IO81NB5F5 AD7 IO97NB6F6 Y5 Bank 4 IO81PB5F5 AD8 IO97PB6F6 W5 IO62NB4F4 V19 IO82NB5F5 AB10 IO98NB6F6 T2 IO62PB4F4 W19 IO82PB5F5 AB11 IO98PB6F6 U2 IO63NB4F4 AE19 IO83NB5F5 AE6 IO99NB6F6 N3 IO63PB4F4 AE20 IO83PB5F5 AE7 IO99PB6F6 P3 IO64NB4F4 W18 IO84NB5F5 AB8 IO100NB6F6 T1 IO64PB4F4 V18 IO84PB5F5 AC8 IO100PB6F6 U1 IO65NB4F4 AC20 IO85NB5F5 AE4 IO101NB6F6 N4 IO65PB4F4 AC21 IO85PB5F5 AE5 IO101PB6F6 P4 IO66NB4F4 AD14 IO86NB5F5 U13 IO102NB6F6 P2 IO66PB4F4 AC14 IO86PB5F5 V13 IO102PB6F6 R2 IO67NB4F4 AD21 IO87NB5F5 AC5 IO103NB6F6 R8 IO67PB4F4 AD22 IO87PB5F5 AC6 IO103PB6F6 T8 IO68NB4F4 AD15 IO88NB5F5 Y7 IO104NB6F6 P1 IO68PB4F4 AD16 IO88PB5F5 W7 IO104PB6F6 R1 IO69NB4F4 AD19 IO89NB5F5 AB7 IO105NB6F6 M2 IO69PB4F4 AD20 IO89PB5F5 AC7 IO105PB6F6 N2 IO70NB4F4 AB14 IO76NB5F5/CLKGN W13 IO106NB6F6 M1 IO70PB4F4 AB15 IO76PB5F5/CLKGP Y13 IO106PB6F6 N1 IO71NB4F4 AD17 IO77NB5F5/CLKHN AC12 Bank 7 IO71PB4F4 AD18 IO77PB5F5/CLKHP AD12 IO107NB7F7 H4 IO72NB4F4 V15 Bank 6 IO107PB7F7 J4 IO72PB4F4 V16 IO90NB6F6 Y3 IO108NB7F7 K1 IO73NB4F4 AE15 IO90PB6F6 AA3 IO108PB7F7 L1 3-36 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number IO109NB7F7 L3 GND V5 GND C10 IO109PB7F7 M3 GND AA10 GND C16 IO10NB0F0 D12 GND AA16 GND C23 IO10PB0F0 D11 GND AA18 GND C3 IO110NB7F7 J2 GND T21 GND D22 IO110PB7F7 J1 GND K21 GND D4 IO111NB7F7 N10 GND H21 GND E21 IO111PB7F7 N9 GND E16 GND E5 IO112NB7F7 K2 GND E10 GND H1 IO112PB7F7 L2 GND E8 GND H25 IO113NB7F7 K8 GND A18 GND K23 IO113PB7F7 L8 GND A2 GND K3 IO114NB7F7 F1 GND A24 GND L11 IO114PB7F7 G1 GND A25 GND L12 IO115NB7F7 J6 GND A8 GND L13 IO115PB7F7 J5 GND AA21 GND L14 IO116NB7F7 H3 GND AA5 GND L15 IO116PB7F7 H2 GND AB22 GND M11 IO117NB7F7 K4 GND AB4 GND M12 IO117PB7F7 L4 GND AC10 GND M13 IO118NB7F7 E2 GND AC16 GND M14 IO118PB7F7 F2 GND AC23 GND M15 IO119NB7F7 M9 GND AC3 GND N11 IO119PB7F7 M8 GND AD1 GND N12 IO11NB0F0 A11 GND AD2 GND N13 IO11PB0F0 A10 GND AD24 GND N14 IO120NB7F7 D1 GND AD25 GND N15 IO120PB7F7 E1 GND AE1 GND P11 IO121NB7F7 F3 GND AE18 GND P12 IO121PB7F7 E3 GND AE2 GND P13 IO122NB7F7 G4 GND AE24 GND P14 IO122PB7F7 G3 GND AE25 GND P15 IO123NB7F7 H5 GND AE8 GND R11 IO123PB7F7 H6 GND B1 GND R12 Dedicated I/O GND B2 GND R13 GND K5 GND B24 GND R14 GND T5 GND B25 GND R15 Revision 14 3-37 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number GND T23 NC AE17 NC F17 GND T3 NC AE21 NC F18 GND V1 NC AE22 NC F19 GND V25 NC AE9 NC F20 NC A12 NC B12 NC F21 NC A14 NC B15 NC F24 NC A17 NC B18 NC F7 NC AA11 NC B19 NC F8 NC AA12 NC B20 NC F9 NC AA14 NC B21 NC G10 NC AA17 NC B22 NC G11 NC AA19 NC B6 NC G16 NC AA2 NC B7 NC G18 NC AA20 NC B8 NC G19 NC AA6 NC C11 NC G2 NC AA8 NC C17 NC G20 NC AA9 NC C7 NC G21 NC AB13 NC D13 NC G22 NC AB16 NC D2 NC G24 NC AB17 NC D24 NC G6 NC AB18 NC D7 NC G7 NC AB19 NC D8 NC G8 NC AB2 NC E11 NC G9 NC AB24 NC E12 NC H11 NC AB6 NC E14 NC H12 NC AB9 NC E15 NC H13 NC AC15 NC E17 NC H14 NC AC17 NC E18 NC H15 NC AC18 NC E24 NC H16 NC AC19 NC E7 NC H18 NC AC9 NC E9 NC J12 NC AD11 NC F10 NC J13 NC AD4 NC F11 NC J14 NC AD5 NC F12 NC J18 NC AD6 NC F14 NC J19 NC AE12 NC F15 NC J23 NC AE14 NC F16 NC J25 3-38 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number NC J3 NC R21 NC W4 NC K13 NC R3 NC W6 NC K19 NC R5 NC W8 NC K20 NC R6 NC W9 NC K6 NC R7 NC Y10 NC K7 NC T13 NC Y11 NC L19 NC T19 NC Y12 NC L20 NC T20 NC Y14 NC L21 NC T22 NC Y15 NC L23 NC T6 NC Y16 NC L5 NC T7 NC Y17 NC L6 NC U12 NC Y18 NC L7 NC U14 NC Y19 NC M17 NC U18 NC Y20 NC M20 NC U19 NC Y6 NC M21 NC U21 NC Y8 NC M4 NC U3 NC Y9 NC M5 NC U5 PRA F13 NC M6 NC U6 PRB A13 NC M7 NC U7 PRC AB12 NC N16 NC U8 PRD AE13 NC N17 NC V11 TCK F5 NC N20 NC V12 TDI C5 NC N6 NC V14 TDO F6 NC N7 NC V17 TMS D6 NC N8 NC V2 TRST E6 NC P17 NC V21 VCCA F4 NC P18 NC V6 VCCA Y4 NC P21 NC V7 VCCA AB20 NC P24 NC V8 VCCA F22 NC P5 NC W10 VCCA J17 NC P6 NC W11 VCCA J9 NC P7 NC W12 VCCA K10 NC P8 NC W16 VCCA K11 NC P9 NC W17 VCCA K15 NC R19 NC W20 VCCA K16 NC R20 NC W24 VCCA L10 Revision 14 3-39 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX250S/SL Function Number RTAX250S/SL Function Number RTAX250S/SL Function Number VCCA L16 VCCIB2 D23 VCCIB7 K9 VCCA R10 VCCIB2 E22 VCCIB7 L9 VCCA R16 VCCIB2 K17 VCCIB7 M10 VCCA T10 VCCIB2 L17 VPUMP E20 VCCA T11 VCCIB2 M16 VCCA T15 VCCIB3 AA22 VCCA T16 VCCIB3 AB23 VCCA U17 VCCIB3 AC24 VCCA U9 VCCIB3 AC25 VCCDA G5 VCCIB3 P16 VCCDA N5 VCCIB3 R17 VCCDA AA7 VCCIB3 T17 VCCDA AC11 VCCIB4 AB21 VCCDA AA13 VCCIB4 AC22 VCCDA AA15 VCCIB4 AD23 VCCDA W21 VCCIB4 AE23 VCCDA N21 VCCIB4 T14 VCCDA E19 VCCIB4 U15 VCCDA C15 VCCIB4 U16 VCCDA E13 VCCIB5 AB5 VCCDA C6 VCCIB5 AC4 VCCIB0 A3 VCCIB5 AD3 VCCIB0 B3 VCCIB5 AE3 VCCIB0 C4 VCCIB5 T12 VCCIB0 D5 VCCIB5 U10 VCCIB0 J10 VCCIB5 U11 VCCIB0 J11 VCCIB6 AA4 VCCIB0 K12 VCCIB6 AB3 VCCIB1 A23 VCCIB6 AC1 VCCIB1 B23 VCCIB6 AC2 VCCIB1 C22 VCCIB6 P10 VCCIB1 D21 VCCIB6 R9 VCCIB1 J15 VCCIB6 T9 VCCIB1 J16 VCCIB7 C1 VCCIB1 K14 VCCIB7 C2 VCCIB2 C24 VCCIB7 D3 VCCIB2 C25 VCCIB7 E4 3-40 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number Bank 0 IO23PB0F2 F11 IO43NB1F4 A16 IO24NB0F2 D7 IO43PB1F4 A15 IO00NB0F0 F8 IO00PB0F0 F7 IO24PB0F2 E7 IO44NB1F4 A20 IO02NB0F0 G7 IO25PB0F2 B12 IO44PB1F4 A19 IO02PB0F0 G6 IO26NB0F2 H11 IO45NB1F4 B17 IO04NB0F0 E9 IO26PB0F2 G11 IO45PB1F4 B16 IO04PB0F0 D8 IO27NB0F2 C11 IO46NB1F4 G17 IO06NB0F0 G9 IO27PB0F2 B8 IO46PB1F4 H17 IO06PB0F0 G8 IO28NB0F2 J13 IO47NB1F4 A17 IO07PB0F0 B6 IO28PB0F2 K13 IO48NB1F4 C19 IO08NB0F0 F10 IO29NB0F2 J8 IO48PB1F4 C18 IO08PB0F0 F9 IO29PB0F2 J7 IO49NB1F4 B20 IO09PB0F0 C7 IO30NB0F2/HCLKAN G13 IO49PB1F4 B19 IO10NB0F0 H8 IO30PB0F2/HCLKAP G12 IO50NB1F4 H20 IO10PB0F0 H7 IO31NB0F2/HCLKBN C13 IO50PB1F4 H19 IO11NB0F0 D10 IO31PB0F2/HCLKBP C12 IO51NB1F4 A22 IO11PB0F0 D9 Bank 1 IO51PB1F4 A21 IO12NB0F1 B5 IO32NB1F3/HCLKCN G15 IO52NB1F4 C21 IO12PB0F1 B4 IO32PB1F3/HCLKCP G14 IO52PB1F4 C20 IO13NB0F1 A7 IO33NB1F3/HCLKDN B14 IO53NB1F4 B22 IO13PB0F1 A6 IO33PB1F3/HCLKDP B13 IO53PB1F4 B21 IO14NB0F1 C9 IO34NB1F3 G16 IO54NB1F5 J18 IO14PB0F1 C8 IO34PB1F3 H16 IO54PB1F5 J19 IO15PB0F1 B7 IO35NB1F3 C17 IO55NB1F5 D18 IO16NB0F1 A5 IO35PB1F3 B18 IO55PB1F5 D17 IO16PB0F1 A4 IO36NB1F3 H18 IO56NB1F5 F20 IO17NB0F1 A9 IO36PB1F3 H15 IO56PB1F5 F19 IO17PB0F1 B9 IO37NB1F3 H13 IO58NB1F5 E17 IO18NB0F1 D12 IO38NB1F3 E15 IO58PB1F5 F17 IO18PB0F1 D11 IO38PB1F3 F15 IO60NB1F5 D20 IO20NB0F1 B11 IO39NB1F3 D14 IO60PB1F5 D19 IO20PB0F1 B10 IO39PB1F3 C14 IO62NB1F5 E18 IO21NB0F1 A11 IO40NB1F3 D16 IO62PB1F5 F18 IO21PB0F1 A10 IO40PB1F3 D15 IO63NB1F5 G19 IO22NB0F2 H10 IO41NB1F4 F16 IO63PB1F5 G18 IO22PB0F2 H9 IO42NB1F4 G21 Bank 2 IO23NB0F2 E11 IO42PB1F4 G20 IO64NB2F6 M17 Revision 14 3-41 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number IO64PB2F6 G22 IO87NB2F8 L24 IO108NB3F10 R25 IO65NB2F6 J21 IO87PB2F8 K24 IO108PB3F10 P25 IO65PB2F6 J20 IO88NB2F8 G24 IO109NB3F10 U25 IO66NB2F6 L23 IO88PB2F8 F24 IO109PB3F10 T25 IO66PB2F6 K20 IO89NB2F8 J25 IO110NB3F10 U24 IO67NB2F6 F23 IO90NB2F8 G25 IO110PB3F10 U23 IO67PB2F6 E23 IO90PB2F8 F25 IO112NB3F10 T24 IO68NB2F6 L18 IO91NB2F8 L25 IO112PB3F10 R24 IO68PB2F6 K18 IO91PB2F8 K25 IO113NB3F10 Y25 IO70NB2F6 E24 IO92NB2F8 J24 IO113PB3F10 W25 IO70PB2F6 D24 IO92PB2F8 H24 IO114NB3F10 V23 IO71NB2F6 H23 IO93PB2F8 J23 IO114PB3F10 V24 IO71PB2F6 G23 IO94NB2F8 N24 IO116NB3F10 AA24 IO72NB2F6 L19 IO94PB2F8 M24 IO116PB3F10 Y24 IO72PB2F6 K19 IO95NB2F8 N25 IO117NB3F10 AB25 IO74NB2F7 J22 IO95PB2F8 M25 IO117PB3F10 AA25 IO74PB2F7 H22 Bank 3 IO118NB3F11 T20 IO75NB2F7 N23 IO96NB3F9 T18 IO118PB3F11 R21 IO75PB2F7 M23 IO96PB3F9 R18 IO120NB3F11 W22 IO76NB2F7 N17 IO97NB3F9 N20 IO120PB3F11 W23 IO76PB2F7 N16 IO97PB3F9 P24 IO122NB3F11 V22 IO77NB2F7 L22 IO98NB3F9 P20 IO122PB3F11 U22 IO77PB2F7 K22 IO98PB3F9 P19 IO124NB3F11 Y23 IO78NB2F7 M19 IO99NB3F9 P21 IO124PB3F11 AA23 IO78PB2F7 M18 IO100NB3F9 T22 IO126NB3F11 V21 IO79NB2F7 N19 IO100PB3F9 W24 IO126PB3F11 U21 IO79PB2F7 N18 IO101NB3F9 R22 IO128NB3F11 Y22 IO80NB2F7 L21 IO101PB3F9 P22 IO128PB3F11 Y21 IO80PB2F7 L20 IO102NB3F9 U19 Bank 4 IO82NB2F7 P18 IO102PB3F9 T19 IO129NB4F12 W20 IO82PB2F7 P17 IO104NB3F9 V20 IO129PB4F12 Y20 IO83NB2F7 N22 IO104PB3F9 U20 IO131NB4F12 V19 IO83PB2F7 M22 IO105NB3F9 R23 IO131PB4F12 W19 IO84NB2F7 M20 IO105PB3F9 P23 IO133NB4F12 Y18 IO84PB2F7 M21 IO106NB3F9 R19 IO133PB4F12 Y19 IO86NB2F8 E25 IO106PB3F9 R20 IO135NB4F12 W18 IO86PB2F8 D25 IO107NB3F10 AB24 IO135PB4F12 V18 3-42 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number IO137NB4F12 Y17 IO157PB4F14 AC18 IO178PB5F16 W6 IO137PB4F12 AA17 IO158NB4F14 AC15 IO179NB5F16 Y10 IO138NB4F12 AB19 IO158PB4F14 AC19 IO179PB5F16 W10 IO138PB4F12 AB18 IO159NB4F14/CLKEN W14 IO180NB5F16 Y7 IO139NB4F13 AA19 IO159PB4F14/CLKEP W15 IO180PB5F16 W7 IO139PB4F13 U18 IO160NB4F14/CLKFN AC13 IO181NB5F17 AD9 IO140NB4F13 AC20 IO160PB4F14/CLKFP AD13 IO181PB5F17 AD10 IO140PB4F13 AC21 Bank 5 IO182NB5F17 AE10 IO141NB4F13 AD17 IO161NB5F15/CLKGN W13 IO182PB5F17 AE11 IO141PB4F13 AD18 IO161PB5F15/CLKGP Y13 IO183NB5F17 AD7 IO142NB4F13 AD21 IO162NB5F15/CLKHN AC12 IO183PB5F17 AD8 IO142PB4F13 AD22 IO162PB5F15/CLKHP AD12 IO184NB5F17 AB9 IO143NB4F13 AB17 IO163NB5F15 V9 IO185NB5F17 AE6 IO143PB4F13 AC17 IO163PB5F15 V10 IO185PB5F17 AE7 IO144PB4F13 AE22 IO164NB5F15 V11 IO186NB5F17 AE4 IO145NB4F13 AE15 IO164PB5F15 T13 IO186PB5F17 AE5 IO145PB4F13 AE16 IO165NB5F15 U13 IO187NB5F17 AA9 IO146NB4F13 AD19 IO165PB5F15 V13 IO187PB5F17 Y9 IO146PB4F13 AD20 IO167NB5F15 W11 IO188NB5F17 U8 IO147NB4F13 AD15 IO167PB5F15 W12 IO189NB5F17 AD5 IO147PB4F13 AD16 IO168NB5F15 AB6 IO189PB5F17 AD6 IO148PB4F13 AE21 IO168PB5F15 AA6 IO191NB5F17 AC5 IO149NB4F13 AD14 IO169NB5F15 V8 IO191PB5F17 AC6 IO149PB4F13 AC14 IO169PB5F15 V7 IO192NB5F17 AB7 IO150NB4F13 AE19 IO171NB5F16 W8 IO192PB5F17 AC7 IO150PB4F13 AE20 IO171PB5F16 W9 Bank 6 IO151NB4F13 V17 IO172NB5F16 AB8 IO193NB6F18 U6 IO151PB4F13 W17 IO172PB5F16 AC8 IO193PB6F18 U5 IO152NB4F14 AB16 IO173NB5F16 AA11 IO194NB6F18 Y3 IO152PB4F14 W16 IO173PB5F16 Y11 IO194PB6F18 AA3 IO153NB4F14 Y15 IO174NB5F16 AB10 IO195NB6F18 V6 IO153PB4F14 Y16 IO174PB5F16 AB11 IO195PB6F18 W4 IO155NB4F14 V15 IO175NB5F16 AC9 IO197NB6F18 R5 IO155PB4F14 V16 IO175PB5F16 AE9 IO197PB6F18 U3 IO156NB4F14 AB14 IO177NB5F16 AA8 IO198NB6F18 P6 IO156PB4F14 AB15 IO177PB5F16 Y8 IO199NB6F18 Y5 IO157NB4F14 AE14 IO178NB5F16 Y6 IO199PB6F18 W5 Revision 14 3-43 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number IO200NB6F18 V3 IO221PB6F20 P4 IO244NB7F22 P9 IO200PB6F18 W3 IO223NB6F20 M2 IO244PB7F22 N6 IO201NB6F18 T7 IO223PB6F20 N2 IO245NB7F22 K8 IO201PB6F18 U7 IO224NB6F20 N3 IO245PB7F22 L8 IO202NB6F18 V2 IO224PB6F20 P3 IO246NB7F22 F3 IO203NB6F19 W2 Bank 7 IO246PB7F22 E3 IO203PB6F19 Y2 IO225NB7F21 J2 IO247NB7F23 K7 IO204NB6F19 AA1 IO225PB7F21 J1 IO247PB7F23 K6 IO204PB6F19 AB1 IO226PB7F21 G2 IO248NB7F23 D2 IO205NB6F19 R6 IO227NB7F21 H3 IO249NB7F23 G4 IO205PB6F19 T6 IO227PB7F21 H2 IO249PB7F23 G3 IO206NB6F19 W1 IO229NB7F21 K2 IO251NB7F23 N10 IO206PB6F19 Y1 IO229PB7F21 L2 IO251PB7F23 N9 IO207NB6F19 T2 IO230NB7F21 K1 IO253NB7F23 H4 IO207PB6F19 U2 IO230PB7F21 L1 IO253PB7F23 J4 IO208NB6F19 T1 IO231NB7F21 E2 IO255NB7F23 J6 IO208PB6F19 U1 IO231PB7F21 F2 IO255PB7F23 J5 IO209NB6F19 AA2 IO232NB7F21 F1 IO257NB7F23 H5 IO209PB6F19 AB2 IO232PB7F21 G1 IO257PB7F23 H6 IO210NB6F19 P5 IO233NB7F21 L3 Dedicated I/O IO211NB6F19 M1 IO233PB7F21 M3 GND K5 IO211PB6F19 N1 IO234NB7F21 D1 GND A18 IO212NB6F19 P1 IO234PB7F21 E1 GND A2 IO212PB6F19 R1 IO235NB7F21 K4 GND A24 IO213NB6F19 R8 IO235PB7F21 L4 GND A25 IO213PB6F19 T8 IO236NB7F22 M6 GND A8 IO215NB6F20 U4 IO237NB7F22 N8 GND AA10 IO215PB6F20 V4 IO237PB7F22 N7 GND AA16 IO216NB6F20 P8 IO238NB7F22 M5 GND AA18 IO216PB6F20 R3 IO239NB7F22 L6 GND AA21 IO217NB6F20 P7 IO239PB7F22 L5 GND AA5 IO217PB6F20 R7 IO240NB7F22 M4 GND AB22 IO219NB6F20 R4 IO241NB7F22 L7 GND AB4 IO219PB6F20 T4 IO241PB7F22 M7 GND AC10 IO220NB6F20 P2 IO242NB7F22 J3 GND AC16 IO220PB6F20 R2 IO243NB7F22 M9 GND AC23 IO221NB6F20 N4 IO243PB7F22 M8 GND AC3 3-44 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number GND AD1 GND M12 NC F21 GND AD2 GND M13 NC G10 GND AD24 GND M14 NC H12 GND AD25 GND M15 NC H14 GND AE1 GND N11 NC J12 GND AE18 GND N12 NC J14 GND AE2 GND N13 NC U12 GND AE24 GND N14 NC U14 GND AE25 GND N15 NC V12 GND AE8 GND P11 NC V14 GND B1 GND P12 NC Y12 GND B2 GND P13 NC Y14 GND B24 GND P14 PRA F13 GND B25 GND P15 PRB A13 GND C10 GND R11 PRC AB12 GND C16 GND R12 PRD AE13 GND C23 GND R13 TCK F5 GND C3 GND R14 TDI C5 GND D22 GND R15 TDO F6 GND D4 GND T21 TMS D6 GND E10 GND T23 TRST E6 GND E16 GND T3 VCCA AB20 GND E21 GND T5 VCCA F22 GND E5 GND V1 VCCA F4 GND E8 GND V25 VCCA J17 GND H1 GND V5 VCCA J9 GND H21 NC A14 VCCA K10 GND H25 NC AA12 VCCA K11 GND K21 NC AA14 VCCA K15 GND K23 NC AA20 VCCA K16 GND K3 NC AB13 VCCA L10 GND L11 NC AD4 VCCA L16 GND L12 NC AE12 VCCA R10 GND L13 NC E12 VCCA R16 GND L14 NC E14 VCCA T10 GND L15 NC F12 VCCA T11 GND M11 NC F14 VCCA T15 Revision 14 3-45 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX1000S/SL Function Number RTAX1000S/SL Function Number RTAX1000S/SL Function Number VCCA T16 VCCIB2 D23 VCCIB7 K9 VCCA U17 VCCIB2 E22 VCCIB7 L9 VCCA U9 VCCIB2 K17 VCCIB7 M10 VCCA Y4 VCCIB2 L17 VPUMP E20 VCCDA A12 VCCIB2 M16 VCCDA AA13 VCCIB3 AA22 VCCDA AA15 VCCIB3 AB23 VCCDA AA7 VCCIB3 AC24 VCCDA AC11 VCCIB3 AC25 VCCDA AD11 VCCIB3 P16 VCCDA AE17 VCCIB3 R17 VCCDA B15 VCCIB3 T17 VCCDA C15 VCCIB4 AB21 VCCDA C6 VCCIB4 AC22 VCCDA D13 VCCIB4 AD23 VCCDA E13 VCCIB4 AE23 VCCDA E19 VCCIB4 T14 VCCDA G5 VCCIB4 U15 VCCDA N21 VCCIB4 U16 VCCDA N5 VCCIB5 AB5 VCCDA W21 VCCIB5 AC4 VCCIB0 A3 VCCIB5 AD3 VCCIB0 B3 VCCIB5 AE3 VCCIB0 C4 VCCIB5 T12 VCCIB0 D5 VCCIB5 U10 VCCIB0 J10 VCCIB5 U11 VCCIB0 J11 VCCIB6 AA4 VCCIB0 K12 VCCIB6 AB3 VCCIB1 A23 VCCIB6 AC1 VCCIB1 B23 VCCIB6 AC2 VCCIB1 C22 VCCIB6 P10 VCCIB1 D21 VCCIB6 R9 VCCIB1 J15 VCCIB6 T9 VCCIB1 J16 VCCIB7 C1 VCCIB1 K14 VCCIB7 C2 VCCIB2 C24 VCCIB7 D3 VCCIB2 C25 VCCIB7 E4 3-46 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number Bank 0 IO30PB0F2 B10 IO58PB1F5 A21 IO31NB0F2 E11 IO59NB1F5 F16 IO00NB0F0 D7 IO00PB0F0 E7 IO31PB0F2 F11 IO61NB1F5 G17 IO01NB0F0 G7 IO33NB0F2 D12 IO61PB1F5 H17 IO01PB0F0 G6 IO33PB0F2 D11 IO62NB1F5 B17 IO02NB0F0 B5 IO34NB0F3 A11 IO62PB1F5 B16 IO02PB0F0 B4 IO34PB0F3 A10 IO63NB1F5 H18 IO04PB0F0 C7 IO37NB0F3 J13 IO65NB1F6 C17 IO05NB0F0 F8 IO37PB0F3 K13 IO66PB1F6 B18 IO05PB0F0 F7 IO38NB0F3 H11 IO67NB1F6 J18 IO06NB0F0 H8 IO38PB0F3 G11 IO67PB1F6 J19 IO06PB0F0 H7 IO40PB0F3 B12 IO68NB1F6 B20 IO11NB0F0 J8 IO41NB0F3/HCLKAN G13 IO68PB1F6 B19 IO11PB0F0 J7 IO41PB0F3/HCLKAP G12 IO69NB1F6 E17 IO12PB0F1 B6 IO42NB0F3/HCLKBN C13 IO69PB1F6 F17 IO13NB0F1 E9 IO42PB0F3/HCLKBP C12 IO70NB1F6 B22 IO13PB0F1 D8 Bank 1 IO70PB1F6 B21 IO15NB0F1 C9 IO43NB1F4/HCLKCN G15 IO71PB1F6 G18 IO15PB0F1 C8 IO43PB1F4/HCLKCP G14 IO73NB1F6 G19 IO16NB0F1 A5 IO44NB1F4/HCLKDN B14 IO74NB1F6 C19 IO16PB0F1 A4 IO44PB1F4/HCLKDP B13 IO74PB1F6 C18 IO17NB0F1 D10 IO45NB1F4 H13 IO75NB1F6 D18 IO17PB0F1 D9 IO47NB1F4 D14 IO75PB1F6 D17 IO18NB0F1 A7 IO47PB1F4 C14 IO76NB1F7 C21 IO18PB0F1 A6 IO48NB1F4 A16 IO76PB1F7 C20 IO19NB0F1 G9 IO48PB1F4 A15 IO79NB1F7 H20 IO19PB0F1 G8 IO49PB1F4 H15 IO79PB1F7 H19 IO20PB0F1 B7 IO51NB1F4 E15 IO80NB1F7 E18 IO23NB0F2 F10 IO51PB1F4 F15 IO80PB1F7 F18 IO23PB0F2 F9 IO52NB1F4 A17 IO81NB1F7 G21 IO26NB0F2 C11 IO55NB1F5 G16 IO81PB1F7 G20 IO26PB0F2 B8 IO55PB1F5 H16 IO82NB1F7 F20 IO27NB0F2 H10 IO56NB1F5 A20 IO82PB1F7 F19 IO27PB0F2 H9 IO56PB1F5 A19 IO85NB1F7 D20 IO28NB0F2 A9 IO57NB1F5 D16 IO85PB1F7 D19 IO28PB0F2 B9 IO57PB1F5 D15 Bank 2 IO30NB0F2 B11 IO58NB1F5 A22 IO86NB2F8 F23 Revision 14 3-47 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO86PB2F8 E23 IO115PB2F10 M21 IO148PB3F13 T25 IO87NB2F8 H23 IO117NB2F10 N19 IO149NB3F13 T22 IO87PB2F8 G23 IO117PB2F10 N18 IO153NB3F14 U19 IO88NB2F8 E24 IO118NB2F11 J25 IO153PB3F14 T19 IO88PB2F8 D24 IO121NB2F11 N24 IO154NB3F14 Y25 IO89NB2F8 M17 IO121PB2F11 M24 IO154PB3F14 W25 IO89PB2F8 G22 IO122NB2F11 L25 IO157NB3F14 V20 IO91NB2F8 J22 IO122PB2F11 K25 IO157PB3F14 U20 IO91PB2F8 H22 IO123NB2F11 N22 IO158NB3F14 AB25 IO92NB2F8 L18 IO123PB2F11 M22 IO158PB3F14 AA25 IO92PB2F8 K18 IO124NB2F11 N23 IO160PB3F14 W24 IO96NB2F9 G24 IO124PB2F11 M23 IO161NB3F15 U24 IO96PB2F9 F24 IO127NB2F11 P18 IO161PB3F15 U23 IO97NB2F9 J21 IO127PB2F11 P17 IO162NB3F15 AA24 IO97PB2F9 J20 IO128NB2F11 N25 IO162PB3F15 Y24 IO98PB2F9 J23 IO128PB2F11 M25 IO163NB3F15 V22 IO99NB2F9 L19 Bank 3 IO163PB3F15 U22 IO99PB2F9 K19 IO129NB3F12 N20 IO164NB3F15 V23 IO100NB2F9 E25 IO130PB3F12 P24 IO164PB3F15 V24 IO100PB2F9 D25 IO131NB3F12 P21 IO166NB3F15 AB24 IO103PB2F9 K20 IO133NB3F12 P20 IO167NB3F15 V21 IO105NB2F9 M19 IO133PB3F12 P19 IO167PB3F15 U21 IO105PB2F9 M18 IO138NB3F12 R23 IO168NB3F15 Y23 IO106NB2F9 J24 IO138PB3F12 P23 IO168PB3F15 AA23 IO106PB2F9 H24 IO139NB3F13 R22 IO169NB3F15 W22 IO107NB2F10 L23 IO139PB3F13 P22 IO169PB3F15 W23 IO107PB2F10 N16 IO141NB3F13 R19 IO170NB3F15 Y22 IO109NB2F10 L22 IO142NB3F13 R25 IO170PB3F15 Y21 IO109PB2F10 K22 IO142PB3F13 P25 Bank 4 IO110NB2F10 G25 IO143PB3F13 R21 IO171NB4F16 AC20 IO110PB2F10 F25 IO145NB3F13 T18 IO171PB4F16 AC21 IO111NB2F10 L21 IO145PB3F13 R18 IO172NB4F16 W20 IO111PB2F10 L20 IO146NB3F13 T24 IO172PB4F16 Y20 IO112NB2F10 L24 IO146PB3F13 R24 IO173NB4F16 AD21 IO112PB2F10 K24 IO147NB3F13 T20 IO173PB4F16 AD22 IO113NB2F10 N17 IO147PB3F13 R20 IO174NB4F16 AA19 IO115NB2F10 M20 IO148NB3F13 U25 IO176NB4F16 Y18 3-48 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO176PB4F16 Y19 IO210PB4F19 V16 IO238PB5F22 W9 IO177NB4F16 AB19 IO211NB4F19 AD14 IO239NB5F22 AE4 IO177PB4F16 AB18 IO211PB4F19 AC14 IO239PB5F22 AE5 IO182NB4F17 V19 IO212NB4F19/CLKEN W14 IO240NB5F22 AB9 IO182PB4F17 W19 IO212PB4F19/CLKEP W15 IO242NB5F22 AA9 IO183PB4F17 AC19 IO213NB4F19/CLKFN AC13 IO242PB5F22 Y9 IO184NB4F17 AB17 IO213PB4F19/CLKFP AD13 IO243NB5F22 AD5 IO184PB4F17 AC17 Bank 5 IO243PB5F22 AD6 IO185NB4F17 AD19 IO214NB5F20/CLKGN W13 IO244NB5F22 U8 IO185PB4F17 AD20 IO214PB5F20/CLKGP Y13 IO246NB5F23 AB8 IO187PB4F17 AC18 IO215NB5F20/CLKHN AC12 IO246PB5F23 AC8 IO188NB4F17 Y17 IO215PB5F20/CLKHP AD12 IO247NB5F23 AB7 IO188PB4F17 AA17 IO216NB5F20 U13 IO247PB5F23 AC7 IO189PB4F17 AE22 IO216PB5F20 V13 IO250NB5F23 AA8 IO191NB4F17 W18 IO217NB5F20 AE10 IO250PB5F23 Y8 IO191PB4F17 V18 IO217PB5F20 AE11 IO251NB5F23 V8 IO192PB4F17 U18 IO218NB5F20 W11 IO251PB5F23 V7 IO195PB4F18 AE21 IO218PB5F20 W12 IO252NB5F23 Y7 IO196NB4F18 AB16 IO222NB5F20 AA11 IO252PB5F23 W7 IO197NB4F18 AD17 IO222PB5F20 Y11 IO253NB5F23 AC5 IO197PB4F18 AD18 IO223PB5F21 AE9 IO253PB5F23 AC6 IO198NB4F18 V17 IO225NB5F21 AE6 IO254NB5F23 Y6 IO198PB4F18 W17 IO225PB5F21 AE7 IO254PB5F23 W6 IO199NB4F18 AE19 IO226NB5F21 Y10 IO256NB5F23 AB6 IO199PB4F18 AE20 IO226PB5F21 W10 IO256PB5F23 AA6 IO200NB4F18 AC15 IO227PB5F21 T13 Bank 6 IO201NB4F18 AD15 IO228NB5F21 AB10 IO257NB6F24 Y3 IO201PB4F18 AD16 IO228PB5F21 AB11 IO257PB6F24 AA3 IO202NB4F18 Y15 IO229NB5F21 AD9 IO258NB6F24 V3 IO202PB4F18 Y16 IO229PB5F21 AD10 IO258PB6F24 W3 IO206NB4F19 AB14 IO230NB5F21 V11 IO259NB6F24 AA2 IO206PB4F19 AB15 IO233NB5F21 AD7 IO259PB6F24 AB2 IO207NB4F19 AE15 IO233PB5F21 AD8 IO260NB6F24 V6 IO207PB4F19 AE16 IO234NB5F21 V9 IO260PB6F24 W4 IO208PB4F19 W16 IO234PB5F21 V10 IO262NB6F24 U4 IO209NB4F19 AE14 IO236NB5F22 AC9 IO262PB6F24 V4 IO210NB4F19 V15 IO238NB5F22 W8 IO263NB6F24 Y5 Revision 14 3-49 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO263PB6F24 W5 IO296PB6F27 P3 IO329PB7F30 E1 IO268NB6F25 U6 IO298NB6F27 N4 IO331PB7F30 G2 IO268PB6F25 U5 IO298PB6F27 P4 IO332NB7F31 H3 IO269PB6F25 U3 IO299NB6F27 M2 IO332PB7F31 H2 IO272NB6F25 T2 IO299PB6F27 N2 IO333NB7F31 E2 IO272PB6F25 U2 Bank 7 IO333PB7F31 F2 IO273NB6F25 W2 IO300NB7F28 P9 IO334NB7F31 H4 IO273PB6F25 Y2 IO300PB7F28 N6 IO334PB7F31 J4 IO274NB6F25 R6 IO302NB7F28 M6 IO335NB7F31 H5 IO274PB6F25 T6 IO304NB7F28 N8 IO335PB7F31 H6 IO275NB6F25 T7 IO304PB7F28 N7 IO337NB7F31 D2 IO275PB6F25 U7 IO308NB7F28 M4 IO338NB7F31 J6 IO277NB6F25 V2 IO309NB7F28 L3 IO338PB7F31 J5 IO278NB6F26 R4 IO309PB7F28 M3 IO339NB7F31 F3 IO278PB6F26 T4 IO310NB7F29 N10 IO339PB7F31 E3 IO279PB6F26 R3 IO310PB7F29 N9 IO340NB7F31 G4 IO280NB6F26 R5 IO311NB7F29 K1 IO340PB7F31 G3 IO281NB6F26 AA1 IO311PB7F29 L1 IO341NB7F31 K8 IO281PB6F26 AB1 IO313NB7F29 M5 IO341PB7F31 L8 IO284NB6F26 R8 IO316NB7F29 L6 Dedicated I/O IO284PB6F26 T8 IO316PB7F29 L5 GND K5 IO285NB6F26 W1 IO317NB7F29 K2 GND A18 IO285PB6F26 Y1 IO317PB7F29 L2 GND A2 IO286NB6F26 P2 IO318NB7F29 K4 GND A24 IO286PB6F26 R2 IO318PB7F29 L4 GND A25 IO287NB6F26 T1 IO320NB7F29 J3 GND A8 IO287PB6F26 U1 IO321NB7F30 J2 GND AA10 IO288NB6F26 P5 IO321PB7F30 J1 GND AA16 IO290NB6F27 P6 IO323NB7F30 L7 GND AA18 IO291NB6F27 P1 IO323PB7F30 M7 GND AA21 IO291PB6F27 R1 IO324NB7F30 M9 GND AA5 IO292NB6F27 P7 IO324PB7F30 M8 GND AB22 IO292PB6F27 R7 IO327NB7F30 F1 GND AB4 IO293NB6F27 M1 IO327PB7F30 G1 GND AC10 IO293PB6F27 N1 IO328NB7F30 K7 GND AC16 IO294NB6F27 P8 IO328PB7F30 K6 GND AC23 IO296NB6F27 N3 IO329NB7F30 D1 GND AC3 3-50 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number GND AD1 GND M12 NC U14 GND AD2 GND M13 NC V12 GND AD24 GND M14 NC V14 GND AD25 GND M15 NC Y12 GND AE1 GND N11 NC Y14 GND AE18 GND N12 PRA F13 GND AE2 GND N13 PRB A13 GND AE24 GND N14 PRC AB12 GND AE25 GND N15 PRD AE13 GND AE8 GND P11 TCK F5 GND B1 GND P12 TDI C5 GND B2 GND P13 TDO F6 GND B24 GND P14 TMS D6 GND B25 GND P15 TRST E6 GND C10 GND R11 VCCA AB20 GND C16 GND R12 VCCA F22 GND C23 GND R13 VCCA F4 GND C3 GND R14 VCCA J17 GND D22 GND R15 VCCA J9 GND D4 GND T21 VCCA K10 GND E10 GND T23 VCCA K11 GND E16 GND T3 VCCA K15 GND E21 GND T5 VCCA K16 GND E5 GND V1 VCCA L10 GND E8 GND V25 VCCA L16 GND H1 GND V5 VCCA R10 GND H21 NC AA12 VCCA R16 GND H25 NC AA14 VCCA T10 GND K21 NC E12 VCCA T11 GND K23 NC E14 VCCA T15 GND K3 NC F12 VCCA T16 GND L11 NC F14 VCCA U17 GND L12 NC H12 VCCA U9 GND L13 NC H14 VCCA Y4 GND L14 NC J12 VCCDA A12 GND L15 NC J14 VCCDA A14 GND M11 NC U12 VCCDA AA13 Revision 14 3-51 Package Pin Assignments CG624/LG624 CG624/LG624 CG624/LG624 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number VCCDA AA15 VCCIB2 D23 VCCIB7 K9 VCCDA AA20 VCCIB2 E22 VCCIB7 L9 VCCDA AA7 VCCIB2 K17 VCCIB7 M10 VCCDA AB13 VCCIB2 L17 VPUMP E20 VCCDA AC11 VCCIB2 M16 VCCDA AD11 VCCIB3 AA22 VCCDA AD4 VCCIB3 AB23 VCCDA AE12 VCCIB3 AC24 VCCDA AE17 VCCIB3 AC25 VCCDA B15 VCCIB3 P16 VCCDA C15 VCCIB3 R17 VCCDA C6 VCCIB3 T17 VCCDA D13 VCCIB4 AB21 VCCDA E13 VCCIB4 AC22 VCCDA E19 VCCIB4 AD23 VCCDA F21 VCCIB4 AE23 VCCDA G10 VCCIB4 T14 VCCDA G5 VCCIB4 U15 VCCDA N21 VCCIB4 U16 VCCDA N5 VCCIB5 AB5 VCCDA W21 VCCIB5 AC4 VCCIB0 A3 VCCIB5 AD3 VCCIB0 B3 VCCIB5 AE3 VCCIB0 C4 VCCIB5 T12 VCCIB0 D5 VCCIB5 U10 VCCIB0 J10 VCCIB5 U11 VCCIB0 J11 VCCIB6 AA4 VCCIB0 K12 VCCIB6 AB3 VCCIB1 A23 VCCIB6 AC1 VCCIB1 B23 VCCIB6 AC2 VCCIB1 C22 VCCIB6 P10 VCCIB1 D21 VCCIB6 R9 VCCIB1 J15 VCCIB6 T9 VCCIB1 J16 VCCIB7 C1 VCCIB1 K14 VCCIB7 C2 VCCIB2 C24 VCCIB7 D3 VCCIB2 C25 VCCIB7 E4 3-52 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 14 3-53 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number Bank 0 IO18NB0F1 E11 IO36PB0F3 A16 IO18PB0F1 E10 IO37NB0F3 G16 IO00NB0F0 D6 IO00PB0F0 C6 IO19NB0F1 F13 IO37PB0F3 G15 IO01NB0F0 H10 IO19PB0F1 G13 IO38NB0F3 D16 IO01PB0F0 H9 IO20NB0F1 A10 IO38PB0F3 C16 IO02NB0F0 F8 IO20PB0F1 A9 IO39NB0F3 K16 IO02PB0F0 G8 IO21NB0F1 K14 IO39PB0F3 L16 IO03NB0F0 A6 IO21PB0F1 K13 IO40NB0F3 D17 IO03PB0F0 B6 IO22NB0F2 B11 IO40PB0F3 C17 IO04NB0F0 C7 IO22PB0F2 B10 IO41NB0F3/HCLKAN E16 IO04PB0F0 D7 IO23NB0F2 C12 IO41PB0F3/HCLKAP F16 IO05NB0F0 K10 IO23PB0F2 C11 IO42NB0F3/HCLKBN G17 IO05PB0F0 J10 IO24NB0F2 A12 IO42PB0F3/HCLKBP F17 IO06NB0F0 F9 IO24PB0F2 A11 Bank 1 IO06PB0F0 G9 IO25NB0F2 H14 IO43NB1F4/HCLKCN G19 IO07NB0F0 F10 IO25PB0F2 J14 IO43PB1F4/HCLKCP G18 IO07PB0F0 G10 IO26NB0F2 D13 IO44NB1F4/HCLKDN E19 IO08NB0F0 E9 IO26PB0F2 D12 IO44PB1F4/HCLKDP F19 IO08PB0F0 E8 IO27NB0F2 F14 IO45NB1F4 C18 IO09NB0F0 J11 IO27PB0F2 G14 IO45PB1F4 D18 IO09PB0F0 K11 IO28NB0F2 E14 IO46NB1F4 A18 IO10NB0F0 C8 IO28PB0F2 E13 IO46PB1F4 B18 IO10PB0F0 D8 IO29NB0F2 B13 IO47NB1F4 K19 IO11NB0F0 K12 IO29PB0F2 B12 IO47PB1F4 L19 IO11PB0F0 J12 IO30NB0F2 C14 IO48NB1F4 C19 IO12NB0F1 G11 IO30PB0F2 C13 IO48PB1F4 D19 IO12PB0F1 H11 IO31NB0F2 H15 IO49NB1F4 K20 IO13NB0F1 G12 IO31PB0F2 J15 IO49PB1F4 L20 IO13PB0F1 H12 IO32NB0F2 A14 IO50NB1F4 A19 IO14NB0F1 A7 IO32PB0F2 B14 IO50PB1F4 B19 IO14PB0F1 B7 IO33NB0F2 K15 IO51NB1F4 H20 IO15NB0F1 H13 IO33PB0F2 L15 IO51PB1F4 J20 IO15PB0F1 J13 IO34NB0F3 D15 IO52NB1F4 B20 IO16NB0F1 C9 IO34PB0F3 D14 IO52PB1F4 A20 IO16PB0F1 D9 IO35NB0F3 A15 IO53NB1F4 F20 IO17NB0F1 F12 IO35PB0F3 B15 IO53PB1F4 E20 IO17PB0F1 F11 IO36NB0F3 B16 IO54NB1F5 B21 3-54 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO54PB1F5 A21 IO73NB1F6 E26 IO91NB2F8 K28 IO55NB1F5 K21 IO73PB1F6 E25 IO91PB2F8 K27 IO55PB1F5 J21 IO74NB1F6 F26 IO92NB2F8 J30 IO56NB1F5 D21 IO74PB1F6 F25 IO92PB2F8 H30 IO56PB1F5 C21 IO75NB1F6 K25 IO93NB2F8 L28 IO57NB1F5 G22 IO75PB1F6 K24 IO93PB2F8 L27 IO57PB1F5 G21 IO76NB1F7 D27 IO94NB2F8 K29 IO58NB1F5 E22 IO76PB1F7 D26 IO94PB2F8 J29 IO58PB1F5 E21 IO77NB1F7 B29 IO95NB2F8 K31 IO59NB1F5 D22 IO77PB1F7 A29 IO95PB2F8 J31 IO59PB1F5 C22 IO78NB1F7 D28 IO96NB2F9 J32 IO60NB1F5 B23 IO78PB1F7 C28 IO96PB2F9 H32 IO60PB1F5 A23 IO79NB1F7 H25 IO97NB2F9 M27 IO61NB1F5 H22 IO79PB1F7 G25 IO97PB2F9 M26 IO61PB1F5 H21 IO80NB1F7 F27 IO98NB2F9 L30 IO62NB1F5 C24 IO80PB1F7 E27 IO98PB2F9 K30 IO62PB1F5 C23 IO81NB1F7 J25 IO99NB2F9 N25 IO63NB1F5 F23 IO81PB1F7 J24 IO99PB2F9 N26 IO63PB1F5 F22 IO82NB1F7 D29 IO100NB2F9 M29 IO64NB1F6 B24 IO82PB1F7 C29 IO100PB2F9 L29 IO64PB1F6 A24 IO83NB1F7 H26 IO101NB2F9 L33 IO65NB1F6 J22 IO83PB1F7 G26 IO101PB2F9 L32 IO65PB1F6 K22 IO84NB1F7 F28 IO102NB2F9 K34 IO66NB1F6 B25 IO84PB1F7 E28 IO102PB2F9 K33 IO66PB1F6 A25 IO85NB1F7 H27 IO103NB2F9 N28 IO67NB1F6 K23 IO85PB1F7 G27 IO103PB2F9 M28 IO67PB1F6 J23 Bank 2 IO104NB2F9 M34 IO68NB1F6 F24 IO86NB2F8 J28 IO104PB2F9 L34 IO68PB1F6 E24 IO86PB2F8 J27 IO105NB2F9 P27 IO69NB1F6 C27 IO87NB2F8 M25 IO105PB2F9 N27 IO69PB1F6 C26 IO87PB2F8 L25 IO106NB2F9 M32 IO70NB1F6 H24 IO88NB2F8 L26 IO106PB2F9 M31 IO70PB1F6 G24 IO88PB2F8 K26 IO107NB2F10 P25 IO71NB1F6 H23 IO89NB2F8 G31 IO107PB2F10 P26 IO71PB1F6 G23 IO89PB2F8 F31 IO108NB2F10 N33 IO72NB1F6 B28 IO90NB2F8 H29 IO108PB2F10 M33 IO72PB1F6 A28 IO90PB2F8 G29 IO109NB2F10 P29 Revision 14 3-55 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO109PB2F10 N29 IO128NB2F11 U31 IO146NB3F13 AA29 IO110NB2F10 P30 IO128PB2F11 U32 IO146PB3F13 AA30 IO110PB2F10 N30 Bank 3 IO147NB3F13 AB30 IO111NB2F10 R24 IO129NB3F12 V29 IO147PB3F13 AB29 IO111PB2F10 R25 IO129PB3F12 U29 IO148NB3F13 AB32 IO112NB2F10 P31 IO130NB3F12 V31 IO148PB3F13 AA32 IO112PB2F10 N31 IO130PB3F12 V32 IO149NB3F13 AB27 IO113NB2F10 R28 IO131NB3F12 V24 IO149PB3F13 AA27 IO113PB2F10 P28 IO131PB3F12 V25 IO150NB3F14 AC31 IO114NB2F10 P32 IO132NB3F12 W28 IO150PB3F14 AB31 IO114PB2F10 N32 IO132PB3F12 V28 IO151NB3F14 AD33 IO115NB2F10 R30 IO133NB3F12 W26 IO151PB3F14 AC33 IO115PB2F10 R29 IO133PB3F12 V26 IO152NB3F14 AC28 IO116NB2F10 P34 IO134NB3F12 W33 IO152PB3F14 AB28 IO116PB2F10 P33 IO134PB3F12 V33 IO153NB3F14 AB25 IO117NB2F10 R27 IO135NB3F12 W25 IO153PB3F14 AA25 IO117PB2F10 R26 IO135PB3F12 W24 IO154NB3F14 AD32 IO118NB2F11 R34 IO136NB3F12 W31 IO154PB3F14 AC32 IO118PB2F11 R33 IO136PB3F12 W32 IO155NB3F14 AD29 IO119NB2F11 T24 IO137NB3F12 Y30 IO155PB3F14 AC29 IO119PB2F11 T25 IO137PB3F12 W30 IO156NB3F14 AE30 IO120NB2F11 T33 IO138NB3F12 Y29 IO156PB3F14 AD30 IO120PB2F11 T34 IO138PB3F12 W29 IO157NB3F14 AC26 IO121NB2F11 T27 IO139NB3F13 Y27 IO157PB3F14 AB26 IO121PB2F11 T26 IO139PB3F13 W27 IO158NB3F14 AH33 IO122NB2F11 T30 IO140NB3F13 AA33 IO158PB3F14 AG33 IO122PB2F11 T29 IO140PB3F13 Y33 IO159NB3F14 AD27 IO123NB2F11 U28 IO141NB3F13 Y25 IO159PB3F14 AC27 IO123PB2F11 T28 IO141PB3F13 Y24 IO160NB3F14 AG32 IO124NB2F11 T31 IO142NB3F13 AA31 IO160PB3F14 AF32 IO124PB2F11 T32 IO142PB3F13 Y31 IO161NB3F15 AG31 IO125NB2F11 U24 IO143NB3F13 AA28 IO161PB3F15 AF31 IO125PB2F11 U25 IO143PB3F13 Y28 IO162NB3F15 AF29 IO126NB2F11 U33 IO144NB3F13 AA34 IO162PB3F15 AE29 IO126PB2F11 U34 IO144PB3F13 Y34 IO163NB3F15 AE28 IO127NB2F11 U26 IO145NB3F13 AA26 IO163PB3F15 AD28 IO127PB2F11 U27 IO145PB3F13 Y26 IO164NB3F15 AG30 3-56 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO164PB3F15 AF30 IO182PB4F17 AE24 IO201NB4F18 AM21 IO165NB3F15 AE26 IO183NB4F17 AH24 IO201PB4F18 AL21 IO165PB3F15 AD26 IO183PB4F17 AH25 IO202NB4F18 AE20 IO166NB3F15 AJ30 IO184NB4F17 AG23 IO202PB4F18 AD20 IO166PB3F15 AH30 IO184PB4F17 AG24 IO203NB4F19 AN21 IO167NB3F15 AG28 IO185NB4F17 AL25 IO203PB4F19 AP21 IO167PB3F15 AF28 IO185PB4F17 AL26 IO204NB4F19 AP20 IO168NB3F15 AF27 IO186NB4F17 AP25 IO204PB4F19 AN20 IO168PB3F15 AE27 IO186PB4F17 AP26 IO205NB4F19 AN19 IO169NB3F15 AH29 IO187NB4F17 AK24 IO205PB4F19 AP19 IO169PB3F15 AG29 IO187PB4F17 AK25 IO206NB4F19 AG20 IO170NB3F15 AD25 IO188NB4F17 AF23 IO206PB4F19 AF20 IO170PB3F15 AC25 IO188PB4F17 AE23 IO207NB4F19 AL19 Bank 4 IO189NB4F17 AN24 IO207PB4F19 AL20 IO171NB4F16 AP29 IO189PB4F17 AM24 IO208NB4F19 AG19 IO171PB4F16 AN29 IO190NB4F17 AH22 IO208PB4F19 AF19 IO172NB4F16 AH26 IO190PB4F17 AH23 IO209NB4F19 AN18 IO172PB4F16 AH27 IO191NB4F17 AJ23 IO209PB4F19 AP18 IO173NB4F16 AJ27 IO191PB4F17 AJ24 IO210NB4F19 AE19 IO173PB4F16 AJ28 IO192NB4F17 AG21 IO210PB4F19 AD19 IO174NB4F16 AL27 IO192PB4F17 AG22 IO211NB4F19 AL18 IO174PB4F16 AL28 IO193NB4F18 AP23 IO211PB4F19 AM18 IO175NB4F16 AM28 IO193PB4F18 AP24 IO212NB4F19/CLKEN AJ20 IO175PB4F16 AM29 IO194NB4F18 AN22 IO212PB4F19/CLKEP AK20 IO176NB4F16 AG25 IO194PB4F18 AN23 IO213NB4F19/CLKFN AJ18 IO176PB4F16 AG26 IO195NB4F18 AM23 IO213PB4F19/CLKFP AJ19 IO177NB4F16 AK26 IO195PB4F18 AL23 Bank 5 IO177PB4F16 AK27 IO196NB4F18 AF21 IO214NB5F20/CLKGN AJ16 IO178NB4F16 AF25 IO196PB4F18 AF22 IO214PB5F20/CLKGP AJ17 IO178PB4F16 AE25 IO197NB4F18 AL22 IO215NB5F20/CLKHN AJ15 IO179NB4F16 AP28 IO197PB4F18 AM22 IO215PB5F20/CLKHP AK15 IO179PB4F16 AN28 IO198NB4F18 AE21 IO216NB5F20 AD16 IO180NB4F16 AJ25 IO198PB4F18 AE22 IO216PB5F20 AE17 IO180PB4F16 AJ26 IO199NB4F18 AJ21 IO217NB5F20 AM17 IO181NB4F17 AM26 IO199PB4F18 AJ22 IO217PB5F20 AL17 IO181PB4F17 AM27 IO200NB4F18 AK21 IO218NB5F20 AG16 IO182NB4F17 AF24 IO200PB4F18 AK22 IO218PB5F20 AF16 Revision 14 3-57 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO219NB5F20 AM16 IO237PB5F22 AJ12 IO256NB5F23 AL6 IO219PB5F20 AL16 IO238NB5F22 AH11 IO256PB5F23 AM6 IO220NB5F20 AP16 IO238PB5F22 AH12 Bank 6 IO220PB5F20 AN16 IO239NB5F22 AK10 IO257NB6F24 AG6 IO221NB5F20 AN15 IO239PB5F22 AK11 IO257PB6F24 AH6 IO221PB5F20 AP15 IO240NB5F22 AE12 IO258NB6F24 AD9 IO222NB5F20 AD15 IO240PB5F22 AF12 IO258PB6F24 AE9 IO222PB5F20 AE16 IO241NB5F22 AN10 IO259NB6F24 AF7 IO223NB5F21 AL14 IO241PB5F22 AP10 IO259PB6F24 AG7 IO223PB5F21 AL15 IO242NB5F22 AG11 IO260NB6F24 AH3 IO224NB5F21 AN14 IO242PB5F22 AG12 IO260PB6F24 AH4 IO224PB5F21 AP14 IO243NB5F22 AL9 IO261NB6F24 AH5 IO225NB5F21 AK13 IO243PB5F22 AL10 IO261PB6F24 AJ5 IO225PB5F21 AK14 IO244NB5F22 AM8 IO262NB6F24 AE6 IO226NB5F21 AE15 IO244PB5F22 AM9 IO262PB6F24 AF6 IO226PB5F21 AF15 IO245NB5F23 AH10 IO263NB6F24 AF5 IO227NB5F21 AG14 IO245PB5F23 AJ10 IO263PB6F24 AG5 IO227PB5F21 AG15 IO246NB5F23 AF10 IO264NB6F24 AD8 IO228NB5F21 AJ13 IO246PB5F23 AF11 IO264PB6F24 AE8 IO228PB5F21 AJ14 IO247NB5F23 AJ9 IO265NB6F24 AF3 IO229NB5F21 AM13 IO247PB5F23 AK9 IO265PB6F24 AG3 IO229PB5F21 AM14 IO248NB5F23 AN7 IO266NB6F24 AC10 IO230NB5F21 AE14 IO248PB5F23 AP7 IO266PB6F24 AD10 IO230PB5F21 AF14 IO249NB5F23 AL7 IO267NB6F25 AD7 IO231NB5F21 AN12 IO249PB5F23 AL8 IO267PB6F25 AE7 IO231PB5F21 AP12 IO250NB5F23 AE10 IO268NB6F25 AD5 IO232NB5F21 AG13 IO250PB5F23 AE11 IO268PB6F25 AE5 IO232PB5F21 AH13 IO251NB5F23 AK8 IO269NB6F25 AE4 IO233NB5F21 AL12 IO251PB5F23 AJ8 IO269PB6F25 AF4 IO233PB5F21 AL13 IO252NB5F23 AH8 IO270NB6F25 AB9 IO234NB5F21 AE13 IO252PB5F23 AH9 IO270PB6F25 AC9 IO234PB5F21 AF13 IO253NB5F23 AN6 IO271NB6F25 AC6 IO235NB5F22 AN11 IO253PB5F23 AP6 IO271PB6F25 AD6 IO235PB5F22 AP11 IO254NB5F23 AG9 IO272NB6F25 AB8 IO236NB5F22 AM11 IO254PB5F23 AG10 IO272PB6F25 AC8 IO236PB5F22 AM12 IO255NB5F23 AJ7 IO273NB6F25 AE1 IO237NB5F22 AJ11 IO255PB5F23 AK7 IO273PB6F25 AE2 3-58 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO274NB6F25 AA10 IO292PB6F27 W7 IO310PB7F29 T8 IO274PB6F25 AB10 IO293NB6F27 W4 IO311NB7F29 N3 IO275NB6F25 AB7 IO293PB6F27 Y4 IO311PB7F29 P3 IO275PB6F25 AC7 IO294NB6F27 V10 IO312NB7F29 P7 IO276NB6F25 AD1 IO294PB6F27 V11 IO312PB7F29 R7 IO276PB6F25 AD2 IO295NB6F27 Y1 IO313NB7F29 P6 IO277NB6F25 AC4 IO295PB6F27 Y2 IO313PB7F29 R6 IO277PB6F25 AC3 IO296NB6F27 W1 IO314NB7F29 M2 IO278NB6F26 AA8 IO296PB6F27 W2 IO314PB7F29 N2 IO278PB6F26 AA9 IO297NB6F27 V1 IO315NB7F29 N4 IO279NB6F26 AB5 IO297PB6F27 V2 IO315PB7F29 P4 IO279PB6F26 AB6 IO298NB6F27 V9 IO316NB7F29 R9 IO280NB6F26 Y10 IO298PB6F27 V8 IO316PB7F29 R8 IO280PB6F26 Y11 IO299NB6F27 U4 IO317NB7F29 N5 IO281NB6F26 AB3 IO299PB6F27 V4 IO317PB7F29 P5 IO281PB6F26 AB4 Bank 7 IO318NB7F29 R10 IO282NB6F26 Y7 IO300NB7F28 U10 IO318PB7F29 R11 IO282PB6F26 AA7 IO300PB7F28 U11 IO319NB7F29 L2 IO283NB6F26 AC2 IO301NB7F28 U2 IO319PB7F29 L1 IO283PB6F26 AC1 IO301PB7F28 U1 IO320NB7F29 N8 IO284NB6F26 Y9 IO302NB7F28 U6 IO320PB7F29 P8 IO284PB6F26 Y8 IO302PB7F28 U7 IO321NB7F30 M6 IO285NB6F26 AA5 IO303NB7F28 T3 IO321PB7F30 N6 IO285PB6F26 AA6 IO303PB7F28 U3 IO322NB7F30 P10 IO286NB6F26 W10 IO304NB7F28 U9 IO322PB7F30 P9 IO286PB6F26 W11 IO304PB7F28 U8 IO323NB7F30 L3 IO287NB6F26 AA3 IO305NB7F28 R2 IO323PB7F30 M3 IO287PB6F26 AA4 IO305PB7F28 R1 IO324NB7F30 M7 IO288NB6F26 W9 IO306NB7F28 R4 IO324PB7F30 N7 IO288PB6F26 W8 IO306PB7F28 T4 IO325NB7F30 K2 IO289NB6F27 AA1 IO307NB7F28 R5 IO325PB7F30 K1 IO289PB6F27 AA2 IO307PB7F28 T5 IO326NB7F30 G2 IO290NB6F27 W6 IO308NB7F28 T11 IO326PB7F30 H2 IO290PB6F27 Y6 IO308PB7F28 T10 IO327NB7F30 L6 IO291NB6F27 W5 IO309NB7F28 T6 IO327PB7F30 L5 IO291PB6F27 Y5 IO309PB7F28 T7 IO328NB7F30 N10 IO292NB6F27 V7 IO310NB7F29 T9 IO328PB7F30 N9 Revision 14 3-59 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number IO329NB7F30 J4 GND AA14 GND AK5 IO329PB7F30 K4 GND AA15 GND AL1 IO330NB7F30 J5 GND AA16 GND AL11 IO330PB7F30 K5 GND AA17 GND AL2 IO331NB7F30 M10 GND AA18 GND AL24 IO331PB7F30 M9 GND AA19 GND AL3 IO332NB7F31 L8 GND AA20 GND AL31 IO332PB7F31 M8 GND AA21 GND AL32 IO333NB7F31 F2 GND AB1 GND AL33 IO333PB7F31 F1 GND AB13 GND AL34 IO334NB7F31 J6 GND AB22 GND AL4 IO334PB7F31 K6 GND AB34 GND AM1 IO335NB7F31 H4 GND AC12 GND AM10 IO335PB7F31 H3 GND AC23 GND AM15 IO336NB7F31 K7 GND AC30 GND AM2 IO336PB7F31 L7 GND AC5 GND AM20 IO337NB7F31 G4 GND AD11 GND AM25 IO337PB7F31 G3 GND AD24 GND AM3 IO338NB7F31 K9 GND AD31 GND AM31 IO338PB7F31 L9 GND AD4 GND AM32 IO339NB7F31 H6 GND AE3 GND AM33 IO339PB7F31 H5 GND AE32 GND AM34 IO340NB7F31 H7 GND AF2 GND AM4 IO340PB7F31 J7 GND AF33 GND AN1 IO341NB7F31 J8 GND AG1 GND AN2 IO341PB7F31 K8 GND AG27 GND AN26 Dedicated I/O GND AG34 GND AN3 GND A13 GND AG8 GND AN31 GND A2 GND AH28 GND AN32 GND A22 GND AH7 GND AN33 GND A27 GND AJ29 GND AN34 GND A3 GND AJ6 GND AN4 GND A31 GND AK12 GND AN9 GND A32 GND AK17 GND AP13 GND A33 GND AK18 GND AP2 GND A4 GND AK23 GND AP22 GND A8 GND AK30 GND AP27 3-60 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number GND AP3 GND D4 GND P20 GND AP31 GND E12 GND P21 GND AP32 GND E17 GND R14 GND AP33 GND E18 GND R15 GND AP4 GND E23 GND R16 GND AP8 GND E30 GND R17 GND B1 GND E5 GND R18 GND B2 GND F29 GND R19 GND B26 GND F30 GND R20 GND B3 GND F6 GND R21 GND B31 GND G28 GND R3 GND B32 GND G6 GND R32 GND B33 GND G7 GND T14 GND B34 GND H1 GND T15 GND B4 GND H34 GND T16 GND B9 GND J2 GND T17 GND C1 GND J33 GND T18 GND C10 GND K3 GND T19 GND C15 GND K32 GND T20 GND C2 GND L11 GND T21 GND C20 GND L24 GND U14 GND C25 GND L31 GND U15 GND C3 GND L4 GND U16 GND C31 GND M12 GND U17 GND C32 GND M23 GND U18 GND C33 GND M30 GND U19 GND C34 GND M5 GND U20 GND C4 GND N1 GND U21 GND D1 GND N13 GND U30 GND D11 GND N22 GND U5 GND D2 GND N34 GND V14 GND D24 GND P14 GND V15 GND D3 GND P15 GND V16 GND D31 GND P16 GND V17 GND D32 GND P17 GND V18 GND D33 GND P18 GND V19 GND D34 GND P19 GND V20 Revision 14 3-61 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number GND V21 NC AG2 NC F3 GND V30 NC AG4 NC F32 GND V5 NC AH1 NC F33 GND W14 NC AH16 NC F34 GND W15 NC AH19 NC F4 GND W16 NC AH2 NC G1 GND W17 NC AH31 NC G32 GND W18 NC AH32 NC G33 GND W19 NC AH34 NC G34 GND W20 NC AJ1 NC H16 GND W21 NC AJ2 NC H19 GND Y14 NC AJ3 NC H31 GND Y15 NC AJ31 NC H33 GND Y16 NC AJ32 NC J1 GND Y17 NC AJ33 NC J16 GND Y18 NC AJ34 NC J19 GND Y19 NC AJ4 NC J3 GND Y20 NC AK16 NC J34 GND Y21 NC AK19 NC K17 GND Y3 NC AL29 NC K18 GND Y32 NC AM19 NC L17 NC A17 NC AM7 NC L18 NC A26 NC AN13 NC M1 NC AB2 NC AN17 NC M4 NC AB33 NC AN25 NC P1 NC AC34 NC AN27 NC P2 NC AD17 NC AN8 NC R31 NC AD3 NC AP17 NC T1 NC AD34 NC AP9 NC T2 NC AE18 NC B17 NC V3 NC AE31 NC B22 NC V34 NC AE33 NC B27 NC W3 NC AE34 NC B8 NC W34 NC AF1 NC D10 PRA J17 NC AF17 NC D20 PRB F18 NC AF18 NC D23 PRC AD18 NC AF34 NC D25 PRD AH18 3-62 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1152/LG1152 CG1152/LG1152 CG1152/LG1152 Pin Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number RTAX2000S/SL Function Number TCK J9 VCCA W13 VCCIB0 M15 TDI F7 VCCA W22 VCCIB0 M16 TDO L10 VCCA Y13 VCCIB0 M17 TMS H8 VCCA Y22 VCCIB1 A30 TRST E6 VCCDA AF26 VCCIB1 B30 VCCA AA13 VCCDA AF9 VCCIB1 C30 VCCA AA22 VCCDA AG17 VCCIB1 D30 VCCA AB14 VCCDA AG18 VCCIB1 L21 VCCA AB15 VCCDA AH14 VCCIB1 L22 VCCA AB16 VCCDA AH15 VCCIB1 L23 VCCA AB17 VCCDA AH17 VCCIB1 M18 VCCA AB18 VCCDA AH20 VCCIB1 M19 VCCA AB19 VCCDA AH21 VCCIB1 M20 VCCA AB20 VCCDA AK29 VCCIB1 M21 VCCA AB21 VCCDA AK6 VCCIB1 M22 VCCA AF8 VCCDA E15 VCCIB2 E31 VCCA AK28 VCCDA E29 VCCIB2 E32 VCCA G30 VCCDA E7 VCCIB2 E33 VCCA G5 VCCDA F15 VCCIB2 E34 VCCA N14 VCCDA F21 VCCIB2 M24 VCCA N15 VCCDA F5 VCCIB2 N23 VCCA N16 VCCDA G20 VCCIB2 N24 VCCA N17 VCCDA H17 VCCIB2 P23 VCCA N18 VCCDA H18 VCCIB2 P24 VCCA N19 VCCDA H28 VCCIB2 R23 VCCA N20 VCCDA J18 VCCIB2 T23 VCCA N21 VCCDA V27 VCCIB2 U23 VCCA P13 VCCDA V6 VCCIB3 AA23 VCCA P22 VCCIB0 A5 VCCIB3 AA24 VCCA R13 VCCIB0 B5 VCCIB3 AB23 VCCA R22 VCCIB0 C5 VCCIB3 AB24 VCCA T13 VCCIB0 D5 VCCIB3 AC24 VCCA T22 VCCIB0 L12 VCCIB3 AK31 VCCA U13 VCCIB0 L13 VCCIB3 AK32 VCCA U22 VCCIB0 L14 VCCIB3 AK33 VCCA V13 VCCIB0 M13 VCCIB3 AK34 VCCA V22 VCCIB0 M14 VCCIB3 V23 Revision 14 3-63 Package Pin Assignments CG1152/LG1152 CG1152/LG1152 Pin Pin RTAX2000S/SL Function Number RTAX2000S/SL Function Number VCCIB3 W23 VCCIB6 Y12 VCCIB3 Y23 VCCIB7 E1 VCCIB4 AC18 VCCIB7 E2 VCCIB4 AC19 VCCIB7 E3 VCCIB4 AC20 VCCIB7 E4 VCCIB4 AC21 VCCIB7 M11 VCCIB4 AC22 VCCIB7 N11 VCCIB4 AD21 VCCIB7 N12 VCCIB4 AD22 VCCIB7 P11 VCCIB4 AD23 VCCIB7 P12 VCCIB4 AL30 VCCIB7 R12 VCCIB4 AM30 VCCIB7 T12 VCCIB4 AN30 VCCIB7 U12 VCCIB4 AP30 VPUMP J26 VCCIB5 AC13 VCCIB5 AC14 VCCIB5 AC15 VCCIB5 AC16 VCCIB5 AC17 VCCIB5 AD12 VCCIB5 AD13 VCCIB5 AD14 VCCIB5 AL5 VCCIB5 AM5 VCCIB5 AN5 VCCIB5 AP5 VCCIB6 AA11 VCCIB6 AA12 VCCIB6 AB11 VCCIB6 AB12 VCCIB6 AC11 VCCIB6 AK1 VCCIB6 AK2 VCCIB6 AK3 VCCIB6 AK4 VCCIB6 V12 VCCIB6 W12 3-64 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 14 3-65 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number Bank 0 IO17NB0F1 E12 IO34PB0F3 F15 IO00NB0F0 E9 IO17PB0F1 E11 IO35NB0F3 C15 IO00PB0F0 D9 IO18NB0F1 K13 IO35PB0F3 D15 IO01NB0F0 D8 IO18PB0F1 K12 IO36NB0F3 J16 IO01PB0F0 D7 IO19NB0F1 B4 IO36PB0F3 J15 IO02NB0F0 J10 IO19PB0F1 C4 IO37NB0F3 A11 IO02PB0F0 J9 IO20NB0F1 H13 IO37PB0F3 A10 IO03NB0F0 E7 IO20PB0F1 H12 IO38NB0F3 H15 IO03PB0F0 E8 IO21NB0F2 C13 IO38PB0F3 H14 IO04NB0F0 F9 IO21PB0F2 C12 IO39NB0F3 B16 IO04PB0F0 G9 IO22NB0F2 M14 IO39PB0F3 B15 IO05NB0F0 B7 IO22PB0F2 M13 IO40NB0F3 M16 IO05PB0F0 B6 IO23NB0F2 B10 IO40PB0F3 M17 IO06NB0F0 L13 IO23PB0F2 B9 IO41NB0F3 E16 IO06PB0F0 L12 IO24NB0F2 J14 IO41PB0F3 F16 IO07NB0F0 C7 IO24PB0F2 J13 IO42NB0F4 H17 IO07PB0F0 C6 IO25NB0F2 A8 IO42PB0F4 J17 IO08NB0F0 F10 IO25PB0F2 A9 IO43NB0F4 A14 IO08PB0F0 G10 IO26NB0F2 G13 IO43PB0F4 A15 IO09NB0F0 D10 IO26PB0F2 F13 IO44NB0F4 G16 IO09PB0F0 E10 IO27NB0F2 D14 IO44PB0F4 H16 IO10NB0F0 H11 IO27PB0F2 D13 IO45NB0F4 A17 IO10PB0F0 H10 IO28NB0F2 L16 IO45PB0F4 A16 IO11NB0F0 A5 IO28PB0F2 L15 IO46NB0F4 M18 IO11PB0F0 A4 IO29NB0F2 B13 IO46PB0F4 M19 IO12NB0F1 D6 IO29PB0F2 B12 IO47NB0F4 E18 IO12PB0F1 D5 IO30NB0F2 C10 IO47PB0F4 E17 IO13NB0F1 A7 IO30PB0F2 C9 IO48NB0F4 G18 IO13PB0F1 A6 IO31NB0F2 E15 IO48PB0F4 H18 IO14NB0F1 J12 IO31PB0F2 E14 IO49NB0F4 C18 IO14PB0F1 J11 IO32NB0F2 K15 IO49PB0F4 B18 IO15NB0F1 D12 IO32PB0F2 K16 IO50NB0F4/HCLKAN J18 IO15PB0F1 D11 IO33NB0F3 A13 IO50PB0F4/HCLKAP K18 IO16NB0F1 F12 IO33PB0F3 A12 IO51NB0F4/HCLKBN D18 IO16PB0F1 G12 IO34NB0F3 G15 IO51PB0F4/HCLKBP D17 3-66 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number Bank 1 IO69NB1F7 A27 IO86PB1F9 F25 IO52NB1F6/HCLKCN K19 IO69PB1F7 A26 IO87NB1F9 E26 IO52PB1F6/HCLKCP J19 IO70NB1F7 F22 IO87PB1F9 E25 IO53NB1F6/HCLKDN D20 IO70PB1F7 G22 IO88NB1F9 J26 IO53PB1F6/HCLKDP D19 IO71NB1F7 E23 IO88PB1F9 J25 IO54NB1F6 H19 IO71PB1F7 E22 IO89NB1F9 D26 IO54PB1F6 G19 IO72NB1F8 L22 IO89PB1F9 D25 IO55NB1F6 B19 IO72PB1F8 L21 IO90NB1F9 E31 IO55PB1F6 C19 IO73NB1F8 A25 IO90PB1F9 E32 IO56NB1F6 M20 IO73PB1F8 A24 IO91NB1F9 A31 IO56PB1F6 M21 IO74NB1F8 C28 IO91PB1F9 A30 IO57NB1F6 E20 IO74PB1F8 C27 IO92NB1F9 H27 IO57PB1F6 E19 IO75NB1F8 D24 IO92PB1F9 H26 IO58NB1F6 H21 IO75PB1F8 D23 IO93NB1F9 C33 IO58PB1F6 G21 IO76NB1F8 J24 IO93PB1F9 B33 IO59NB1F6 A21 IO76PB1F8 J23 IO94NB1F10 G27 IO59PB1F6 A20 IO77NB1F8 B25 IO94PB1F10 F27 IO60NB1F7 H20 IO77PB1F8 B24 IO95NB1F10 E27 IO60PB1F7 J20 IO78NB1F8 F24 IO95PB1F10 D27 IO61NB1F7 A22 IO78PB1F8 G24 IO96NB1F10 L24 IO61PB1F7 A23 IO79NB1F8 A28 IO96PB1F10 L25 IO62NB1F7 D32 IO79PB1F8 A29 IO97NB1F10 C31 IO62PB1F7 D31 IO80NB1F8 M24 IO97PB1F10 C30 IO63NB1F7 F21 IO80PB1F8 M23 IO98NB1F10 F28 IO63PB1F7 E21 IO81NB1F8 B28 IO98PB1F10 G28 IO64NB1F7 J22 IO81PB1F8 B27 IO99NB1F10 B31 IO64PB1F7 J21 IO82NB1F9 H25 IO99PB1F10 B30 IO65NB1F7 B22 IO82PB1F9 H24 IO100NB1F10 J28 IO65PB1F7 B21 IO83NB1F9 C25 IO100PB1F10 J27 IO66NB1F7 H23 IO83PB1F9 C24 IO101NB1F10 E29 IO66PB1F7 H22 IO84NB1F9 K25 IO101PB1F10 E30 IO67NB1F7 D22 IO84PB1F9 K24 IO102NB1F10 D28 IO67PB1F7 C22 IO85NB1F9 A33 IO102PB1F10 E28 IO68NB1F7 K22 IO85PB1F9 A32 IO103NB1F10 D30 IO68PB1F7 K21 IO86NB1F9 G25 IO103PB1F10 D29 Revision 14 3-67 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number Bank 2 IO121NB2F14 N28 IO138PB2F15 P32 IO104NB2F12 L29 IO121PB2F14 N27 IO139NB2F16 R31 IO104PB2F12 L28 IO122NB2F14 L33 IO139PB2F16 R30 IO105NB2F12 D35 IO122PB2F14 L32 IO140NB2F16 P36 IO105PB2F12 D34 IO123NB2F14 N30 IO140PB2F16 N36 IO106NB2F12 H33 IO123PB2F14 N29 IO141NB2F16 T28 IO106PB2F12 J33 IO124NB2F14 K35 IO141PB2F16 T27 IO107NB2F12 F34 IO124PB2F14 J35 IO142NB2F16 R35 IO107PB2F12 F33 IO125NB2F14 P25 IO142PB2F16 R34 IO108NB2F12 G33 IO125PB2F14 N25 IO143NB2F16 T32 IO108PB2F12 G32 IO126NB2F14 H36 IO143PB2F16 T31 IO109NB2F12 M28 IO126PB2F14 G36 IO144NB2F16 T35 IO109PB2F12 M27 IO127NB2F14 N32 IO144PB2F16 T34 IO110NB2F12 K33 IO127PB2F14 N31 IO145NB2F16 T30 IO110PB2F12 K32 IO128NB2F14 N34 IO145PB2F16 T29 IO111NB2F12 K31 IO128PB2F14 M34 IO146NB2F16 R33 IO111PB2F12 K30 IO129NB2F14 P29 IO146PB2F16 R32 IO112NB2F13 K34 IO129PB2F14 P28 IO147NB2F16 V25 IO112PB2F13 J34 IO130NB2F15 N33 IO147PB2F16 U25 IO113NB2F13 N26 IO130PB2F15 M33 IO148NB2F17 T36 IO113PB2F13 M26 IO131NB2F15 R26 IO148PB2F17 R36 IO114NB2F13 K28 IO131PB2F15 R25 IO149NB2F17 U29 IO114PB2F13 K29 IO132NB2F15 K36 IO149PB2F17 U28 IO115NB2F13 H32 IO132PB2F15 J36 IO150NB2F17 U33 IO115PB2F13 J32 IO133NB2F15 R29 IO150PB2F17 T33 IO116NB2F13 G35 IO133PB2F15 R28 IO151NB2F17 W25 IO116PB2F13 G34 IO134NB2F15 N35 IO151PB2F17 Y25 IO117NB2F13 M29 IO134PB2F15 M35 IO152NB2F17 V36 IO117PB2F13 M30 IO135NB2F15 F35 IO152PB2F17 U36 IO118NB2F13 E33 IO135PB2F15 F36 IO153NB2F17 V31 IO118PB2F13 D33 IO136NB2F15 M36 IO153PB2F17 V30 IO119NB2F13 M32 IO136PB2F15 L36 IO154NB2F17 V32 IO119PB2F13 M31 IO137NB2F15 T26 IO154PB2F17 U32 IO120NB2F13 E36 IO137PB2F15 T25 IO155NB2F17 V27 IO120PB2F13 D36 IO138NB2F15 P33 IO155PB2F17 V28 3-68 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO156NB2F17 W34 IO173NB3F19 AA27 IO190PB3F21 AK36 IO156PB2F17 V34 IO173PB3F19 AA28 IO191NB3F21 AE32 Bank 3 IO174NB3F19 AB34 IO191PB3F21 AE31 IO157NB3F18 W29 IO174PB3F19 AB35 IO192NB3F21 AN36 IO157PB3F18 V29 IO175NB3F20 AL35 IO192PB3F21 AM36 IO158NB3F18 W35 IO175PB3F20 AL36 IO193NB3F22 AD27 IO158PB3F18 V35 IO176NB3F20 AG36 IO193PB3F22 AD28 IO159NB3F18 W30 IO176PB3F20 AF36 IO194NB3F22 AF32 IO159PB3F18 W31 IO177NB3F20 AB25 IO194PB3F22 AF33 IO160NB3F18 AA36 IO177PB3F20 AB26 IO195NB3F22 AE30 IO160PB3F18 Y36 IO178NB3F20 AC32 IO195PB3F22 AE29 IO161NB3F18 W27 IO178PB3F20 AC33 IO196NB3F22 AK34 IO161PB3F18 W28 IO179NB3F20 AB29 IO196PB3F22 AL34 IO162NB3F18 Y32 IO179PB3F20 AB28 IO197NB3F22 AE28 IO162PB3F18 W32 IO180NB3F20 AJ36 IO197PB3F22 AE27 IO163NB3F18 Y28 IO180PB3F20 AH36 IO198NB3F22 AN33 IO163PB3F18 Y29 IO181NB3F20 AC25 IO198PB3F22 AM33 IO164NB3F18 AC36 IO181PB3F20 AD25 IO199NB3F22 AH31 IO164PB3F18 AB36 IO182NB3F20 AE35 IO199PB3F22 AH30 IO165NB3F18 AA26 IO182PB3F20 AD35 IO200NB3F22 AH34 IO165PB3F18 AA25 IO183NB3F20 AC29 IO200PB3F22 AG34 IO166NB3F19 AA33 IO183PB3F20 AC28 IO201NB3F22 AF29 IO166PB3F19 Y33 IO184NB3F21 AE34 IO201PB3F22 AF28 IO167NB3F19 AA32 IO184PB3F21 AD34 IO202NB3F23 AG32 IO167PB3F19 AA31 IO185NB3F21 AE26 IO202PB3F23 AG33 IO168NB3F19 AA34 IO185PB3F21 AD26 IO203NB3F23 AG31 IO168PB3F19 AA35 IO186NB3F21 AE33 IO203PB3F23 AG30 IO169NB3F19 AA29 IO186PB3F21 AD33 IO204NB3F23 AL33 IO169PB3F19 AA30 IO187NB3F21 AD30 IO204PB3F23 AK33 IO170NB3F19 AB32 IO187PB3F21 AD29 IO205NB3F23 AK32 IO170PB3F19 AB33 IO188NB3F21 AH35 IO205PB3F23 AK31 IO171NB3F19 AB31 IO188PB3F21 AG35 IO206NB3F23 AH33 IO171PB3F19 AB30 IO189NB3F21 AD32 IO206PB3F23 AJ33 IO172NB3F19 AE36 IO189PB3F21 AD31 IO207NB3F23 AN34 IO172PB3F19 AD36 IO190NB3F21 AK35 IO207PB3F23 AN35 Revision 14 3-69 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO208NB3F23 AG29 IO225NB4F25 AN25 IO242PB4F27 AG22 IO208PB3F23 AG28 IO225PB4F25 AN26 IO243NB4F27 AM22 IO209NB3F23 AJ32 IO226NB4F25 AL25 IO243PB4F27 AM23 IO209PB3F23 AH32 IO226PB4F25 AK25 IO244NB4F27 AK22 Bank 4 IO227NB4F25 AM25 IO244PB4F27 AL22 IO210NB4F24 AM28 IO227PB4F25 AM26 IO245NB4F27 AT24 IO210PB4F24 AN28 IO228NB4F25 AG25 IO245PB4F27 AT25 IO211NB4F24 AN29 IO228PB4F25 AG24 IO246NB4F27 AH21 IO211PB4F24 AN30 IO229NB4F25 AR33 IO246PB4F27 AH22 IO212NB4F24 AH27 IO229PB4F25 AP33 IO247NB4F27 AP22 IO212PB4F24 AH28 IO230NB4F25 AJ24 IO247PB4F27 AN22 IO213NB4F24 AM30 IO230PB4F25 AJ25 IO248NB4F27 AJ22 IO213PB4F24 AM29 IO231NB4F25 AT26 IO248PB4F27 AJ23 IO214NB4F24 AL28 IO231PB4F25 AT27 IO249NB4F27 AR21 IO214PB4F24 AK28 IO232NB4F26 AE23 IO249PB4F27 AR22 IO215NB4F24 AR30 IO232PB4F26 AE24 IO250NB4F27 AE21 IO215PB4F24 AR31 IO233NB4F26 AR27 IO250PB4F27 AE20 IO216NB4F24 AF24 IO233PB4F26 AR28 IO251NB4F27 AM21 IO216PB4F24 AF25 IO234NB4F26 AH23 IO251PB4F27 AL21 IO217NB4F24 AP30 IO234PB4F26 AH24 IO252NB4F27 AH20 IO217PB4F24 AP31 IO235NB4F26 AT29 IO252PB4F27 AJ20 IO218NB4F24 AL27 IO235PB4F26 AT28 IO253NB4F27 AT23 IO218PB4F24 AK27 IO236NB4F26 AK24 IO253PB4F27 AT22 IO219NB4F24 AN27 IO236PB4F26 AL24 IO254NB4F28 AK21 IO219PB4F24 AM27 IO237NB4F26 AR24 IO254PB4F28 AJ21 IO220NB4F25 AJ26 IO237PB4F26 AR25 IO255NB4F28 AT20 IO220PB4F25 AJ27 IO238NB4F26 AF21 IO255PB4F28 AT21 IO221NB4F25 AT32 IO238PB4F26 AF22 IO256NB4F28 AE18 IO221PB4F25 AT33 IO239NB4F26 AP24 IO256PB4F28 AE19 IO222NB4F25 AN31 IO239PB4F26 AP25 IO257NB4F28 AM19 IO222PB4F25 AN32 IO240NB4F26 AP27 IO257PB4F28 AM20 IO223NB4F25 AT30 IO240PB4F26 AP28 IO258NB4F28 AK19 IO223PB4F25 AT31 IO241NB4F26 AN23 IO258PB4F28 AJ19 IO224NB4F25 AH25 IO241PB4F26 AN24 IO259NB4F28 AP19 IO224PB4F25 AH26 IO242NB4F27 AG21 IO259PB4F28 AR19 3-70 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO260NB4F28/CLKEN AH19 IO277NB5F31 AN15 IO294PB5F33 AF13 IO260PB4F28/CLKEP AG19 IO277PB5F31 AP15 IO295NB5F33 AP4 IO261NB4F28/CLKFN AN19 IO278NB5F31 AG15 IO295PB5F33 AR4 IO261PB4F28/CLKFP AN20 IO278PB5F31 AG16 IO296NB5F33 AG12 Bank 5 IO279NB5F31 AT10 IO296PB5F33 AF12 IO262NB5F30/CLKGN AG18 IO279PB5F31 AT11 IO297NB5F33 AM11 IO262PB5F30/CLKGP AH18 IO280NB5F31 AL15 IO297PB5F33 AM12 IO263NB5F30/CLKHN AN17 IO280PB5F31 AK15 IO298NB5F33 AK12 IO263PB5F30/CLKHP AN18 IO281NB5F32 AM14 IO298PB5F33 AL12 IO264NB5F30 AJ18 IO281PB5F32 AM15 IO299NB5F33 AN11 IO264PB5F30 AK18 IO282NB5F32 AE13 IO299PB5F33 AN12 IO265NB5F30 AR18 IO282PB5F32 AE14 IO300NB5F33 AN5 IO265PB5F30 AP18 IO283NB5F32 AT12 IO300PB5F33 AN6 IO266NB5F30 AE17 IO283PB5F32 AT13 IO301NB5F33 AT6 IO266PB5F30 AE16 IO284NB5F32 AP9 IO301PB5F33 AT7 IO267NB5F30 AM17 IO284PB5F32 AP10 IO302NB5F34 AH11 IO267PB5F30 AM18 IO285NB5F32 AN13 IO302PB5F34 AH12 IO268NB5F30 AJ16 IO285PB5F32 AN14 IO303NB5F34 AT4 IO268PB5F30 AK16 IO286NB5F32 AN9 IO303PB5F34 AT5 IO269NB5F30 AT16 IO286PB5F32 AM9 IO304NB5F34 AJ10 IO269PB5F30 AT17 IO287NB5F32 AR12 IO304PB5F34 AJ11 IO270NB5F30 AF16 IO287PB5F32 AR13 IO305NB5F34 AM10 IO270PB5F30 AF15 IO288NB5F32 AL13 IO305PB5F34 AN10 IO271NB5F30 AT15 IO288PB5F32 AK13 IO306NB5F34 AK10 IO271PB5F30 AT14 IO289NB5F32 AT9 IO306PB5F34 AL10 IO272NB5F31 AH17 IO289PB5F32 AT8 IO307NB5F34 AP6 IO272PB5F31 AJ17 IO290NB5F32 AH13 IO307PB5F34 AP7 IO273NB5F31 AL16 IO290PB5F32 AH14 IO308NB5F34 AK9 IO273PB5F31 AM16 IO291NB5F32 AR9 IO308PB5F34 AL9 IO274NB5F31 AH15 IO291PB5F32 AR10 IO309NB5F34 AR6 IO274PB5F31 AH16 IO292NB5F32 AJ12 IO309PB5F34 AR7 IO275NB5F31 AR15 IO292PB5F32 AJ13 IO310NB5F34 AH9 IO275PB5F31 AR16 IO293NB5F33 AP12 IO310PB5F34 AH10 IO276NB5F31 AJ14 IO293PB5F33 AP13 IO311NB5F34 AM8 IO276PB5F31 AJ15 IO294NB5F33 AG13 IO311PB5F34 AM7 Revision 14 3-71 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO312NB5F34 AG9 IO329NB6F37 AD9 IO346PB6F39 AF1 IO312PB5F34 AG8 IO329PB6F37 AD10 IO347NB6F39 AL1 IO313NB5F34 AN7 IO330NB6F37 AM1 IO347PB6F39 AL2 IO313PB5F34 AN8 IO330PB6F37 AN1 IO348NB6F39 AC4 Bank 6 IO331NB6F38 AE5 IO348PB6F39 AC5 IO314NB6F36 AF8 IO331PB6F38 AE6 IO349NB6F40 AB6 IO314PB6F36 AF9 IO332NB6F38 AF4 IO349PB6F40 AB7 IO315NB6F36 AN2 IO332PB6F38 AF5 IO350NB6F40 AC1 IO315PB6F36 AN3 IO333NB6F38 AD8 IO350PB6F40 AD1 IO316NB6F36 AH4 IO333PB6F38 AD7 IO351NB6F40 AA9 IO316PB6F36 AJ4 IO334NB6F38 AG2 IO351PB6F40 AA10 IO317NB6F36 AL3 IO334PB6F38 AH2 IO352NB6F40 AB2 IO317PB6F36 AL4 IO335NB6F38 AC12 IO352PB6F40 AB3 IO318NB6F36 AK4 IO335PB6F38 AD12 IO353NB6F40 AA7 IO318PB6F36 AK5 IO336NB6F38 AJ1 IO353PB6F40 AA8 IO319NB6F36 AE10 IO336PB6F38 AK1 IO354NB6F40 AA2 IO319PB6F36 AE9 IO337NB6F38 AC8 IO354PB6F40 AA3 IO320NB6F36 AG4 IO337PB6F38 AC9 IO355NB6F40 AA5 IO320PB6F36 AG5 IO338NB6F38 AD3 IO355PB6F40 AA6 IO321NB6F36 AE11 IO338PB6F38 AE3 IO356NB6F40 AB4 IO321PB6F36 AD11 IO339NB6F38 AD5 IO356PB6F40 AB5 IO322NB6F37 AG3 IO339PB6F38 AD6 IO357NB6F40 W12 IO322PB6F37 AH3 IO340NB6F39 AD4 IO357PB6F40 Y12 IO323NB6F37 AG7 IO340PB6F39 AE4 IO358NB6F41 AA1 IO323PB6F37 AG6 IO341NB6F39 AB8 IO358PB6F41 AB1 IO324NB6F37 AH7 IO341PB6F39 AB9 IO359NB6F41 Y8 IO324PB6F37 AH6 IO342NB6F39 AG1 IO359PB6F41 Y9 IO325NB6F37 AJ5 IO342PB6F39 AH1 IO360NB6F41 Y4 IO325PB6F37 AH5 IO343NB6F39 AA12 IO360PB6F41 AA4 IO326NB6F37 AK2 IO343PB6F39 AB12 IO361NB6F41 U12 IO326PB6F37 AK3 IO344NB6F39 AD2 IO361PB6F41 V12 IO327NB6F37 AE7 IO344PB6F39 AE2 IO362NB6F41 W1 IO327PB6F37 AE8 IO345NB6F39 AA11 IO362PB6F41 Y1 IO328NB6F37 AM4 IO345PB6F39 AB11 IO363NB6F41 W6 IO328PB6F37 AN4 IO346NB6F39 AE1 IO363PB6F41 W7 3-72 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO364NB6F41 W5 IO381NB7F43 R6 IO398PB7F45 K2 IO364PB6F41 Y5 IO381PB7F43 R7 IO399NB7F45 N8 IO365NB6F41 W10 IO382NB7F43 N1 IO399PB7F45 N7 IO365PB6F41 W9 IO382PB7F43 P1 IO400NB7F45 G1 IO366NB6F41 V2 IO383NB7F43 T10 IO400PB7F45 H1 IO366PB6F41 W2 IO383PB7F43 T9 IO401NB7F45 M5 Bank 7 IO384NB7F43 R3 IO401PB7F45 M6 IO367NB7F42 V8 IO384PB7F43 R2 IO402NB7F45 E1 IO367PB7F42 W8 IO385NB7F44 R12 IO402PB7F45 F1 IO368NB7F42 V3 IO385PB7F44 R11 IO403NB7F46 N10 IO368PB7F42 W3 IO386NB7F44 L1 IO403PB7F46 N9 IO369NB7F42 V9 IO386PB7F44 M1 IO404NB7F46 L5 IO369PB7F42 V10 IO387NB7F44 G2 IO404PB7F46 L4 IO370NB7F42 U1 IO387PB7F44 F2 IO405NB7F46 M7 IO370PB7F42 V1 IO388NB7F44 P5 IO405PB7F46 M8 IO371NB7F42 V7 IO388PB7F44 P4 IO406NB7F46 G3 IO371PB7F42 V6 IO389NB7F44 R8 IO406PB7F46 F3 IO372NB7F42 U5 IO389PB7F44 R9 IO407NB7F46 M10 IO372PB7F42 V5 IO390NB7F44 J1 IO407PB7F46 M9 IO373NB7F42 U9 IO390PB7F44 K1 IO408NB7F46 D4 IO373PB7F42 U8 IO391NB7F44 N12 IO408PB7F46 D3 IO374NB7F42 R1 IO391PB7F44 P12 IO409NB7F46 J7 IO374PB7F42 T1 IO392NB7F44 M2 IO409PB7F46 J6 IO375NB7F42 T11 IO392PB7F44 N2 IO410NB7F46 J3 IO375PB7F42 T12 IO393NB7F44 P9 IO410PB7F46 K3 IO376NB7F43 T4 IO393PB7F44 P8 IO411NB7F46 L8 IO376PB7F43 U4 IO394NB7F45 M3 IO411PB7F46 L9 IO377NB7F43 T8 IO394PB7F45 N3 IO412NB7F47 K5 IO377PB7F43 T7 IO395NB7F45 M11 IO412PB7F47 K4 IO378NB7F43 T3 IO395PB7F45 N11 IO413NB7F47 K7 IO378PB7F43 T2 IO396NB7F45 M4 IO413PB7F47 K6 IO379NB7F43 T5 IO396PB7F45 N4 IO414NB7F47 E4 IO379PB7F43 T6 IO397NB7F45 N5 IO414PB7F47 F4 IO380NB7F43 R5 IO397PB7F45 N6 IO415NB7F47 G4 IO380PB7F43 R4 IO398NB7F45 J2 IO415PB7F47 G5 Revision 14 3-73 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number IO416NB7F47 H4 GND AD13 GND AK8 IO416PB7F47 J4 GND AD14 GND AL18 IO417NB7F47 D2 GND AD16 GND AL31 IO417PB7F47 D1 GND AD18 GND AL7 IO418NB7F47 K8 GND AD19 GND AM3 IO418PB7F47 K9 GND AD21 GND AM34 IO419NB7F47 H5 GND AD23 GND AP11 IO419PB7F47 J5 GND AD24 GND AP14 Dedicated I/O GND AE15 GND AP17 GND J8 GND AE25 GND AP2 GND AA13 GND AF10 GND AP20 GND AA15 GND AF11 GND AP23 GND AA17 GND AF14 GND AP26 GND AA19 GND AF17 GND AP29 GND AA21 GND AF20 GND AP32 GND AA23 GND AF23 GND AP35 GND AA24 GND AF26 GND AP5 GND AB14 GND AF27 GND AP8 GND AB16 GND AF3 GND AR3 GND AB18 GND AF30 GND AR34 GND AB20 GND AF34 GND B3 GND AB22 GND AF7 GND B34 GND AC11 GND AJ29 GND C11 GND AC13 GND AJ3 GND C14 GND AC15 GND AJ30 GND C17 GND AC17 GND AJ34 GND C2 GND AC19 GND AJ7 GND C20 GND AC21 GND AK11 GND C23 GND AC23 GND AK14 GND C26 GND AC24 GND AK17 GND C29 GND AC26 GND AK20 GND C32 GND AC3 GND AK23 GND C35 GND AC30 GND AK26 GND C5 GND AC34 GND AK29 GND C8 GND AC7 GND AK6 GND E3 3-74 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number GND E34 GND N23 GND U3 GND F30 GND N24 GND U30 GND F7 GND P11 GND U34 GND G11 GND P13 GND U7 GND G14 GND P14 GND V13 GND G17 GND P16 GND V14 GND G20 GND P18 GND V16 GND G23 GND P20 GND V18 GND G26 GND P22 GND V20 GND G29 GND P24 GND V22 GND G8 GND P26 GND V24 GND H3 GND P3 GND V33 GND H30 GND P30 GND V4 GND H34 GND P34 GND W11 GND H7 GND P7 GND W13 GND J31 GND R15 GND W15 GND L10 GND R17 GND W17 GND L11 GND R19 GND W19 GND L14 GND R21 GND W21 GND L17 GND R23 GND W23 GND L20 GND R27 GND W24 GND L23 GND T13 GND W26 GND L26 GND T14 GND W4 GND L27 GND T16 GND Y11 GND L3 GND T18 GND Y14 GND L30 GND T20 GND Y16 GND L34 GND T22 GND Y18 GND L7 GND T24 GND Y20 GND M15 GND U11 GND Y22 GND M25 GND U15 GND Y26 GND N14 GND U17 GND Y3 GND N16 GND U19 GND Y30 GND N18 GND U21 GND Y34 GND N19 GND U23 GND Y7 GND N21 GND U26 NC AJ8 Revision 14 3-75 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number NC W36 VCCA M12 VCCA Y21 PRA F18 VCCA P15 VCCA Y23 PRB A18 VCCA P17 VCCDA AB10 PRC AL19 VCCA P19 VCCDA AB27 PRD AT19 VCCA P21 VCCDA AE22 TCK H8 VCCA P23 VCCDA AF18 TDI F6 VCCA R14 VCCDA AF19 TDO H9 VCCA R16 VCCDA AH29 TMS F5 VCCA R18 VCCDA AH8 TRST G7 VCCA R20 VCCDA AJ28 VCCA A19 VCCA R22 VCCDA AJ9 VCCA AA14 VCCA T15 VCCDA AK30 VCCA AA16 VCCA T17 VCCDA AK7 VCCA AA18 VCCA T19 VCCDA AL30 VCCA AA20 VCCA T21 VCCDA AL6 VCCA AA22 VCCA T23 VCCDA AM13 VCCA AB15 VCCA U14 VCCDA AM24 VCCA AB17 VCCA U16 VCCDA AM31 VCCA AB19 VCCA U18 VCCDA AM32 VCCA AB21 VCCA U20 VCCDA AM5 VCCA AB23 VCCA U22 VCCDA AM6 VCCA AC14 VCCA V15 VCCDA AN16 VCCA AC16 VCCA V17 VCCDA AN21 VCCA AC18 VCCA V19 VCCDA AP16 VCCA AC20 VCCA V21 VCCDA AP21 VCCA AC22 VCCA V23 VCCDA C16 VCCA AE12 VCCA W14 VCCDA C21 VCCA AL32 VCCA W16 VCCDA D16 VCCA AL5 VCCA W18 VCCDA D21 VCCA AP3 VCCA W20 VCCDA E13 VCCA AP34 VCCA W22 VCCDA E24 VCCA AT18 VCCA W33 VCCDA E5 VCCA C3 VCCA Y15 VCCDA E6 VCCA C34 VCCA Y17 VCCDA F19 VCCA J30 VCCA Y19 VCCDA F31 3-76 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 Pin Pin Pin RTAX4000S/SL Function Number RTAX4000S/SL Function Number RTAX4000S/SL Function Number VCCDA G30 VCCIB1 F29 VCCIB4 AD22 VCCDA G31 VCCIB1 K20 VCCIB4 AG20 VCCDA G6 VCCIB1 K23 VCCIB4 AG23 VCCDA H28 VCCIB1 K26 VCCIB4 AG26 VCCDA H29 VCCIB1 N20 VCCIB4 AL20 VCCDA J29 VCCIB1 N22 VCCIB4 AL23 VCCDA L18 VCCIB2 E35 VCCIB4 AL26 VCCDA L19 VCCIB2 H31 VCCIB4 AL29 VCCDA M22 VCCIB2 H35 VCCIB4 AR20 VCCDA N13 VCCIB2 K27 VCCIB4 AR23 VCCDA R10 VCCIB2 L31 VCCIB4 AR26 VCCDA V11 VCCIB2 L35 VCCIB4 AR29 VCCDA V26 VCCIB2 P27 VCCIB4 AR32 VCCIB0 B11 VCCIB2 P31 VCCIB5 AD15 VCCIB0 B14 VCCIB2 P35 VCCIB5 AD17 VCCIB0 B17 VCCIB2 R24 VCCIB5 AG11 VCCIB0 B5 VCCIB2 U24 VCCIB5 AG14 VCCIB0 B8 VCCIB2 U27 VCCIB5 AG17 VCCIB0 F11 VCCIB2 U31 VCCIB5 AL11 VCCIB0 F14 VCCIB2 U35 VCCIB5 AL14 VCCIB0 F17 VCCIB3 AB24 VCCIB5 AL17 VCCIB0 F8 VCCIB3 AC27 VCCIB5 AL8 VCCIB0 K11 VCCIB3 AC31 VCCIB5 AR11 VCCIB0 K14 VCCIB3 AC35 VCCIB5 AR14 VCCIB0 K17 VCCIB3 AF31 VCCIB5 AR17 VCCIB0 N15 VCCIB3 AF35 VCCIB5 AR5 VCCIB0 N17 VCCIB3 AG27 VCCIB5 AR8 VCCIB1 B20 VCCIB3 AJ31 VCCIB6 AB13 VCCIB1 B23 VCCIB3 AJ35 VCCIB6 AC10 VCCIB1 B26 VCCIB3 AM35 VCCIB6 AC2 VCCIB1 B29 VCCIB3 Y24 VCCIB6 AC6 VCCIB1 B32 VCCIB3 Y27 VCCIB6 AF2 VCCIB1 F20 VCCIB3 Y31 VCCIB6 AF6 VCCIB1 F23 VCCIB3 Y35 VCCIB6 AG10 VCCIB1 F26 VCCIB4 AD20 VCCIB6 AJ2 Revision 14 3-77 Package Pin Assignments CG1272/LG1272 Pin RTAX4000S/SL Function Number VCCIB6 AJ6 VCCIB6 AM2 VCCIB6 Y10 VCCIB6 Y13 VCCIB6 Y2 VCCIB6 Y6 VCCIB7 E2 VCCIB7 H2 VCCIB7 H6 VCCIB7 K10 VCCIB7 L2 VCCIB7 L6 VCCIB7 P10 VCCIB7 P2 VCCIB7 P6 VCCIB7 R13 VCCIB7 U10 VCCIB7 U13 VCCIB7 U2 VCCIB7 U6 VPUMP F32 3-78 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number Bank 0 IO17PB0F1 F13 IO35PB0F3 M19 IO00NB0F0 F10 IO18NB0F1 D14 IO36NB0F3 A13 IO00PB0F0 G10 IO18PB0F1 D13 IO36PB0F3 A12 IO01NB0F0 E7 IO19NB0F1 K15 IO37NB0F3 G18 IO01PB0F0 E8 IO19PB0F1 K16 IO37PB0F3 H18 IO02NB0F0 E9 IO20NB0F1 A11 IO38NB0F3 A17 IO02PB0F0 D9 IO20PB0F1 A10 IO38PB0F3 A16 IO03NB0F0 J12 IO21NB0F1 H15 IO39NB0F3 M16 IO03PB0F0 J11 IO21PB0F1 H14 IO39PB0F3 M17 IO04NB0F0 A7 IO22NB0F2 B7 IO40NB0F3 C18 IO04PB0F0 A6 IO22PB0F2 B6 IO40PB0F3 B18 IO05NB0F0 J10 IO23NB0F2 A8 IO41NB0F3/HCLKAN J18 IO05PB0F0 J9 IO23PB0F2 A9 IO41PB0F3/HCLKAP K18 IO06NB0F0 C7 IO24NB0F2 B13 IO42NB0F3/HCLKBN D18 IO06PB0F0 C6 IO24PB0F2 B12 IO42PB0F3/HCLKBP D17 IO07NB0F0 E12 IO25NB0F2 J16 Bank 1 IO07PB0F0 E11 IO25PB0F2 J15 IO43NB1F4/HCLKCN K19 IO08NB0F0 C10 IO26NB0F2 G15 IO43PB1F4/HCLKCP J19 IO08PB0F0 C9 IO26PB0F2 F15 IO44NB1F4/HCLKDN D20 IO09NB0F0 H13 IO27NB0F2 E15 IO44PB1F4/HCLKDP D19 IO09PB0F0 H12 IO27PB0F2 E14 IO45NB1F4 H19 IO10NB0F0 B4 IO28NB0F2 C15 IO45PB1F4 G19 IO10PB0F0 C4 IO28PB0F2 D15 IO46NB1F4 A21 IO11NB0F0 L13 IO29NB0F2 E18 IO46PB1F4 A20 IO11PB0F0 L12 IO29PB0F2 E17 IO47NB1F4 M20 IO12NB0F1 F12 IO30NB0F2 C13 IO47PB1F4 M21 IO12PB0F1 G12 IO30PB0F2 C12 IO48NB1F4 B19 IO13NB0F1 J14 IO31NB0F2 G16 IO48PB1F4 C19 IO13PB0F1 J13 IO31PB0F2 H16 IO49NB1F4 F22 IO14NB0F1 A5 IO32NB0F2 A14 IO49PB1F4 G22 IO14PB0F1 A4 IO32PB0F2 A15 IO50NB1F4 F21 IO15NB0F1 D12 IO33NB0F2 L16 IO50PB1F4 E21 IO15PB0F1 D11 IO33PB0F2 L15 IO51NB1F4 L22 IO16NB0F1 B10 IO34NB0F3 E16 IO51PB1F4 L21 IO16PB0F1 B9 IO34PB0F3 F16 IO52NB1F4 D22 IO17NB0F1 G13 IO35NB0F3 M18 IO52PB1F4 C22 Revision 14 3-79 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO53NB1F4 K22 IO71NB1F6 E29 IO88PB2F8 D33 IO53PB1F4 K21 IO71PB1F6 E30 IO89NB2F8 G33 IO54NB1F5 A22 IO72NB1F6 B31 IO89PB2F8 G32 IO54PB1F5 A23 IO72PB1F6 B30 IO90NB2F8 F35 IO55NB1F5 E20 IO73NB1F6 E26 IO90PB2F8 F36 IO55PB1F5 E19 IO73PB1F6 E25 IO91NB2F8 L33 IO56NB1F5 B22 IO74NB1F6 A31 IO91PB2F8 L32 IO56PB1F5 B21 IO74PB1F6 A30 IO92NB2F8 H32 IO57NB1F5 E23 IO75NB1F6 K25 IO92PB2F8 J32 IO57PB1F5 E22 IO75PB1F6 K24 IO93NB2F8 M32 IO58NB1F5 A25 IO76NB1F7 D30 IO93PB2F8 M31 IO58PB1F5 A24 IO76PB1F7 D29 IO94NB2F8 H36 IO59NB1F5 M24 IO77NB1F7 G27 IO94PB2F8 G36 IO59PB1F5 M23 IO77PB1F7 F27 IO95NB2F8 M28 IO60NB1F5 C28 IO78NB1F7 A33 IO95PB2F8 M27 IO60PB1F5 C27 IO78PB1F7 A32 IO96NB2F9 F34 IO61NB1F5 H23 IO79NB1F7 J26 IO96PB2F9 F33 IO61PB1F5 H22 IO79PB1F7 J25 IO97NB2F9 N30 IO62NB1F5 D24 IO80NB1F7 D32 IO97PB2F9 N29 IO62PB1F5 D23 IO80PB1F7 D31 IO98NB2F9 K33 IO63NB1F5 D26 IO81NB1F7 H27 IO98PB2F9 K32 IO63PB1F5 D25 IO81PB1F7 H26 IO99NB2F9 P29 IO64NB1F6 B25 IO82NB1F7 C33 IO99PB2F9 P28 IO64PB1F6 B24 IO82PB1F7 B33 IO100NB2F9 H33 IO65NB1F6 E27 IO83NB1F7 F28 IO100PB2F9 J33 IO65PB1F6 D27 IO83PB1F7 G28 IO101NB2F9 P33 IO66NB1F6 A27 IO84NB1F7 D28 IO101PB2F9 P32 IO66PB1F6 A26 IO84PB1F7 E28 IO102NB2F9 K36 IO67NB1F6 F24 IO85NB1F7 E31 IO102PB2F9 J36 IO67PB1F6 G24 IO85PB1F7 E32 IO103NB2F9 R29 IO68NB1F6 B28 Bank 2 IO103PB2F9 R28 IO68PB1F6 B27 IO86NB2F8 K31 IO104NB2F9 E36 IO69NB1F6 L24 IO86PB2F8 K30 IO104PB2F9 D36 IO69PB1F6 L25 IO87NB2F8 L29 IO105NB2F9 R31 IO70NB1F6 A28 IO87PB2F8 L28 IO105PB2F9 R30 IO70PB1F6 A29 IO88NB2F8 E33 IO106NB2F9 N34 3-80 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO106PB2F9 M34 IO124PB2F11 U32 IO142NB3F13 AE36 IO107NB2F10 R33 IO125NB2F11 V25 IO142PB3F13 AD36 IO107PB2F10 R32 IO125PB2F11 U25 IO143NB3F13 AA27 IO108NB2F10 K35 IO126NB2F11 V36 IO143PB3F13 AA28 IO108PB2F10 J35 IO126PB2F11 U36 IO144NB3F13 Y32 IO109NB2F10 T28 IO127NB2F11 V27 IO144PB3F13 W32 IO109PB2F10 T27 IO127PB2F11 V28 IO145NB3F13 AB25 IO110NB2F10 R35 IO128NB2F11 W34 IO145PB3F13 AB26 IO110PB2F10 R34 IO128PB2F11 V34 IO146NB3F13 AE34 IO111NB2F10 N28 Bank 3 IO146PB3F13 AD34 IO111PB2F10 N27 IO129NB3F12 AH33 IO147NB3F13 AB31 IO112NB2F10 N35 IO129PB3F12 AJ33 IO147PB3F13 AB30 IO112PB2F10 M35 IO130NB3F12 AA36 IO148NB3F13 AE35 IO113NB2F10 T32 IO130PB3F12 Y36 IO148PB3F13 AD35 IO113PB2F10 T31 IO131NB3F12 W30 IO149NB3F13 AF32 IO114NB2F10 M36 IO131PB3F12 W31 IO149PB3F13 AF33 IO114PB2F10 L36 IO132NB3F12 W35 IO150NB3F14 AG36 IO115NB2F10 T30 IO132PB3F12 V35 IO150PB3F14 AF36 IO115PB2F10 T29 IO133NB3F12 W27 IO151NB3F14 AC32 IO116NB2F10 U33 IO133PB3F12 W28 IO151PB3F14 AC33 IO116PB2F10 T33 IO134NB3F12 AC36 IO152NB3F14 AH34 IO117NB2F10 R26 IO134PB3F12 AB36 IO152PB3F14 AG34 IO117PB2F10 R25 IO135NB3F12 AA26 IO153NB3F14 AC29 IO118NB2F11 P36 IO135PB3F12 AA25 IO153PB3F14 AC28 IO118PB2F11 N36 IO136NB3F12 AA34 IO154NB3F14 AJ36 IO119NB2F11 U29 IO136PB3F12 AA35 IO154PB3F14 AH36 IO119PB2F11 U28 IO137NB3F12 Y28 IO155NB3F14 AJ32 IO120NB2F11 T35 IO137PB3F12 Y29 IO155PB3F14 AH32 IO120PB2F11 T34 IO138NB3F12 AA33 IO156NB3F14 AH35 IO121NB2F11 T26 IO138PB3F12 Y33 IO156PB3F14 AG35 IO121PB2F11 T25 IO139NB3F13 AB32 IO157NB3F14 AE26 IO122NB2F11 T36 IO139PB3F13 AB33 IO157PB3F14 AD26 IO122PB2F11 R36 IO140NB3F13 AB34 IO158NB3F14 AG32 IO123NB2F11 V31 IO140PB3F13 AB35 IO158PB3F14 AG33 IO123PB2F11 V30 IO141NB3F13 AA32 IO159NB3F14 AD32 IO124NB2F11 V32 IO141PB3F13 AA31 IO159PB3F14 AD31 Revision 14 3-81 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO160NB3F14 AK35 IO177PB4F16 AM29 IO195PB4F18 AP28 IO160PB3F14 AK36 IO178NB4F16 AH27 IO196NB4F18 AG21 IO161NB3F15 AC25 IO178PB4F16 AH28 IO196PB4F18 AG22 IO161PB3F15 AD25 IO179NB4F16 AT29 IO197NB4F18 AT24 IO162NB3F15 AL35 IO179PB4F16 AT28 IO197PB4F18 AT25 IO162PB3F15 AL36 IO180NB4F16 AF24 IO198NB4F18 AH21 IO163NB3F15 AE32 IO180PB4F16 AF25 IO198PB4F18 AH22 IO163PB3F15 AE31 IO181NB4F17 AT32 IO199NB4F18 AP24 IO164NB3F15 AN33 IO181PB4F17 AT33 IO199PB4F18 AP25 IO164PB3F15 AM33 IO182NB4F17 AK24 IO200NB4F18 AK22 IO165NB3F15 AD27 IO182PB4F17 AL24 IO200PB4F18 AL22 IO165PB3F15 AD28 IO183NB4F17 AM25 IO201NB4F18 AP22 IO166NB3F15 AN36 IO183PB4F17 AM26 IO201PB4F18 AN22 IO166PB3F15 AM36 IO184NB4F17 AG25 IO202NB4F18 AM22 IO167NB3F15 AF29 IO184PB4F17 AG24 IO202PB4F18 AM23 IO167PB3F15 AF28 IO185NB4F17 AN29 IO203NB4F19 AR27 IO168NB3F15 AN34 IO185PB4F17 AN30 IO203PB4F19 AR28 IO168PB3F15 AN35 IO186NB4F17 AL25 IO204NB4F19 AM21 IO169NB3F15 AK32 IO186PB4F17 AK25 IO204PB4F19 AL21 IO169PB3F15 AK31 IO187NB4F17 AR30 IO205NB4F19 AT23 IO170NB3F15 AG31 IO187PB4F17 AR31 IO205PB4F19 AT22 IO170PB3F15 AG30 IO188NB4F17 AF21 IO206NB4F19 AE21 Bank 4 IO188PB4F17 AF22 IO206PB4F19 AE20 IO171NB4F16 AN31 IO189NB4F17 AT26 IO207NB4F19 AR24 IO171PB4F16 AN32 IO189PB4F17 AT27 IO207PB4F19 AR25 IO172NB4F16 AJ26 IO190NB4F17 AE23 IO208NB4F19 AM19 IO172PB4F16 AJ27 IO190PB4F17 AE24 IO208PB4F19 AM20 IO173NB4F16 AR33 IO191NB4F17 AN25 IO209NB4F19 AT20 IO173PB4F16 AP33 IO191PB4F17 AN26 IO209PB4F19 AT21 IO174NB4F16 AL28 IO192NB4F17 AJ22 IO210NB4F19 AH20 IO174PB4F16 AK28 IO192PB4F17 AJ23 IO210PB4F19 AJ20 IO175NB4F16 AT30 IO193NB4F18 AN23 IO211NB4F19 AP19 IO175PB4F16 AT31 IO193PB4F18 AN24 IO211PB4F19 AR19 IO176NB4F16 AH25 IO194NB4F18 AL27 IO212NB4F19/CLKEN AH19 IO176PB4F16 AH26 IO194PB4F18 AK27 IO212PB4F19/CLKEP AG19 IO177NB4F16 AM30 IO195NB4F18 AP27 IO213NB4F19/CLKFN AN19 3-82 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO213PB4F19/CLKFP AN20 IO231NB5F21 AP12 IO249NB5F23 AT10 Bank 5 IO231PB5F21 AP13 IO249PB5F23 AT11 IO214NB5F20/CLKGN AG18 IO232NB5F21 AF16 IO250NB5F23 AG12 IO214PB5F20/CLKGP AH18 IO232PB5F21 AF15 IO250PB5F23 AF12 IO215NB5F20/CLKHN AN17 IO233NB5F21 AN13 IO251NB5F23 AR6 IO215PB5F20/CLKHP AN18 IO233PB5F21 AN14 IO251PB5F23 AR7 IO216NB5F20 AJ18 IO234NB5F21 AJ14 IO252NB5F23 AP4 IO216PB5F20 AK18 IO234PB5F21 AJ15 IO252PB5F23 AR4 IO217NB5F20 AR18 IO235NB5F22 AR9 IO253NB5F23 AT6 IO217PB5F20 AP18 IO235PB5F22 AR10 IO253PB5F23 AT7 IO218NB5F20 AH17 IO236NB5F22 AG13 IO254NB5F23 AJ10 IO218PB5F20 AJ17 IO236PB5F22 AF13 IO254PB5F23 AJ11 IO219NB5F20 AT16 IO237NB5F22 AP9 IO255NB5F23 AK9 IO219PB5F20 AT17 IO237PB5F22 AP10 IO255PB5F23 AL9 IO220NB5F20 AM17 IO238NB5F22 AM8 IO256NB5F23 AH9 IO220PB5F20 AM18 IO238PB5F22 AM7 IO256PB5F23 AH10 IO221NB5F20 AR15 IO239NB5F22 AM11 Bank 6 IO221PB5F20 AR16 IO239PB5F22 AM12 IO257NB6F24 AH7 IO222NB5F20 AL16 IO240NB5F22 AH11 IO257PB6F24 AH6 IO222PB5F20 AM16 IO240PB5F22 AH12 IO258NB6F24 AG7 IO223NB5F21 AR12 IO241NB5F22 AT12 IO258PB6F24 AG6 IO223PB5F21 AR13 IO241PB5F22 AT13 IO259NB6F24 AN2 IO224NB5F21 AE17 IO242NB5F22 AE13 IO259PB6F24 AN3 IO224PB5F21 AE16 IO242PB5F22 AE14 IO260NB6F24 AE7 IO225NB5F21 AT9 IO243NB5F22 AM10 IO260PB6F24 AE8 IO225PB5F21 AT8 IO243PB5F22 AN10 IO261NB6F24 AJ1 IO226NB5F21 AG15 IO244NB5F22 AN9 IO261PB6F24 AK1 IO226PB5F21 AG16 IO244PB5F22 AM9 IO262NB6F24 AE10 IO227NB5F21 AH15 IO245NB5F23 AN7 IO262PB6F24 AE9 IO227PB5F21 AH16 IO245PB5F23 AN8 IO263NB6F24 AM4 IO228NB5F21 AM14 IO246NB5F23 AK12 IO263PB6F24 AN4 IO228PB5F21 AM15 IO246PB5F23 AL12 IO264NB6F24 AE5 IO229NB5F21 AN15 IO247NB5F23 AN5 IO264PB6F24 AE6 IO229PB5F21 AP15 IO247PB5F23 AN6 IO265NB6F24 AG1 IO230NB5F21 AL15 IO248NB5F23 AJ12 IO265PB6F24 AH1 IO230PB5F21 AK15 IO248PB5F23 AJ13 IO266NB6F24 AD8 Revision 14 3-83 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO266PB6F24 AD7 IO284PB6F26 AD12 IO302NB7F28 R12 IO267NB6F25 AM1 IO285NB6F26 AB2 IO302PB7F28 R11 IO267PB6F25 AN1 IO285PB6F26 AB3 IO303NB7F28 T3 IO268NB6F25 AD5 IO286NB6F26 AD3 IO303PB7F28 T2 IO268PB6F25 AD6 IO286PB6F26 AE3 IO304NB7F28 U5 IO269NB6F25 AF4 IO287NB6F26 AG2 IO304PB7F28 V5 IO269PB6F25 AF5 IO287PB6F26 AH2 IO305NB7F28 N1 IO270NB6F25 AD9 IO288NB6F26 Y8 IO305PB7F28 P1 IO270PB6F25 AD10 IO288PB6F26 Y9 IO306NB7F28 N12 IO271NB6F25 AJ5 IO289NB6F27 AA1 IO306PB7F28 P12 IO271PB6F25 AH5 IO289PB6F27 AB1 IO307NB7F28 R3 IO272NB6F25 AF8 IO290NB6F27 AA12 IO307PB7F28 R2 IO272PB6F25 AF9 IO290PB6F27 AB12 IO308NB7F28 T10 IO273NB6F25 AE1 IO291NB6F27 AA5 IO308PB7F28 T9 IO273PB6F25 AF1 IO291PB6F27 AA6 IO309NB7F28 V3 IO274NB6F25 AB6 IO292NB6F27 AB4 IO309PB7F28 W3 IO274PB6F25 AB7 IO292PB6F27 AB5 IO310NB7F29 U9 IO275NB6F25 AL1 IO293NB6F27 AA2 IO310PB7F29 U8 IO275PB6F25 AL2 IO293PB6F27 AA3 IO311NB7F29 V7 IO276NB6F25 AA11 IO294NB6F27 W12 IO311PB7F29 V6 IO276PB6F25 AB11 IO294PB6F27 Y12 IO312NB7F29 M11 IO277NB6F25 AK4 IO295NB6F27 AD2 IO312PB7F29 N11 IO277PB6F25 AK5 IO295PB6F27 AE2 IO313NB7F29 T4 IO278NB6F26 AC4 IO296NB6F27 W10 IO313PB7F29 U4 IO278PB6F26 AC5 IO296PB6F27 W9 IO314NB7F29 T11 IO279NB6F26 AG3 IO297NB6F27 W1 IO314PB7F29 T12 IO279PB6F26 AH3 IO297PB6F27 Y1 IO315NB7F29 T5 IO280NB6F26 AE11 IO298NB6F27 W5 IO315PB7F29 T6 IO280PB6F26 AD11 IO298PB6F27 Y5 IO316NB7F29 R5 IO281NB6F26 AC1 IO299NB6F27 V2 IO316PB7F29 R4 IO281PB6F26 AD1 IO299PB6F27 W2 IO317NB7F29 M2 IO282NB6F26 AA7 Bank 7 IO317PB7F29 N2 IO282PB6F26 AA8 IO300NB7F28 V9 IO318NB7F29 R8 IO283NB6F26 AK2 IO300PB7F28 V10 IO318PB7F29 R9 IO283PB6F26 AK3 IO301NB7F28 U1 IO319NB7F29 J2 IO284NB6F26 AC12 IO301PB7F28 V1 IO319PB7F29 K2 3-84 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number IO320NB7F29 R6 IO338NB7F31 G4 GND AD18 IO320PB7F29 R7 IO338PB7F31 G5 GND AD19 IO321NB7F30 M3 IO339NB7F31 E4 GND AD21 IO321PB7F30 N3 IO339PB7F31 F4 GND AD23 IO322NB7F30 N10 IO340NB7F31 K8 GND AF3 IO322PB7F30 N9 IO340PB7F31 K9 GND AF7 IO323NB7F30 P5 IO341NB7F31 D4 GND AF10 IO323PB7F30 P4 IO341PB7F31 D3 GND AF11 IO324NB7F30 M5 Dedicated I/O GND AF14 IO324PB7F30 M6 GND AA13 GND AF17 IO325NB7F30 L1 GND AA15 GND AF20 IO325PB7F30 M1 GND AA17 GND AF23 IO326NB7F30 N5 GND AA19 GND AF26 IO326PB7F30 N6 GND AA21 GND AF27 IO327NB7F30 G2 GND AA23 GND AF30 IO327PB7F30 F2 GND AA24 GND AF34 IO328NB7F30 L5 GND AB14 GND AJ3 IO328PB7F30 L4 GND AB16 GND AJ7 IO329NB7F30 G3 GND AB18 GND AJ29 IO329PB7F30 F3 GND AB20 GND AJ30 IO330NB7F30 M7 GND AB22 GND AJ34 IO330PB7F30 M8 GND AC3 GND AK6 IO331NB7F30 H4 GND AC7 GND AK8 IO331PB7F30 J4 GND AC11 GND AK11 IO332NB7F31 K5 GND AC13 GND AK14 IO332PB7F31 K4 GND AC15 GND AK17 IO333NB7F31 J1 GND AC17 GND AK20 IO333PB7F31 K1 GND AC19 GND AK23 IO334NB7F31 H5 GND AC21 GND AK26 IO334PB7F31 J5 GND AC23 GND AK29 IO335NB7F31 E1 GND AC24 GND AL7 IO335PB7F31 F1 GND AC26 GND AL18 IO336NB7F31 M10 GND AC30 GND AL31 IO336PB7F31 M9 GND AC34 GND AM3 IO337NB7F31 G1 GND AD14 GND AM34 IO337PB7F31 H1 GND AD16 GND AP2 Revision 14 3-85 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number GND AP5 GND G23 GND P22 GND AP8 GND G26 GND P24 GND AP11 GND G29 GND P26 GND AP14 GND H3 GND P30 GND AP17 GND H7 GND P34 GND AP20 GND H30 GND R15 GND AP23 GND H34 GND R17 GND AP26 GND J8 GND R19 GND AP29 GND J31 GND R21 GND AP32 GND L3 GND R23 GND AP35 GND L7 GND T13 GND AR3 GND L10 GND T14 GND AR34 GND L11 GND T16 GND B3 GND L14 GND T18 GND B34 GND L17 GND T20 GND C2 GND L20 GND T22 GND C5 GND L23 GND T24 GND C8 GND L26 GND U3 GND C11 GND L27 GND U7 GND C14 GND L30 GND U11 GND C17 GND L34 GND U15 GND C20 GND M15 GND U17 GND C23 GND N14 GND U19 GND C26 GND N16 GND U21 GND C29 GND N18 GND U23 GND C32 GND N19 GND U26 GND C35 GND N21 GND U30 GND E3 GND N23 GND U34 GND E34 GND P3 GND V13 GND F7 GND P7 GND V14 GND F30 GND P11 GND V16 GND G8 GND P13 GND V18 GND G11 GND P14 GND V20 GND G14 GND P16 GND V22 GND G17 GND P18 GND V24 GND G20 GND P20 GND V33 3-86 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number GND W4 NC AD33 NC AJ8 GND W13 NC AD4 NC AK10 GND W15 NC AE12 NC AK13 GND W17 NC AE15 NC AK16 GND W19 NC AE18 NC AK19 GND W21 NC AE19 NC AK21 GND W23 NC AE22 NC AK33 GND W24 NC AE25 NC AK34 GND Y3 NC AE27 NC AK7 GND Y7 NC AE28 NC AL10 GND Y11 NC AE29 NC AL13 GND Y14 NC AE30 NC AL3 GND Y16 NC AE33 NC AL30 GND Y18 NC AE4 NC AL33 GND Y20 NC AG28 NC AL34 GND Y22 NC AG29 NC AL4 GND Y26 NC AG4 NC AL6 GND Y30 NC AG5 NC AM24 GND Y34 NC AG8 NC AM27 NC A19 NC AG9 NC AM28 NC AA10 NC AH13 NC AM31 NC AA29 NC AH14 NC AM5 NC AA30 NC AH23 NC AN11 NC AA4 NC AH24 NC AN12 NC AA9 NC AH29 NC AN27 NC AB10 NC AH30 NC AN28 NC AB28 NC AH31 NC AP30 NC AB29 NC AH4 NC AP31 NC AB8 NC AH8 NC AP6 NC AB9 NC AJ16 NC AP7 NC AC8 NC AJ19 NC AR21 NC AC9 NC AJ21 NC AR22 NC AD13 NC AJ24 NC AT14 NC AD24 NC AJ25 NC AT15 NC AD29 NC AJ28 NC AT18 NC AD30 NC AJ4 NC AT4 Revision 14 3-87 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number NC AT5 NC H29 NC N26 NC B15 NC J17 NC N31 NC B16 NC J20 NC N32 NC C24 NC J21 NC N33 NC C25 NC J22 NC N4 NC C30 NC J23 NC N7 NC C31 NC J24 NC N8 NC D1 NC J27 NC P25 NC D10 NC J28 NC P8 NC D2 NC J29 NC P9 NC D34 NC J3 NC R1 NC D35 NC J34 NC R10 NC D5 NC J6 NC R27 NC D6 NC J7 NC T1 NC D7 NC K12 NC T7 NC D8 NC K13 NC T8 NC E10 NC K28 NC U12 NC E13 NC K29 NC V12 NC E24 NC K3 NC V26 NC E6 NC K34 NC V29 NC F25 NC K6 NC V4 NC F31 NC K7 NC V8 NC F9 NC L18 NC W11 NC G21 NC L8 NC W25 NC G25 NC L9 NC W26 NC G30 NC M13 NC W29 NC G34 NC M14 NC W33 NC G35 NC M25 NC W36 NC G9 NC M26 NC W6 NC H10 NC M29 NC W7 NC H11 NC M30 NC W8 NC H17 NC M33 NC Y25 NC H20 NC M4 NC Y4 NC H21 NC N13 PRA F18 NC H24 NC N24 PRB A18 NC H25 NC N25 PRC AL19 3-88 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number PRD AT19 VCCA R18 VCCDA AF19 TCK H8 VCCA R20 VCCDA AN21 TDI F6 VCCA R22 VCCDA AF18 TDO H9 VCCA T15 VCCDA AM32 TMS F5 VCCA T17 VCCDA AK30 TRST G7 VCCA T19 VCCDA AB27 VCCA M12 VCCA T21 VCCDA G31 VCCA AL5 VCCA T23 VCCDA H28 VCCA AL32 VCCA U14 VCCDA C21 VCCA J30 VCCA U16 VCCDA M22 VCCA AA14 VCCA U18 VCCDA D21 VCCA AA16 VCCA U20 VCCDA L19 VCCA AA18 VCCA U22 VCCDA F19 VCCA AA20 VCCA V15 VCCDA D16 VCCA AA22 VCCA V17 VCCDA C16 VCCA AB15 VCCA V19 VCCDA E5 VCCA AB17 VCCA V21 VCCIB0 B11 VCCA AB19 VCCA V23 VCCIB0 B14 VCCA AB21 VCCA W14 VCCIB0 B17 VCCA AB23 VCCA W16 VCCIB0 B5 VCCA AC14 VCCA W18 VCCIB0 B8 VCCA AC16 VCCA W20 VCCIB0 F11 VCCA AC18 VCCA W22 VCCIB0 F14 VCCA AC20 VCCA Y15 VCCIB0 F17 VCCA AC22 VCCA Y17 VCCIB0 F8 VCCA AP3 VCCA Y19 VCCIB0 K11 VCCA AP34 VCCA Y21 VCCIB0 K14 VCCA C3 VCCA Y23 VCCIB0 K17 VCCA C34 VCCDA G6 VCCIB0 N15 VCCA P15 VCCDA V11 VCCIB0 N17 VCCA P17 VCCDA AJ9 VCCIB1 B20 VCCA P19 VCCDA AM6 VCCIB1 B23 VCCA P21 VCCDA AP16 VCCIB1 B26 VCCA P23 VCCDA AM13 VCCIB1 B29 VCCA R14 VCCDA AN16 VCCIB1 B32 VCCA R16 VCCDA AP21 VCCIB1 F20 Revision 14 3-89 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX2000D Function Pin Number RTAX2000D Function Pin Number RTAX2000D Function Pin Number VCCIB1 F23 VCCIB4 AD20 VCCIB6 AJ6 VCCIB1 F26 VCCIB4 AD22 VCCIB6 AM2 VCCIB1 F29 VCCIB4 AG20 VCCIB6 Y10 VCCIB1 K20 VCCIB4 AG23 VCCIB6 Y13 VCCIB1 K23 VCCIB4 AG26 VCCIB6 Y2 VCCIB1 K26 VCCIB4 AL20 VCCIB6 Y6 VCCIB1 N20 VCCIB4 AL23 VCCIB7 E2 VCCIB1 N22 VCCIB4 AL26 VCCIB7 H2 VCCIB2 E35 VCCIB4 AL29 VCCIB7 H6 VCCIB2 H31 VCCIB4 AR20 VCCIB7 K10 VCCIB2 H35 VCCIB4 AR23 VCCIB7 L2 VCCIB2 K27 VCCIB4 AR26 VCCIB7 L6 VCCIB2 L31 VCCIB4 AR29 VCCIB7 P10 VCCIB2 L35 VCCIB4 AR32 VCCIB7 P2 VCCIB2 P27 VCCIB5 AD15 VCCIB7 P6 VCCIB2 P31 VCCIB5 AD17 VCCIB7 R13 VCCIB2 P35 VCCIB5 AG11 VCCIB7 U10 VCCIB2 R24 VCCIB5 AG14 VCCIB7 U13 VCCIB2 U24 VCCIB5 AG17 VCCIB7 U2 VCCIB2 U27 VCCIB5 AL11 VCCIB7 U6 VCCIB2 U31 VCCIB5 AL14 VPUMP F32 VCCIB2 U35 VCCIB5 AL17 VCCIB3 AB24 VCCIB5 AL8 VCCIB3 AC27 VCCIB5 AR11 VCCIB3 AC31 VCCIB5 AR14 VCCIB3 AC35 VCCIB5 AR17 VCCIB3 AF31 VCCIB5 AR5 VCCIB3 AF35 VCCIB5 AR8 VCCIB3 AG27 VCCIB6 AB13 VCCIB3 AJ31 VCCIB6 AC10 VCCIB3 AJ35 VCCIB6 AC2 VCCIB3 AM35 VCCIB6 AC6 VCCIB3 Y24 VCCIB6 AF2 VCCIB3 Y27 VCCIB6 AF6 VCCIB3 Y31 VCCIB6 AG10 VCCIB3 Y35 VCCIB6 AJ2 3-90 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number Bank 0 IO17PB0F1 E11 IO35PB0F3 D15 IO00NB0F0 E9 IO18NB0F1 K13 IO36NB0F3 J16 IO00PB0F0 D9 IO18PB0F1 K12 IO36PB0F3 J15 IO01NB0F0 D8 IO19NB0F1 B4 IO37NB0F3 A11 IO01PB0F0 D7 IO19PB0F1 C4 IO37PB0F3 A10 IO02NB0F0 J10 IO20NB0F1 H13 IO38NB0F3 H15 IO02PB0F0 J9 IO20PB0F1 H12 IO38PB0F3 H14 IO03NB0F0 E7 IO21NB0F2 C13 IO39NB0F3 B16 IO03PB0F0 E8 IO21PB0F2 C12 IO39PB0F3 B15 IO04NB0F0 F9 IO22NB0F2 M14 IO40NB0F3 M16 IO04PB0F0 G9 IO22PB0F2 M13 IO40PB0F3 M17 IO05NB0F0 B7 IO23NB0F2 B10 IO41NB0F3 E16 IO05PB0F0 B6 IO23PB0F2 B9 IO41PB0F3 F16 IO06NB0F0 L13 IO24NB0F2 J14 IO42NB0F4 H17 IO06PB0F0 L12 IO24PB0F2 J13 IO42PB0F4 J17 IO07NB0F0 C7 IO25NB0F2 A8 IO43NB0F4 A14 IO07PB0F0 C6 IO25PB0F2 A9 IO43PB0F4 A15 IO08NB0F0 F10 IO26NB0F2 G13 IO44NB0F4 G16 IO08PB0F0 G10 IO26PB0F2 F13 IO44PB0F4 H16 IO09NB0F0 D10 IO27NB0F2 D14 IO45NB0F4 A17 IO09PB0F0 E10 IO27PB0F2 D13 IO45PB0F4 A16 IO10NB0F0 H11 IO28NB0F2 L16 IO46NB0F4 M18 IO10PB0F0 H10 IO28PB0F2 L15 IO46PB0F4 M19 IO11NB0F0 A5 IO29NB0F2 B13 IO47NB0F4 E18 IO11PB0F0 A4 IO29PB0F2 B12 IO47PB0F4 E17 IO12NB0F1 D6 IO30NB0F2 C10 IO48NB0F4 G18 IO12PB0F1 D5 IO30PB0F2 C9 IO48PB0F4 H18 IO13NB0F1 A7 IO31NB0F2 E15 IO49NB0F4 C18 IO13PB0F1 A6 IO31PB0F2 E14 IO49PB0F4 B18 IO14NB0F1 J12 IO32NB0F2 K15 IO50NB0F4/HCLKAN J18 IO14PB0F1 J11 IO32PB0F2 K16 IO50PB0F4/HCLKAP K18 IO15NB0F1 D12 IO33NB0F3 A13 IO51NB0F4/HCLKBN D18 IO15PB0F1 D11 IO33PB0F3 A12 IO51PB0F4/HCLKBP D17 IO16NB0F1 F12 IO34NB0F3 G15 Bank 1 IO16PB0F1 G12 IO34PB0F3 F15 IO52NB1F6/HCLKCN K19 IO17NB0F1 E12 IO35NB0F3 C15 IO52PB1F6/HCLKCP J19 Revision 14 3-91 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO53NB1F6/HCLKDN D20 IO71NB1F7 E23 IO89NB1F9 D26 IO53PB1F6/HCLKDP D19 IO71PB1F7 E22 IO89PB1F9 D25 IO54NB1F6 H19 IO72NB1F8 L22 IO90NB1F9 E31 IO54PB1F6 G19 IO72PB1F8 L21 IO90PB1F9 E32 IO55NB1F6 B19 IO73NB1F8 A25 IO91NB1F9 A31 IO55PB1F6 C19 IO73PB1F8 A24 IO91PB1F9 A30 IO56NB1F6 M20 IO74NB1F8 C28 IO92NB1F9 H27 IO56PB1F6 M21 IO74PB1F8 C27 IO92PB1F9 H26 IO57NB1F6 E20 IO75NB1F8 D24 IO93NB1F9 C33 IO57PB1F6 E19 IO75PB1F8 D23 IO93PB1F9 B33 IO58NB1F6 H21 IO76NB1F8 J24 IO94NB1F10 G27 IO58PB1F6 G21 IO76PB1F8 J23 IO94PB1F10 F27 IO59NB1F6 A21 IO77NB1F8 B25 IO95NB1F10 E27 IO59PB1F6 A20 IO77PB1F8 B24 IO95PB1F10 D27 IO60NB1F7 H20 IO78NB1F8 F24 IO96NB1F10 L24 IO60PB1F7 J20 IO78PB1F8 G24 IO96PB1F10 L25 IO61NB1F7 A22 IO79NB1F8 A28 IO97NB1F10 C31 IO61PB1F7 A23 IO79PB1F8 A29 IO97PB1F10 C30 IO62NB1F7 D32 IO80NB1F8 M24 IO98NB1F10 F28 IO62PB1F7 D31 IO80PB1F8 M23 IO98PB1F10 G28 IO63NB1F7 F21 IO81NB1F8 B28 IO99NB1F10 B31 IO63PB1F7 E21 IO81PB1F8 B27 IO99PB1F10 B30 IO64NB1F7 J22 IO82NB1F9 H25 IO100NB1F10 J28 IO64PB1F7 J21 IO82PB1F9 H24 IO100PB1F10 J27 IO65NB1F7 B22 IO83NB1F9 C25 IO101NB1F10 E29 IO65PB1F7 B21 IO83PB1F9 C24 IO101PB1F10 E30 IO66NB1F7 H23 IO84NB1F9 K25 IO102NB1F10 D28 IO66PB1F7 H22 IO84PB1F9 K24 IO102PB1F10 E28 IO67NB1F7 D22 IO85NB1F9 A33 IO103NB1F10 D30 IO67PB1F7 C22 IO85PB1F9 A32 IO103PB1F10 D29 IO68NB1F7 K22 IO86NB1F9 G25 Bank 2 IO68PB1F7 K21 IO86PB1F9 F25 IO104NB2F12 L29 IO69NB1F7 A27 IO87NB1F9 E26 IO104PB2F12 L28 IO69PB1F7 A26 IO87PB1F9 E25 IO105NB2F12 D35 IO70NB1F7 F22 IO88NB1F9 J26 IO105PB2F12 D34 IO70PB1F7 G22 IO88PB1F9 J25 IO106NB2F12 H33 3-92 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO106PB2F12 J33 IO124PB2F14 J35 IO142PB2F16 R34 IO107NB2F12 F34 IO125NB2F14 P25 IO143NB2F16 T32 IO107PB2F12 F33 IO125PB2F14 N25 IO143PB2F16 T31 IO108NB2F12 G33 IO126NB2F14 H36 IO144NB2F16 T35 IO108PB2F12 G32 IO126PB2F14 G36 IO144PB2F16 T34 IO109NB2F12 M28 IO127NB2F14 N32 IO145NB2F16 T30 IO109PB2F12 M27 IO127PB2F14 N31 IO145PB2F16 T29 IO110NB2F12 K33 IO128NB2F14 N34 IO146NB2F16 R33 IO110PB2F12 K32 IO128PB2F14 M34 IO146PB2F16 R32 IO111NB2F12 K31 IO129NB2F14 P29 IO147NB2F16 V25 IO111PB2F12 K30 IO129PB2F14 P28 IO147PB2F16 U25 IO112NB2F13 K34 IO130NB2F15 N33 IO148NB2F17 T36 IO112PB2F13 J34 IO130PB2F15 M33 IO148PB2F17 R36 IO113NB2F13 N26 IO131NB2F15 R26 IO149NB2F17 U29 IO113PB2F13 M26 IO131PB2F15 R25 IO149PB2F17 U28 IO114NB2F13 K28 IO132NB2F15 K36 IO150NB2F17 U33 IO114PB2F13 K29 IO132PB2F15 J36 IO150PB2F17 T33 IO115NB2F13 H32 IO133NB2F15 R29 IO151NB2F17 W25 IO115PB2F13 J32 IO133PB2F15 R28 IO151PB2F17 Y25 IO116NB2F13 G35 IO134NB2F15 N35 IO152NB2F17 V36 IO116PB2F13 G34 IO134PB2F15 M35 IO152PB2F17 U36 IO117NB2F13 M29 IO135NB2F15 F35 IO153NB2F17 V31 IO117PB2F13 M30 IO135PB2F15 F36 IO153PB2F17 V30 IO118NB2F13 E33 IO136NB2F15 M36 IO154NB2F17 V32 IO118PB2F13 D33 IO136PB2F15 L36 IO154PB2F17 U32 IO119NB2F13 M32 IO137NB2F15 T26 IO155NB2F17 V27 IO119PB2F13 M31 IO137PB2F15 T25 IO155PB2F17 V28 IO120NB2F13 E36 IO138NB2F15 P33 IO156NB2F17 W34 IO120PB2F13 D36 IO138PB2F15 P32 IO156PB2F17 V34 IO121NB2F14 N28 IO139NB2F16 R31 Bank 3 IO121PB2F14 N27 IO139PB2F16 R30 IO157NB3F18 W29 IO122NB2F14 L33 IO140NB2F16 P36 IO157PB3F18 V29 IO122PB2F14 L32 IO140PB2F16 N36 IO158NB3F18 W35 IO123NB2F14 N30 IO141NB2F16 T28 IO158PB3F18 V35 IO123PB2F14 N29 IO141PB2F16 T27 IO159NB3F18 W30 IO124NB2F14 K35 IO142NB2F16 R35 IO159PB3F18 W31 Revision 14 3-93 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO160NB3F18 AA36 IO178NB3F20 AC32 IO196NB3F22 AK34 IO160PB3F18 Y36 IO178PB3F20 AC33 IO196PB3F22 AL34 IO161NB3F18 W27 IO179NB3F20 AB29 IO197NB3F22 AE28 IO161PB3F18 W28 IO179PB3F20 AB28 IO197PB3F22 AE27 IO162NB3F18 Y32 IO180NB3F20 AJ36 IO198NB3F22 AN33 IO162PB3F18 W32 IO180PB3F20 AH36 IO198PB3F22 AM33 IO163NB3F18 Y28 IO181NB3F20 AC25 IO199NB3F22 AH31 IO163PB3F18 Y29 IO181PB3F20 AD25 IO199PB3F22 AH30 IO164NB3F18 AC36 IO182NB3F20 AE35 IO200NB3F22 AH34 IO164PB3F18 AB36 IO182PB3F20 AD35 IO200PB3F22 AG34 IO165NB3F18 AA26 IO183NB3F20 AC29 IO201NB3F22 AF29 IO165PB3F18 AA25 IO183PB3F20 AC28 IO201PB3F22 AF28 IO166NB3F19 AA33 IO184NB3F21 AE34 IO202NB3F23 AG32 IO166PB3F19 Y33 IO184PB3F21 AD34 IO202PB3F23 AG33 IO167NB3F19 AA32 IO185NB3F21 AE26 IO203NB3F23 AG31 IO167PB3F19 AA31 IO185PB3F21 AD26 IO203PB3F23 AG30 IO168NB3F19 AA34 IO186NB3F21 AE33 IO204NB3F23 AL33 IO168PB3F19 AA35 IO186PB3F21 AD33 IO204PB3F23 AK33 IO169NB3F19 AA29 IO187NB3F21 AD30 IO205NB3F23 AK32 IO169PB3F19 AA30 IO187PB3F21 AD29 IO205PB3F23 AK31 IO170NB3F19 AB32 IO188NB3F21 AH35 IO206NB3F23 AH33 IO170PB3F19 AB33 IO188PB3F21 AG35 IO206PB3F23 AJ33 IO171NB3F19 AB31 IO189NB3F21 AD32 IO207NB3F23 AN34 IO171PB3F19 AB30 IO189PB3F21 AD31 IO207PB3F23 AN35 IO172NB3F19 AE36 IO190NB3F21 AK35 IO208NB3F23 AG29 IO172PB3F19 AD36 IO190PB3F21 AK36 IO208PB3F23 AG28 IO173NB3F19 AA27 IO191NB3F21 AE32 IO209NB3F23 AJ32 IO173PB3F19 AA28 IO191PB3F21 AE31 IO209PB3F23 AH32 IO174NB3F19 AB34 IO192NB3F21 AN36 Bank 4 IO174PB3F19 AB35 IO192PB3F21 AM36 IO210NB4F24 AM28 IO175NB3F20 AL35 IO193NB3F22 AD27 IO210PB4F24 AN28 IO175PB3F20 AL36 IO193PB3F22 AD28 IO211NB4F24 AN29 IO176NB3F20 AG36 IO194NB3F22 AF32 IO211PB4F24 AN30 IO176PB3F20 AF36 IO194PB3F22 AF33 IO212NB4F24 AH27 IO177NB3F20 AB25 IO195NB3F22 AE30 IO212PB4F24 AH28 IO177PB3F20 AB26 IO195PB3F22 AE29 IO213NB4F24 AM30 3-94 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO213PB4F24 AM29 IO231PB4F25 AT27 IO249PB4F27 AR22 IO214NB4F24 AL28 IO232NB4F26 AE23 IO250NB4F27 AE21 IO214PB4F24 AK28 IO232PB4F26 AE24 IO250PB4F27 AE20 IO215NB4F24 AR30 IO233NB4F26 AR27 IO251NB4F27 AM21 IO215PB4F24 AR31 IO233PB4F26 AR28 IO251PB4F27 AL21 IO216NB4F24 AF24 IO234NB4F26 AH23 IO252NB4F27 AH20 IO216PB4F24 AF25 IO234PB4F26 AH24 IO252PB4F27 AJ20 IO217NB4F24 AP30 IO235NB4F26 AT29 IO253NB4F27 AT23 IO217PB4F24 AP31 IO235PB4F26 AT28 IO253PB4F27 AT22 IO218NB4F24 AL27 IO236NB4F26 AK24 IO254NB4F28 AK21 IO218PB4F24 AK27 IO236PB4F26 AL24 IO254PB4F28 AJ21 IO219NB4F24 AN27 IO237NB4F26 AR24 IO255NB4F28 AT20 IO219PB4F24 AM27 IO237PB4F26 AR25 IO255PB4F28 AT21 IO220NB4F25 AJ26 IO238NB4F26 AF21 IO256NB4F28 AE18 IO220PB4F25 AJ27 IO238PB4F26 AF22 IO256PB4F28 AE19 IO221NB4F25 AT32 IO239NB4F26 AP24 IO257NB4F28 AM19 IO221PB4F25 AT33 IO239PB4F26 AP25 IO257PB4F28 AM20 IO222NB4F25 AN31 IO240NB4F26 AP27 IO258NB4F28 AK19 IO222PB4F25 AN32 IO240PB4F26 AP28 IO258PB4F28 AJ19 IO223NB4F25 AT30 IO241NB4F26 AN23 IO259NB4F28 AP19 IO223PB4F25 AT31 IO241PB4F26 AN24 IO259PB4F28 AR19 IO224NB4F25 AH25 IO242NB4F27 AG21 IO260NB4F28/CLKEN AH19 IO224PB4F25 AH26 IO242PB4F27 AG22 IO260PB4F28/CLKEP AG19 IO225NB4F25 AN25 IO243NB4F27 AM22 IO261NB4F28/CLKFN AN19 IO225PB4F25 AN26 IO243PB4F27 AM23 IO261PB4F28/CLKFP AN20 IO226NB4F25 AL25 IO244NB4F27 AK22 Bank 5 IO226PB4F25 AK25 IO244PB4F27 AL22 IO262NB5F30/CLKGN AG18 IO227NB4F25 AM25 IO245NB4F27 AT24 IO262PB5F30/CLKGP AH18 IO227PB4F25 AM26 IO245PB4F27 AT25 IO263NB5F30/CLKHN AN17 IO228NB4F25 AG25 IO246NB4F27 AH21 IO263PB5F30/CLKHP AN18 IO228PB4F25 AG24 IO246PB4F27 AH22 IO264NB5F30 AJ18 IO229NB4F25 AR33 IO247NB4F27 AP22 IO264PB5F30 AK18 IO229PB4F25 AP33 IO247PB4F27 AN22 IO265NB5F30 AR18 IO230NB4F25 AJ24 IO248NB4F27 AJ22 IO265PB5F30 AP18 IO230PB4F25 AJ25 IO248PB4F27 AJ23 IO266NB5F30 AE17 IO231NB4F25 AT26 IO249NB4F27 AR21 IO266PB5F30 AE16 Revision 14 3-95 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO267NB5F30 AM17 IO285NB5F32 AN13 IO303NB5F34 AT4 IO267PB5F30 AM18 IO285PB5F32 AN14 IO303PB5F34 AT5 IO268NB5F30 AJ16 IO286NB5F32 AN9 IO304NB5F34 AJ10 IO268PB5F30 AK16 IO286PB5F32 AM9 IO304PB5F34 AJ11 IO269NB5F30 AT16 IO287NB5F32 AR12 IO305NB5F34 AM10 IO269PB5F30 AT17 IO287PB5F32 AR13 IO305PB5F34 AN10 IO270NB5F30 AF16 IO288NB5F32 AL13 IO306NB5F34 AK10 IO270PB5F30 AF15 IO288PB5F32 AK13 IO306PB5F34 AL10 IO271NB5F30 AT15 IO289NB5F32 AT9 IO307NB5F34 AP6 IO271PB5F30 AT14 IO289PB5F32 AT8 IO307PB5F34 AP7 IO272NB5F31 AH17 IO290NB5F32 AH13 IO308NB5F34 AK9 IO272PB5F31 AJ17 IO290PB5F32 AH14 IO308PB5F34 AL9 IO273NB5F31 AL16 IO291NB5F32 AR9 IO309NB5F34 AR6 IO273PB5F31 AM16 IO291PB5F32 AR10 IO309PB5F34 AR7 IO274NB5F31 AH15 IO292NB5F32 AJ12 IO310NB5F34 AH9 IO274PB5F31 AH16 IO292PB5F32 AJ13 IO310PB5F34 AH10 IO275NB5F31 AR15 IO293NB5F33 AP12 IO311NB5F34 AM8 IO275PB5F31 AR16 IO293PB5F33 AP13 IO311PB5F34 AM7 IO276NB5F31 AJ14 IO294NB5F33 AG13 IO312NB5F34 AG9 IO276PB5F31 AJ15 IO294PB5F33 AF13 IO312PB5F34 AG8 IO277NB5F31 AN15 IO295NB5F33 AP4 IO313NB5F34 AN7 IO277PB5F31 AP15 IO295PB5F33 AR4 IO313PB5F34 AN8 IO278NB5F31 AG15 IO296NB5F33 AG12 Bank 6 IO278PB5F31 AG16 IO296PB5F33 AF12 IO314NB6F36 AF8 IO279NB5F31 AT10 IO297NB5F33 AM11 IO314PB6F36 AF9 IO279PB5F31 AT11 IO297PB5F33 AM12 IO315NB6F36 AN2 IO280NB5F31 AL15 IO298NB5F33 AK12 IO315PB6F36 AN3 IO280PB5F31 AK15 IO298PB5F33 AL12 IO316NB6F36 AH4 IO281NB5F32 AM14 IO299NB5F33 AN11 IO316PB6F36 AJ4 IO281PB5F32 AM15 IO299PB5F33 AN12 IO317NB6F36 AL3 IO282NB5F32 AE13 IO300NB5F33 AN5 IO317PB6F36 AL4 IO282PB5F32 AE14 IO300PB5F33 AN6 IO318NB6F36 AK4 IO283NB5F32 AT12 IO301NB5F33 AT6 IO318PB6F36 AK5 IO283PB5F32 AT13 IO301PB5F33 AT7 IO319NB6F36 AE10 IO284NB5F32 AP9 IO302NB5F34 AH11 IO319PB6F36 AE9 IO284PB5F32 AP10 IO302PB5F34 AH12 IO320NB6F36 AG4 3-96 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO320PB6F36 AG5 IO338PB6F38 AE3 IO356PB6F40 AB5 IO321NB6F36 AE11 IO339NB6F38 AD5 IO357NB6F40 W12 IO321PB6F36 AD11 IO339PB6F38 AD6 IO357PB6F40 Y12 IO322NB6F37 AG3 IO340NB6F39 AD4 IO358NB6F41 AA1 IO322PB6F37 AH3 IO340PB6F39 AE4 IO358PB6F41 AB1 IO323NB6F37 AG7 IO341NB6F39 AB8 IO359NB6F41 Y8 IO323PB6F37 AG6 IO341PB6F39 AB9 IO359PB6F41 Y9 IO324NB6F37 AH7 IO342NB6F39 AG1 IO360NB6F41 Y4 IO324PB6F37 AH6 IO342PB6F39 AH1 IO360PB6F41 AA4 IO325NB6F37 AJ5 IO343NB6F39 AA12 IO361NB6F41 U12 IO325PB6F37 AH5 IO343PB6F39 AB12 IO361PB6F41 V12 IO326NB6F37 AK2 IO344NB6F39 AD2 IO362NB6F41 W1 IO326PB6F37 AK3 IO344PB6F39 AE2 IO362PB6F41 Y1 IO327NB6F37 AE7 IO345NB6F39 AA11 IO363NB6F41 W6 IO327PB6F37 AE8 IO345PB6F39 AB11 IO363PB6F41 W7 IO328NB6F37 AM4 IO346NB6F39 AE1 IO364NB6F41 W5 IO328PB6F37 AN4 IO346PB6F39 AF1 IO364PB6F41 Y5 IO329NB6F37 AD9 IO347NB6F39 AL1 IO365NB6F41 W10 IO329PB6F37 AD10 IO347PB6F39 AL2 IO365PB6F41 W9 IO330NB6F37 AM1 IO348NB6F39 AC4 IO366NB6F41 V2 IO330PB6F37 AN1 IO348PB6F39 AC5 IO366PB6F41 W2 IO331NB6F38 AE5 IO349NB6F40 AB6 Bank 7 IO331PB6F38 AE6 IO349PB6F40 AB7 IO367NB7F42 V8 IO332NB6F38 AF4 IO350NB6F40 AC1 IO367PB7F42 W8 IO332PB6F38 AF5 IO350PB6F40 AD1 IO368NB7F42 V3 IO333NB6F38 AD8 IO351NB6F40 AA9 IO368PB7F42 W3 IO333PB6F38 AD7 IO351PB6F40 AA10 IO369NB7F42 V9 IO334NB6F38 AG2 IO352NB6F40 AB2 IO369PB7F42 V10 IO334PB6F38 AH2 IO352PB6F40 AB3 IO370NB7F42 U1 IO335NB6F38 AC12 IO353NB6F40 AA7 IO370PB7F42 V1 IO335PB6F38 AD12 IO353PB6F40 AA8 IO371NB7F42 V7 IO336NB6F38 AJ1 IO354NB6F40 AA2 IO371PB7F42 V6 IO336PB6F38 AK1 IO354PB6F40 AA3 IO372NB7F42 U5 IO337NB6F38 AC8 IO355NB6F40 AA5 IO372PB7F42 V5 IO337PB6F38 AC9 IO355PB6F40 AA6 IO373NB7F42 U9 IO338NB6F38 AD3 IO356NB6F40 AB4 IO373PB7F42 U8 Revision 14 3-97 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number IO374NB7F42 R1 IO392NB7F44 M2 IO410NB7F46 J3 IO374PB7F42 T1 IO392PB7F44 N2 IO410PB7F46 K3 IO375NB7F42 T11 IO393NB7F44 P9 IO411NB7F46 L8 IO375PB7F42 T12 IO393PB7F44 P8 IO411PB7F46 L9 IO376NB7F43 T4 IO394NB7F45 M3 IO412NB7F47 K5 IO376PB7F43 U4 IO394PB7F45 N3 IO412PB7F47 K4 IO377NB7F43 T8 IO395NB7F45 M11 IO413NB7F47 K7 IO377PB7F43 T7 IO395PB7F45 N11 IO413PB7F47 K6 IO378NB7F43 T3 IO396NB7F45 M4 IO414NB7F47 E4 IO378PB7F43 T2 IO396PB7F45 N4 IO414PB7F47 F4 IO379NB7F43 T5 IO397NB7F45 N5 IO415NB7F47 G4 IO379PB7F43 T6 IO397PB7F45 N6 IO415PB7F47 G5 IO380NB7F43 R5 IO398NB7F45 J2 IO416NB7F47 H4 IO380PB7F43 R4 IO398PB7F45 K2 IO416PB7F47 J4 IO381NB7F43 R6 IO399NB7F45 N8 IO417NB7F47 D2 IO381PB7F43 R7 IO399PB7F45 N7 IO417PB7F47 D1 IO382NB7F43 N1 IO400NB7F45 G1 IO418NB7F47 K8 IO382PB7F43 P1 IO400PB7F45 H1 IO418PB7F47 K9 IO383NB7F43 T10 IO401NB7F45 M5 IO419NB7F47 H5 IO383PB7F43 T9 IO401PB7F45 M6 IO419PB7F47 J5 IO384NB7F43 R3 IO402NB7F45 E1 Dedicated I/O IO384PB7F43 R2 IO402PB7F45 F1 GND AA13 IO385NB7F44 R12 IO403NB7F46 N10 GND AA15 IO385PB7F44 R11 IO403PB7F46 N9 GND AA17 IO386NB7F44 L1 IO404NB7F46 L5 GND AA19 IO386PB7F44 M1 IO404PB7F46 L4 GND AA21 IO387NB7F44 G2 IO405NB7F46 M7 GND AA23 IO387PB7F44 F2 IO405PB7F46 M8 GND AA24 IO388NB7F44 P5 IO406NB7F46 G3 GND AB14 IO388PB7F44 P4 IO406PB7F46 F3 GND AB16 IO389NB7F44 R8 IO407NB7F46 M10 GND AB18 IO389PB7F44 R9 IO407PB7F46 M9 GND AB20 IO390NB7F44 J1 IO408NB7F46 D4 GND AB22 IO390PB7F44 K1 IO408PB7F46 D3 GND AC3 IO391NB7F44 N12 IO409NB7F46 J7 GND AC7 IO391PB7F44 P12 IO409PB7F46 J6 GND AC11 3-98 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number GND AC13 GND AJ34 GND C17 GND AC15 GND AK6 GND C20 GND AC17 GND AK8 GND C23 GND AC19 GND AK11 GND C26 GND AC21 GND AK14 GND C29 GND AC23 GND AK17 GND C32 GND AC24 GND AK20 GND C35 GND AC26 GND AK23 GND E3 GND AC30 GND AK26 GND E34 GND AC34 GND AK29 GND F7 GND AD13 GND AL7 GND F30 GND AD14 GND AL18 GND G8 GND AD16 GND AL31 GND G11 GND AD18 GND AM3 GND G14 GND AD19 GND AM34 GND G17 GND AD21 GND AP2 GND G20 GND AD23 GND AP5 GND G23 GND AD24 GND AP8 GND G26 GND AE15 GND AP11 GND G29 GND AE25 GND AP14 GND H3 GND AF3 GND AP17 GND H7 GND AF7 GND AP20 GND H30 GND AF10 GND AP23 GND H34 GND AF11 GND AP26 GND J8 GND AF14 GND AP29 GND J31 GND AF17 GND AP32 GND L3 GND AF20 GND AP35 GND L7 GND AF23 GND AR3 GND L10 GND AF26 GND AR34 GND L11 GND AF27 GND B3 GND L14 GND AF30 GND B34 GND L17 GND AF34 GND C2 GND L20 GND AJ3 GND C5 GND L23 GND AJ7 GND C8 GND L26 GND AJ29 GND C11 GND L27 GND AJ30 GND C14 GND L30 Revision 14 3-99 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number GND L34 GND U3 GND Y20 GND M15 GND U7 GND Y22 GND M25 GND U11 GND Y26 GND N14 GND U15 GND Y30 GND N16 GND U17 GND Y34 GND N18 GND U19 NC AJ8 GND N19 GND U21 NC W36 GND N21 GND U23 PRA F18 GND N23 GND U26 PRB A18 GND N24 GND U30 PRC AL19 GND P3 GND U34 PRD AT19 GND P7 GND V4 TCK H8 GND P11 GND V13 TDI F6 GND P13 GND V14 TDO H9 GND P14 GND V16 TMS F5 GND P16 GND V18 TRST G7 GND P18 GND V20 VCCA M12 GND P20 GND V22 VCCA AE12 GND P22 GND V24 VCCA AL5 GND P24 GND V33 VCCA AT18 GND P26 GND W4 VCCA AL32 GND P30 GND W11 VCCA W33 GND P34 GND W13 VCCA J30 GND R15 GND W15 VCCA A19 GND R17 GND W17 VCCA AA14 GND R19 GND W19 VCCA AA16 GND R21 GND W21 VCCA AA18 GND R23 GND W23 VCCA AA20 GND R27 GND W24 VCCA AA22 GND T13 GND W26 VCCA AB15 GND T14 GND Y3 VCCA AB17 GND T16 GND Y7 VCCA AB19 GND T18 GND Y11 VCCA AB21 GND T20 GND Y14 VCCA AB23 GND T22 GND Y16 VCCA AC14 GND T24 GND Y18 VCCA AC16 3-100 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number VCCA AC18 VCCA W22 VCCDA G30 VCCA AC20 VCCA Y15 VCCDA J29 VCCA AC22 VCCA Y17 VCCDA G31 VCCA AP3 VCCA Y19 VCCDA C21 VCCA AP34 VCCA Y21 VCCDA F31 VCCA C3 VCCA Y23 VCCDA D21 VCCA C34 VCCDA G6 VCCDA M22 VCCA P15 VCCDA R10 VCCDA F19 VCCA P17 VCCDA V11 VCCDA D16 VCCA P19 VCCDA AB10 VCCDA L19 VCCA P21 VCCDA AK7 VCCDA C16 VCCA P23 VCCDA AL6 VCCDA L18 VCCA R14 VCCDA AM13 VCCDA N13 VCCA R16 VCCDA AH8 VCCDA E6 VCCA R18 VCCDA AM5 VCCDA E13 VCCA R20 VCCDA AJ9 VCCDA E5 VCCA R22 VCCDA AP16 VCCIB0 B11 VCCA T15 VCCDA AM6 VCCIB0 B14 VCCA T17 VCCDA AN16 VCCIB0 B17 VCCA T19 VCCDA AF18 VCCIB0 B5 VCCA T21 VCCDA AF19 VCCIB0 B8 VCCA T23 VCCDA AN21 VCCIB0 F11 VCCA U14 VCCDA AE22 VCCIB0 F14 VCCA U16 VCCDA AP21 VCCIB0 F17 VCCA U18 VCCDA AM31 VCCIB0 F8 VCCA U20 VCCDA AJ28 VCCIB0 K11 VCCA U22 VCCDA AM32 VCCIB0 K14 VCCA V15 VCCDA AM24 VCCIB0 K17 VCCA V17 VCCDA AL30 VCCIB0 N15 VCCA V19 VCCDA AK30 VCCIB0 N17 VCCA V21 VCCDA AH29 VCCIB1 B20 VCCA V23 VCCDA V26 VCCIB1 B23 VCCA W14 VCCDA AB27 VCCIB1 B26 VCCA W16 VCCDA H29 VCCIB1 B29 VCCA W18 VCCDA H28 VCCIB1 B32 VCCA W20 VCCDA E24 VCCIB1 F20 Revision 14 3-101 Package Pin Assignments CG1272/LG1272 CG1272/LG1272 CG1272/LG1272 RTAX4000D Function Pin Number RTAX4000D Function Pin Number RTAX4000D Function Pin Number VCCIB1 F23 VCCIB4 AD20 VCCIB6 AJ6 VCCIB1 F26 VCCIB4 AD22 VCCIB6 AM2 VCCIB1 F29 VCCIB4 AG20 VCCIB6 Y10 VCCIB1 K20 VCCIB4 AG23 VCCIB6 Y13 VCCIB1 K23 VCCIB4 AG26 VCCIB6 Y2 VCCIB1 K26 VCCIB4 AL20 VCCIB6 Y6 VCCIB1 N20 VCCIB4 AL23 VCCIB7 E2 VCCIB1 N22 VCCIB4 AL26 VCCIB7 H2 VCCIB2 E35 VCCIB4 AL29 VCCIB7 H6 VCCIB2 H31 VCCIB4 AR20 VCCIB7 K10 VCCIB2 H35 VCCIB4 AR23 VCCIB7 L2 VCCIB2 K27 VCCIB4 AR26 VCCIB7 L6 VCCIB2 L31 VCCIB4 AR29 VCCIB7 P10 VCCIB2 L35 VCCIB4 AR32 VCCIB7 P2 VCCIB2 P27 VCCIB5 AD15 VCCIB7 P6 VCCIB2 P31 VCCIB5 AD17 VCCIB7 R13 VCCIB2 P35 VCCIB5 AG11 VCCIB7 U10 VCCIB2 R24 VCCIB5 AG14 VCCIB7 U13 VCCIB2 U24 VCCIB5 AG17 VCCIB7 U2 VCCIB2 U27 VCCIB5 AL11 VCCIB7 U6 VCCIB2 U31 VCCIB5 AL14 VPUMP F32 VCCIB2 U35 VCCIB5 AL17 VCCIB3 AB24 VCCIB5 AL8 VCCIB3 AC27 VCCIB5 AR11 VCCIB3 AC31 VCCIB5 AR14 VCCIB3 AC35 VCCIB5 AR17 VCCIB3 AF31 VCCIB5 AR5 VCCIB3 AF35 VCCIB5 AR8 VCCIB3 AG27 VCCIB6 AB13 VCCIB3 AJ31 VCCIB6 AC10 VCCIB3 AJ35 VCCIB6 AC2 VCCIB3 AM35 VCCIB6 AC6 VCCIB3 Y24 VCCIB6 AF2 VCCIB3 Y27 VCCIB6 AF6 VCCIB3 Y31 VCCIB6 AG10 VCCIB3 Y35 VCCIB6 AJ2 3-102 Revision 14 4 – Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.microsemi.com/soc/documents/SSN_AN.pdf Differences Between RTAX-S/SL and Axcelerator http://www.microsemi.com/soc/documents/RTAXS_AX_Features_AN.pdf Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs http://www.microsemi.com/soc/documents/EDAC_AN.pdf Prototyping for RTAX-S and RTAX-SL Devices http://www.microsemi.com/soc/documents/PrototypingRTAXS_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf Actel CQFP to FBGA Adapter Socket Instructions http://www.microsemi.com/soc/documents/CCGA_FBGA_AN.pdf Actel CCGA to FBGA Adapter Socket Instructions http://www.microsemi.com/soc/documents/CQ352-FPGA_Adapter_AN.pdf IEEE Standard 1149.1 (JTAG) in the Axcelerator Family http://www.microsemi.com/soc/documents/AX_JTAG_AN.pdf User’s Guides and Manuals Antifuse Macro Library Guide http://www.microsemi.com/soc/documents/libguide_UG.pdf SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide http://www.microsemi.com/soc/documents/smarttime_ug.pdf Silicon Sculptor User’s Guide http://www.microsemi.com/soc/documents/SiliSculptII_Sculpt3_ug.pdf Silicon Explorer II User’s Guide http://www.microsemi.com/soc/documents/Silexpl_UG.pdf White Papers Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.microsemi.com/soc/documents/AntifuseSecurityWP.pdf RTAX-S/SL Testing and Reliability Update http://www.microsemi.com/soc/documents/RTAXS_Rel_Test_WP.pdf Miscellaneous Libero IDE flow diagram http://www.microsemi.com/soc/products/software/libero/#flow Revision 14 4-1 5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the document. Revision Changes Page Revision 14 The DL option was added to the "Ordering Information" section and product tables (SAR ii to vii (September 2011) 33149). The user I/Os for the CQ352 package in RTAX2000D and RTAX4000D were changed iii from 150 to 166 in the "Device Resources" section (SAR 31157). The "RTAX-S/SL and RTAX-DSP Device Status" table was updated to note that iii RTAX2000D/DL and RTAX4000D/DL have moved from Preliminary to Production status (SAR 33353). The "Speed Grade and Temperature Grade Matrix" table and "Ordering Information" section now reflect that these devices are available for speed grade –1 (SAR 33148). The "Programmable Interconnect Element" section and "Security" section were revised 1-1, to clarify that although no existing security measures can give an absolute guarantee, 2-135 Microsemi FPGAs implement the best security available in the industry (SAR 32865). Definitions and information about hot-swap and cold-swap was added to the "I/O Logic" 1-6 section (SAR 31419). P1 and P2 in Figure 1-12 • Mathblocks Cascaded Together as Part of a Complex DSP 1-8 Function were replaced with CDOUT1 and CDOUT2 (SAR 32581). Figure 2-1 • Use of an External Resistor for 5 V Tolerance was revised to show the VCCI 2-1 and GND clamp diodes. The explanatory text above the figure was revised as well (SAR 29699). In Table 2-2 • Absolute Maximum Ratings, the VCCA limits were changed from "–0.3 to 2-2 1.6" to "–0.3 to 1.7" (SAR 30847). The VI limits were changed from "–0.5 to 3.75" to "–0.5 to 4.1" (SAR 29757). A note was added to the table for VCCI stating, "The absolute maximum ratings of VCCI are applicable to all I/O standards supported by the device" (SAR 31241). Values for RTAX2000D were added to Table 2-6 • RTAX-D Standby Current (SAR 2-4 33286). Table 2-7 • RTAX-DL Standby Current is new (SAR 33149). In Table 2-9 • Different Components Contributing to the Total Power Consumption in 2-6 RTAX-S/SL/DSP Devices, the P1 value for RTAX4000D was corrected from 7000 to 700.0 (SAR 29953). P13 through P17 were added to the table (SAR 30059). P was added to the power calculation formulas (SAR 30059). 2-7 MathBlock A value for θ was added to Table 2-10 • Package Thermal Characteristics and note 4 2-9, 2-10 jc was revised to include θ . "Free convection = 0" was removed from "Sample Case 1" jc and "Sample Case 2" (SAR 33910). The following text was added to the "User-Defined Supply Pins" section (SAR 24308): 2-14 The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed only for input and bidirectional I/Os. In the Introduction to the "User I/Os" section, the following sentence was added to clarify 2-16 the slew rate setting (SAR 29760): The slew rate setting is effective for both rising and falling edges. Revision 14 5-1 Datasheet Information Revision Changes Page Revision 14 The following sentence was added for clarification in the "Using the Weak Pull-Up and 2-20 (continued) Pull-Down Circuits" section (SAR 31246): The weak pull-up and pull-down is active only when the device is powered-up. 1 Reference to Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances replaced the statement of "on the order of 10 kΩ" (SAR 28695). Additional information was added to clarify how the weak pull-up and pull-down resistors are physically implemented (SAR 32714). Figure 2-11 • Timing Model was replaced (SAR 33043). 2-28 The note in Table 2-16 • Bank Wide Delay Values was revised to reflect that the values in 2-21 the table apply not only to RTAX2000S/SL but to all RTAX-DSP and RTAX-S devices (SAR 32491). The description for the C parameter in Table 2-20 • Input Capacitance was changed 2-26 INCLK from "Input capacitance on clock pin" to "Input capacitance on HCLK and RCLK pin" (SAR 31245). 1 In Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances , notes 2 and 3 were corrected 2-26 to give formulas for R( ) and R( ) rather than WEAK PULL-UP-MAX WEAK PULL-DOWN-MAX R( ) and R( ) and the note regarding output buffers was PULL-UP-MAX PULL-DOWN-MAX removed as not applicable (SARs 29301, 32285). Two parameter names were corrected in Figure 2-10 • Output Buffer Delays. One 2-27 occurrence of t was changed to t and one occurrence of t was changed to ENLZ ENZL ENHZ t (SAR 33315). ENZH The definitions for t and t were corrected in Table 2-25 • Worst-Case Military 2-31 ENZL ENHZ Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C through Table 2-38 • Worst-Case through Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C (SAR 33315). 2-66 Previous definitions: t – Enable to Pad delay through the Output Buffer—High to Z ENZL t – Enable to Pad delay through the Output Buffer—Z to Low ENHZ Corrected definitions: t – Enable to Pad delay through the Output Buffer—Z to Low ENZL t – Enable to Pad delay through the Output Buffer—High to Z ENHZ The minimum VIL for 1.5 V LVCMOS was corrected from –0.5 to –0.3 in Table 2-32 • DC 2-55 Input and Output Levels (SAR 34280). The minimum VIL for 3.3 V PCI was corrected from –0.5 to –0.3 in Table 2-35 • DC Input 2-64 and Output Levels (SAR 34280). The enable signal in Figure 2-36 • R-Cell Delays was corrected to show it is active low 2-91 rather than active high (SAR 32428). The "Global Resource Distribution" section previously stated, "24 segments per HCLK 2-108 driving north-south and 28 segments per CLK driving east-west per core tile." This text was removed and replaced by a reference to the RTAX-S/SL Clocking Resource and Implementation application note (SAR 28040). Package names used in the "Package Pin Assignments" section were revised to match 3-1 standards given in Package Mechanical Drawings (SAR 27395). Bank numbers were added to the following pin tables for RTAX-DSP packages (SAR 28992): "CQ352" for RTAX2000D 3-26 "CQ352" for RTAX4000D 3-30 "CG1272/LG1272" for RTAX2000D 3-79 "CG1272/LG1272" for RTAX4000D 3-91 5-2 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Revision Changes Page Revision 13 The versioning system for datasheets has been changed. Datasheets are assigned a N/A (August 2010) revision number that increments each time the datasheet is revised. The "RTAX-S/SL and RTAX-DSP Device Status" table indicates the status for each device in the device family. References to "Timer" were changed to "SmartTime," which is the current name of the N/A tool. The RTAX-DSP family was added to this datasheet. The RTAX2000D and RTAX4000D N/A devices were included in applicable tables, text, and the "Ordering Information" section. PROTO was added to the "Screening Levels" table for RTAX-S/SL. ii The "Device Resources" table was updated by including a user I/O count of 150 for the iii CQ352 package, RTAX2000D. Two notes were added to the table: 1. RTAX2000S/SL and RTAX2000D are not pin compatible in the CQ352 package type. 2. The package overhang for RTAX4000D is slightly larger than RTAX4000S/SL, but they are pin compatible. The "I/Os per Package" table was updated for CQ352 and CGD1272/LGD1272. The iv column headings "Differential Pair" and "Pair" were changed to "Adjacent Differential Pairs" and "Non-Adjacent Differential Pairs." Notes were added to the table to define terms and state how to calculate total number of I/Os (SAR 23483). Table 2 • MIL-STD-883 Class B Product Flow for RTAX-S/SL and RTAX-DSP 1, 2 was v revised to change the method for Step 4. CQ256 was added to Condition B and LGD1272 was added to Condition A. Table note 3 was revised to state, "Condition A applies to RTAX4000S/SL, RTAX2000D, and RTAX4000D packages only." Table 3 • Extended Flow for RTAX-S/SL and RTAX-DSP1, 2, 3, 4 was revised to change vi the method for Step 5. CQ256 was added to Condition B and LGD1272 was added to Condition A. Table note 5 was revised to state, "Condition A applies to RTAX4000S/SL, RTAX2000D, and RTAX4000D packages only." Table 4 • "EV" Flow (Class V Equivalent Flow Processing) for RTAX-S/SL and RTAX- vii DSP1, 2, 3 was revised to change the method for Step 5. CQ256 was added to Condition B and LGD1272 was added to Condition A. Table note 4 was revised to state, "Condition A applies to RTAX4000S/SL, RTAX2000D, and RTAX4000D packages only." The "Embedded Memory" section was revised to note that the pipelined register in each 1-5 memory block is not hardened and susceptible to single-event upsets (SAR 24153). Table 2-1 • I/O Features Comparison was revised to add a clarifying statement to the first 2-1 table note: In other words, 5 V tolerance and hot-swapping/cold-sparing cannot coexist. Note 2 ("Can be implemented with an external resistor") was indicated as applicable for 3.3 V LVTTL. The "5 V Tolerance" section was revised to state that the voltage at the input will not be 2-1 clamped if the VCCI or VCCA are powered off. Previously VCCI only was mentioned (SAR 79584). The VCCA and VI limits were revised in Table 2-2 • Absolute Maximum Ratings. 2-2 The "Power-Up/Down Sequence" section was updated to add, "During power-down, all 2-3 RTAX-S/SL and RTAX-DSP I/Os are tristated (SAR 20917). A reference to the Board- Level Considerations for Power-Up and Power-Down of RTAX-S/SL FPGAs application note was included. In Table 2-4 • RTAX-S Standby Current, ICCDIFFA was revised for RTAX2000S, 2-3 RTAX1000S, and RTAX250S at 125°C. In Table 2-8 • Default Cload / VCCI, P10 and PI/O values for Single-Ended with VREF 2-5 voltages were updated. Revision 14 5-3 Datasheet Information Revision Changes Page Revision 13 The core tile RCLK power component was updated for RTAX250S/SL in Table 2-9 • 2-6 (continued) Different Components Contributing to the Total Power Consumption in RTAX-S/SL/DSP Devices (SAR 23848). "Convection" was changed to "free convection" in "Sample Case 1" and "Sample Case 2-10 2". The values in Table 2-11 • Temperature and Voltage Timing Derating Factors were 2-11 updated. The "Timing Model" was updated (SAR 79604). The calculated results in the "Hardwired 2-12, Clock" section and "Routed Clock" section were updated to match. 2-13 The "NC No Connection" pin description was revised to state, "This pin is not connected 2-15 to circuitry within the device, or to any other pin in the package" (SAR 79409). Table 2-14 • Compatible I/O Standards for Different VCCI Values now refers to Table 2-3 2-18 • RTAX-S/SL and RTAX-DSP Recommended Operating Conditions for VCCI tolerances rather than stating in a table note that VCCI tolerance is ±5%. The example in the paragraphs below the table was modified to use ±5% rather than ±8% VCCI tolerance for LVCMOS. Figure 2-5 • I/O Cluster Interface was revised to add HCLK or RCLK (SAR 21507). 2-20 Values in the following tables were updated (note that in previous versions of this datasheet, timing numbers were shown for VCCA at 1.4 V): 2-31 Table 2-25 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-40 Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-48 Table 2-29 • DC Input and Output Levels (SARs 26059, 79593) 2-49 Table 2-31 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.7 V, TJ = 125°C 2-55 Table 2-32 • DC Input and Output Levels (SAR 79593) 2-56 Table 2-34 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 125°C 2-65 Table 2-37 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-68 Table 2-41 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-70 Table 2-44 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 125°C 2-72 Table 2-47 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-74 Table 2-50 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-76 Table 2-53 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-78 Table 2-56 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-80 Table 2-59 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-81 Table 2-60 • DC Input and Output Levels 2-82 Table 2-62 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-84 Table 2-63 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-91 Table 2-64 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-92 Table 2-65 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C Figure 2-36 • R-Cell Delays was revised to correct the placement of t (SAR 79526). 2-91 CLR The "Mathblock Timing Specification" section is new. 2-93 5-4 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Revision Changes Page Revision 13 Values in the following tables were updated (note that in previous versions of this (continued) datasheet, timing numbers were shown for VCCA at 1.4 V): 2-101 Table 2-74 • RTAX4000S (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125°C) 2-102 Table 2-76 • RTAX250S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-102 Table 2-78 • RTAX1000S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-103 Table 2-80 • RTAX2000S/SL (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-103 Table 2-82 • RTAX4000S (Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-103 Table 2-83 • RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J 2-105 Table 2-88 • RTAX250S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-105 Table 2-90 • RTAX1000S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-106 Table 2-92 • RTAX2000S/SL (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C) 2-106 Table 2-93 • RTAX2000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = J 125°C) 2-106 Table 2-94 • RTAX4000S (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 3.0 V, T = 125°C) J 2-106 Table 2-95 • RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, T = 125°C) J Figure 2-55 • RAM Read Timing Waveforms was revised to interchange the captions for 2-114 t and t (SAR 24794). RCK2RD1 RCK2RD2 The timing tables in the RAM "Timing Characteristics" section were updated. 2-115 The timing tables in the FIFO "Timing Characteristics" section were updated. 2-126 The configuration information for PRA/B/C/D was revised in Table 2-117 • JTAG and 2-134 Probe Pin Recommendations for Flight (SAR 79412). The IDCODE length and USERCODE length for different devices were specified in the 2-135 "Data Registers (DRs)" section (SAR 26407). The "CQ352" and "CG1272/LG1272" pin tables for RTAX2000D and RTAX4000D are 3-26, new. 3-79 v5.4 RTAX4000S now supports the low-power grade option. In addition, this device has N/A (May 2009) moved from a preliminary state to a production state. RTAX250S/SL supports 624-CCGA/LGA. The following tables were updated: N/A Table 1 • RTAX Family Product Profile, "Screening Levels","Ordering Information". All DC input and output tables and timing characteristic tables were updated. N/A The "Ordering Information" section was updated. B was deleted from the Package Type ii and the speed grade description was updated. The "Screening Levels" table note was updated. ii The "Speed Grade and Temperature Grade Matrix" table was updated. iii The "I/Os per Package" table is new. iv In Table 2 • MIL-STD-883 Class B Product Flow for RTAX-S/SL and RTAX-DSP 1, 2, v "TBD" in step 4 was changed to "Condition A". Revision 14 5-5 Datasheet Information Revision Changes Page v5.4 In Table 3 • Extended Flow for RTAX-S/SL and RTAX-DSP1, 2, 3, 4, "TBD" in step 4 was vi (continued) changed to "Condition A". The first paragraph of the "General Description" section originally stated there were two 1-1 million equivalent system gates; this has been corrected to four million equivalent system gates. Information about segmenting clocks was added to the "Design Environment" section. 1-11 The "Prototyping with ProASIC3E Reprogrammable Units" section is new. 1-12 In Table 2-1 • I/O Features Comparison, LVTTL was updated. Note 1 was updated and 2-1 note 4 is new. In Table 2-2 • Absolute Maximum Ratings, the limit for V was changed from 4.0 to 4.1 2-2 I and V was added to the table. PUMP The "5 V Tolerance" section was significantly updated. 2-1 RTAX4000S/SL data was updated in Table 2-4 • RTAX-S Standby Current. 2-3 For RTAX2000S/SL, I was changed from 2.96 to 3.13. The I /I heading was CCDIFFA IL IH changed to I , I , or I . Note 1 is new. IH IL OZ RTAX4000S/SL data was added to Table 2-5 • RTAX-SL Standby Current. 2-4 I data was updated for Typical 25°C for RTAX2000S/SL, RTAX1000S/SL, and CCA RTAX250S/SL. The I /I heading was changed to I , I , or I . Note 1 is new. IL IH IH IL OZ Table 2-8 • Default Cload / VCCI was significantly updated. 2-5 In the "Ptotal = Pdc + Pac" section, P definition, N was deleted. 2-7 DC banks In the "Power Estimation Example" section, P definition, N was deleted. 2-8 DC banks Table 2-10 • Package Thermal Characteristics was updated to include 624-pin 2-9 CCGA/LGA Table 2-11 • Temperature and Voltage Timing Derating Factors was significantly 2-11 updated. In the "Hardwired Clock" section, the Clock-to-Out (Pad-to-Pad) was updated. T was 2-13 RCO changed from 0.9 to 0.96. In the "Routed Clock" section, the Clock-to-Out (Pad-to-Pad) was updated. T was 2-13 RCO changed from 0.9 to 0.96. Footnote 1 is new. The "VCCIBx Supply Voltage" section was updated to include information about unused 2-14 banks. The "HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C, and D" section was updated. 2-14 The "VPUMP Supply Voltage (External Pump)" section was updated. 2-14 The "CLKE/F/G/H Global Clocks E, F, G, and H" section was updated. 2-14 The "PRA/B/C/D Probes A, B, C, and D" section was updated. 2-15 Information about SEUs and cell buffers was added to "Introduction" section. 2-16 In Table 2-17 • Macros for Single-Ended I/O Standards, the macro names for LVTTL 2-23 were changed from _H_ to _F_ The "Customizing the I/O" section was updated. Table 2-16 • Bank Wide Delay Values is 2-21 new. 1 The data in Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances was significantly 2-26 updated. Notes 1, 2, and 3 were also updated. The note was updated to include pin compatibility information for "CQ352". 3-8 The note was updated to include pin compatibility information for "CG624/LG624". the 3-34 RTAX250S/SL pin table is new. The "CQ352" table for the RTAX250S/SL device is new. 3-10 In Table 2-23 • DC Input and Output Levels, the footnote is new. 2-30 5-6 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Revision Changes Page v5.4 In Table 2-38 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 2-66 (continued) 125°C, the footnote is new. Table 2-56 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C 2-78 was significantly updated. Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-40 to to Table 2-107 • Sixteen RAM Blocks Are Cascaded (Worst-Case Military Conditions 2-119 VCCA = 1.425 V, VCCI = 3.0 V, TJ = 125°C) were updated. Table 2-111 • One FIFO Block (Worst-Case MIlitary Conditions VCCA = 1.425 V, VCCI = 2-128 to 3.0 V, TJ = 125°C) to Table 2-116 • JTAG Instruction Code were updated. 2-133 In the "RTAX2000S/SL Function" table, the block numbers were removed. For example 3-5 "Bank 0, Block 0" was changed to "Bank 0". v5.3 In Table 2-5 • RTAX-SL Standby Current, the I specifications were updated for 2-4 CCA (October 2008) 125°C. v5.2 The "I/O Logic" section was updated to include information about user flip-flops being 1-6 (August 2007) immune to SEU. The "Low-Cost Prototyping Solutions" section was updated significantly. 1-11 Table 2-4 • RTAX-S Standby Current was updated to include I /I . 2-3 IH IL Table 2-5 • RTAX-SL Standby Current was updated to include I /I . 2-4 IH IL The CG1272 was updated in the Table 2-10 • Package Thermal Characteristics. 2-9 The temperature in note 1 was changed from 175 to 125 in the Table 2-11 • Temperature 2-11 and Voltage Timing Derating Factors. In the "Timing Model", the Hardwired Clock was changed to Routed or Hardwired. 2-12 v5.1 The "Ordering Information" section was updated to include the Sigma Six Column and ii (August 2007) BAE Column designation. A note was added to the "Screening Levels" table regarding the Sigma Six Column and BAE Column. v5.0 RTAX-SL information is new. N/A (June 2007) EV Flow (Class V Flow Equivalent Processing) information is new. N/A The "Ordering Information" section was updated. ii The "MIL-STD-883 Class B Product Flow" table was updated. v The "Extended Flow" table was updated. vi The "Low-Cost Prototyping Solutions" section was updated to include RTAX-SL 1-11 prototyping information. Table 2-5 • RTAX-SL Standby Current is new. 2-4 In the "Sample Case 2" section, θ was changed to T . 2-10 cb j The Axcelerator figure listed below the "VCCDA Supply Voltage" section was incorrect 2-14 and has been removed from the datasheet. The "CQ256" table for the RTAX2000S/SL device is new. 3-5 v4.0 All information regarding the RTAX4000S device is new. N/A (May 2007) The "Timing Model" was updated. 2-12 The "Specifications" section was updated. i The SEL and SET information was updated in the "Designed for Space" section.i The maximum I/O counts for the RTAX250S and RTAX1000S were updated in Table 1 • i RTAX Family Product Profile. The "Device Resources" table was updated for CG1272/LG1272. iii Revision 14 5-7 Datasheet Information Revision Changes Page v4.0 The RTAX-S/SL Testing and Reliability Update white paper was added to the "White 4-1 (continued) Papers" section. The "User I/Os" section was updated with information on configuring unused I/Os. 2-16 Implementing DDR was updated in the "Using DDR (Double Data Rate)" section. 2-22 PSET was changed to PRE and D was changed to E in Figure 2-6 • DDR Register. 2-22 The "JTAG" section was updated with JTAG pin information. 2-133 Figure 2-1 • Use of an External Resistor for 5 V Tolerance was updated. 2-1 Note 2 in Table 2-2 • Absolute Maximum Ratings was updated. 2-2 The "Calculating Power Dissipation" section was updated. 2-3 Table 2-28 • Worst-Case Military Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 125°C 2-40 was updated. The "Hardwired Clock" and "Routed Clock" equations were updated. 2-13 Table 2-4 • RTAX-S Standby Current was updated. 2-3 Table 2-8 • Default Cload / VCCI was updated. 2-5 Table 2-11 • Temperature and Voltage Timing Derating Factors was updated. 2-11 All timing characteristic tables were updated. N/A The "CQ352" table for the RTAX4000S is new. 3-22 The "CG1272/LG1272" table for the RTAX4000S is new. 3-66 v3.0 All Timing Characteristics tables were updated. N/A (September 2006) Cold Sparing was added to the Hot Insertion heading in Table 2-1 • I/O Features 2-1 Comparison. The "Thermal Characteristics" section was updated. 2-9 The "Simultaneous Switching Outputs (SSO)" section was updated. 2-17 v3.0 The "Timing Model" has been updated. 2-12 (continued) The "Hardwired Clock" and "Routed Clock" equations were updated. 2-13 Table 2-8 • Default Cload / VCCI was updated. 2-5 1 Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances is new. 2-26 A note was added to Table 2-60 • DC Input and Output Levels. 2-81 v2.2 The LVDS Capable I/O specification was added to "Leading-Edge Performance". i-i (May 2006) Table 1 • RTAX Family Product Profile was updated to include CQ256. i CQ256 was added to the"Screening Levels" table. ii CQ256 is new and CQ352 for the RTAX1000S device was updated in the "Device iii Resources" table. The "Overshoot/Undershoot Limits" section is new. 2-3 Table 2-2 • Absolute Maximum Ratings was updated. 2-2 Table 2-3 • RTAX-S/SL and RTAX-DSP Recommended Operating Conditions was 2-2 updated. The "Timing Model" has been updated. 2-12 The "Hardwired Clock" and "Routed Clock" equations were updated. 2-13 5-8 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Revision Changes Page v2.2 This sentence was updated in the "CLKE/F/G/H Global Clocks E, F, G, and H" section: 2-14 (continued) When the CLK pins are unused, Microsemi recommends that they are tied to a known state. Figure 2-27 • LVPECL Circuit was updated. The following labels were corrected: 2-81 INBUF_LVPECL OUTBUF_LVPECL The following sentence was removed from the "Global Resource Distribution" section: 2-108 "An unused input can be tied to ground for power savings." The "RAM" section was updated. 2-111 The "CQ256" package figure and is new. 3-4 v2.1 In Table 2-4 • RTAX-S Standby Current, the I column heading was changed to I 2-3 CCA CCDA (October 2005) and note 3 is new. v2.0 The "Designed for Space" section was updated. i Table 1 • RTAX Family Product Profile was updated to include 1152 CCGA/LGA. i The "Screening Levels" table was updated to include the 1152 CCGA. iii The RTAX1000S and the RTAX2000S columns were updated in the "Device Resources" iii table. Figure 1-15 • Probe Setup RTAX-S/SL and RTAX-DSP was updated and a note was 1-12 added to the figure. Table 2-4 • RTAX-S Standby Current was updated. The LVPECL and LVDS 2-3 specifications were updated. A note was also added to the table. The "Global Resource Access Macros" section was updated. 2-110 The "JTAG" section section was updated. 2-133 In the "Data Registers (DRs)" section, the IDCODE and USERCODE were changed from 2-135 32 bits to 33 bits. 150°C was changed to 125°C in the "Thermal Characteristics" section. 2-9 Table 2-10 • Package Thermal Characteristics was updated to include the 1152 CCGA. 2-9 Values in the table were updated. A note was added to the "FIFO" section section. 2-120 Table 2-9 • Different Components Contributing to the Total Power Consumption in RTAX- 2-6 S/SL/DSP Devices was updated. 1 Table 2-21 • I/O Weak Pull-Up/Pull-Down Resistances was updated. 2-26 All Timing Characteristic tables from Table 2-25 • Worst-Case Military Conditions VCCA 2-31 to = 1.425 V, VCCI = 3.0 V, TJ = 125°C to Table 2-101 • RAM Signal Description were 2-112 updated. In the "MIL-STD-883 Class B Product Flow" table, #3 for the 883 Method was updated. A v note was also added to the table. In the "Extended Flow" table, #5 for the Method column was updated. The notes were vi also added to the table. In the "Pin Descriptions" section section, the descriptions for the "HCLKA/B/C/D 2-14 Dedicated (Hardwired) Clocks A, B, C, and D" and "CLKE/F/G/H Global Clocks E, F, G, and H" were updated. A footnote was added to the "PRA/B/C/D Probes A, B, C, and D", "TCK2 Test Clock", 2-15 "TDI2 Test Data Input", and "TDI2 Test Data Input" descriptions. The "CG1152/LG1152" section is new. 3-53 Revision 14 5-9 Datasheet Information Revision Changes Page Advance v0.5 LET values for SEU and SEL updated under "Designed for Space".i-i TH "Ordering Information" was updated/ The "Screening Levels", "Speed Grade and i-ii Temperature Grade Matrix"tables are new and the "Device Resources" was updated. Sections "MIL-STD-883 Class B Product Flow" and "Extended Flow" are new. v, vi "General Description" was updated. 1-1 Table 2-9 • Different Components Contributing to the Total Power Consumption in RTAX- 2-6 S/SL/DSP Devices was updated. The "Thermal Characteristics" section was updated. 2-9 Figure 2-4 • Timing Model, the "Hardwired Clock" section and the "Routed Clock" section 2-12 were updated. The "Introduction" section under "User I/Os" was updated to give details regarding VREF 2-16 usage. The "Simultaneous Switching Outputs (SSO)" section under "User I/Os" was updated. 2-17 "Using DDR (Double Data Rate)" section is new. 2-22 Table 2-20 • Input Capacitance was updated. 2-26 All Timing Characteristic Tables were updated. 2-31 to 2-132 The "Introduction" section was updated. 2-16 The "SEU Hardened D Flip-Flop (DFF)" section was moved under "R-Cell" and updated. 2-89 The "Global Resource Distribution" section is new. 2-108 The "Enhancing SEU Performance" section is new. 2-113 Figure 2-54 • RAM Write Timing Waveforms and Figure 2-55 • RAM Read Timing 2-114 Waveforms were updated. Figure 2-62 • FIFO Write Timing and Figure 2-63 • FIFO Read Timing were updated. 2-126 The "Charge Pump Bypass" section is new. 2-133 The "TRST" section was updated. 2-133 The "Global Set Fuse" section is new. 2-136 The "CQ208" for both the RTAX250S and RTAX1000S were added. 3-1 The "CQ352" pin tables for both the RTAX1000S and RTAX2000S were updated. 3-8 The "CG624/LG624" pin tables for both the RTAX1000S and RTAX2000S were updated. 3-34 Advance v0.4 The "Designed for Space" section was updated. i A new device, the RTAX250S, was added to the "Designed for Space", "Ordering i to iii Information", "Screening Levels" and "Device Resources" sections. 2.5V GTL+ support across full military range was removed. n/a Table 1-1 • Number of Core Tiles per Device was updated. 1-4 Table 2-4 • RTAX-S Standby Current and Table 2-8 • Default Cload / VCCI were updated. 2-3, 2-5 Table 2-9 • Different Components Contributing to the Total Power Consumption in RTAX- 2-6 S/SL/DSP Devices was updated. Table 2-15 • Legal I/O Usage Matrix was updated. 2-19 Table 2-19 • I/O Macros for Voltage-Referenced I/O Standards 2-24 5-10 Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Revision Changes Page Advanced v0.3 In the "CQ352" for the RTAX1000S, pin 80 has been changed from VCCI to VCCIB6. 3-14 In the "CQ208" and "CQ352", the NC (V ) was changed to NC for all pins. 3-2 to PP 3-14 Advanced v0.2 The "CQ352" pin table for RTAX1000S is new. 3-10 Pins 14 and 32 have been changed from VCCA to VCCI for the RTAX2000S in the 3-10 "CQ352". The "CG624/LG624" for the RTAX1000S is new. 3-47 Revision 14 5-11 Datasheet Information Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "RTAX-S/SL and RTAX-DSP Device Status" table, is designated as either “Product Brief,” “Advanced,” “Production,” and “Datasheet Supplement.” The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Production This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. International Traffic in Arms Regulations (ITAR) The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. 5-12 Revision 14 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise Drive, Aliso Viejo CA 92656 © 2011 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Within the USA: (800) 713-4113 Corporation. All other trademarks and service marks are the property of their respective owners. Outside the USA: (949) 221-7100 Fax: (949) 756-0308 · www.microsemi.com 5172169-14/10.11