Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs with Flash*Freeze Technology High-Performance Routing Hierarchy Features and Benefits • Segmented, Hierarchical Routing and Clock Structure MIL-STD-883 Class B Qualified Packaging • High-Performance, Low-Skew Global Network • Ceramic Column Grid Array with Six Sigma Copper-Wrapped • Architecture Supports Ultra-High Utilization Lead-Tin Columns Advanced and Pro (Professional) I/Os • Land Grid Array • 700 Mbps DDR, LVDS-Capable I/Os • Ceramic Quad Flat Pack • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Low Power • Bank-Selectable I/O Voltages—up to 8 Banks per Chip • Dramatic Reduction in Dynamic and Static Power • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power 2.5V/1.8V/1.5V/1.2V, 3.3V PCI / 3.3V PCI-X, and • Low Power Consumption in Flash*Freeze Mode LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS Radiation Performance • Voltage-Referenced I/O Standards: GTL+ 2.5V/3.3V, GTL • 25Krad to 30Krad with 10% Propagation Delay Increase 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 (TM 1019 Cond. A, Dose Rate 5 Krad/min) Class I and II (RT3PE3000L only) • Up to 40 Krad with 10% Propagation Delay Increase, Dose Rate • I/O Registers on Input, Output, and Enable Paths < 1 Krad/min • Hot-Swappable and Cold-Sparing I/Os • Up to 55 Krad with 15% Propagation Delay Increase, Dose • Programmable Output Slew Rate and Drive Strength Rate < 1 Krad/min • Programmable Input Delay (RT3PE3000L only) • Wafer-Lot-Specific TID Reports • Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L) High Capacity • Weak Pull-Up/-Down • 600 k to 3 M System Gates • IEEE 1149.1 (JTAG) Boundary Scan Test • Up to 504 kbits of True Dual-Port SRAM • Pin-Compatible Packages across the Radiation-Tolerant (RT) • Up to 620 User I/Os ® ProASIC 3 Family Reprogrammable Flash Technology Clock Conditioning Circuit (CCC) and PLL • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS • Six CCC Blocks, All with Integrated PLL • Live-at-Power-Up (LAPU) Level 0 Support • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, • Single-Chip Solution and External Feedback • Retains Programmed Design when Powered Off • Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2V High Performance systems) and 350 MHz (1.5 V systems) • 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance SRAMs and FIFOs • 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V) • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, In-System Programming (ISP) and Security and ×18 organizations available) • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) • True Dual-Port SRAM (except ×18) Decryption via JTAG (IEEE 1532–compliant) • 24 SRAM and FIFO Blocks with Synchronous Operation: ® • FlashLock Designed to Secure FPGA Contents – 250 MHz: For 1.2 V Systems – 350 MHz: For 1.5 V Systems Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low Power Spaceflight FPGAs RT ProASIC3 Devices RT3PE600L RT3PE3000L System Gates 600,000 3,000,000 VersaTiles (D-flip-flops) 13,824 75,264 RAM kbits (1,024 bits) 108 504 4,608-Bit Blocks 24 112 FlashROM Kbits 1 1 Secure (AES) ISP Yes Yes Integrated PLL in CCCs 6 6 VersaNet Globals 18 18 I/O Banks 8 8 Maximum User I/Os 270 620 Package Pins CCGA/LGA CG/LG484 CG/LG484, CG/LG896 CQFP CQ256 CQ256 October 2011 I © 2011 Microsemi Corporation ProASIC3 nano Flash FPGAs 1 I/Os Per Package RT ProASIC3 Low Power Devices RT3PE600L RT3PE3000L Differential I/O 2 2 Package Single-Ended I/Os Differential I/O Pairs Single-Ended I/Os Pairs CG/LG484 270 135 341 168 CG/LG896 – – 620 310 CQ256 166 82 166 82 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For RT3PE3000L devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V / GTL 2.5 V: up to 72 I/Os per north or south bank 4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. RT ProASIC3 Device Status RT ProASIC3 Devices Status RT3PE600L Production RT3PE3000L Production II Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs RT ProASIC3 Ordering Information _ RT3PE3000L 1 CG 484 Y B Application (Screening Level) B = MIL-STD-883 Class B Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Package Type = CG Ceramic Column Grid Array (1.0 mm pitch) = LG Land Grid Array (1.0 mm pitch) = CQ Ceramic Quad Flat Pack Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number RT ProASIC3 Spaceflight FPGAs RT3PE600L = 600,000 System Gates RT3PE3000L = 3,000,000 System Gates Temperature Grade Offerings Package RT3PE600L RT3PE3000L CG/LG484 B B CG/LG896 – B CQ256 B B Note: B = MIL-STD-883 Class B screening Speed Grade and Temperature Grade Matrix Temperature Grade Std. –1 B ✓✓ Note: B = MIL-STD-883 Class B screening. Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. Revision 3 III ProASIC3 nano Flash FPGAs MIL-STD-883 Class B Product Flow Table 2 • MIL-STD-883 Class B Product Flow for RT ProASIC3 Devices* Step Screen Method Requirement 1 Internal Visual 2010, Condition B 100% 2 Serialization 100% 3 Temperature Cycling 1010, Condition C, 10 cycles minimum 100% 4 Constant Acceleration 2001, Y1 Orientation Only 100% Condition B for CQ256, CQ352, LG624, LG1152 Condition D for CQ208 Condition A for LG1272, LGD1272, CQ352 5 Particle Impact Noise Detection 2020, Condition A 100% 6 Seal (Fine & Gross Leak Test) 1014 100% 7 Pre-Burn-In Electrical Parameters In accordance with applicable Microsemi device 100% specification 8 Dynamic Burn-In 1015, Condition D, 100% 160 hours at 125°C or 80 hours at 150°C minimum 9 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device 100% specification 10 Percent Defective Allowable (PDA) Calculation 5% All Lots 11 Final Electrical Test In accordance with applicable Microsemi device 100% specification, which includes a, b, and c: a. Static Tests 5005, Table 1, Subgroup 1 (1) 25°C 5005, Table 1, Subgroup 2, 3 (2) –55°C and +125°C b. Functional Tests 5005, Table 1, Subgroup 7 (1) 25°C 5005, Table 1, Subgroup 8a, 8b (2) –55°C and +125°C 5005, Table 1, Subgroup 9 c. Switching Tests at 25°C 12 External Visual 2009 100% Note: *For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. IV Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Table of Contents Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-103 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Package Pin Assignments CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Revision 3 V 1 – Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview General Description The radiation-tolerant (RT) ProASIC3 family of Microsemi flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50%. These power savings are coupled with performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and advanced features. The RT ProASIC3 FPGA is based on the ProASIC3EL family of low power FPGAs. Microsemi's proven Flash*Freeze technology enables RT ProASIC3 device users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies, and retaining internal states of the device. This greatly simplifies power management. In addition, optimized software tools using power-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives RT ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). RT ProASIC3 devices offer dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high performance. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. RT ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). RT ProASIC3 devices support devices from 600 k system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. Flash*Freeze Technology RT ProASIC3 devices offer the proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state. When Flash*Freeze mode is activated, RT ProASIC3 devices enter a static state while retaining the contents of registers and SRAM. Power is conserved without the need for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of RT ProASIC3 devices to support a 1.2 V core voltage allows for an even greater reduction in power consumption, which enables low total system power. When the RT ProASIC3 device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low power modes, combined with a reprogrammable, single-chip, single-voltage solution, make RT ProASIC3 devices suitable for low power data transfer and manipulation in military- temperature applications where available power may be limited (e.g., in battery-powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling). Flash Advantages Low Power The RT ProASIC3 family of flash-based FPGAs provides a low power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single-chip, reprogrammable, and live-at-power-up device. RT ProASIC3 devices offer 40% dynamic power and 50% static power savings by reducing the core ® operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero Integrated Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze technology, an RT ProASIC3 device is able to retain device SRAM and logic while dynamic power is reduced to a Revision 3 1-1 Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview minimum, without the need to stop clock or power supplies. Combining these features provides a low power, feature-rich, and high-performance solution. Security Nonvolatile, flash-based RT ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. RT ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. RT ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in RT ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. RT ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. RT ProASIC3 devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. AES-based security is used to prevent the contents of a programmed device from being read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the RT ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The RT ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An RT ProASIC3 device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based RT ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Flash-based RT ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based RT ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based RT ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based RT ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms are designed to prevent access to all the programming information and enable the highest level of security available for remote updates of the FPGA logic. Designers can perform remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property is protected and very unlikely to be compromised or copied. ISP can be performed using the industry-standard AES algorithm. The RT ProASIC3 family device architecture mitigates the need for ASIC migration at higher volumes. This makes the RT ProASIC3 family a cost-effective ASIC replacement. 1-2 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Advanced Flash Technology The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The RT ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs • I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of RT ProASIC3 devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES User Nonvolatile Flash*Freeze Charge Decryption* FlashRom Technology Pumps Figure 1-1 • RT ProASIC3 Device Architecture Overview Revision 3 1-3 Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview Flash*Freeze Technology RT ProASIC3 devices offer proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks can still be driven or can be toggling without impact on power consumption; all core registers and SRAM cells retain their states. I/Os are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLLs. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static and dynamic capabilities of the RT ProASIC3 device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. Actel RT ProASIC3 Flash*Freeze FPGA Mode Control Flash*Freeze Pin Figure 1-2 • RT ProASIC3 Flash*Freeze Mode VersaTiles PLUS® The RT ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC core tiles. The RT ProASIC3 VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. Enable D-Flip-Flop with Clear or Set LUT-3 Equivalent D-Flip-Flop with Clear or Set Data Y X1 Data Y X2 CLK LUT-3 Y D-FF D-FF CLK X3 CLR Enable CLR Figure 1-3 • VersaTile Configurations 1-4 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs User Nonvolatile FlashROM RT ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management FlashROM is written using the standard RT ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to provide a high level of security when loading data over public networks, as in security keys stored in the FlashROM for a user design. FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The RT ProASIC3 development software solution, Libero IDE, has extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero IDE software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO RT ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each variable- aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC RT ProASIC3 space-flight FPGAs provide designers with flexible clock conditioning circuit (CCC) capabilities. Each member of the RT ProASIC3 family contains six CCCs, located at the four corners and the centers of the east and west sides. All six CCC blocks are equipped with a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: Revision 3 1-5 Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview • Wide input frequency range (f ) = 1.5 MHz up to 250 MHz IN_CCC • Output frequency range (f ) = 0.75 MHz up to 250 MHz OUT_CCC • 2 programmable delay types for clock skew minimization • Clock frequency synthesis Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration. • Output duty cycle = 50% ± 1.5% or better • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used • Maximum acquisition time is 300 µs • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns • Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / f OUT_CCC Global Clocking RT ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The RT ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for RT ProASIC3 devices. RT ProASIC3 FPGAs support different I/O standards, including single-ended, differential, and voltage- referenced. The I/Os are organized into banks, with eight banks per device. The configuration of these banks determines the I/O standards supported. For RT ProASIC3, each I/O bank is subdivided into V REF minibanks, which are used by voltage-referenced I/Os. V minibanks contain 8 to 18 I/Os. All the I/Os REF in a given minibank share a common V line. Therefore, if any I/O in a given V minibank is REF REF configured as a V pin, the remaining I/Os in that minibank will be able to use that reference voltage. REF Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) • Double-data-rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). RT ProASIC3 banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. 1-6 Revision 3 2 – Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V 2 VCCI and VMV DC I/O buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is V enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) T Storage temperature –65 to +150 °C STG T Junction temperature +150 °C J Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7. 2. VMV pins must be connected to the corresponding VCCI pins. Refer to the "Pin Descriptions" section on page 3-1 for further information. 3. For recommended operating limits, refer to Table 2-2 on page 2-2. Revision 3 2-1 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics 1,2 Table 2-2 • Recommended Operating Conditions Symbol Parameter Military Units T Ambient temperature –55 to 125 °C A T Junction temperature –55 to 125 °C J 6 3 VCC 1.5 V DC core supply voltage 1.425 to 1.575 V 4 1.2 – 1.5 V Wide Range DC core supply voltage 1.14 to 1.575 V 6 VJTAG JTAG DC voltage 1.4 to 3.6 V 5,6 VPUMP Programming voltage Programming mode 3.15 to 3.45 V Operation 0 V 6 3 VCCPLL Analog power supply (PLL) 1.5 V DC core supply voltage 1.425 to 1.575 V 4 1.2 – 1.5 V DC core supply voltage 1.14 to 1.575 V 6 4 VCCI and VMV 1.2 V DC supply voltage 1.14 to 1.26 V 4 1.2 V Wide Range DC supply voltage 1.14 to 1.575 V 1.5 V DC supply voltage 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 V 7 3.0 V DC supply voltage 2.7 to 3.6 3.3 V DC supply voltage 3.0 to 3.6 V LVDS differential I/O 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. For RT ProASIC3 devices operating at VCC = 1.5 V core voltage. 4. For RT ProASIC3 devices operating at VCC = 1.2 V core voltage and VCCI ≥ VCC. 5. VPUMP should be tied to 0 V to optimize total ionizing dose performance during operation in spaceflight applications. 6. See the "Pin Descriptions" section on page 3-1 for instructions and recommendations on tie-off and supply grouping. 7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. 8. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-20. 2-2 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs 110 HTR Lifetime 100 Tj (°C) (yrs) 90 70 102.7 80 85 43.8 100 20.0 70 105 15.6 60 110 12.3 50 115 9.7 40 120 7.7 125 6.2 30 130 5.0 20 135 4.0 10 140 3.3 0 145 2.7 150 2.2 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (ºC) Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 • High-Temperature Data Retention (HTR) Table 2-3 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or Undershoot Maximum Overshoot/Undershoot VCCI and VMV Duration as a Percentage of Clock Cycle (125ºC) 2.7 V or less 10% 0.72 V 5% 0.82 V 3 V 10% 0.72 V 5% 0.81 V 3.3 V 10% 0.69 V 5% 0.70 V 3.6 V 10% N/A 5% N/A Notes: 1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 2. This table does not provide PCI overshoot/undershoot limits. Revision 3 2-3 Years Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics I/O Power-Up and Supply Voltage Thresholds for Power-On Reset ® Sophisticated power-up management circuitry is designed into every ProASIC 3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6. There are five regions to consider during power-up. RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure2-2 on page2-5 and Figure 2-3 on page 2-6). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power- up behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and Figure 2- 3 on page 2-6 for more details). When PLL power supply voltage and/or VCC levels drop below the V brownout levels (0.75 V CC ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/- Down Behavior of Low Power Flash Devices" chapter of the Radiation-Tolerant ProASIC3 FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. 2-4 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 5: I/O buffers are ON Region 4: I/O Region 1: I/O Buffers are OFF and power supplies are within buffers are ON. specification. I/Os are functional I/Os meet the entire datasheet (except differential and timer specifications for but slower because VCCI speed, VIH / VIL, VOH / VOL, is below specification. For the etc. same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.425 V Region 2: I/O buffers are ON. Region 3: I/O buffers are ON. I/Os are functional (except differential inputs) I/Os are functional; I/O DC but slower because VCCI / VCC are below specifications are met, specification. For the same reason, input but I/Os are slower because buffers do not meet VIH / VIL levels, and the VCC is below specification. output buffers do not meet VOH / VOL levels. Activation trip point: V = 0.85 V ± 0.25 V a Deactivation trip point: Region 1: I/O buffers are OFF V = 0.75 V ± 0.25 V d VCCI Activation trip point: Min VCCI datasheet specification V = 0.9 V ± 0.3 V voltage at a selected I/O a Deactivation trip point: standard; i.e., 1.425 V or 1.7 V V = 0.8 V ± 0.3 V or 2.3 V or 3.0 V d Figure 2-2 • Devices Operating at 1.5 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage Levels Revision 3 2-5 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 5: I/O buffers are ON Region 4: I/O Region 4: I/O Region 1: I/O Buffers are OFF and power supplies are within buf buffers are ON. fers are ON. specification. I/Os are functional I/Os are functional I/Os meet the entire datasheet (except dif (except differential ferential inputs) and timer specifications for but slower because VCCI is speed, VIH / VIL , VOH / VOL , etc. below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.14 V Region 2: I/O buffers are ON. Region 3: I/O buffers are ON. I/Os are functional (except differential inputs) I/Os are functional; I/O DC but slower because VCCI/VCC are below specifications are met, specification. For the same reason, input but I/Os are slower because buffers do not meet VIH/VIL levels, and the VCC is below specification. output buffers do not meet VOH/VOL levels. Activation trip point: V = 0.85 V ± 0.2 V a Deactivation trip point: Region 1: I/O buffers are OFF V = 0.75 V ± 0.2 V d VCCI Activation trip point: Min VCCI datasheet specification voltage at a selected I/O V = 0.9 V ± 0.15 V a standard; i.e., 1.14 V,1.425 V, 1.7 V, Deactivation trip point: 2.3 V, or 3.0 V V = 0.8 V ± 0.15 V d Figure 2-3 • Devices Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage Levels 2-6 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Thermal Characteristics Introduction The temperature variable in the Libero IDE software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. T = Junction Temperature = ΔT + T J A EQ 1 where: T = Ambient Temperature A ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ * P ja θ = Junction-to-ambient of the package. θ numbers are located in Table 2-4. ja ja P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is θ and the junction-to-ambient air thermal resistivity is jc θ . The thermal characteristics for θ are shown for two air flow rates. The recommended maximum ja ja junction temperature is 125°C. EQ 2 shows a sample calculation of the recommended maximum power dissipation allowed for a 484-pin CCGA package with the junction at 125°C and with the case temperature maintained at 70°C. Max. junction temp. (°C) – Max. case temp. (°C) Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------- θ (°C/W) jc EQ 2 Table 2-4 • Package Thermal Resistivities θ ja Pin Package Type Device Count θ θ Still Air 200 ft./min. 500 ft./min. Units jb jc Ceramic Column Grid Array (CCGA) RT3PE600L 484 TBD TBD TBD TBD TBD C/W RT3PE3000L 484 TBD TBD TBD TBD TBD C/W RT3PE3000L 896 3.5 2.8 11.9 TBD TBD C/W Temperature and Voltage Derating Factors Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T = 125°C, VCC = 1.14 V) J Junction Temperature Array Voltage VCC (V) –55°C –40°C 0°C 25°C 70°C 85°C 125°C 1.14 0.86 0.87 0.90 0.92 0.96 0.97 1.00 1.2 0.82 0.83 0.86 0.88 0.92 0.93 0.96 1.26 0.79 0.80 0.83 0.84 0.88 0.89 0.92 1.3 0.77 0.77 0.80 0.82 0.86 0.87 0.90 1.35 0.74 0.75 0.77 0.79 0.83 0.84 0.86 1.4 0.71 0.72 0.74 0.76 0.79 0.80 0.83 1.425 0.70 0.70 0.73 0.75 0.78 0.79 0.82 1.5 0.66 0.67 0.69 0.71 0.74 0.75 0.77 1.575 0.63 0.64 0.67 0.68 0.71 0.72 0.74 Revision 3 2-7 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-6 • Power Supply State per Mode 1 Power Supply Configurations 2 Modes/Power Supplies VCC VCCPLL VCCI VJTAG VPUMP 3 Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off 3 Static and Active On On On On On/off/floating Notes: 1. Off: Power Supply level = 0 V. 2. VPUMP should be tied to 0 V to optimize total ionizing dose performance during operation in spaceflight applications. 3. Even though the power supply configuration in Flash*Freeze and Static and Active mode is the same, the device’s clocks and inputs are shut off in Flash*Freeze mode. * Table 2-7 • Quiescent Supply Current (IDD) Characteristics, Flash*Freeze Mode Core Voltage RT3PE600L RT3PE3000L Units Nominal (25°C) 1.2 V 0.55 2.75 mA 1.5 V 0.83 4.2 mA Typical maximum (25°C) 1.2 V 9 17 mA 1.5 V 12 20 mA Military maximum (125°C) 1.2 V 65 165 mA 1.5 V 85 185 mA Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Under Flash*Freeze conditions, VCCI, VPUMP. and VCCPLL currents are negligible. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-8 • Quiescent Supply Current (IDD) Characteristics, Sleep Mode (VCC = 0 V)* Core Voltage RT3PE600L RT3PE3000L Units VCCI / VJTAG = 1.2 V (per bank) 1.2 V 1.7 1.7 µA Typical (25°C) VCCI / VJTAG = 1.5 V (per bank) 1.2 V / 1.5 V 1.8 1.8 µA Typical (25°C) VCCI / VJTAG = 1.8 V (per bank) 1.2 V / 1.5 V 1.9 1.9 µA Typical (25°C) VCCI / VJTAG = 2.5 V (per bank) 1.2 V / 1.5 V 2.2 2.2 µA Typical (25°C) VCCI / VJTAG = 3.3 V (per bank) 1.2 V / 1.5 V 2.5 2.5 µA Typical (25°C) Note: IDD = N × ICCI. Values do not include I/O static contribution (PDC6 and PDC7), which is shown in Table 2-15 BANKS on page 2-13. 2-8 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Table 2-9 • Quiescent Supply Current (IDD) Characteristics Shutdown Mode Core Voltage RT3PE600L RT3PE3000L Units Nominal (25°C) 1.2 V / 1.5 V 0 µA Military (125ºC) 1.2 V / 1.5 V 0 µA 1 Table 2-10 • Quiescent Supply Current (IDD), Static Mode and Active Mode Core Voltage RT3PE600L RT3PE3000L Units 2 ICCA Current Nominal (25°C) 1.2 V 0.55 2.75 mA 1.5 V 0.83 4.2 mA Typical maximum (25°C) 1.2 V 9 17 mA 1.5 V 12 20 mA Military maximum (125°C) 1.2 V 65 165 mA 1.5 V 85 185 mA 3 ICCI or IJTAG Current VCCI / VJTAG = 1.2 V (per bank) 1.2 V 1.7 1.7 µA Typical (25°C) VCCI / VJTAG = 1.5 V (per bank) 1.2 V / 1.5 V 1.8 1.8 µA Typical (25°C) VCCI / VJTAG = 1.8 V (per bank) 1.2 V / 1.5 V 1.9 1.9 µA Typical (25°C) VCCI / VJTAG = 2.5 V (per bank) 1.2 V / 1.5 V 2.2 2.2 µA Typical (25°C) VCCI / VJTAG = 3.3 V (per bank) 1.2 V / 1.5 V 2.5 2.5 µA Typical (25°C) Notes: 1. IDD = NBANKS × ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC , VCCPLL, and VPUMP currents. VPUMP and VCCPLL currents are negligible. 3. Values do not include I/O static contribution (PDC6 and PDC7). Revision 3 2-9 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Power per I/O Pin Table 2-11 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Static Power Dynamic Power PAC9 1 2 VCCI (V) PDC6 (mW) (µW/MHz) Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.34 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49 3.3 V LVCMOS Wide Range 3.3 – 16.34 3.3 V LVCMOS – Schmitt trigger Wide Range 3.3 – 24.49 2.5 V LVCMOS 2.5 – 4.71 2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13 1.8 V LVCMOS 1.8 – 1.66 1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78 1.5 V LVCMOS (JESD8-11) 1.5 – 1.01 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97 3 1.2 V LVCMOS 1.2 – 0.60 3 1.2 V LVCMOS (JESD8-11) – Schmitt trigger 1.2 – 0.53 3 1.2 V LVCMOS Wide Range 1.2 – 0.60 3 1.2 V LVCMOS Schmitt trigger Wide Range 1.2 – 0.53 3.3 V PCI 3.3 – 17.76 3.3 V PCI – Schmitt trigger 3.3 – 19.10 3.3 V PCI-X 3.3 – 17.76 3.3 V PCI-X – Schmitt trigger 3.3 – 19.10 Voltage-Referenced 3.3 V GTL 3.3 2.90 7.14 2.5 V GTL 2.5 2.13 3.54 3.3 V GTL+ 3.3 2.81 2.91 2.5 V GTL+ 2.5 2.57 2.61 HSTL (I) 1.5 0.17 0.79 HSTL (II) 1.5 0.17 0.79 SSTL2 (I) 2.5 1.38 3.26 SSTL2 (II) 2.5 1.38 3.26 SSTL3 (I) 3.3 3.21 7.97 SSTL3 (II) 3.3 3.21 7.97 Differential LVDS 2.5 2.26 0.89 LVPECL 3.3 5.71 1.94 Notes: 1. PDC6 is the static power measured on VCCI for voltage referenced and differential I/O standards. Single-ended I/O standards do not have the PDC6 static component. Refer to the "Power Calculation Methodology" section on page 2-13 for details on how to calculate total static and dynamic power. 2. PAC9 is the total dynamic power measured on VCCI. 3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V and VCCI ≥ VCC. 2-10 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs 1 Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Static Power Dynamic Power 2 3 C (pF) VCCI (V) PDC7 (mW) PAC10 (µW/MHz) LOAD Single-Ended 3.3 V LVTTL/LVCMOS 5 3.3 – 148.00 3.3 V LVCMOS Wide Range 5 3.3 – 148.00 2.5 V LVCMOS 5 2.5 – 83.23 1.8 V LVCMOS 5 1.8 – 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05 1.2 V LVCMOS 5 1.2 – 17.94 1.2 V LVCMOS Wide Range 5 1.2 – 17.94 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 Voltage-Referenced 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.18 SSTL2 (I) 30 2.5 16.69 105.65 SSTL2 (II) 30 2.5 25.91 116.48 SSTL3 (I) 30 3.3 26.02 114.67 SSTL3 (II) 30 3.3 42.21 131.69 Differential LVDS – 2.5 7.70 89.58 LVPECL – 3.3 19.42 167.86 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power measured on VCCI for voltage referenced and differential I/O standards. Single-ended I/O standards do not have the PDC7 static component. Refer to the "Power Calculation Methodology" section on page 2-13 for details on how to calculate total static and dynamic power. 3. PAC10 is the total dynamic power measured on VCCI. Revision 3 2-11 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-13 • Different Components Contributing to Dynamic Power Consumption in Devices Operating at 1.2 V VCC Device-Specific Dynamic Power (µW/MHz) Parameter Definition RT3PE3000L RT3PE600L PAC1 Clock contribution of a Global Rib 8.34 3.99 PAC2 Clock contribution of a Global Spine 4.28 2.22 PAC3 Clock contribution of a VersaTile row 0.94 0.94 PAC4 Clock contribution of a VersaTile used as a sequential module 0.08 0.08 PAC5 First contribution of a VersaTile used as a sequential module 0.05 PAC6 Second contribution of a VersaTile used as a sequential 0.19 module PAC7 Contribution of a VersaTile used as a combinatorial module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-11 on page 2-10. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-12 on page 2-11. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 1.74 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in the Libero IDE software. Table 2-14 • Different Components Contributing to Dynamic Power Consumption in RT ProASIC3 Devices at 1.5 V VCC Device-Specific Dynamic Power (µW/MHz) Parameter Definition RT3PE3000L RT3PE600L PAC1 Clock contribution of a Global Rib 13.03 6.24 PAC2 Clock contribution of a Global Spine 6.69 3.47 PAC3 Clock contribution of a VersaTile row 1.46 1.46 PAC4 Clock contribution of a VersaTile used as a sequential module 0.13 0.13 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential 0.29 module PAC7 Contribution of a VersaTile used as a combinatorial module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-11 on page 2-10. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-12 on page 2-11. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in the Libero IDE software. 2-12 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Table 2-15 • Different Components Contributing to the Static Power Consumption in RT ProASIC3 Devices Device-Specific Dynamic Power Parameter Definition (µW) PDC0 Array static power in Sleep mode 0 mW PDC1 Array static power in Active mode See Table 2-10 on page 2-9. PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-9. PDC3 Array static power in Flash*Freeze mode See Table 2-7 on page 2-8. PDC4 Static PLL contribution at 1.2 V operating core voltage 1.42 mW Static PLL contribution 1.5 V operating core voltage 2.55 mW PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-8, Table 2-8 on page 2-8, Table 2-10 on page 2-9. PDC6 I/O input pin static power (standard-dependent) See Table 2-11 on page 2-10. PDC7 I/O output pin static power (standard-dependent) See Table 2-12 on page 2-11. Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power ® spreadsheet calculator or SmartPower tool in Libero Integrated Design Environment (IDE). Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table2-16 on page 2-15. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on page 2-15. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-17 on page 2-15. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL P = P + P TOTAL STAT DYN P is the total static power consumption. STAT P is the total dynamic power consumption. DYN Total Static Power Consumption—P STAT P = (PDC0 or PDC1 or PDC2 or PDC3) + N * PDC5 + N * PDC6 + N * PDC7 STAT BANKS INPUTS OUTPUTS N is the number of I/O input buffers used in the design. INPUTS N is the number of I/O output buffers used in the design. OUTPUTS N is the number of I/O banks powered in the design. BANKS Revision 3 2-13 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Total Dynamic Power Consumption—P DYN P = P + P + P + P + P + P + P + P DYN CLOCK S-CELL C-CELL NET INPUTS OUTPUTS MEMORY PLL Global Clock Contribution—P CLOCK P = (PAC1 + N * PAC2 + N * PAC3 + N * PAC4) * F CLOCK SPINE ROW S-CELL CLK N is the number of global spines used in the user design—guidelines are provided in SPINE the "Spine Architecture" section of the Global Resources chapter in the RT ProASIC3 FPGA Fabric User's Guide. N is the number of VersaTile rows used in the design—guidelines are provided in ROW "Spine Architecture" section of the Global Resources chapter in the RT ProASIC3 FPGA Fabric User's Guide. F is the global clock signal frequency. CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL P = N * (PAC5 + α / 2 * PAC6) * F S-CELL S-CELL 1 CLK N is the number of VersaTiles used as sequential modules in the design. When a S-CELL multi-tile sequential cell is used, it should be accounted for as 1. α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on 1 page 2-15. F is the global clock signal frequency. CLK Combinatorial Cells Contribution—P C-CELL P = N * α / 2 * PAC7 * F C-CELL C-CELL 1 CLK N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on 1 page 2-15. F is the global clock signal frequency. CLK Routing Net Contribution—P NET P = (N + N ) * α / 2 * PAC8 * F NET S-CELL C-CELL 1 CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on 1 page 2-15. F is the global clock signal frequency. CLK I/O Input Buffer Contribution—P INPUTS P = N * α / 2 * PAC9 * F INPUTS INPUTS 2 CLK N is the number of I/O input buffers used in the design. INPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-15. 2 F is the global clock signal frequency. CLK I/O Output Buffer Contribution—P OUTPUTS P = N * α / 2 * β * PAC10 * F OUTPUTS OUTPUTS 2 1 CLK N is the number of I/O output buffers used in the design. OUTPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-15. 2 β is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-15. 1 F is the global clock signal frequency. CLK 2-14 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs RAM Contribution—P MEMORY P = PAC11 * N * F * β + PAC12 * N * F * β MEMORY BLOCKS READ-CLOCK 2 BLOCK WRITE-CLOCK 3 N is the number of RAM blocks used in the design. BLOCKS F is the memory read clock frequency. READ-CLOCK β is the RAM enable rate for read operations. 2 F is the memory write clock frequency. WRITE-CLOCK β is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on 3 page 2-15. PLL Contribution—P PLL P = PDC4 + PAC1 *F PLL 3 CLKOUT 1 F is the output clock frequency. CLKOUT Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% –… – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline α Toggle rate of VersaTile outputs 10% 1 α I/O buffer toggle rate 10% 2 Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline β I/O output buffer enable rate 100% 1 β RAM enable rate for read operations 12.5% 2 β RAM enable rate for write operations 12.5% 3 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (P * F product) to the total PLL contribution. AC13 CLKOUT Revision 3 2-15 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell LVPECL Y Y t = 0.78 ns t = 0.67 ns PD PD t = 1.59 ns DP I/O Module (Non-Registered) Combinational Cell Y LVTTL Output Drive Strength = 12 mA High Slew Rate t = 2.09 ns t = 1.21 ns DP PD I/O Module Combinational Cell (Non-Registered) I/O Module Y (Registered) LVTTL Output Drive Strength = 8 mA t = 1.84 ns PY High Slew Rate t = 2.38 ns DP LVPECL t = 0.70 ns PD I/O Module DQ (Non-Registered) Combinational Cell Y LVCMOS 1.5 V Output Drive Strength = 4 mA High Slew Rate t = 0.33 ns ICLKQ t = 2.84 ns t = 0.65 ns DP t = 0.36 ns PD ISUD Input LVTTL Clock I/O Module Register Cell (Registered) Register Cell Combinational Cell t = 1.49 ns PY Y DQ DQ DQ LVTTL 3.3 V Output Drive I/O Module Strength = 12 mA t = 0.65 ns PD t = 2.09 ns (Non-Registered) DP High Slew Rate t = 0.76 ns CLKQ t = 0.81 ns t = 0.76 ns OCLKQ CLKQ LVDS, t = 0.59 ns SUD t = 0.43 ns t = 0.59 ns OSUD SUD B-LVDS, M-LVDS Input LVTTL Input LVTTL Clock Clock t = 2.11 ns PY t = 1.49 ns t = 1.49 ns PY PY Figure 2-4 • Timing Model Operating Conditions: –1 Speed, Military Temperature Range (T = 125°C), Worst-Case J VCC = 1.14 V (example for RT3PE3000L and RT3PE600L) 2-16 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs t t PY DIN D Q PAD DIN Y CLK To Array I/O Interface t = MAX(t (R), t (F)) PY PY PY t = MAX(t (R), t (F)) DIN DIN DIN VIH V V trip trip VIL PAD VCC 50% 50% Y GND t t PY PY (R) (F) VCC 50% 50% DIN t GND t DOUT DOUT (R) (F) Figure 2-5 • Input Buffer Timing Model and Delays (example) Revision 3 2-17 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics t t DOUT DP D Q PAD DOUT CLK Std D Load From Array t = MAX(t (R), t (F)) DP DP DP I/O Interface t = MAX(t (R), t (F)) DOUT DOUT DOUT t t DOUT DOUT VCC (R) (F) 50% 50% D 0 V VCC 50% 50% DOUT 0 V VOH Vtrip Vtrip V OL PAD t t DP DP (R) (F) Figure 2-6 • Output Buffer Model and Delays (example) 2-18 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs t EOUT D Q CLK , t , t , t , t , t t E ZL ZH HZ LZ ZLS ZHS EOUT D Q PAD DOUT CLK D t = MAX(t (r), t (f)) I/O Interface EOUT EOUT EOUT VCC D VCC 50% 50% E t EOUT (F) t EOUT (R) VCC 50% 50% 50% 50% t LZ EOUT t ZH t t ZL HZ VCCI 90% VCCI PAD Vtrip Vtrip VOL 10% V CCI VCC D VCC 50% 50% E t t EOUT (F) EOUT (R) VCC 50% 50% EOUT 50% t ZHS t ZLS VOH PAD Vtrip Vtrip VOL Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example) Revision 3 2-19 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Output Levels Software Default Settings Equiv. VOL VOH IOL IOH Software Default Drive Strength 1 Drive Option Slew Max. Min. (mA) Rate V VmAmA I/O Standard Strgth. –55 ≤ T ≤ 100 100 < T ≤ 125 –55 ≤ T ≤ 100 100 < T ≤ 125 –55 ≤ T ≤ 125 J J J J J (°C) (°C) (°C) (°C) (°C) 3.3 V LVTTL / 12 mA 12 High 0.4 0.4 2.4 2.4 12 12 3.3 V LVCMOS 3.3 V LVCMOS 100 µA 12 High 0.2 0.2 VCCI – 0.2 VCCI – 0.2 0.1 0.1 1,2 Wide Range 2.5 V LVCMOS 12 mA 12 High 0.7 0.7 1.7 1.7 12 12 1.8 V LVCMOS 12 mA 12 High 0.45 0.45 VCCI – 0.45 VCCI – 0.45 12 12 1.5 V LVCMOS 12 mA 12 High 0.25 * VCCI 0.25 * VCCI 0.75 * VCCI 0.75 * VCCI 12 12 3,4 1.2 V LVCMOS 2 mA 2 High 0.25 * VCCI 0.25 * VCCI 0.75 * VCCI 0.75 * VCCI 2 2 1.2 V LVCMOS 100 µA 2 High 0.1 0.1 VCCI – 0.1 VCCI – 0.1 0.1 0.1 1,3,4 Wide Range 3.3 V PCI Per PCI Specification 3.3 V PCI-X Per PCI-X Specification 5 5 3.3 V GTL 20 20 High 0.4 0.5 – – 20 20 5 5 2.5 V GTL 20 20 High 0.4 0.5 – – 20 20 3.3 V GTL+ 35 35 High 0.6 0.75 – – 35 35 2.5 V GTL+ 33 33 High 0.6 0.75 – – 33 33 HSTL (I) 8 8 High 0.4 0.4 VCCI – 0.4 VCCI – 0.4 8 8 5 5 HSTL (II) 15 15 High 0.4 0.5 VCCI – 0.4 VCCI – 0.5 15 15 SSTL2 (I) 15 15 High 0.54 0.54 VCCI – 0.62 VCCI – 0.62 15 15 SSTL2 (II) 18 18 High 0.35 0.44 VCCI – 0.43 VCCI – 0.43 18 18 SSTL3 (I) 14 14 High 0.7 0.7 VCCI – 1.1 VCCI – 1.1 14 14 SSTL3 (II) 21 21 High 0.5 0.625 VCCI – 0.9 VCCI – 0.9 21 21 Notes: 1. The minimum drive strength for any 1.2 V LVCMOS or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V and VCCI ≥ VCC. 4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Output drive strength is below JEDEC specification. 6. Output slew rate can be extracted using the IBIS models. 2-20 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Table 2-19 • Summary of Maximum and Minimum DC Input Levels Software Default Settings 1 2 VIL VIH IIL IIH Min. Max. Min. Max. I/O Standard V V V VµA µA –55 ≤ T ≤ 125 (°C) –55 ≤ T ≤ 125 (°C) –55 ≤ T ≤ 125 (°C) J J J 3.3 V LVTTL / 3.3 V LVCMOS –0.3 0.8 2 3.6 15 15 3.3 V LVCMOS Wide Range –0.3 0.8 2 3.6 15 15 2.5 V LVCMOS –0.3 0.7 1.7 3.6 15 15 1.8 V LVCMOS –0.3 0.35 * VCCI 0.65 * VCCI 3.6 15 15 1.5 V LVCMOS –0.3 0.35 * VCCI 0.65 * VCCI 3.6 15 15 3 1.2 V LVCMOS –0.3 0.35 * VCCI 0.65 * VCCI 3.6 15 15 3 1.2 V LVCMOS Wide Range –0.3 0.3 * VCCI 0.7 * VCCI 3.6 15 15 3.3 V PCI Per PCI Specification 3.3 V PCI-X Per PCI-X Specification 3.3 V GTL –0.3 VREF – 0.05 VREF + 0.05 3.6 15 15 2.5 V GTL –0.3 VREF – 0.05 VREF + 0.05 3.6 15 15 3.3 V GTL+ –0.3 VREF – 0.1 VREF + 0.1 3.6 15 15 2.5 V GTL+ –0.3 VREF – 0.1 VREF + 0.1 3.6 15 15 HSTL (I) –0.3 VREF – 0.1 VREF + 0.1 3.6 15 15 HSTL (II) –0.3 VREF – 0.1 VREF + 0.1 3.6 15 15 SSTL2 (I) –0.3 VREF – 0.2 VREF + 0.2 3.6 15 15 SSTL2 (II) –0.3 VREF – 0.2 VREF + 0.2 3.6 15 15 SSTL3 (I) –0.3 VREF – 0.2 VREF + 0.2 3.6 15 15 SSTL3 (II) –0.3 VREF – 0.2 VREF + 0.2 3.6 15 15 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.). 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V core voltage and VCCI ≥ VCC. Revision 3 2-21 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-20 • Summary of AC Measuring Points* Input/Output Input Reference Board Termination Measuring Trip Standard Supply Voltage Voltage (VREF_TYP) Voltage (VTT_REF) Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 3.30 V – – 1.4 V 3.3 V LVCMOS Wide Range 3.30 V – 1.4 V 2.5 V LVCMOS 2.50 V – – 1.2 V 1.8 V LVCMOS 2.50 V – – 0.90 V 1.5 V LVCMOS 1.80 V – – 0.75 V 1.2 V LVCMOS* 1.50 V – – 0.6V 1.2 V LVCMOS – Wide Range* 1.20 V – – 0.6 V 3.3 V PCI 1.20 V – – 0.285 * VCCI (RR) 3.30 V – – 0.615 * VCCI (FF)) 3.3 V PCI-X 3.30 V – – 0.285 * VCCI (RR) 3.30 V – – 0.615 * VCCI (FF) 3.3 V GTL 2.50 V 0.8 V 1.2 V VREF 2.5 V GTL 3.30 V 0.8 V 1.2 V VREF 3.3 V GTL+ 2.50 V 1.0 V 1.5 V VREF 2.5 V GTL+ 1.50 V 1.0 V 1.5 V VREF HSTL (I) 1.50 V 0.75 V 0.75 V VREF HSTL (II) 3.30 V 0.75 V 0.75 V VREF SSTL2 (I) 3.30 V 1.25 V 1.25 V VREF SSTL2 (II) 2.50 V 1.25 V 1.25 V VREF SSTL3 (I) 2.50 V 1.5 V 1.485 V VREF SSTL3 (II) 2.50 V 1.5 V 1.485 V VREF LVDS 3.30 V – – Cross point LVPECL – – Cross point Note: *Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only Table 2-21 • I/O AC Parameter Definitions Parameter Parameter Definition t Data to Pad delay through the Output Buffer DP t Pad to Data delay through the Input Buffer PY t Data to Output Buffer delay through the I/O interface DOUT t Enable to Output Buffer Tristate Control delay through the I/O interface EOUT t Input Buffer to Data delay through the I/O interface DIN t Enable to Pad delay through the Output Buffer—High to Z HZ t Enable to Pad delay through the Output Buffer—Z to High ZH t Enable to Pad delay through the Output Buffer—Low to Z LZ t Enable to Pad delay through the Output Buffer—Z to Low ZL t Enable to Pad delay through the Output Buffer with delayed enable—Z to High ZHS t Enable to Pad delay through the Output Buffer with delayed enable—Z to Low ZLS 2-22 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs 1.2 V Core Operating Voltage Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings = 125°C, Worst Case VCC = 1.14 V, –1 Speed Grade, Military-Case Conditions: T J Worst Case VCCI Standard 3.3 V LVTTL / 12 mA 12 mA High 5 – 0.68 2.09 0.05 1.49 2.03 0.44 2.12 1.56 2.76 3.06 3.99 3.43 3.3 V LVCMOS 3.3 V LVCMOS 100 µA 12 mA High 5 – 0.68 3.01 0.05 1.86 2.69 0.44 3.01 2.22 4.03 4.42 4.89 4.09 2 Wide Range 2.5 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.12 0.05 1.73 2.17 0.44 2.15 1.74 2.84 2.95 4.03 3.62 1.8 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27 3.81 1.5 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.71 0.05 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63 4.12 1.2 V LVCMOS 2 mA 2 mA High 5 – 0.68 4.39 0.05 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61 1.2 V LVCMOS 100 µA 2 mA High 5 – 0.68 4.39 0.05 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61 3 Wide Range 4 3.3 V PCI Per PCI –High1025 0.68 2.37 0.05 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56 spec 4 3.3 V PCI-X Per PCI-X –High1025 0.68 2.37 0.05 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56 spec 5 5 3.3 V GTL 20 mA 20 mA High 10 25 0.68 1.75 0.05 1.99 – 0.44 1.71 1.75 – – 3.59 3.62 5 5 2.5 V GTL 20 mA 20 mA High 10 25 0.68 1.79 0.05 1.93 – 0.44 1.82 1.79 – – 3.70 3.67 3.3 V GTL+ 35 mA 35 mA High 10 25 0.68 1.74 0.05 1.99 – 0.44 1.76 1.73 – – 3.64 3.61 2.5 V GTL+ 33 mA 33 mA High 10 25 0.68 1.86 0.05 1.93 – 0.44 1.89 1.77 – – 3.77 3.64 HSTL (I) 8 mA 8 mA High 20 25 0.68 2.68 0.05 2.34 – 0.44 2.73 2.65 – – 4.60 4.52 5 5 HSTL (II) 15 mA 15 mA High 20 50 0.68 2.55 0.05 2.34 – 0.44 2.59 2.28 – – 4.47 4.16 SSTL2 (I) 15 mA 15 mA High 30 25 0.68 1.80 0.05 1.78 – 0.44 1.82 1.55 – – 1.82 1.55 SSTL2 (II) 18 mA 18 mA High 30 50 0.68 1.83 0.05 1.78 – 0.44 1.86 1.49 – – 1.86 1.49 SSTL3 (I) 14 mA 14 mA High 30 25 0.68 1.95 0.05 1.71 – 0.44 1.98 1.55 – – 1.98 1.55 SSTL3 (II) 21 mA 21 mA High 30 50 0.68 1.75 0.05 1.71 – 0.44 1.77 1.41 – – 1.77 1.41 LVDS 24 mA–High––0.681.590.052.11–––––––– LVPECL 24 mA –High––0.681.510.051.84––– ––––– Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-48 for connectivity. This resistor is not required during normal operation. 5. Output drive strength is below JEDEC specification. 6. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values. Revision 3 2-23 Drive Strength (mA) Equivalent Software Default Drive Strength 1 Option Slew Rate Capacitive Load (pF) External Resistor (Ω) t (ns) DOUT t (ns) DP t (ns) DIN t (ns) PY t (ns) PYS t (ns) EOUT t (ns) ZL t (ns) ZH t (ns) LZ t (ns) HZ t (ns) ZLS t (ns) ZHS Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics 1.5 V Core Voltage Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings = 125°C, VCC = 1.425 V, Worst Case VCCI –1 Speed Grade, Military-Case Conditions: T J Standard 3.3 V LVTTL / 12 mA 12 mA High 5 – 0.52 1.97 0.03 1.23 1.78 0.34 1.99 1.46 2.63 2.89 3.23 2.71 3.3 V LVCMOS 3.3V LVCMOS 100 µA 12 mA High 5 – 0.52 2.89 0.03 1.61 2.44 0.34 2.88 2.12 3.89 4.25 4.12 3.36 2 Wide Range 2.5 V LVCMOS 12 mA 12 mA High 5 – 0.52 2.01 0.03 1.49 1.93 0.34 2.02 1.65 2.71 2.78 3.27 2.89 1.8 V LVCMOS 12 mA 12 mA High 5 – 0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51 3.08 1.5 V LVCMOS 12 mA 12 mA High 5 – 0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87 3.39 3 3.3 V PCI Per PCI – High 10 25 0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83 spec 3 3.3 V PCI-X Per PCI-X – High 10 25 0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83 spec 4 4 3.3 V GTL 20 mA 20 mA High 10 25 0.52 1.68 0.03 1.79 – 0.34 1.58 1.68 – – 2.83 2.92 4 4 2.5 V GTL 20 mA 20 mA High 10 25 0.52 1.72 0.03 1.73 – 0.34 1.69 1.72 – – 2.93 2.97 3.3 V GTL+ 35 mA 35 mA High 10 25 0.52 1.66 0.03 1.79 – 0.34 1.63 1.66 – – 2.88 2.90 2.5 V GTL+ 33 mA 33 mA High 10 25 0.52 1.75 0.03 1.73 – 0.34 1.76 1.69 – – 3.00 2.94 HSTL (I) 8 mA 8 mA High 20 25 0.52 2.57 0.03 2.14 – 0.34 2.59 2.55 – – 3.84 3.79 4 4 HSTL (II) 15 mA 15 mA High 20 50 0.52 2.44 0.03 2.14 – 0.34 2.46 2.19 – – 3.71 3.43 SSTL2 (I) 15 mA 15 mA High 30 25 0.52 1.68 0.03 1.58 – 0.34 1.69 1.46 – – 1.69 1.46 SSTL2 (II) 18 mA 18 mA High 30 50 0.52 1.72 0.03 1.58 – 0.34 1.73 1.39 – – 1.73 1.39 SSTL3 (I) 14 mA 14 mA High 30 25 0.52 1.83 0.03 1.51 – 0.34 1.84 1.45 – – 1.84 1.45 SSTL3 (II) 21 mA 21 mA High 30 50 0.52 1.63 0.03 1.51 – 0.34 1.64 1.31 – – 1.64 1.31 LVDS 24 mA – High – – 0.52 1.75 0.04 2.18 – – – – – – – – LVPECL 24 mA – High – – 0.52 1.65 0.04 1.89 – – – – – – – – Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-48 for connectivity. This resistor is not required during normal operation. 4. Output drive strength is below JEDEC specification. 5. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values. 2-24 Revision 3 Drive Strength (mA) Equivalent Software Default Drive Strength 1 Option Slew Rate Capacitive Load (pF) External Resistor (Ω) t (ns) DOUT t (ns) DP t (ns) DIN t (ns) PY t (ns) PYS t (ns) EOUT t (ns) ZL t (ns) ZH t (ns) LZ t (ns) HZ t (ns) ZLS t (ns) ZHS Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Detailed I/O DC Characteristics Table 2-24 • Input Capacitance Symbol Definition Conditions Min. Max. Units Input capacitance V = 0, f = 1.0 MHz 8 pF C IN IN C Input capacitance on the clock pin V = 0, f = 1.0 MHz 8 pF INCLK IN 1 Table 2-25 • I/O Output Buffer Maximum Resistances R R PULL-DOWN PULL-UP 2 3 Standard Drive Strength (Ω) (Ω) 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS 2.5 V LVCMOS 4 mA 100 200 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 1.8 V LVCMOS 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 1.5 V LVCMOS 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 4 1.2 V LVCMOS 2 mA 158 158 4 1.2 V LVCMOS Wide Range 100 µA 158 158 3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75 5 3.3 V GTL 20 mA 11 – 5 2.5 V GTL 20 mA 14 – 3.3 V GTL+ 35 mA 12 – Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R = (VOLspec) / IOLspec (PULL-DOWN-MAX) 3. R = (VCCImax – VOHspec) / IOHspec (PULL-UP-MAX) 4. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only. 5. Output drive strength is below JEDEC specification. Revision 3 2-25 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics 1 Table 2-25 • I/O Output Buffer Maximum Resistances (continued) R R PULL-DOWN PULL-UP 2 3 Standard Drive Strength (Ω) (Ω) 2.5 V GTL+ 33 mA 15 – HSTL (I) 8 mA 50 50 5 HSTL (II) 15 mA 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R = (VOLspec) / IOLspec (PULL-DOWN-MAX) 3. R = (VCCImax – VOHspec) / IOHspec (PULL-UP-MAX) 4. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only. 5. Output drive strength is below JEDEC specification. Table 2-26 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values 1 2 R R (WEAK PULL-UP) (WEAK PULL-DOWN) (Ω) (Ω) VCCI Min. Max. Min. Max. 3.3 V 10 k 95 k 13 k 45 k 3.3 V (wide range I/Os) 10 k 95 k 13 k 45 k 2.5 V 11 k 100 k 17 k 74 k 1.8 V 19 k 85 k 23 k 110 k 1.5 V 20 k 120 k 17 k 156 k 1.2 V 30 k 450 k 25 k 300 k 1.2 V (wide range I/Os) 20 k 450 k 17 k 300 k Notes: 1. R = (VCCImax – VOHspec) / I (WEAK PULL-UP-MAX) (WEAK PULL-UP-MIN) 2. R = VOLspec / I (WEAK PULL-DOWN-MAX) (WEAK PULL-DOWN-MIN) 2-26 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Table 2-27 • I/O Short Currents IOSH/IOSL 1 1 Drive Strength IOSH (mA) IOSL (mA) 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24mA 268 181 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS 2.5 V LVCMOS 4 mA 16 18 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 1.8 V LVCMOS 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 1.5 V LVCMOS 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 1.2 V LVCMOS 2 mA TBD TBD 1. V LVCMOS Wide Range 100 µA TBD TBD 3.3 V PCI/PCIX Per PCI/PCI-X Per PCI Curves Specification 2 3.3 V GTL 20 mA 268 181 2 2.5 V GTL 20 mA 169 124 3.3 V GTL+ 35 mA 268 181 2.5 V GTL+ 33 mA 169 124 HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 66 55 SSTL2 (I) 15 mA 83 87 2 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 SSTL3 (II) 21 mA 103 109 Notes: 1. T = 100°C J 2. Output drive strength is below JEDEC specification. Revision 3 2-27 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics Table 2-28 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers Applicable Input Buffer Configuration Hysteresis Value (typical) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV The length of time an I/O can withstand I /I events depends on the junction temperature. The OSH OSL reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-29 • Duration of Short Circuit Event before Failure Temperature Time before Failure –55ºC > 20 years –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months 110°C 3 months 125°C 1 month Table 2-30 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C) LVDS/B-LVDS/ No requirement 10 ns * 10 years (100°C) M-LVDS/LVPECL Note: *The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2-28 Revision 3 Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-31 • Minimum and Maximum DC Output Levels 3.3 V LVTTL / 3.3 V LVCMOS VOL VOH IOL IOH IOSH IOSL Drive Max. Min. Max. Max. Strgth. V VmAmA mA mA –55 ≤ T ≤ 100 (ºC) 100