XILINX XCV600-4FG680I

0 R Virtex™ 2.5 V Field Programmable Gate Arrays 00 DS003-1 (v2.5 ) April 2, 2001 Product Specification Features • Fast, high-density Field-Programmable Gate Arrays  Supported by FPGA Foundation™ and Alliance Development Systems - Densities from 50k to 1M system gates - System performance up to 200 MHz - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - 66-MHz PCI Compliant - Wide selection of PC and workstation platforms - Hot-swappable for Compact PCI  SRAM-based in-system configuration  Multi-standard SelectIO™ interfaces - Unlimited re-programmability - 16 high-performance interface standards - Four programming modes - Connects directly to ZBTRAM devices 0.22 µm 5-layer metal process  Built-in clock-management circuitry  100% factory tested - Four dedicated delay-locked loops (DLLs) for advanced clock control Description - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets The Virtex FPGA family delivers high-performance,  Hierarchical memory system high-capacity programmable logic solutions. Dramatic - LUTs configurable as 16-bit RAM, 32-bit RAM, increases in silicon efficiency result from optimizing the new 16-bit dual-ported RAM, or 16-bit Shift Register architecture for place-and-route efficiency and exploiting an - Configurable synchronous dual-ported 4k-bit aggressive 5-layer-metal 0.22 µm CMOS process. These RAMs advances make Virtex FPGAs powerful and flexible alterna- tives to mask-programmed gate arrays. The Virtex family - Fast interfaces to external high-performance RAMs comprises the nine members shown in Table 1.  Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step - Dedicated multiplier support forward in programmable logic design. Combining a wide - Cascade chain for wide-input functions variety of programmable system features, a rich hierarchy of - Abundant registers/latches with clock enable, and fast, flexible interconnect resources, and advanced process dual synchronous/asynchronous set and reset technology, the Virtex family delivers a high-speed and - Internal 3-state bussing high-capacity programmable logic solution that enhances - IEEE 1149.1 boundary-scan logic design flexibility while reducing time-to-market. - Die-temperature sensor diode Table 1: Virtex Field-Programmable Gate Array Family Members Maximum Block RAM Maximum Device System Gates CLB Array Logic Cells Available I/O Bits SelectRAM+™ Bits XCV50 57,906 16x24 1,728 180 32,768 24,576 XCV100 108,904 20x30 2,700 180 40,960 38,400 XCV150 164,674 24x36 3,888 260 49,152 55,296 XCV200 236,666 28x42 5,292 284 57,344 75,264 XCV300 322,970 32x48 6,912 316 65,536 98,304 XCV400 468,252 40x60 10,800 404 81,920 153,600 XCV600 661,111 48x72 15,552 512 98,304 221,184 XCV800 888,439 56x84 21,168 512 114,688 301,056 XCV1000 1,124,022 64x96 27,648 512 131,072 393,216 © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-1 (v2.5 ) April 2, 2001 www.xilinx.com Module 1 of 4 Product Specification 1-800-255-7778 1 R Virtex™ 2.5 V Field Programmable Gate Arrays Xilinx thoroughly benchmarked the Virtex family. While per- Virtex Architecture formance is design-dependent, many designs operated Virtex devices feature a flexible, regular architecture that internally at speeds in excess of 100 MHz and can achieve comprises an array of configurable logic blocks (CLBs) sur- 200 MHz. Table 2 shows performance data for representa- rounded by programmable input/output blocks (IOBs), all tive circuits, using worst-case timing parameters. interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Table 2: Performance for Common Circuit Functions Virtex family to accommodate even the largest and most Function Bits Virtex -6 complex designs. Register-to-Register Virtex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In 16 5.0 ns some modes, the FPGA reads its own configuration data Adder 64 7.2 ns from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (Select- Pipelined Multiplier 8 x 8 5.1 ns MAP™, slave serial, and JTAG modes). 16 x 16 6.0 ns The standard Xilinx Foundation™ and Alliance Series™ Address Decoder 16 4.4 ns Development systems deliver complete design support for Virtex, covering every aspect from behavioral and sche- 64 6.4 ns matic entry, through simulation, automatic design transla- 16:1 Multiplexer 5.4 ns tion and implementation, to the creation, downloading, and readback of a configuration bit stream. Parity Tree 9 4.1 ns 18 5.0 ns Higher Performance 36 6.9 ns Virtex devices provide better performance than previous Chip-to-Chip generations of FPGA. Designs can achieve synchronous system clock rates up to 200 MHz including I/O. Virtex HSTL Class IV 200 MHz inputs and outputs comply fully with PCI specifications, and LVTTL,16mA, fast slew 180 MHz interfaces can be implemented that operate at 33 MHz or 66 MHz. Additionally, Virtex supports the hot-swapping requirements of Compact PCI. Module 1 of 4 www.xilinx.com DS003-1 (v2.5 ) April 2, 2001 2 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Device/Package Combinations and Maximum I/O Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 CS144 94 94 TQ144 98 98 PQ240 166 166 166 166 166 HQ240 166 166 166 BG256 180 180 180 180 BG352 260 260 260 BG432 316 316 316 316 BG560 404 404 404 404 FG256 176 176 176 176 FG456 260 284 312 FG676 404 444 444 FG680 512 512 512 Virtex Ordering Information Example: XCV300 -6 PQ 240 C Device Type Temperature Range C = Commercial (T = 0°C to +85°C) J I = Industrial (T = –40°C to +100°C) J Speed Grade -4 Number of Pins -5 -6 Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale Package Figure 1: Virtex Ordering Information DS003-1 (v2.5 ) April 2, 2001 www.xilinx.com Module 1 of 4 Product Specification 1-800-255-7778 3 R Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, “0” hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added T parameter, changed T to IJITCC OJIT T . OPHASE 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for V in CS144 package on p.43. CCO 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified “Pins not listed ...” statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18.  Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. 09/00 2.3  Corrected Units column in table under IOB Input Switching Characteristics.  Added values to table under CLB SelectRAM Switching Characteristics.  Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in 10/00 2.4 Table 18.  Corrected BG256 Pin Function Diagram.  Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. 04/01 2.5  Converted file to modularized format. See Virtex Data Sheet section. Virtex Data Sheet The Virtex Data Sheet contains the following modules:  DS003-1, Virtex 2.5V FPGAs:  DS003-3, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)  DS003-2, Virtex 2.5V FPGAs:  DS003-4, Virtex 2.5V FPGAs: Functional Description (Module 2) Pinout Tables (Module 4) Module 1 of 4 www.xilinx.com DS003-1 (v2.5 ) April 2, 2001 4 1-800-255-7778 Product Specification IOBs VersaRing BRAMs 0 R Virtex™ 2.5 V Field Programmable Gate Arrays 00 DS003-2 (v2.8.1) December 9, 2002 Product Specification The output buffer and all of the IOB control signals have Architectural Description independent polarity controls. Virtex Array The Virtex user-programmable gate array, shown in DLL IOBs DLL Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks VersaRing (IOBs).  CLBs provide the functional elements for constructing logic  IOBs provide the interface between the package pins and the CLBs CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlock™ that also provides local routing resources to connect the CLB to the GRM. The VersaRing™ I/O interface provides additional routing VersaRing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. IOBs DLL DLL The Virtex architecture also includes the following circuits that connect to the GRM. vao_b.eps  Dedicated block memories of 4096 bits each Figure 1: Virtex Architecture Overview  Clock DLLs for clock-distribution delay compensation and clock domain control All pads are protected against damage from electrostatic  3-State buffers (BUFTs) associated with each CLB that discharge (ESD) and from over-voltage transients. Two drive dedicated segmentable horizontal routing forms of over-voltage protection are provided, one that per- resources mits 5 V compliance, and one that does not. For 5 V compli- Values stored in static memory cells control the configurable ance, a Zener-like structure connected to ground turns on logic elements and interconnect resources. These values when the output rises to approximately 6.5 V. When PCI load into the memory cells on power-up, and can reload if 3.3 V compliance is required, a conventional clamp diode is necessary to change the function of the device. connected to the output supply voltage, V . CCO Input/Output Block Optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each pad. Prior to con- The Virtex IOB, Figure 2, features SelectIO™ inputs and figuration, all pins not involved in configuration are forced outputs that support a wide variety of I/O signalling stan- into their high-impedance state. The pull-down resistors and dards, see Table 1. the weak-keeper circuits are inactive, but inputs can option- The three IOB storage elements function either as edge-trig- ally be pulled up. gered D-type flip-flops or as level sensitive latches. Each The activation of pull-up resistors prior to configuration is IOB has a clock signal (CLK) shared by the three flip-flops controlled on a global basis by the configuration mode pins. and independent clock enable signals for each flip-flop. If the pull-up resistors are not activated, all the pins will float. Consequently, external pull-up or pull-down resistors must In addition to the CLK and CE control signals, the three be provided on pins required to be at a well-defined logic flip-flops share a Set/Reset (SR). For each flip-flop, this sig- level prior to configuration. nal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asyn- All Virtex IOBs support IEEE 1149.1-compatible boundary chronous Clear. scan testing. © 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 1 IOBs VersaRing BRAMs R Virtex™ 2.5 V Field Programmable Gate Arrays Q D T CE TCE Weak Keeper SR PAD Q O D CE OBUFT OCE SR I IQ Q Programmable D Delay CE IBUF Vref SR SR CLK ICE ds022_02_091300 Figure 2: Virtex Input/Output Block (IOB) Table 1: Supported Select I/O Standards Input Reference Output Source Board Termination I/O Standard Voltage (V ) Voltage (V ) Voltage (V )5 V Tolerant REF CCO TT LVTTL 2 – 24 mA N/A 3.3 N/A Yes LVCMOS2 N/A 2.5 N/A Yes PCI, 5 V N/A 3.3 N/A Yes PCI, 3.3 V N/A 3.3 N/A No GTL 0.8 N/A 1.2 No GTL+ 1.0 N/A 1.5 No HSTL Class I 0.75 1.5 0.75 No HSTL Class III 0.9 1.5 1.5 No HSTL Class IV 0.9 1.5 1.5 No SSTL3 Class I &II 1.5 3.3 1.5 No SSTL2 Class I & II 1.25 2.5 1.25 No CTT 1.5 3.3 1.5 No AGP 1.32 3.3 N/A No Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 2 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Eight I/O banks result from separating each edge of the Input Path FPGA into two banks, as shown in Figure 3. Each bank has A buffer In the Virtex IOB input path routes the input signal multiple V pins, all of which must be connected to the CCO either directly to internal logic or through an optional input same voltage. This voltage is determined by the output flip-flop. standards in use. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Bank 0 Bank 1 GCLK3 GCLK2 Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied Virtex threshold voltage, V . The need to supply V imposes REF REF Device constraints on which standards can used in close proximity to each other. See I/O Banking, page 3. GCLK1 GCLK0 There are optional pull-up and pull-down resistors at each Bank 5 Bank 4 user I/O input for use after configuration. Their value is in the range 50 kΩ – 100 kΩ. X8778_b Output Path Figure 3: Virtex I/O Banks The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be Within a bank, output standards can be mixed only if they routed to the buffer directly from the internal logic or through use the same V . Compatible standards are shown in CCO an optional IOB output flip-flop. Table 2. GTL and GTL+ appear under all voltages because The 3-state control of the output can also be routed directly their open-drain outputs do not depend on V . CCO from the internal logic or through a flip-flip that provides syn- chronous enable and disable. Table 2: Compatible Output Standards Each output driver can be individually programmed for a V Compatible Standards CCO wide range of low-voltage signalling standards. Each output 3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, buffer can source up to 24 mA and sink up to 48mA. Drive GTL+ strength and slew rate controls minimize bus transients. 2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+ In most signalling standards, the output High voltage depends on an externally supplied V voltage. The need CCO 1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+ to supply V imposes constraints on which standards CCO can be used in close proximity to each other. See I/O Bank- Some input standards require a user-supplied threshold ing, page 3. voltage, V . In this case, certain user-I/O pins are auto- REF An optional weak-keeper circuit is connected to each out- matically configured as inputs for the V voltage. Approx- REF put. When selected, the circuit monitors the voltage on the imately one in six of the I/O pins in the bank assume this pad and weakly drives the pin High or Low to match the role. input signal. If the pin is connected to a multiple-source sig- The V pins within a bank are interconnected internally REF nal, the weak keeper holds the signal in its last state if all and consequently only one V voltage can be used within REF drivers are disabled. Maintaining a valid logic level in this each bank. All V pins in the bank, however, must be con- REF way eliminates bus chatter. nected to the external voltage source for correct operation. Because the weak-keeper circuit uses the IOB input buffer Within a bank, inputs that require V can be mixed with REF to monitor the input level, an appropriate V voltage must REF those that do not. However, only one V voltage can be REF be provided if the signalling standard requires one. The pro- used within a bank. Input buffers that use V are not 5 V REF vision of this voltage must comply with the I/O banking tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V rules. tolerant. I/O Banking The V and V pins for each bank appear in the device CCO REF Some of the I/O standards described above require V Pinout tables and diagrams. The diagrams also show the CCO and/or V voltages. These voltages externally and con- bank affiliation of each I/O. REF nected to device pins that serve groups of IOBs, called Within a given package, the number of V and V pins REF CCO banks. Consequently, restrictions exist about which I/O can vary depending on the size of device. In larger devices, standards can be combined within a given bank. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 3 Bank 6 Bank 7 Bank 3 Bank 2 R Virtex™ 2.5 V Field Programmable Gate Arrays more I/O pins convert to V pins. Since these are always of five or six inputs. Consequently, when estimating the REF a superset of the V pins used for smaller devices, it is number of system gates provided by a given device, each REF possible to design a PCB that permits migration to a larger CLB counts as 4.5 LCs. device if necessary. All the V pins for the largest device REF Look-Up Tables anticipated must be connected to the V voltage, and not REF Virtex function generators are implemented as 4-input used for I/O. look-up tables (LUTs). In addition to operating as a function In smaller devices, some V pins used in larger devices CCO generator, each LUT can provide a 16 x 1-bit synchronous do not connect within the package. These unconnected pins RAM. Furthermore, the two LUTs within a slice can be com- can be left unconnected externally, or can be connected to bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, the V voltage to permit migration to a larger device if CCO or a 16x1-bit dual-port synchronous RAM. necessary. The Virtex LUT can also provide a 16-bit shift register that is In TQ144 and PQ/HQ240 packages, all V pins are CCO ideal for capturing high-speed or burst-mode data. This bonded together internally, and consequently the same mode can also be used to store data in applications such as V voltage must be connected to all of them. In the CCO Digital Signal Processing. CS144 package, bank pairs that share a side are intercon- nected internally, permitting four choices for V . In both Storage Elements CCO cases, the V pins remain internally connected as eight REF The storage elements in the Virtex slice can be configured banks, and can be used as described previously. either as edge-triggered D-type flip-flops or as level-sensi- tive latches. The D inputs can be driven either by the func- Configurable Logic Block tion generators within the slice or directly from slice inputs, The basic building block of the Virtex CLB is the logic cell bypassing the function generators. (LC). An LC includes a 4-input function generator, carry In addition to Clock and Clock Enable signals, each Slice logic, and a storage element. The output from the function has synchronous set and reset signals (SR and BY). SR generator in each LC drives both the CLB output and the D forces a storage element into the initialization state speci- input of the flip-flop. Each Virtex CLB contains four LCs, fied for it in the configuration. BY forces it into the opposite organized in two similar slices, as shown in Figure 4. state. Alternatively, these signals can be configured to oper- Figure 5 shows a more detailed view of a single slice. ate asynchronously. All of the control signals are indepen- dently invertible, and are shared by the two flip-flops within In addition to the four basic LCs, the Virtex CLB contains the slice. logic that combines function generators to provide functions COUT COUT YB YB Y Y G4 G4 SP SP G3 G3 Carry & Carry & LUT LUT D Q YQ D Q YQ G2 Control G2 Control EC EC G1 G1 RC RC BY BY XB XB X X F4 F4 SP SP F3 F3 LUT Carry & LUT Carry & D Q XQ D Q XQ F2 F2 Control Control EC EC F1 F1 RC RC BX BX Slice 1 Slice 0 slice_b.eps CIN CIN Figure 4: 2-Slice Virtex CLB Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 4 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays COUT YB CY G4 I3 Y O G3 I2 LUT G2 I1 INIT D G1 I0 Q YQ WE DI EC 0 1 REV BY XB F5IN F6 CY F5 F5 BY DG CK WSO X WE A4 BX WSH DI INIT D Q XQ BX EC DI WE I3 F4 I2 F3 REV O I1 F2 LUT I0 F1 0 1 SR CLK CE CIN viewslc4.eps Figure 5: Detailed View of VIrtex Slice Additional Logic Block SelectRAM The F5 multiplexer in each slice combines the function gen- Virtex FPGAs incorporate several large block SelectRAM erator outputs. This combination provides either a function memories. These complement the distributed LUT generator that can implement any 5-input function, a 4:1 SelectRAMs that provide shallow RAM structures imple- multiplexer, or selected functions of up to nine inputs. mented in CLBs. Similarly, the F6 multiplexer combines the outputs of all four Block SelectRAM memory blocks are organized in columns. function generators in the CLB by selecting one of the All Virtex devices contain two such columns, one along F5-multiplexer outputs. This permits the implementation of each vertical edge. These columns extend the full height of any 6-input function, an 8:1 multiplexer, or selected func- the chip. Each memory block is four CLBs high, and conse- tions of up to 19 inputs. quently, a Virtex device 64 CLBs high contains 16 memory Each CLB has four direct feedthrough paths, one per LC. blocks per column, and a total of 32 blocks. These paths provide extra data input lines or additional local Table 3 shows the amount of block SelectRAM memory that routing that does not consume logic resources. is available in each Virtex device. Arithmetic Logic Table 3: Virtex Block SelectRAM Amounts Dedicated carry logic provides fast arithmetic carry capabil- Device # of Blocks Total Block SelectRAM Bits ity for high-speed arithmetic functions. The Virtex CLB sup- ports two separate carry chains, one per Slice. The height XCV50 8 32,768 of the carry chains is two bits per CLB. XCV100 10 40,960 The arithmetic logic includes an XOR gate that allows a XCV150 12 49,152 1-bit full adder to be implemented within an LC. In addition, a dedicated AND gate improves the efficiency of multiplier XCV200 14 57,344 implementation. XCV300 16 65,536 The dedicated carry path can also be used to cascade func- tion generators for implementing wide logic functions. XCV400 20 81,920 BUFTs XCV600 24 98,304 Each Virtex CLB contains two 3-state drivers (BUFTs) that XCV800 28 114,688 can drive on-chip busses. See Dedicated Routing, page 7. Each Virtex BUFT has an independent 3-state control pin XCV1000 32 131,072 and an independent input pin. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 5 R Virtex™ 2.5 V Field Programmable Gate Arrays Each block SelectRAM cell, as illustrated in Figure 6, is a Table 4: Block SelectRAM Port Aspect Ratios fully synchronous dual-ported 4096-bit RAM with indepen- Width Depth ADDR Bus Data Bus dent control signals for each port. The data widths of the two ports can be configured independently, providing 1 4096 ADDR<11:0> DATA<0> built-in bus-width conversion. 2 2048 ADDR<10:0> DATA<1:0> 4 1024 ADDR<9:0> DATA<3:0> RAMB4_S#_S# 8 512 ADDR<8:0> DATA<7:0> WEA ENA 16 256 ADDR<7:0> DATA<15:0> RSTA DOA[#:0] CLKA ADDRA[#:0] The Virtex block SelectRAM also includes dedicated routing DIA[#:0] to provide an efficient interface with both CLBs and other block SelectRAMs. Refer to XAPP130 for block SelectRAM timing waveforms. WEB ENB RSTB DOB[#:0] Programmable Routing Matrix CLKB It is the longest delay path that limits the speed of any ADDRB[#:0] DIB[#:0] worst-case design. Consequently, the Virtex routing archi- tecture and its place-and-route software were defined in a xcv_ds_006 single optimization process. This joint optimization mini- Figure 6: Dual-Port Block SelectRAM mizes long-path delays, and consequently, yields the best system performance. Table 4 shows the depth and width aspect ratios for the The joint optimization also reduces design compilation block SelectRAM. times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times. To Adjacent GRM To Adjacent To Adjacent GRM GRM GRM To Adjacent GRM Direct Connection Direct Connection CLB To Adjacent To Adjacent CLB CLB X8794b Figure 7: Virtex Local Routing  Internal CLB feedback paths that provide high-speed Local Routing connections to LUTs within the same CLB, chaining The VersaBlock provides local routing resources, as shown them together with minimal routing delay in Figure 7, providing the following three types of connec-  Direct paths that provide high-speed connections tions. between horizontally adjacent CLBs, eliminating the  Interconnections among the LUTs, flip-flops, and GRM delay of the GRM. Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 6 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays  12 Longlines are buffered, bidirectional wires that General Purpose Routing distribute signals across the device quickly and Most Virtex signals are routed on the general purpose rout- efficiently. Vertical Longlines span the full height of the ing, and consequently, the majority of interconnect device, and horizontal ones span the full width of the resources are associated with this level of the routing hier- device. archy. The general routing resources are located in horizon- tal and vertical routing channels associated with the rows I/O Routing and columns CLBs. The general-purpose routing resources Virtex devices have additional routing resources around are listed below. their periphery that form an interface between the CLB array  Adjacent to each CLB is a General Routing Matrix and the IOBs. This additional routing, called the VersaRing, (GRM). The GRM is the switch matrix through which facilitates pin-swapping and pin-locking, such that logic horizontal and vertical routing resources connect, and redesigns can adapt to existing PCB layouts. Time-to-mar- is also the means by which the CLB gains access to ket is reduced, since PCBs and other system components the general purpose routing. can be manufactured while the logic design is still in  24 single-length lines route GRM signals to adjacent progress. GRMs in each of the four directions. Dedicated Routing  12 buffered Hex lines route GRM signals to another Some classes of signal require dedicated routing resources GRMs six-blocks away in each one of the four to maximize performance. In the Virtex architecture, dedi- directions. Organized in a staggered pattern, Hex lines cated routing resources are provided for two classes of sig- can be driven only at their endpoints. Hex-line signals nal. can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of  Horizontal routing resources are provided for on-chip the Hex lines are bidirectional, while the remaining 3-state busses. Four partitionable bus lines are ones are uni-directional. provided per CLB row, permitting multiple busses within a row, as shown in Figure 8.  Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB. Tri-State Lines CLB CLB CLB CLB buft_c.eps Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines  The secondary local clock routing resources consist of Global Routing 24 backbone lines, 12 across the top of the chip and 12 Global Routing resources distribute clocks and other sig- across bottom. From these lines, up to 12 unique nals with very high fanout throughout the device. Virtex signals per column can be distributed via the 12 devices include two tiers of global routing resources longlines in the column. These secondary resources referred to as primary global and secondary local clock rout- are more flexible than the primary resources since they ing resources. are not restricted to routing only to clock pins.  The primary global routing resources are four Clock Distribution dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with Virtex provides high-speed, low-skew clock distribution minimal skew. Each global clock net can drive all CLB, through the primary global routing resources described IOB, and block RAM clock pins. The primary global above. A typical clock distribution net is shown in Figure 9. nets can only be driven by global buffers. There are Four global buffers are provided, two at the top center of the four global buffers, one for each global net. device and two at the bottom center. These drive the four primary global nets that in turn drive any clock pin. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 7 R Virtex™ 2.5 V Field Programmable Gate Arrays Four dedicated clock pads are provided, one adjacent to selected either from these pads or from signals in the gen- each of the global buffers. The input to the global buffer is eral purpose routing. GCLKPAD2 GCLKPAD3 Global Clock Rows GCLKBUF3 GCLKBUF2 Global Clock Column Global Clock Spine GCLKBUF1 GCLKBUF0 GCLKPAD0 GCLKPAD1 gclkbu_2.eps Figure 9: Global Clock Distribution Network Delay-Locked Loop (DLL) Boundary Scan Associated with each global clock input buffer is a fully digi- Virtex devices support all the mandatory boundary-scan tal Delay-Locked Loop (DLL) that can eliminate skew instructions specified in the IEEE standard 1149.1. A Test between the clock input pad and internal clock-input pins Access Port (TAP) and registers are provided that implement throughout the device. Each DLL can drive two global clock the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, networks.The DLL monitors the input clock and the distrib- IDCODE, USERCODE, and HIGHZ instructions. The TAP uted clock, and automatically adjusts a clock delay element. also supports two internal scan chains and configura- Clock edges reach internal flip-flops one to four clock peri- tion/readback of the device.The TAP uses dedicated package ods after they arrive at the input. This closed-loop system pins that always operate using LVTTL. For TDO to operate effectively eliminates clock-distribution delay by ensuring using LVTTL, the V for Bank 2 should be 3.3 V. Other- CCO that clock edges arrive at internal flip-flops in synchronism wise, TDO switches rail-to-rail between ground and V . CCO with clock edges arriving at the input. Boundary-scan operation is independent of individual IOB In addition to eliminating clock-distribution delay, the DLL configurations, and unaffected by package type. All IOBs, provides advanced control of multiple clock domains. The including un-bonded ones, are treated as independent DLL provides four quadrature phases of the source clock, 3-state bidirectional pins in a single scan chain. Retention of can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, the bidirectional test capability after configuration facilitates 5, 8, or 16. the testing of external interconnections, provided the user design or application is turned off. The DLL also operates as a clock mirror. By driving the out- put from a DLL off-chip and then back on again, the DLL can Table 5 lists the boundary-scan instructions supported in be used to de-skew a board level clock among multiple Vir- Virtex FPGAs. Internal signals can be captured during tex devices. EXTEST by connecting them to un-bonded or unused IOBs. They can also be connected to the unused outputs of IOBs In order to guarantee that the system clock is operating cor- defined as unidirectional input pins. rectly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process Before the device is configured, all instructions except until after it has achieved lock. USER1 and USER2 are available. After configuration, all instructions are available. During configuration, it is recom- See DLL Timing Parameters, page 21 of Module 3, for fre- mended that those operations using the boundary-scan quency range information. register (SAMPLE/PRELOAD, INTEST, EXTEST) not be performed. Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 8 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays In addition to the test instructions outlined above, the The FPGA supports up to two additional internal scan boundary-scan circuitry can be used to configure the chains that can be specified using the BSCAN macro. The FPGA, and also to read back the configuration data. macro provides two user pins (SEL1 and SEL2) which are decodes of the USER1 and USER2 instructions respec- Figure 10 is a diagram of the Virtex Series boundary scan tively. For these instructions, two corresponding pins (TDO1 logic. It includes three bits of Data Register per IOB, the and TDO2) allow user scan data to be shifted out of TDO. IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. Likewise, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin Instruction Set (TDI) and shared output pins that represent the state of the The Virtex Series boundary scan instruction set also TAP controller (RESET, SHIFT, and UPDATE). includes instructions to configure the device and read back Bit Sequence configuration data (CFG_IN, CFG_OUT, and JSTART). The complete instruction set is coded as shown in Table 5. The order within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary Data Registers scan I/O data register, while the output-only pins contributes The primary data register is the boundary scan register. For all three bits. each IOB pin in the FPGA, bonded or not, it includes three From a cavity-up view of the chip (as shown in EPIC), start- bits for In, Out, and 3-State Control. Non-IOB pins have ing in the upper right chip corner, the boundary scan appropriate partial bit population if input-only or output-only. data-register bits are ordered as shown in Figure 11. Each EXTEST CAPTURED-OR state captures all In, Out, BSDL (Boundary Scan Description Language) files for Vir- and 3-state pins. tex Series devices are available on the Xilinx web site in the The other standard data register is the single flip-flop File Download area. BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. DATA IN IOB.T 0 1 sd 1 D Q DQ 0 LE IOB IOB IOB IOB IOB IOB IOB sd 1 D Q DQ 0 IOB IOB LE IOB IOB 1 IOB.I 0 IOB IOB 1 sd D Q DQ IOB IOB 0 LE IOB IOB 1 0 IOB.Q IOB IOB BYPASS REGISTER IOB.T 0 M TDO 1 sd INSTRUCTION REGISTER U 1 TDI D Q DQ X 0 LE 1 sd D Q DQ 0 LE 1 IOB.I 0 DATAOUT UPDATE EXTEST SHIFT/ CLOCK DATA CAPTURE REGISTER X9016 Figure 10: Virtex Series Boundary Scan Logic DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 9 R Virtex™ 2.5 V Field Programmable Gate Arrays Identification Registers Right half of Top-edge IOBs (Right-to-Left) Bit 0 ( TDO end) Bit 1 The IDCODE register is supported. By using the IDCODE, GCLK2 Bit 2 the device connected to the JTAG port can be determined. GCLK3 Left half of Top-edge IOBs (Right-to-Left) The IDCODE register has the following binary format: Left-edge IOBs (Top-to-Bottom) vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 M1 where M0 M2 v = the die version number Left half of Bottom-edge IOBs (Left-to-Right) f = the family code (03h for Virtex family) GCLK1 GCLK0 a = the number of CLB rows (ranges from 010h for XCV50 Right half of Bottom-edge IOBs (Left-to-Right) to 040h for XCV1000) DONE c = the company code (49h for Xilinx) PROG The USERCODE register is supported. By using the USER- Right-edge IOBs (Bottom -to-Top) CODE, a user-programmable identification code can be (TDI end) CCLK loaded and shifted out for examination. The identification 990602001 code is embedded in the bitstream during bitstream gener- Figure 11: Boundary Scan Bit Sequence ation and is valid only after configuration. Table 6: IDCODEs Assigned to Virtex FPGAs Table 5: Boundary Scan Instructions FPGA IDCODE Boundary-Scan Binary Command Code(4:0) Description XCV50 v0610093h EXTEST 00000 Enables boundary-scan XCV100 v0614093h EXTEST operation XCV150 v0618093h SAMPLE/PRELOAD 00001 Enables boundary-scan SAMPLE/PRELOAD XCV200 v061C093h operation XCV300 v0620093h USER 1 00010 Access user-defined XCV400 v0628093h register 1 XCV600 v0630093h USER 2 00011 Access user-defined register 2 XCV800 v0638093h CFG_OUT 00100 Access the configuration XCV1000 v0640093h bus for read operations. CFG_IN 00101 Access the configuration Including Boundary Scan in a Design bus for write operations. Since the boundary scan pins are dedicated, no special ele- INTEST 00111 Enables boundary-scan ment needs to be added to the design unless an internal INTEST operation data register (USER1 or USER2) is desired. USERCODE 01000 Enables shifting out If an internal data register is used, insert the boundary scan USER code symbol and connect the necessary pins as appropriate. IDCODE 01001 Enables shifting out of ID Code Development System HIGHZ 01010 3-states output pins while Virtex FPGAs are supported by the Xilinx Foundation and enabling the Bypass Alliance CAE tools. The basic methodology for Virtex design Register consists of three interrelated steps: design entry, imple- JSTART 01100 Clock the start-up mentation, and verification. Industry-standard tools are sequence when used for design entry and simulation (for example, Synop- StartupClk is TCK sys FPGA Express), while Xilinx provides proprietary archi- BYPASS 11111 Enables BYPASS tecture-specific tools for implementation. The Xilinx development system is integrated under the Xil- RESERVED All other Xilinx reserved codes instructions inx Design Manager (XDM™) software, providing designers Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 10 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays with a common user interface regardless of their choice of design, thus allowing the most convenient entry method to entry and verification tools. The XDM software simplifies the be used for each portion of the design. selection of implementation options with pull-down menus and on-line help. Design Implementation The place-and-route tools (PAR) automatically provide the Application programs ranging from schematic capture to implementation flow described in this section. The parti- Placement and Routing (PAR) can be accessed through the tioner takes the EDIF net list for the design and maps the XDM software. The program command sequence is gener- logic into the architectural resources of the FPGA (CLBs ated prior to execution, and stored for documentation. and IOBs, for example). The placer then determines the Several advanced software features facilitate Virtex design. best locations for these blocks based on their interconnec- RPMs, for example, are schematic-based macros with rela- tions and the desired performance. Finally, the router inter- tive location constraints to guide their placement. They help connects the blocks. ensure optimal implementation of common functions. The PAR algorithms support fully automatic implementation For HDL design entry, the Xilinx FPGA Foundation develop- of most designs. For demanding applications, however, the ment system provides interfaces to the following synthesis user can exercise various degrees of control over the pro- design environments. cess. User partitioning, placement, and routing information  Synopsys (FPGA Compiler, FPGA Express) is optionally specified during the design-entry process. The implementation of highly structured designs can benefit  Exemplar (Spectrum) greatly from basic floor planning.  Synplicity (Synplify) ® The implementation software incorporates Timing Wizard For schematic design entry, the Xilinx FPGA Foundation timing-driven placement and routing. Designers specify tim- and alliance development system provides interfaces to the ing requirements along entire paths during design entry. following schematic-capture design environments. The timing path analysis routines in PAR then recognize  Mentor Graphics V8 (Design Architect, QuickSim II) these user-specified requirements and accommodate them.  Viewlogic Systems (Viewdraw) Timing requirements are entered on a schematic in a form Third-party vendors support many other environments. directly relating to the system requirements, such as the tar- geted clock frequency, or the maximum allowable delay A standard interface-file specification, Electronic Design between two registers. In this way, the overall performance Interchange Format (EDIF), simplifies file transfers into and of the system along entire signal paths is automatically tai- out of the development system. lored to user-generated specifications. Specific timing infor- Virtex FPGAs supported by a unified library of standard mation for individual nets is unnecessary. functions. This library contains over 400 primitives and mac- ros, ranging from 2-input AND gates to 16-bit accumulators, Design Verification and includes arithmetic functions, comparators, counters, In addition to conventional software simulation, FPGA users data registers, decoders, encoders, I/O functions, latches, can use in-circuit debugging techniques. Because Xilinx Boolean functions, multiplexers, shift registers, and barrel devices are infinitely reprogrammable, designs can be veri- shifters. fied in real time without the need for extensive sets of soft- The “soft macro” portion of the library contains detailed ware simulation vectors. descriptions of common logic functions, but does not con- The development system supports both software simulation tain any partitioning or placement information. The perfor- and in-circuit debugging techniques. For simulation, the mance of these macros depends, therefore, on the system extracts the post-layout timing information from the partitioning and placement obtained during implementation. design database, and back-annotates this information into RPMs, on the other hand, do contain predetermined parti- the net list for use by the simulator. Alternatively, the user tioning and placement information that permits optimal can verify timing-critical portions of the design using the implementation of these functions. Users can create their ® TRACE static timing analyzer. own library of soft macros or RPMs based on the macros For in-circuit debugging, the development system includes and primitives in the standard library. a download and readback cable. This cable connects the The design environment supports hierarchical design entry, FPGA in the target system to a PC or workstation. After with high-level schematics that comprise major functional downloading the design into the FPGA, the designer can blocks, while lower-level schematics define the logic in single-step the logic, readback the contents of the flip-flops, these blocks. These hierarchical design elements are auto- and so observe the internal logic state. Simple modifica- matically combined by the implementation tools. Different tions can be downloaded into the system in a matter of min- design entry tools can be combined within a hierarchical utes. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 11 R Virtex™ 2.5 V Field Programmable Gate Arrays After Virtex devices are configured, unused IOBs function Configuration as 3-state OBUFTs with weak pull downs. For a more Virtex devices are configured by loading configuration data detailed description than that given below, see the into the internal configuration memory. Some of the pins XAPP138, Virtex Configuration and Readback. used for this are dedicated configuration pins, while others can be re-used as general purpose inputs and outputs once Configuration Modes configuration is complete. Virtex supports the following four configuration modes. The following are dedicated pins:  Slave-serial mode  Mode pins (M2, M1, M0)  Master-serial mode  Configuration clock pin (CCLK)  SelectMAP mode  PROGRAM pin  Boundary-scan mode  DONE pin The Configuration mode pins (M2, M1, M0) select among  Boundary-scan pins (TDI, TDO, TMS, TCK) these configuration modes with the option in each case of Depending on the configuration mode chosen, CCLK can having the IOB pins either pulled up or left floating prior to be an output generated by the FPGA, or it can be generated configuration. The selection codes are listed in Table 7. externally and provided to the FPGA as an input. The Configuration through the boundary-scan port is always PROGRAM pin must be pulled High prior to reconfiguration. available, independent of the mode selection. Selecting the Note that some configuration pins can act as outputs. For boundary-scan mode simply turns off the other modes. The correct operation, these pins can require a V of 3.3 V to CCO three mode pins have internal pull-up resistors, and default permit LVTTL operation. All the pins affected are in banks 2 to a logic High if left unconnected. However, it is recom- or 3. The configuration pins needed for SelectMap (CS, mended to drive the configuration mode pins externally. Write) are located in bank 1. Table 7: Configuration Codes Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial D Configuration Pull-ups out Master-serial mode 0 0 0 Out 1 Yes No Boundary-scan mode 1 0 1 N/A 1 No No SelectMAP mode 1 1 0 In 8 No No Slave-serial mode 1 1 1 In 1 Yes No Master-serial mode 1 0 0 Out 1 Yes Yes Boundary-scan mode 0 0 1 N/A 1 No Yes SelectMAP mode 0 1 0 In 8 No Yes Slave-serial mode 0 1 1 In 1 Yes Yes mixed configuration chains. This change was made to Slave-Serial Mode improve serial configuration rates for Virtex-only chains. In slave-serial mode, the FPGA receives configuration data Figure 12 shows a full master/slave system. A Virtex device in bit-serial form from a serial PROM or other source of in slave-serial mode should be connected as shown in the serial configuration data. The serial bitstream must be setup third device from the left. at the DIN input pin a short time before each rising edge of an externally generated CCLK. Slave-serial mode is selected by applying <111> or <011> to the mode pins (M2, M1, M0). A weak pull-up on the mode For more information on serial PROMs, see the PROM data pins makes slave-serial the default mode if the pins are left sheet at: unconnected. However, it is recommended to drive the con- http://www.xilinx.com/bvdocs/publications/ds026.pdf. figuration mode pins externally. Figure 13 shows Multiple FPGAs can be daisy-chained for configuration from a slave-serial mode programming switching characteristics. single source. After a particular FPGA has been configured, Table 8 provides more detail about the characteristics the data for the next device is routed to the DOUT pin. The shown in Figure 13. Configuration must be delayed until the data on the DOUT pin changes on the rising edge of CCLK. INIT pins of all daisy-chained FPGAs are High. The change of DOUT on the rising edge of CCLK differs from previous families, but does not cause a problem for Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 12 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 8: Master/Slave Serial Mode Programming Switching Figure Description References Symbol Values Units DIN setup/hold, slave mode 1/2 T /T 5.0 / 0 ns, min CCD DCC DIN setup/hold, master mode 1/2 T /T 5.0 / 0 ns, min DSCK CKDS DOUT 3 T 12.0 ns, max CCO High time 4 T 5.0 ns, min CCH CCLK Low time 5 T 5.0 ns, min CCL Maximum Frequency F 66 MHz, max CC Frequency Tolerance, master mode with +45% respect to nominal –30% V 3.3V CC M0 M1 4.7 K M0 M1 M2 M2 DOUT DIN DOUT CCLK VIRTEX MASTER VIRTEX, XC1701L SERIAL XC4000XL, CCLK CLK SLAVE Optional Pull-up DIN DATA 1 PROGRAM CE CEO PROGRAM Resistor on Done DONE RESET/OE DONE INIT INIT (Low Reset Option Used) PROGRAM Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to the common DONE line. xcv_12_091499 Figure 12: Master/Slave Serial Mode Circuit Diagram DIN 1 T 2 T 5 T DCC CCD CCL CCLK 4 T CCH 3 T CCO DOUT (Output) X5379_a Figure 13: Slave-Serial Mode Programming Switching Characteristics DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 13 R Virtex™ 2.5 V Field Programmable Gate Arrays daisy-chained FPGAs are fast enough to support the clock Master-Serial Mode rate. In master-serial mode, the CCLK output of the FPGA drives On power-up, the CCLK frequency is 2.5 MHz. This fre- a Xilinx Serial PROM that feeds bit-serial data to the DIN quency is used until the ConfigRate bits have been loaded input. The FPGA accepts this data on each rising CCLK when the frequency changes to the selected ConfigRate. edge. After the FPGA has been loaded, the data for the next Unless a different frequency is specified in the design, the device in a daisy-chain is presented on the DOUT pin after default ConfigRate is 4 MHz. the rising CCLK edge. Figure 12 shows a full master/slave system. In this system, The interface is identical to slave-serial except that an inter- the left-most device operates in master-serial mode. The nal oscillator is used to generate the configuration clock remaining devices operate in slave-serial mode. The (CCLK). A wide range of frequencies can be selected for SPROM RESET pin is driven by INIT, and the CE input is CCLK which always starts at a slow default frequency. Con- driven by DONE. There is the potential for contention on the figuration bits then switch CCLK to a higher frequency for DONE pin, depending on the start-up sequence options the remainder of the configuration. Switching to a lower fre- chosen. quency is prohibited. Figure 14 shows the timing of master-serial configuration. The CCLK frequency is set using the ConfigRate option in Master-serial mode is selected by a <000> or <100> on the the bitstream generation software. The maximum CCLK fre- mode pins (M2, M1, M0). Table 8 shows the timing informa- quency that can be selected is 60 MHz. When selecting a tion for Figure 14. CCLK frequency, ensure that the serial PROM and any CCLK (Output) T 2 CKDS 1 T DSCK Serial Data In Serial DOUT (Output) DS022_44_071201 Figure 14: Master-Serial Mode Programming Switching Characteristics At power-up, V must rise from 1.0 V to V min in less In the SelectMAP mode, multiple Virtex devices can be CC CC than 50ms, otherwise delay configuration by pulling chained in parallel. DATA pins (D7:D0), CCLK, WRITE, PROGRAM Low until V is valid. BUSY, PROGRAM, DONE, and INIT can be connected in CC parallel between all the FPGAs. Note that the data is orga- The sequence of operations necessary to configure a Virtex nized with the MSB of each byte on pin DO and the LSB of FPGA serially appears in Figure 15. each byte on D7. The CS pins are kept separate, insuring SelectMAP Mode that each FPGA can be selected individually. WRITE should be Low before loading the first bitstream and returned High The SelectMAP mode is the fastest configuration option. after the last device has been programmed. Use CS to Byte-wide data is written into the FPGA with a BUSY flag select the appropriate FPGA for loading the bitstream and controlling the flow of data. sending the configuration data. at the end of the bitstream, An external data source provides a byte stream, CCLK, a deselect the loaded device and select the next target FPGA Chip Select (CS) signal and a Write signal (WRITE). If by setting its CS pin High. A free-running oscillator or other BUSY is asserted (High) by the FPGA, the data must be externally generated signal can be used for CCLK. The held until BUSY goes Low. BUSY signal can be ignored for frequencies below 50 MHz. Data can also be read using the SelectMAP mode. If For details about frequencies above 50 MHz, see WRITE is not asserted, configuration data is read out of the XAPP138, Virtex Configuration and Readback. Once all the FPGA as part of a readback operation. devices have been programmed, the DONE pin goes High. Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 14 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases If used to delay Release INIT INIT when finished. configuration Low INIT? High Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. End of No Bitstream? If no CRC errors found, Yes FPGA enters start-up phase causing DONE to go High. Configuration Completed ds003_154_111799 Figure 15: Serial Configuration Flowchart After configuration, the pins of the SelectMAP port can be Multiple Virtex FPGAs can be configured using the Select- used as additional user I/O. Alternatively, the port can be MAP mode, and be made to start-up simultaneously. To retained to permit high-speed 8-bit readback. configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in Retention of the SelectMAP port is selectable on a parallel. The individual devices are loaded separately by design-by-design basis when the bitstream is generated. If asserting the CS pin of each device in turn and writing the retention is selected, PROHIBIT constraints are required to appropriate data. See Table 9 for SelectMAP Write Timing prevent the SelectMAP-port pins from being used as user Characteristics. I/O. . Table 9: SelectMAP Write Timing Characteristics Description Symbol Units DSetup/Hold 1/2T /T 5.0 / 1.7 ns, min 0-7 SMDCC SMCCD CS Setup/Hold 3/4 T /T 7.0 / 1.7 ns, min SMCSCC SMCCCS WRITE Setup/Hold 5/6 T /T 7.0 / 1.7 ns, min SMCCW SMWCC CCLK BUSY Propagation Delay 7 T 12.0 ns, max SMCKBY Maximum Frequency F 66 MHz, max CC Maximum Frequency with no handshake F 50 MHz, max CCNH Write 1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain Write operations send packets of configuration data into the either asserted or de-asserted. Otherwise an abort will FPGA. The sequence of operations for a multi-cycle write be initiated, as described below. operation is shown below. Note that a configuration packet 2. Drive data onto D[7:0]. Note that to avoid contention, can be split into many such sequences. The packet does the data source should not be enabled while CS is Low not have to complete within one assertion of CS, illustrated and WRITE is High. Similarly, while WRITE is High, no in Figure 16. more that one CS should be asserted. DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 15 R Virtex™ 2.5 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is 5. De-assert CS and WRITE. accepted on this clock. If BUSY is High (from a previous A flowchart for the write operation appears in Figure 17. write), the data is not accepted. Acceptance will instead Note that if CCLK is slower than f , the FPGA never CCNH occur on the first clock after BUSY goes Low, and the asserts BUSY. In this case, the above handshake is unnec- data must be held until this has happened. essary, and data can simply be entered into the FPGA every 4. Repeat steps 2 and 3 until all the data has been sent. CCLK cycle. CCLK 3 4 CS 5 6 WRITE 1 2 DATA[0:7] 7 BUSY Write Write No Write Write ds003_16_071902 Figure 16: Write Operations Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 16 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Apply Power FPGA starts to clear configuration memory. PROGRAM No from Low to High FPGA makes a final Yes clearing pass and releases If used to delay INIT when finished. Release INIT configuration Low INIT? High Set WRITE = Low Enter Data Source Sequence A On first FPGA Set CS = Low Apply Configuration Byte Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. High Busy? Low No End of Data? If no errors, Yes first FPGAs enter start-up phase releasing DONE. On first FPGA Set CS = High If no errors, For any other FPGAs Repeat Sequence A later FPGAs enter start-up phase releasing DONE. Disable Data Source Set WRITE = High When all DONE pins are released, DONE goes High Configuration Completed and start-up sequences complete. ds003_17_090602 Figure 17: SelectMAP Flowchart for Write Operation Abort aries, and the FPGA requires a new synchronization word prior to accepting any new packets. During a given assertion of CS, the user cannot switch from To initiate an abort during a write operation, de-assert a write to a read, or vice-versa. This action causes the cur- WRITE. At the rising edge of CCLK, an abort is initiated, as rent packet command to be aborted. The device will remain shown in Figure 18. BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word bound- DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 17 R Virtex™ 2.5 V Field Programmable Gate Arrays The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire process is sig- nalled by DONE going High. CCLK The power-up timing of configuration signals is shown in Figure 19. The corresponding timing characteristics are CS listed in Table 10. WRITE V TPOR CC DATA[0:7] PROGRAM BUSY TPI INIT Abort X8797_c TICCK CCLK OUTPUT or INPUT M0, M1, M2 Figure 18: SelectMAP Write Abort Waveforms VALID (Required) 98122302 Boundary-Scan Mode Figure 19: Power-Up Timing Configuration Signals In the boundary-scan mode, configuration is done through the IEEE 1149.1 Test Access Port. Note that the Table 10: Power-up Timing Characteristics PROGRAM pin must be pulled High prior to reconfiguration. Description Symbol Value Units A Low on the PROGRAM pin resets the TAP controller and no JTAG operations can be performed. Power-on Reset T 2.0 ms, max POR Configuration through the TAP uses the CFG_IN instruc- Program Latency T 100.0 µs, max PL tion. This instruction allows data input on TDI to be con- verted into data packets for the internal configuration bus. CCLK (output) Delay T 0.5 µs, min ICCK The following steps are required to configure the FPGA 4.0 µs, max through the boundary-scan port (when using TCK as a Program Pulse Width T 300 ns, min PROGRAM start-up clock). 1. Load the CFG_IN instruction into the boundary-scan Delaying Configuration instruction register (IR) INIT can be held Low using an open-drain driver. An 2. Enter the Shift-DR (SDR) state open-drain is required since INIT is a bidirectional 3. Shift a configuration bitstream into TDI open-drain pin that is held Low by the FPGA while the con- 4. Return to Run-Test-Idle (RTI) figuration memory is being cleared. Extending the time that 5. Load the JSTART instruction into IR the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the 6. Enter the SDR state phase where data is loaded. 7. Clock TCK through the startup sequence 8. Return to RTI Start-Up Sequence Configuration and readback via the TAP is always available. The default Start-up sequence is that one CCLK cycle after The boundary-scan mode is selected by a <101> or 001> DONE goes High, the global 3-state signal (GTS) is released. on the mode pins (M2, M1, M0). For details on TAP charac- This permits device outputs to turn on as necessary. teristics, refer to XAPP139. One CCLK cycle later, the Global Set/Reset (GSR) and Glo- bal Write Enable (GWE) signals are released. This permits Configuration Sequence the internal storage elements to begin changing state in The configuration of Virtex devices is a three-phase pro- response to the logic and the user clock. cess. First, the configuration memory is cleared. Next, con- The relative timing of these events can be changed. In addi- figuration data is loaded into the memory, and finally, the tion, the GTS, GSR, and GWE events can be made depen- logic is activated by a start-up process. dent on the DONE pins of multiple devices all going High, Configuration is automatically initiated on power-up unless forcing the devices to start in synchronism. The sequence it is delayed by the user, as described below. The configura- can also be paused at any stage until lock has been tion process can also be initiated by asserting PROGRAM. achieved on any or all DLLs. Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 18 1-800-255-7778 Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Data Stream Format Readback Virtex devices are configured by sequentially loading The configuration data stored in the Virtex configuration frames of data. Table 11 lists the total number of bits memory can be readback for verification. Along with the required to configure each device. For more detailed infor- configuration data it is possible to readback the contents all mation, see application note XAPP151 “Virtex Configura- flip-flops/latches, LUTRAMs, and block RAMs. This capabil- tion Architecture Advanced Users Guide”. ity is used for real-time debugging. For more detailed information, see Application Note Table 11: Virtex Bit-Stream Lengths XAPP138: Virtex FPGA Series Configuration and Readback, Device # of Configuration Bits available online at www.xilinx.com. XCV50 559,200 XCV100 781,216 XCV150 1,040,096 XCV200 1,335,840 XCV300 1,751,808 XCV400 2,546,048 XCV600 3,607,968 XCV800 4,715,616 XCV1000 6,127,744 Revision History Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, “0” hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added T parameter, changed T to T . IJITCC OJIT OPHASE 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for V in CS144 package on p.43. CCO DS003-2 (v2.8.1) December 9, 2002 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 19 R Virtex™ 2.5 V Field Programmable Gate Arrays Date Version Revision 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified “Pins not listed ...” statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18.  Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. 09/00 2.3  Corrected Units column in table under IOB Input Switching Characteristics.  Added values to table under CLB SelectRAM Switching Characteristics.  Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in 10/00 2.4 Table 18.  Corrected BG256 Pin Function Diagram.  Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. 04/01 2.5  Updated SelectMAP Write Timing Characteristics values in Table 9.  Converted file to modularized format. See the Virtex Data Sheet section.  Made minor edits to text under Configuration. 07/19/01 2.6  Made minor edit to Figure 16 and Figure 18. 07/19/02 2.7  Added clarifications in the Configuration, Boundary-Scan Mode, and Block 09/10/02 2.8 SelectRAM sections. Revised Figure 17.  Added clarification in the Boundary Scan section. 12/09/02 2.8.1  Corrected number of buffered Hex lines listed in General Purpose Routing section. Virtex Data Sheet The Virtex Data Sheet contains the following modules:  DS003-1, Virtex 2.5V FPGAs:  DS003-3, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)  DS003-2, Virtex 2.5V FPGAs:  DS003-4, Virtex 2.5V FPGAs: Functional Description (Module 2) Pinout Tables (Module 4) Module 2 of 4 www.xilinx.com DS003-2 (v2.8.1) December 9, 2002 20 1-800-255-7778 Product Specification 0 R Virtex™ 2.5 V Field Programmable Gate Arrays 00 DS003-3 (v3.2) September 10, 2002 Production Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a Table 1 correlates the current status of each Virtex device per-speed-grade basis and can be designated as Advance, with a corresponding speed file designation. Preliminary, or Production. Each designation is defined as Table 1: Virtex Device Speed Grade Designations follows: Speed Grade Designations Advance: These speed files are based on simulations only and are typically available soon after device design specifi- Device Advance Preliminary Production cations are frozen. Although speed grades with this desig- nation are considered relatively stable and conservative, XCV50 –6, –5, –4 some under-reporting might still occur. XCV100 –6, –5, –4 Preliminary: These speed files are based on complete ES XCV150 –6, –5, –4 (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a XCV200 –6, –5, –4 better indication of the expected performance of production XCV300 –6, –5, –4 silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. XCV400 –6, –5, –4 Production: These speed files are released once enough XCV600 –6, –5, –4 production silicon of a particular device family member has XCV800 –6, –5, –4 been characterized to provide full correlation between speed files and devices over numerous production lots. XCV1000 –6, –5, –4 There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typ- All specifications are subject to change without notice. ically, the slowest speed grades transition to Production before faster speed grades. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parame- ters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. © 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 1 R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex DC Characteristics Absolute Maximum Ratings (1) Symbol Description Units (2) V Supply voltage relative to GND –0.5 to 3.0 V CCINT (2) V Supply voltage relative to GND –0.5 to 4.0 V CCO V Input Reference Voltage –0.5 to 3.6 V REF (3) Input voltage relative to GND Using V –0.5 to 3.6 V REF V IN Internal threshold –0.5 to 5.5 V V Voltage applied to 3-state output –0.5 to 5.5 V TS V Longest Supply Voltage Rise Time from 1V-2.375V 50 ms CC T Storage temperature (ambient) –65 to +150 °C STG (4) T Junction temperature Plastic Packages +125 °C J Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability. 2. Power supplies can turn on in any order. 3. For protracted periods (e.g., longer than a day), V should not exceed V by more than 3.6 V. IN CCO 4. For soldering guidelines and thermal considerations, see the "Device Packaging" infomation on www.xilinx.com. Recommended Operating Conditions Symbol Description Min Max Units Input Supply voltage relative to GND, T = 0 °C to +85°CCommercial 2.5 – 5% 2.5 + 5% V J (1) V CCINT Input Supply voltage relative to GND, T = –40°C to +100°C Industrial 2.5 – 5% 2.5 + 5% V J Supply voltage relative to GND, T = 0 °C to +85°CCommercial 1.4 3.6 V J (4) V CCO Supply voltage relative to GND, T = –40°C to +100°C Industrial 1.4 3.6 V J T Input signal transition time 250 ns IN Notes: 1. Correct operation is guaranteed with a minimum V of 2.375 V (Nominal V –5%). Below the minimum value, all delay CCINT CCINT parameters increase by 3% for each 50-mV reduction in V below the specified range. CCINT 2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report. 3. Input and output measurement threshold is ~50% of V . CC 4. Min and Max values for V are I/O Standard dependant. CCO Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 2 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays DC Characteristics Over Recommended Operating Conditions Symbol Description Device Min Max Units Data Retention V Voltage CCINT V All 2.0 V DRINT (below which configuration data can be lost) Data Retention V Voltage CCO V All 1.2 V DRIO (below which configuration data can be lost) (1,3) I Quiescent V supply current XCV50 50 mA CCINTQ CCINT XCV100 50 mA XCV150 50 mA XCV200 75 mA XCV300 75 mA XCV400 75 mA XCV600 100 mA XCV800 100 mA XCV1000 100 mA (1) I Quiescent V supply current XCV50 2 mA CCOQ CCO XCV100 2 mA XCV150 2 mA XCV200 2 mA XCV300 2 mA XCV400 2 mA XCV600 2 mA XCV800 2 mA XCV1000 2 mA I V current per V pin All 20 µA REF REF REF I Input or output leakage current All –10 +10 µA L BGA, PQ, HQ, packages C Input capacitance (sample tested) All 8 pF IN I Pad pull-up (when selected) @ V = 0 V, V = 3.3 V (sample RPU in CCO All Note (2) 0.25 mA tested) Note (2) I Pad pull-down (when selected) @ V = 3.6 V (sample tested) 0.15 mA RPD in Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 3. Multiply I limit by two for industrial grade. CCINTQ DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 3 R Virtex™ 2.5 V Field Programmable Gate Arrays Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal (1) power supply voltage of the device from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms). For more details on power supply requirements, see Application Note XAPP158 on www.xilinx.com. (2) (1,3) Product Description Current Requirement Virtex Family, Commercial Grade Minimum required current supply 500 mA Virtex Family, Industrial Grade Minimum required current supply 2 A Notes: 1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold of 1.0V and lasts for less than 3 ms. 2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. Larger currents can result if ramp rates are forced to be faster. DC Input and Output Levels Values for V and V are recommended input voltages. Values for I and I are guaranteed output currents over the IL IH OL OH recommended operating conditions at the V and V test points. Only selected standards are tested. These are chosen OL OH to ensure that all standards meet their specifications. The selected standards are tested at minimum V for each standard CCO with the respective V and V voltage levels shown. Other standards are sample tested. OL OH V V V V I I IL IH OL OH OL OH Input/Output Standard V, min V, max V, min V, max V, Max V, Min mA mA (1) LVTTL – 0.5 0.8 2.0 5.5 0.4 2.4 24 –24 LVCMOS2 – 0.5 .7 1.7 5.5 0.4 1.9 12 –12 Note 2 Note 2 PCI, 3.3 V – 0.5 44% V 60% V V + 0.5 10% V 90% V CCINT CCINT CCO CCO CCO Note 2 Note 2 PCI, 5.0 V – 0.5 0.8 2.0 5.5 0.55 2.4 GTL – 0.5 V – 0.05 V + 0.05 3.6 0.4 n/a 40 n/a REF REF GTL+ – 0.5 V – 0.1 V + 0.1 3.6 0.6 n/a 36 n/a REF REF (3) HSTL I – 0.5 V – 0.1 V + 0.1 3.6 0.4 V – 0.4 8 –8 REF REF CCO HSTL III – 0.5 V – 0.1 V + 0.1 3.6 0.4 V – 0.4 24 –8 REF REF CCO HSTL IV – 0.5 V – 0.1 V + 0.1 3.6 0.4 V – 0.4 48 –8 REF REF CCO SSTL3 I – 0.5 V – 0.2 V + 0.2 3.6 V – 0.6 V + 0.6 8 –8 REF REF REF REF SSTL3 II – 0.5 V – 0.2 V + 0.2 3.6 V – 0.8 V + 0.8 16 –16 REF REF REF REF SSTL2 I – 0.5 V – 0.2 V + 0.2 3.6 V – 0.61 V + 0.61 7.6 –7.6 REF REF REF REF SSTL2 II – 0.5 V – 0.2 V + 0.2 3.6 V – 0.80 V + 0.80 15.2 –15.2 REF REF REF REF CTT – 0.5 V – 0.2 V + 0.2 3.6 V – 0.4 V + 0.4 8 –8 REF REF REF REF Note 2 Note 2 AGP – 0.5 V – 0.2 V + 0.2 3.6 10% V 90% V REF REF CCO CCO Notes: 1. V and V for lower drive currents are sample tested. OL OH 2. Tested according to the relevant specifications. 3. DC input and output levels for HSTL18 (HSTL I/O standard with V of 1.8 V) are provided in an HSTL white paper on CCO www.xilinx.com. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 4 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Switching Characteristics All devices are 100% functionally tested. Internal timing in the Xilinx Development System) and back-annotated to parameters are derived from measuring internal test pat- the simulation net list. All timing parameters assume terns. Listed below are representative values. For more worst-case operating conditions (supply voltage and junc- specific, more precise, and worst-case guaranteed data, tion temperature). Values apply to all Virtex devices unless use the values reported by the static timing analyzer (TRCE otherwise noted. IOB Input Switching Characteristics Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in , page 6. Speed Grade Description Device Symbol Min -6 -5 -4 Units Propagation Delays Pad to I output, no delay All T 0.39 0.8 0.9 1.0 ns, max IOPI Pad to I output, with delay XCV50 T 0.8 1.5 1.7 1.9 ns, max IOPID XCV100 0.8 1.5 1.7 1.9 ns, max XCV150 0.8 1.5 1.7 1.9 ns, max XCV200 0.8 1.5 1.7 1.9 ns, max XCV300 0.8 1.5 1.7 1.9 ns, max XCV400 0.9 1.8 2.0 2.3 ns, max XCV600 0.9 1.8 2.0 2.3 ns, max XCV800 1.1 2.1 2.4 2.7 ns, max XCV1000 1.1 2.1 2.4 2.7 ns, max Pad to output IQ via transparent All T 0.8 1.6 1.8 2.0 ns, max IOPLI latch, no delay Pad to output IQ via transparent XCV50 T 1.9 3.7 4.2 4.8 ns, max IOPLID latch, with delay XCV100 1.9 3.7 4.2 4.8 ns, max XCV150 2.0 3.9 4.3 4.9 ns, max XCV200 2.0 4.0 4.4 5.1 ns, max XCV300 2.0 4.0 4.4 5.1 ns, max XCV400 2.1 4.1 4.6 5.3 ns, max XCV600 2.1 4.2 4.7 5.4 ns, max XCV800 2.2 4.4 4.9 5.6 ns, max XCV1000 2.3 4.5 5.1 5.8 ns, max Sequential Delays Clock CLK All Minimum Pulse Width, High T 0.8 1.5 1.7 2.0 ns, min CH Minimum Pulse Width, Low T 0.8 1.5 1.7 2.0 ns, min CL Clock CLK to output IQ T 0.2 0.7 0.7 0.8 ns, max IOCKIQ DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 5 R Virtex™ 2.5 V Field Programmable Gate Arrays Speed Grade Description Device Symbol Min -6 -5 -4 Units Setup and Hold Times with respect to Clock CLK at IOB input Setup Time / Hold Time (1) register Pad, no delay All T /T 0.8 / 0 1.6 / 0 1.8 / 0 2.0 / 0 ns, min IOPICK IOICKP Pad, with delay XCV50 T /T 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min IOPICKD IOICKPD XCV100 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min XCV150 1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min XCV200 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min XCV300 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min XCV400 2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min XCV600 2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min XCV800 2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min XCV1000 2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min ICE input All T /T 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max IOICECK IOCKICE Set/Reset Delays SR input (IFF, synchronous) All T 0.49 1.0 1.1 1.3 ns, max IOSRCKI SR input to IQ (asynchronous) All T 0.70 1.4 1.6 1.8 ns, max IOSRIQ GSR to output IQ All T 4.9 9.7 10.9 12.5 ns, max GSRQ Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 6 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Speed Grade (1) Description Symbol Standard Min -6-5-4 Units Data Input Delay Adjustments Standard-specific data input delay T LVTTL 0 0 0 0 ns ILVTTL adjustments T LVCMOS2 –0.02 –0.04 –0.04 –0.05 ns ILVCMOS2 T PCI, 33 MHz, 3.3 V –0.05 –0.11 –0.12 –0.14 ns IPCI33_3 T PCI, 33 MHz, 5.0 V 0.13 0.25 0.28 0.33 ns IPCI33_5 T PCI, 66 MHz, 3.3 V –0.05 –0.11 –0.12 –0.14 ns IPCI66_3 T GTL 0.100.200.230.26 ns IGTL T GTL+ 0.06 0.11 0.12 0.14 ns IGTLP T HSTL 0.02 0.03 0.03 0.04 ns IHSTL T SSTL2 –0.04 –0.08 –0.09 –0.10 ns ISSTL2 T SSTL3 –0.02 –0.04 –0.05 –0.06 ns ISSTL3 T CTT 0.010.020.020.02 ns ICTT T AGP –0.03 –0.06 –0.07 –0.08 ns IAGP Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3. IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9. Speed Grade Description Symbol Min -6-5-4 Units Propagation Delays O input to Pad T 1.2 2.9 3.2 3.5 ns, max IOOP O input to Pad via transparent latch T 1.4 3.4 3.7 4.0 ns, max IOOLP 3-State Delays (1) T input to Pad high-impedance T 1.0 2.0 2.2 2.4 ns, max IOTHZ T input to valid data on Pad T 1.4 3.1 3.3 3.7 ns, max IOTON T input to Pad high-impedance via T 1.2 2.4 2.6 3.0 ns, max IOTLPHZ (1) transparent latch T input to valid data on Pad via T 1.6 3.5 3.8 4.2 ns, max IOTLPON transparent latch (1) GTS to Pad high impedance T 2.5 4.9 5.5 6.3 ns, max GTS Sequential Delays Clock CLK Minimum Pulse Width, High T 0.8 1.5 1.7 2.0 ns, min CH Minimum Pulse Width, Low T 0.8 1.5 1.7 2.0 ns, min CL DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 7 R Virtex™ 2.5 V Field Programmable Gate Arrays Speed Grade Description Symbol Min -6-5-4 Units Clock CLK to Pad delay with OBUFT T 1.0 2.9 3.2 3.5 ns, max IOCKP enabled (non-3-state) Clock CLK to Pad high-impedance T 1.1 2.3 2.5 2.9 ns, max (1) IOCKHZ (synchronous) Clock CLK to valid data on Pad delay, plus T 1.5 3.4 3.7 4.1 ns, max IOCKON enable delay for OBUFT (2) Setup and Hold Times before/after Clock CLK Setup Time / Hold Time O input T /T 0.51 / 0 1.1 / 0 1.2 / 0 1.3 / 0 ns, min IOOCK IOCKO OCE input T /T 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min IOOCECK IOCKOCE SR input (OFF) T /T 0.52 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min IOSRCKO IOCKOSR 3-State Setup Times, T input T /T 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min IOTCK IOCKT 3-State Setup Times, TCE input T /T 0.41 / 0 0.9 / 0 0.9 / 0 1.1 / 0 ns, min IOTCECK IOCKTCE 3-State Setup Times, SR input (TFF) T /T 0.49 / 0 1.0 / 0 1.1 / 0 1.3 / 0 ns, min IOSRCKT IOCKTSR Set/Reset Delays SR input to Pad (asynchronous) T 1.6 3.8 4.1 4.6 ns, max IOSRP SR input to Pad high-impedance T 1.6 3.1 3.4 3.9 ns, max IOSRHZ (1) (asynchronous) SR input to valid data on Pad T 2.0 4.2 4.6 5.1 ns, max IOSRON (asynchronous) GSR to Pad T 4.9 9.7 10.9 12.5 ns, max IOGSRQ Notes: 1. 3-state turn-off delays should not be adjusted. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 8 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Speed Grade Unit (1) Description Symbol Standard Min -6-5-4 s Output Delay Adjustments Standard-specific adjustments for T LVTTL, Slow, 2 mA 4.2 14.7 15.8 17.0 ns OLVTTL_S2 output delays terminating at pads T 4 mA 2.5 7.5 8.0 8.6 ns OLVTTL_S4 (based on standard capacitive load, T 6 mA 1.8 4.8 5.1 5.6 ns Csl) OLVTTL_S6 T 8 mA 1.2 3.0 3.3 3.5 ns OLVTTL_S8 T 12 mA 1.0 1.9 2.1 2.2 ns OLVTTL_S12 T 16 mA 0.9 1.7 1.9 2.0 ns OLVTTL_S16 T 24 mA 0.8 1.3 1.4 1.6 ns OLVTTL_S24 T LVTTL, Fast, 2mA 1.9 13.1 14.0 15.1 ns OLVTTL_F2 T 4 mA 0.7 5.3 5.7 6.1 ns OLVTTL_F4 T 6 mA 0.2 3.1 3.3 3.6 ns OLVTTL_F6 T 8 mA 0.1 1.0 1.1 1.2 ns OLVTTL_F8 T 12 mA 0 0 0 0 ns OLVTTL_F12 T 16 mA –0.10 –0.05 –0.05 –0.05 ns OLVTTL_F16 T 24 mA –0.10 –0.20 –0.21 –0.23 ns OLVTTL_F24 T LVCMOS2 0.10 0.10 0.11 0.12 ns OLVCMOS2 T PCI, 33 MHz, 3.3 V 0.50 2.3 2.5 2.7 ns OPCI33_3 T PCI, 33 MHz, 5.0 V 0.40 2.8 3.0 3.3 ns OPCI33_5 T PCI, 66 MHz, 3.3 V 0.10 –0.40 –0.42 –0.46 ns OPCI66_3 T GTL 0.6 0.50 0.54 0.6 ns OGTL T GTL+ 0.7 0.8 0.9 1.0 ns OGTLP T HSTL I 0.10 –0.50 –0.53 –0.5 ns OHSTL_I T HSTL III –0.10 –0.9 –0.9 –1.0 ns OHSTL_III T HSTL IV –0.20 –1.0 –1.0 –1.1 ns OHSTL_IV T SSTL2 I –0.10 –0.50 –0.53 –0.5 ns OSSTL2_I T SSTL2 II –0.20 –0.9 –0.9 –1.0 ns OSSLT2_II T SSTL3 I –0.20 –0.50 –0.53 –0.5 ns OSSTL3_I T SSTL3 II –0.30 –1.0 –1.0 –1.1 ns OSSTL3_II T CTT 0 –0.6 –0.6 –0.6 ns OCTT T AGP 0 –0.9 –0.9 –1.0 ns OAGP Notes: 1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see Table 2 and Table 3. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 9 R Virtex™ 2.5 V Field Programmable Gate Arrays For other capacitive loads, use the formulas below to calcu- Calculation of T as a Function of ioop late the corresponding T . Capacitance ioop T = T + T + (C – C ) * fl T is the propagation delay from the O Input of the IOB to ioop ioop opadjust load sl ioop the pad. The values for T were based on the standard ioop Where: capacitive load (Csl) for each I/O standard as listed in T is reported above in the Output Delay Table 2. opadjust Adjustment section. C is the capacitive load for the design. Table 2: Constants for Calculating T load ioop Csl fl Table 3: Delay Measurement Methodology Standard (pF) (ns/pF) LVTTL Fast Slew Rate, 2mA drive 35 0.41 Meas. V REF (1) (1) (2) Standard V V Point Typ L H LVTTL Fast Slew Rate, 4mA drive 35 0.20 LVTTL 0 3 1.4 - LVTTL Fast Slew Rate, 6mA drive 35 0.13 LVTTL Fast Slew Rate, 8mA drive 35 0.079 LVCMOS2 0 2.5 1.125 - LVTTL Fast Slew Rate, 12mA drive 35 0.044 PCI33_5 Per PCI Spec - LVTTL Fast Slew Rate, 16mA drive 35 0.043 PCI33_3 Per PCI Spec - LVTTL Fast Slew Rate, 24mA drive 35 0.033 PCI66_3 Per PCI Spec - LVTTL Slow Slew Rate, 2mA drive 35 0.41 GTL V –0.2 V +0.2 V 0.80 REF REF REF LVTTL Slow Slew Rate, 4mA drive 35 0.20 GTL+ V –0.2 V +0.2 V 1.0 REF REF REF LVTTL Slow Slew Rate, 6mA drive 35 0.100 HSTL Class I V –0.5 V +0.5 V 0.75 LVTTL Slow Slew Rate, 8mA drive 35 0.086 REF REF REF HSTL Class III V –0.5 V +0.5 V 0.90 LVTTL Slow Slew Rate, 12mA drive 35 0.058 REF REF REF LVTTL Slow Slew Rate, 16mA drive 35 0.050 HSTL Class IV V –0.5 V +0.5 V 0.90 REF REF REF LVTTL Slow Slew Rate, 24mA drive 35 0.048 SSTL3 I & II V –1.0 V +1.0 V 1.5 REF REF REF LVCMOS2 35 0.041 SSTL2 I & II V –0.75 V +0.75 V 1.25 REF REF REF PCI 33MHz 5V 50 0.050 CTT V –0.2 V +0.2 V 1.5 REF REF REF PCI 33MHZ 3.3 V 10 0.050 AGP V – V + V Per REF REF REF PCI 66 MHz 3.3 V 10 0.033 AGP (0.2xV ) (0.2xV ) CCO CCO GTL 0 0.014 Spec GTL+ 0 0.017 Notes: 1. Input waveform switches between V and V . HSTL Class I 20 0.022 L H 2. Measurements are made at VREF (Typ), Maximum, and HSTL Class III 20 0.016 Minimum. Worst-case values are reported. 3. I/O parameter measurements are made with the capacitance HSTL Class IV 20 0.014 values shown in Table 2. See Application Note XAPP133 on SSTL2 Class I 30 0.028 www.xilinx.com for appropriate terminations. 4. I/O standard measurements are reflected in the IBIS model SSTL2 Class II 30 0.016 information except where the IBIS format precludes it. SSTL3 Class I 30 0.029 SSTL3 Class II 30 0.016 CTT 20 0.035 AGP 10 0.037 Notes: 1. I/O parameter measurements are made with the capacitance values shown above. See Application Note XAPP133 on www.xilinx.com for appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 10 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Clock Distribution Guidelines Speed Grade Description Device Symbol -6 -5 -4 Units (1) Global Clock Skew Global Clock Skew between IOB Flip-flops XCV50 T 0.10 0.12 0.14 ns, max GSKEWIOB XCV100 0.12 0.13 0.15 ns, max XCV150 0.12 0.13 0.15 ns, max XCV200 0.13 0.14 0.16 ns, max XCV300 0.14 0.16 0.18 ns, max XCV400 0.13 0.13 0.14 ns, max XCV600 0.14 0.15 0.17 ns, max XCV800 0.16 0.17 0.20 ns, max XCV1000 0.20 0.23 0.25 ns, max Notes: 1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise values for a particular design are provided by the timing analyzer. Clock Distribution Switching Characteristics Speed Grade Description Symbol Min -6 -5 -4 Units GCLK IOB and Buffer Global Clock PAD to output. T 0.33 0.7 0.8 0.9 ns, max GPIO Global Clock Buffer I input to O output T 0.34 0.7 0.8 0.9 ns, max GIO DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 11 R Virtex™ 2.5 V Field Programmable Gate Arrays I/O Standard Global Clock Input Adjustments Speed Grade (1) Description Symbol Standard Min -6 -5 -4 Units Data Input Delay Adjustments Standard-specific global clock input T LVTTL 0 0 0 0 ns, GPLVTTL delay adjustments max T LVCMOS2 –0.02 –0.04 –0.04 –0.05 ns, GPLVCMOS max 2 T PCI, 33 MHz, 3.3 –0.05 –0.11 –0.12 –0.14 ns, GPPCI33_3 V max T PCI, 33 MHz, 5.0 0.13 0.25 0.28 0.33 ns, GPPCI33_5 V max T PCI, 66 MHz, 3.3 –0.05 –0.11 –0.12 –0.14 ns, GPPCI66_3 V max T GTL 0.7 0.8 0.9 0.9 ns, GPGTL max T GTL+ 0.7 0.8 0.8 0.8 ns, GPGTLP max T HSTL 0.7 0.7 0.7 0.7 ns, GPHSTL max T SSTL2 0.6 0.52 0.51 0.50 ns, GPSSTL2 max T SSTL3 0.6 0.6 0.55 0.54 ns, GPSSTL3 max T CTT 0.7 0.7 0.7 0.7 ns, GPCTT max T AGP 0.6 0.54 0.53 0.52 ns, GPAGP max Notes: 1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 12 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade Description Symbol Min -6-5-4 Units Combinatorial Delays 4-input function: F/G inputs to X/Y outputs T 0.29 0.6 0.7 0.8 ns, max ILO 5-input function: F/G inputs to F5 output T 0.32 0.7 0.8 0.9 ns, max IF5 5-input function: F/G inputs to X output T 0.36 0.8 0.8 1.0 ns, max IF5X 6-input function: F/G inputs to Y output via F6 MUX T 0.44 0.9 1.0 1.2 ns, max IF6Y 6-input function: F5IN input to Y output T 0.17 0.32 0.36 0.42 ns, max F5INY Incremental delay routing through transparent latch T 0.31 0.7 0.7 0.8 ns, max IFNCTL to XQ/YQ outputs BY input to YB output T 0.27 0.53 0.6 0.7 ns, max BYYB Sequential Delays FF Clock CLK to XQ/YQ outputs T 0.54 1.1 1.2 1.4 ns, max CKO Latch Clock CLK to XQ/YQ outputs T 0.6 1.2 1.4 1.6 ns, max CKLO (1) Setup and Hold Times before/after Clock CLK Setup Time / Hold Time 4-input function: F/G Inputs T /T 0.6 / 0 1.2 / 0 1.4 / 0 1.5 / 0 ns, min ICK CKI 5-input function: F/G inputs T /T 0.7 / 0 1.3 / 0 1.5 / 0 1.7 / 0 ns, min IF5CK CKIF5 6-input function: F5IN input T /T 0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min F5INCK CKF5IN 6-input function: F/G inputs via F6 MUX T /T 0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min IF6CK CKIF6 BX/BY inputs T /T 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min DICK CKDI CE input T /T 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min CECK CKCE SR/BY inputs (synchronous) T T 0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min RCK CKR Clock CLK Minimum Pulse Width, High T 0.8 1.5 1.7 2.0 ns, min CH Minimum Pulse Width, Low T 0.8 1.5 1.7 2.0 ns, min CL Set/Reset Minimum Pulse Width, SR/BY inputs T 1.3 2.5 2.8 3.3 ns, min RPW Delay from SR/BY inputs to XQ/YQ outputs T 0.54 1.1 1.3 1.4 ns, max RQ (asynchronous) Delay from GSR to XQ/YQ outputs T 4.9 9.7 10.9 12.5 ns, max IOGSRQ Toggle Frequency (MHz) (for export control) F (MHz) 625 333 294 250 MHz TOG Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 13 R Virtex™ 2.5 V Field Programmable Gate Arrays CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade Description Symbol Min -6 -5 -4 Units Combinatorial Delays F operand inputs to X via XOR T 0.37 0.8 0.9 1.0 ns, max OPX F operand input to XB output T 0.54 1.1 1.3 1.4 ns, max OPXB F operand input to Y via XOR T 0.8 1.5 1.7 2.0 ns, max OPY F operand input to YB output T 0.8 1.5 1.7 2.0 ns, max OPYB F operand input to COUT output T 0.6 1.2 1.3 1.5 ns, max OPCYF G operand inputs to Y via XOR T 0.46 1.0 1.1 1.2 ns, max OPGY G operand input to YB output T 0.8 1.6 1.8 2.1 ns, max OPGYB G operand input to COUT output T 0.7 1.3 1.4 1.6 ns, max OPCYG BX initialization input to COUT T 0.41 0.9 1.0 1.1 ns, max BXCY CIN input to X output via XOR T 0.21 0.41 0.46 0.53 ns, max CINX CIN input to XB T 0.02 0.04 0.05 0.06 ns, max CINXB CIN input to Y via XOR T 0.23 0.46 0.52 0.6 ns, max CINY CIN input to YB T 0.23 0.45 0.51 0.6 ns, max CINYB CIN input to COUT output T 0.05 0.09 0.10 0.11 ns, max BYP Multiplier Operation F1/2 operand inputs to XB output via AND T 0.18 0.36 0.40 0.46 ns, max FANDXB F1/2 operand inputs to YB output via AND T 0.40 0.8 0.9 1.1 ns, max FANDYB F1/2 operand inputs to COUT output via AND T 0.22 0.43 0.48 0.6 ns, max FANDCY G1/2 operand inputs to YB output via AND T 0.25 0.50 0.6 0.7 ns, max GANDYB G1/2 operand inputs to COUT output via AND T 0.07 0.13 0.15 0.17 ns, max GANDCY (1) Setup and Hold Times before/after Clock CLK Setup Time / Hold Time CIN input to FFX T /T 0.50 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min CCKX CKCX CIN input to FFY T /T 0.53 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min CCKY CKCY Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 14 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays CLB SelectRAM Switching Characteristics Speed Grade Description Symbol Min -6 -5 -4 Units Sequential Delays Clock CLK to X/Y outputs (WE active) 16 x 1 mode T 1.2 2.3 2.6 3.0 ns, max SHCKO16 Clock CLK to X/Y outputs (WE active) 32 x 1 mode T 1.2 2.7 3.1 3.5 ns, max SHCKO32 Shift-Register Mode Clock CLK to X/Y outputs T 1.2 3.7 4.1 4.7 ns, max REG (1) Setup and Hold Times before/after Clock CLK Setup Time / Hold Time F/G address inputs T /T 0.25 / 0 0.5 / 0 0.6 / 0 0.7 / 0 ns, min AS AH BX/BY data inputs (DIN) T /T 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min DS DH CE input (WE) T /T 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min WS WH Shift-Register Mode BX/BY data inputs (DIN) T 0.34 0.7 0.8 0.9 ns, min SHDICK CE input (WS) T 0.38 0.8 0.9 1.0 ns, min SHCECK Clock CLK Minimum Pulse Width, High T 1.2 2.4 2.7 3.1 ns, min WPH Minimum Pulse Width, Low T 1.2 2.4 2.7 3.1 ns, min WPL Minimum clock period to meet address write cycle T 2.4 4.8 5.4 6.2 ns, min WC time Shift-Register Mode Minimum Pulse Width, High T 1.2 2.4 2.7 3.1 ns, min SRPH Minimum Pulse Width, Low T 1.2 2.4 2.7 3.1 ns, min SRPL Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 15 R Virtex™ 2.5 V Field Programmable Gate Arrays Block RAM Switching Characteristics Speed Grade Description Symbol Min -6-5-4 Units Sequential Delays Clock CLK to DOUT output T 1.7 3.4 3.8 4.3 ns, max BCKO (1) Setup and Hold Times before/after Clock CLK Setup Time / Hold Time ADDR inputs T /T 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min BACK BCKA DIN inputs T /T 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min BDCK BCKD EN input T /T 1.3 / 0 2.6 / 0 3.0 / 0 3.4 / 0 ns, min BECK BCKE RST input T /T 1.3 / 0 2.5 / 0 2.7 / 0 3.2 / 0 ns, min BRCK BCKR WEN input T /T 1.2 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min BWCK BCKW Clock CLK Minimum Pulse Width, High T 0.8 1.5 1.7 2.0 ns, min BPWH Minimum Pulse Width, Low T 0.8 1.5 1.7 2.0 ns, min BPWL CLKA -> CLKB setup time for different ports T 3.0 3.5 4.0 ns, min BCCS Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TBUF Switching Characteristics Speed Grade Description Symbol Min -6 -5 -4 Units Combinatorial Delays IN input to OUT output T 0 000 ns, max IO TRI input to OUT output high-impedance T 0.05 0.09 0.10 0.11 ns, max OFF TRI input to valid data on OUT output T 0.05 0.09 0.10 0.11 ns, max ON JTAG Test Access Port Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units TMS and TDI Setup times before TCK T 4.0 4.0 4.0 ns, min TAPTCK TMS and TDI Hold times after TCK T 2.0 2.0 2.0 ns, min TCKTAP Output delay from clock TCK to output TDO T 11.0 11.0 11.0 ns, max TCKTDO Maximum TCK clock frequency F 33 33 33 MHz, max TCK Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 16 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL Speed Grade Description Symbol Device Min -6 -5 -4 Units LVTTL Global Clock Input to Output Delay using T XCV50 1.0 3.1 3.3 3.6 ns, max ICKOFDLL Output Flip-flop, 12 mA, Fast Slew Rate, with DLL. XCV100 1.0 3.1 3.3 3.6 ns, max For data output with different standards, adjust delays with the values shown in Output Delay XCV150 1.0 3.1 3.3 3.6 ns, max Adjustments. XCV200 1.0 3.1 3.3 3.6 ns, max XCV300 1.0 3.1 3.3 3.6 ns, max XCV400 1.0 3.1 3.3 3.6 ns, max XCV600 1.0 3.1 3.3 3.6 ns, max XCV800 1.0 3.1 3.3 3.6 ns, max XCV1000 1.0 3.1 3.3 3.6 ns, max Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see Table 2 and Table 3. 3. DLL output jitter is already included in the timing calculation. Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL Speed Grade Description Symbol Device Min -6 -5 -4 Units LVTTL Global Clock Input to Output Delay using T XCV50 1.5 4.6 5.1 5.7 ns, max ICKOF Output Flip-flop, 12 mA, Fast Slew Rate, without DLL. XCV100 1.5 4.6 5.1 5.7 ns, max For data output with different standards, adjust delays with the values shown in Input and Output XCV150 1.5 4.7 5.2 5.8 ns, max Delay Adjustments. XCV200 1.5 4.7 5.2 5.8 ns, max For I/O standards requiring V , such as GTL, REF GTL+, SSTL, HSTL, CTT, and AGO, an additional XCV300 1.5 4.7 5.2 5.9 ns, max 600 ps must be added. XCV400 1.5 4.8 5.3 6.0 ns, max XCV600 1.6 4.9 5.4 6.0 ns, max XCV800 1.6 4.9 5.5 6.2 ns, max XCV1000 1.7 5.0 5.6 6.3 ns, max Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see Table 2 and Table 3. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 17 R Virtex™ 2.5 V Field Programmable Gate Arrays Minimum Clock-to-Out for Virtex Devices With DLL Without DLL I/O Standard All Devices V50 V100 V150 V200 V300 V400 V600 V800 V1000 Units *LVTTL_S2 5.2 6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1 6.1 ns *LVTTL_S4 3.5 4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4 4.4 ns *LVTTL_S6 2.8 3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7 3.7 ns *LVTTL_S8 2.2 3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2 3.2 ns *LVTTL_S12 2.0 2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0 3.0 ns *LVTTL_S16 1.9 2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9 2.9 ns *LVTTL_S24 1.8 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7 2.8 ns *LVTTL_F2 2.9 3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9 3.9 ns *LVTTL_F4 1.7 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 ns *LVTTL_F6 1.2 2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1 2.2 ns *LVTTL_F8 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns *LVTTL_F12 1.0 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 ns *LVTTL_F16 0.9 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 1.9 ns *LVTTL_F24 0.9 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.9 ns LVCMOS2 1.1 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 ns PCI33_3 1.5 2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5 2.5 ns PCI33_5 1.4 2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3 2.4 ns PCI66_3 1.1 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 2.1 ns GTL 1.6 2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6 2.6 ns GTL+ 1.7 2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6 2.7 ns HSTL I 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns HSTL III 0.9 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 ns HSTL IV 0.8 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 1.8 ns SSTL2 I 0.9 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 ns SSTL2 II 0.8 1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 ns SSTL3 I 0.8 1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8 ns SSTL3 II 0.7 1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.7 ns CTT 1.0 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 2.0 ns AGP 1.0 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 2.0 ns *S = Slow Slew Rate, F = Fast Slew Rate Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive load is used. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 18 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted Global Clock Set-Up and Hold for LVTTL Standard, with DLL Speed Grade Description Symbol Device Min -6 -5 -4 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. No Delay T /T XCV50 0.40 / –0.4 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4 ns, PSDLL PHDLL min Global Clock and IFF, with DLL XCV100 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV150 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV200 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV300 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV400 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV600 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV800 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min XCV1000 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns, min IFF = Input Flip-Flop or Latch Notes: 1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. DLL output jitter is already included in the timing calculation. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 19 R Virtex™ 2.5 V Field Programmable Gate Arrays Global Clock Set-Up and Hold for LVTTL Standard, without DLL Speed Grade Description Symbol Device Min -6 -5 -4 Units (2) Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. Full Delay T /T XCV50 0.6 / 0 2.3 / 0 2.6 / 0 2.9 / 0 ns, PSFD PHFD min Global Clock and IFF, without DLL XCV100 0.6 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min XCV150 0.6 / 0 2.4 / 0 2.7 / 0 3.1 / 0 ns, min XCV200 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min XCV300 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min XCV400 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min XCV600 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min XCV800 0.7 / 0 2.7 / 0 3.1 / 0 3.5 / 0 ns, min XCV1000 0.7 / 0 2.8 / 0 3.1 / 0 3.6 / 0 ns, min IFF = Input Flip-Flop or Latch Notes: Notes: 1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 20 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -6 -5 -4 Description Symbol Min Max Min Max Min Max Units Input Clock Frequency (CLKDLLHF) FCLKINHF 60 200 60 180 60 180 MHz Input Clock Frequency (CLKDLL) FCLKINLF 25 100 25 90 25 90 MHz Input Clock Pulse Width (CLKDLLHF) T 2.0 - 2.4 - 2.4 - ns DLLPWHF Input Clock Pulse Width (CLKDLL) T 2.5 - 3.0 3.0 - ns DLLPWLF Notes: 1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C). DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. CLKDLLHF CLKDLL Description Symbol F Min Max Min Max Units CLKIN Input Clock Period Tolerance T - 1.0 - 1.0 ns IPTOL Input Clock Jitter Tolerance (Cycle to Cycle) T - ± 150 - ± 300 ps IJITCC Time Required for DLL to Acquire Lock T > 60 MHz - 20 - 20 µs LOCK 50 - 60 MHz - - - 25 µs 40 - 50 MHz - - - 50 µs 30 - 40 MHz - - - 90 µs 25 - 30 MHz - - - 120 µs (1) Output Jitter (cycle-to-cycle) for any DLL Clock Output T ± 60 ± 60 ps OJITCC (2) Phase Offset between CLKIN and CLKO T ± 100 ± 100 ps PHIO (3) Phase Offset between Clock Outputs on the DLL T ± 140 ± 140 ps PHOO Maximum Phase Difference between CLKIN and T ± 160 ± 160 ps PHIOM (4) CLKO Maximum Phase Difference between Clock Outputs on T ± 200 ± 200 ps PHOOM (5) the DLL Notes: 1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter. 2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding Output Jitter and input clock jitter. 3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding Output Jitter and input clock jitter. 4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter). 6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C). DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 21 + Jitter R Virtex™ 2.5 V Field Programmable Gate Arrays Period Tolerance: the allowed input clock period change in nanoseconds. + T T T _ CLKIN CLKIN IPTOL Output Jitter: the difference between an ideal Phase Offset and Maximum Phase Difference reference clock edge and the actual design. Ideal Period Actual Period +/- Jitter + Maximum Phase Difference + Phase Offset ds003_20c_110399 Figure 1: Frequency Tolerance and Clock Jitter Revision History Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added T parameter, changed T to T . IJITCC OJIT OPHASE 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for V in CS144 package on p.43. CCO Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 22 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Date Version Revision 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18.  Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. 09/00 2.3  Corrected Units column in table under IOB Input Switching Characteristics.  Added values to table under CLB SelectRAM Switching Characteristics.  Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in 10/00 2.4 Table 18.  Corrected BG256 Pin Function Diagram.  Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. 04/02/01 2.5  Converted file to modularized format. See the Virtex Data Sheet section.  Clarified TIOCKP and TIOCKON IOB Output Switching Characteristics descriptors. 04/19/01 2.6  Under Absolute Maximum Ratings, changed (T ) to 220 °C . 07/19/01 2.7 SOL  Removed T parameter and added footnote to Absolute Maximum Ratings table. 07/26/01 2.8 SOL  Updated the speed grade designations used in data sheets, and added Table 1, which 10/29/01 2.9 shows the current speed grade designation for each device.  Added footnote to DC Input and Output Levels table. 02/01/02 3.0  Removed mention of MIL-M-38510/605 specification. 07/19/02 3.1  Added link to xapp158 from the Power-On Power Supply Requirements section.  Added Clock CLK to IOB Input Switching Characteristics and IOB Output Switching 09/10/02 3.2 Characteristics. Virtex Data Sheet The Virtex Data Sheet contains the following modules:  DS003-1, Virtex 2.5V FPGAs:  DS003-3, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)  DS003-4, Virtex 2.5V FPGAs:  DS003-2, Virtex 2.5V FPGAs: Pinout Tables (Module 4) Functional Description (Module 2) DS003-3 (v3.2) September 10, 2002 www.xilinx.com Module 3 of 4 Production Product Specification 1-800-255-7778 23 R Virtex™ 2.5 V Field Programmable Gate Arrays Module 3 of 4 www.xilinx.com DS003-3 (v3.2) September 10, 2002 24 1-800-255-7778 Production Product Specification 0 R Virtex™ 2.5 V Field Programmable Gate Arrays 00 DS003-4 (v2.8) July 19, 2002 Production Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Name Pin Direction Description GCK0, GCK1, Yes Input Clock input pins that connect to Global Clock Buffers. These pins become GCK2, GCK3 user inputs when not needed for clocks. M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode. CCLK Yes Input or The configuration Clock I/O pin: it is an input for SelectMAP and Output slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level = Don’t Care. PROGRAM Yes Input Initiates a configuration sequence when asserted Low. DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain. INIT No Bidirectional When Low, indicates that the configuration memory is being cleared. The (Open-drain) pin becomes a user I/O after configuration. BUSY/ No Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the DOUT SelectMAP port is retained. In bit-serial modes, DOUT provides header information to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. D0/DIN, No Input or In SelectMAP mode, D0 - D7 are configuration data pins. These pins D1, D2, Output become user I/Os after configuration unless the SelectMAP port is D3, D4, retained. D5, D6, In bit-serial modes, DIN is the single data input. This pin becomes a user D7 I/O after configuration. WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. TDI, TDO, Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1. TMS, TCK DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN) V Yes Input Power-supply pins for the internal core logic. CCINT V Yes Input Power-supply pins for the output drivers (subject to banking rules) CCO V No Input Input threshold voltage pins. Become user I/Os when an external REF threshold voltage is not needed (subject to banking rules). GND Yes Input Ground © 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 1 R Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Pinout Information Pinout Tables See www.xilinx.com for updates or additional pinout information. For convenience, Table 2, Table 3 and Table 4 list the locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the device/package combination. See the Pinout Diagrams starting on page 17 for any pins not listed for a particular part/package combination. Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) Pin Name Device CS144 TQ144 PQ/HQ240 GCK0 All K7 90 92 GCK1 All M7 93 89 GCK2 All A7 19 210 GCK3 All A6 16 213 M0 All M1 110 60 M1 All L2 112 58 M2 All N2 108 62 CCLK All B13 38 179 PROGRAM All L12 72 122 DONE All M12 74 120 INIT All L13 71 123 BUSY/DOUT All C11 39 178 D0/DIN All C12 40 177 D1 All E10 45 167 D2 All E12 47 163 D3 All F11 51 156 D4 All H12 59 145 D5 All J13 63 138 D6 All J11 65 134 D7 All K10 70 124 WRITE All C10 32 185 CS All D10 33 184 TDI All A11 34 183 TDO All A12 36 181 TMS All B1 143 2 TCK All C3 2 239 V All A9, B6, C5, G3, 10, 15, 25, 57, 84, 94, 16, 32, 43, 77, 88, 104, CCINT G12, M5, M9, N6 99, 126 137, 148, 164, 198, 214, 225 Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 2 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name Device CS144 TQ144 PQ/HQ240 V All Banks 0 and 1: No I/O Banks in this No I/O Banks in this CCO A2, A13, D7 package: package: 1, 17, 37, 55, 73, 92, 15, 30, 44, 61, 76, 90, Banks 2 and 3: 109, 128 105, 121, 136, 150, 165, B12, G11, M13 180, 197, 212, 226, 240 Banks 4 and 5: N1, N7, N13 Banks 6 and 7: B2, G2, M2 V , Bank 0 XCV50 C4, D6 5, 13 218, 232 REF (V pins are listed XCV100/150 ... + B4 ... + 7 ... + 229 REF incrementally. Connect XCV200/300 N/A N/A ... + 236 all pins listed for both the required device XCV400 N/A N/A ... + 215 and all smaller devices XCV600 N/A N/A ... + 230 listed in the same package.) XCV800 N/A N/A ... + 222 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. V , Bank 1 XCV50 A10, B8 22, 30 191, 205 REF (V pins are listed XCV100/150 ... + D9 ... + 28 ... + 194 REF incrementally. Connect XCV200/300 N/A N/A ... + 187 all pins listed for both the required device XCV400 N/A N/A ... + 208 and all smaller devices XCV600 N/A N/A ... + 193 listed in the same package.) XCV800 N/A N/A ... + 201 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. V , Bank 2 XCV50 D11, F10 42, 50 157, 171 REF (V pins are listed XCV100/150 ... + D13 ... + 44 ... + 168 REF incrementally. Connect XCV200/300 N/A N/A ... + 175 all pins listed for both the required device XCV400 N/A N/A ... + 154 and all smaller devices XCV600 N/A N/A ... + 169 listed in the same package.) XCV800 N/A N/A ... + 161 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 3 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name Device CS144 TQ144 PQ/HQ240 V , Bank 3 XCV50 H11, K12 60, 68 130, 144 REF (V pins are listed XCV100/150 ... + J10 ... + 66 ... + 133 REF incrementally. Connect XCV200/300 N/A N/A ... + 126 all pins listed for both the required device XCV400 N/A N/A ... + 147 and all smaller devices XCV600 N/A N/A ... + 132 listed in the same package.) XCV800 N/A N/A ... + 140 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. V , Bank 4 XCV50 L8, L10 79, 87 97, 111 REF (V pins are listed XCV100/150 ... + N10 ... + 81 ... + 108 REF incrementally. Connect XCV200/300 N/A N/A ... + 115 all pins listed for both the required device XCV400 N/A N/A ... + 94 and all smaller devices XCV600 N/A N/A ... + 109 listed in the same package.) XCV800 N/A N/A ... + 101 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. V , Bank 5 XCV50 L4, L6 96, 104 70, 84 REF (V pins are listed XCV100/150 ... + N4 ... + 102 ... + 73 REF incrementally. Connect XCV200/300 N/A N/A ... + 66 all pins listed for both the required device XCV400 N/A N/A ... + 87 and all smaller devices XCV600 N/A N/A ... + 72 listed in the same package.) XCV800 N/A N/A ... + 80 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 4 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name Device CS144 TQ144 PQ/HQ240 V , Bank 6 XCV50 H2, K1 116, 123 36, 50 REF (V pins are listed XCV100/150 ... + J3 ... + 118 ... + 47 REF incrementally. Connect XCV200/300 N/A N/A ... + 54 all pins listed for both the required device XCV400 N/A N/A ... + 33 and all smaller devices XCV600 N/A N/A ... + 48 listed in the same package.) XCV800 N/A N/A ... + 40 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. V , Bank 7 XCV50 D4, E1 133, 140 9, 23 REF (V pins are listed XCV100/150 ... + D2 ... + 138 ... + 12 REF incrementally. Connect XCV200/300 N/A N/A ... + 5 all pins listed for both the required device XCV400 N/A N/A ... + 26 and all smaller devices XCV600 N/A N/A ... + 11 listed in the same package.) XCV800 N/A N/A ... + 19 Within each bank, if input reference voltage is not required, all V pins are general REF I/O. GND All A1, B9, B11, C7, 9, 18, 26, 35, 46, 54, 64, 1, 8, 14, 22, 29, 37, 45, 51, D5, E4, E11, F1, 75, 83, 91, 100, 111, 120, 59, 69, 75, 83, 91, 98, 106, G10, J1, J12, L3, 129, 136, 144, 112, 119, 129, 135, 143, L5, L7, L9, N12 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233 DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 5 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) Pin Name Device BG256 BG352 BG432 BG560 GCK0 All Y11 AE13 AL16 AL17 GCK1 All Y10 AF14 AK16 AJ17 GCK2 All A10 B14 A16 D17 GCK3 All B10 D14 D17 A17 M0 All Y1 AD24 AH28 AJ29 M1 All U3 AB23 AH29 AK30 M2 All W2 AC23 AJ28 AN32 CCLK All B19 C3 D4 C4 PROGRAM All Y20 AC4 AH3 AM1 DONE All W19 AD3 AH4 AJ5 INIT All U18 AD2 AJ2 AH5 BUSY/DOUT All D18 E4 D3 D4 D0/DIN All C19 D3 C2 E4 D1 All E20 G1 K4 K3 D2 All G19 J3 K2 L4 D3 All J19 M3 P4 P3 D4 All M19 R3 V4 W4 D5 All P19 U4 AB1 AB5 D6 All T20 V3 AB3 AC4 D7 All V19 AC3 AG4 AJ4 WRITE All A19 D5 B4 D6 CS All B18 C4 D5 A2 TDI All C17 B3 B3 D5 TDO All A20 D4 C4 E6 TMS All D3 D23 D29 B33 TCK All A1 C24 D28 E29 DXN All W3 AD23 AH27 AK29 DXP All V4 AE24 AK29 AJ28 Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 6 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 V XCV50/100 C10, D6, N/A N/A N/A CCINT D15, F4, Notes: F17, L3,  Superset includes all pins, L18, R4, including the ones in bold R17, U6, type. Subset excludes pins in U15, V10 bold type.  In BG352, for XCV300 all the XCV150/200/300 Same as A20, C14, A10, A17, B23, N/A V pins in the superset CCINT above D10, J24, C14, C19, K3, must be connected. For K4, P2, P25, K29, N2, N29, XCV150/200, V pins in CCINT V24, W2, T1, T29, W2, the subset must be AC10, AE14, W31, AB2, connected, and pins in bold AE19, AB30, AJ10, type can be left unconnected AJ16, AK13, (these unconnected pins B16, D12, AK19, AK22, cannot be used as user I/O.) L1, L25,  In BG432, for R23, T1, B26, C7, F1, XCV400/600/800 all V CCINT AF11, AF16 F30, AE29, AF1, pins in the superset must be AH8, AH24 connected. For XCV300, XCV400/600/800/1000 N/A N/A Same as above A21, B14, B18, V pins in the subset CCINT B28, C24, E9, must be connected, and pins E12, F2, H30, in bold type can be left J1, K32, N1, unconnected (these unconnected pins cannot be N33, U5, U30, used as user I/O.) Y2, Y31, AD2,  In BG560, for XCV800/1000 AD32, AG3, all V pins in the AG31, AK8, CCINT superset must be connected. AK11, AK17, For XCV400/600, V CCINT AK20, AL14, pins in the subset must be AL27, AN25, connected, and pins in bold B12, C22, M3, type can be left unconnected N29, AB2, (these unconnected pins AB32, AJ13, cannot be used as user I/O.) AL22 V , Bank 0 All D7, D8 A17, B25, A21, C29, D21 A22, A26, A30, CCO D19 B19, B32 V , Bank 1 All D13, D14 A10, D7, A1, A11, D11 A10, A16, B13, CCO D13 C3, E5 V , Bank 2 All G17, H17 B2, H4, K1 C3, L1, L4 B2, D1, H1, M1, CCO R2 V , Bank 3 All N17, P17 P4, U1, Y4 AA1, AA4, AJ3 V1, AA2, AD1, CCO AK1, AL2 V , Bank 4 All U13, U14 AC8, AE2, AH11, AL1, AM2, AM15, CCO AF10 AL11 AN4, AN8, AN12 V , Bank 5 All U7, U8 AC14, AC20, AH21, AJ29, AL31, AM21, CCO AF17 AL21 AN18, AN24, AN30 V , Bank 6 All N4, P4 U26, W23, AA28, AA31, W32, AB33, CCO AE25 AL31 AF33, AK33, AM32 DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 7 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 V , Bank 7 All G4, H4 G23, K26, A31, L28, L31 C32, D33, K33, CCO N23 N32, T33 V , Bank 0 XCV50 A8, B4 N/A N/A N/A REF (VREF pins are listed XCV100/150 ... + A4 A16,C19, N/A N/A incrementally. Connect all C21 pins listed for both the XCV200/300 ... + A2 ... + D21 B19, D22, D24, N/A required device and all D26 smaller devices listed in the XCV400 N/A N/A ... + C18 A19, D20, same package.) D26, E23, E27 Within each bank, if input reference voltage is not XCV600 N/A N/A ... + C24 ... + E24 required, all V pins are REF XCV800 N/A N/A ... + B21 ... + E21 general I/O. XCV1000 N/A N/A N/A ... + D29 V , Bank 1 XCV50 A17, B12 N/A N/A N/A REF (VREF pins are listed XCV100/150 ... + B15 B6, C9, N/A N/A incrementally. Connect all C12 pins listed for both the XCV200/300 ... + B17 ... + D6 A13, B7, N/A required device and all smaller devices listed in the C6, C10 same package.) XCV400 N/A N/A ... + B15 A6, D7, Within each bank, if input D11, D16, E15 reference voltage is not required, all V pins are XCV600 N/A N/A ... + D10 ... + D10 REF general I/O. XCV800 N/A N/A ... + B12 ... + D13 XCV1000 N/A N/A N/A ... + E7 V , Bank 2 XCV50 C20, J18 N/A N/A N/A REF (V pins are listed XCV100/150 ... + F19 E2, H2, N/A N/A REF incrementally. Connect all M4 pins listed for both the XCV200/300 ... + G18 ... + D2 E2, G3, N/A required device and all smaller devices listed in the J2, N1 same package.) XCV400 N/A N/A ... + R3 G5, H4, Within each bank, if input L5, P4, R1 reference voltage is not required, all V pins are XCV600 N/A N/A ... + H1 ... + K5 REF general I/O. XCV800 N/A N/A ... + M3 ... + N5 XCV1000 N/A N/A N/A ... + B3 Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 8 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 V , Bank 3 XCV50 M18, V20 N/A N/A N/A REF (V pins are listed XCV100/150 ... + R19 R4, V4, Y3 N/A N/A REF incrementally. Connect all XCV200/300 ... + P18 ... + AC2 V2, AB4, AD4, N/A pins listed for both the AF3 required device and all smaller devices listed in the XCV400 N/A N/A ... + U2 V4, W5, same package.) AD3, AE5, AK2 Within each bank, if input XCV600 N/A N/A ... + AC3 ... + AF1 reference voltage is not XCV800 N/A N/A ... + Y3 ... + AA4 required, all V pins are REF general I/O. XCV1000 N/A N/A N/A ... + AH4 V , Bank 4 XCV50 V12, Y18 N/A N/A N/A REF (V pins are listed XCV100/150 ... + W15 AC12, AE5, N/A N/A REF incrementally. Connect all AE8, pins listed for both the XCV200/300 ... + V14 ... + AE4 AJ7, AL4, AL8, N/A required device and all AL13 smaller devices listed in the same package.) XCV400 N/A N/A ... + AK15 AL7, AL10, AL16, AM4, Within each bank, if input AM14 reference voltage is not required, all V pins are XCV600 N/A N/A ... + AK8 ... + AL9 REF general I/O. XCV800 N/A N/A ... + AJ12 ... + AK13 XCV1000 N/A N/A N/A ... + AN3 V , Bank 5 XCV50 V9, Y3 N/A N/A N/A REF (V pins are listed XCV100/150 ... + W6 AC15, AC18, N/A N/A REF incrementally. Connect all AD20 pins listed for both the XCV200/300 ... + V7 ... + AE23 AJ18, AJ25, N/A required device and all smaller devices listed in the AK23, AK27 same package.) XCV400 N/A N/A ... + AJ17 AJ18, AJ25, Within each bank, if input AL20, AL24, reference voltage is not AL29 required, all V pins are REF XCV600 N/A N/A ... + AL24 ... + AM26 general I/O. XCV800 N/A N/A ... + AH19 ... + AN23 XCV1000 N/A N/A N/A ... + AK28 V , Bank 6 XCV50 M2, R3 N/A N/A N/A REF (V pins are listed XCV100/150 ... + T1 R24, Y26, N/A N/A REF incrementally. Connect all AA25, pins listed for both the XCV200/300 ... + T3 ... + AD26 V28, AB28, N/A required device and all AE30, AF28 smaller devices listed in the XCV400 N/A N/A ... + U28 V29, Y32, AD31, same package.) AE29, AK32 Within each bank, if input reference voltage is not XCV600 N/A N/A ... + AC28 ... + AE31 required, all V pins are REF XCV800 N/A N/A ... + Y30 ... + AA30 general I/O. XCV1000 N/A N/A N/A ... + AH30 DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 9 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 V , Bank 7 XCV50 G3, H1 N/A N/A N/A REF (V pins are listed XCV100/150 ... + D1 D26, G26, N/A N/A REF incrementally. Connect all L26 pins listed for both the XCV200/300 ... + B2 ... + E24 F28, F31, N/A required device and all smaller devices listed in the J30, N30 same package.) Within each bank, if input XCV400 N/A N/A ... + R31 E31, G31, K31, reference voltage is not P31, T31 required, all V pins are REF general I/O. XCV600 N/A N/A ... + J28 ... + H32 XCV800 N/A N/A ... + M28 ... + L33 XCV1000 N/A N/A N/A ... + D31 GND All C3, C18, A1, A2, A5, A2, A3, A7, A9, A1, A7, A12, D4, D5, A8, A14, A14, A18, A23, A14, A18, A20, D9, D10, A19, A22, A25, A29, A30, A24, A29, A32, D11, A25, A26, B1, B2, B30, A33, B1, B6, B9, D12, B1, B26, E1, B31, C1, C31, B15, B23, B27, D16, E26, H1, D16, G1, G31, B31, C2, E1, D17, E4, H26, N1, J1, J31, P1, P31, F32, G2, G33, E17, J4, P26, W1, T4, T28, V1, J32, K1, L2, J17, K4, W26, AB1, V31, AC1, AC31, M33, P1, P33, K17, L4, AB26, AE1, AE1, AE31, R32, T1, V33, L17, M4, AE26, AF1, AH16, AJ1, W2, Y1, Y33, M17, T4, AF2, AF5, AJ31, AK1, AK2, AB1, AC32, T17, U4, AF8, AF13, AK30, AK31, AD33, AE2, U5, U9, AF19, AF22, AL2, AL3, AL7, AG1, AG32, U10, AF25, AF26 AL9 AL14, AL18 AH2, AJ33, U11, AL23, AL25, AL32, AM3, U12, AL29, AL30 AM7, AM11, U16, AM19, AM25, U17, V3, AM28, AM33, V18 AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33 (1) GND All J9, J10, N/A N/A N/A J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 No Connect All N/A N/A N/A C31, AC2, AK4, AL3 Notes: 1. 16 extra balls (grounded) at package center. Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 10 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) Pin Name Device FG256 FG456 FG676 FG680 GCK0 All N8 W12 AA14 AW19 GCK1 All R8 Y11 AB13 AU22 GCK2 All C9 A11 C13 D21 GCK3 All B8 C11 E13 A20 M0 All N3 AB2 AD4 AT37 M1 All P2 U5 W7 AU38 M2 All R3 Y4 AB6 AT35 CCLK All D15 B22 D24 E4 PROGRAM All P15 W20 AA22 AT5 DONE All R14 Y19 AB21 AU5 INIT All N15 V19 Y21 AU2 BUSY/DOUT All C15 C21 E23 E3 D0/DIN All D14 D20 F22 C2 D1 All E16 H22 K24 P4 D2 All F15 H20 K22 P3 D3 All G16 K20 M22 R1 D4 All J16 N22 R24 AD3 D5 All M16 R21 U23 AG2 D6 All N16 T22 V24 AH1 D7 All N14 Y21 AB23 AR4 WRITE All C13 A20 C22 B4 CS All B13 C19 E21 D5 TDI All A15 B20 D22 B3 TDO All B14 A21 C23 C4 TMS All D3 D3 F5 E36 TCK All C4 C4 E6 C36 DXN All R4 Y5 AB7 AV37 DXP All P4 V6 Y8 AU35 DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 11 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 V All C3, C14, D4, E5, E18, F6, G7, G20, H8, H19, AD5, AD35, CCINT D13, E5, F17, G7, G8, G9, J9, J10, J11, J16, AE5, AE35, AL5, E12, M5, G14, G15, G16, J17, J18, K9, K18, AL35, AM5, M12, N4, H7, H16, J7, L9, L18, T9, T18, AM35, AR8, N13, P3, J16, P7, P16, U9, U18, V9, V10, AR9, AR15, P14 R7, R16, T7, T8, V11, V16, V17, AR16, AR24, T9, T14, T15, V18, W8, W19, Y7, AR25, AR31, T16, U6, U17, Y20 AR32, E8, E9, V5, V18 E15, E16, E24, E25, E31, E32, H5, H35, J5, J35, R5, R35, T5, T35 V , Bank 0 All E8, F8 F7, F8, F9, F10 H9, H10, H11, E26, E27, E29, CCO G10, G11 H12, J12, J13 E30, E33, E34 V , Bank 1 All E9, F9 F13, F14, F15, H15, H16, H17, E6, E7, E10, CCO F16, G12, G13 H18, J14, J15 E11, E13, E14 V , Bank 2 All H11, H12 G17, H17, J17, J19, K19, L19, F5, G5, K5, L5, CCO K16, K17, L16 M18, M19, N18 N5, P5 V , Bank 3 All J11, J12 M16, N16, N17, P18, R18, R19, AF5, AG5, AN5, CCO P17, R17, T17 T19, U19, V19 AK5, AJ5, AP5 V , Bank 4 All L9. M9 T12, T13, U13, V14, V15, W15, AR6, AR7, CCO U14, U15, U16, W16, W17, W18 AR10, AR11, AR13, AR14 V , Bank 5 All L8, M8 T10, T11, U7, V12, V13, AR26, AR27, CCO U8, U9, U10 W9,W10, W11, AR29, AR30, W12 AR33, AR34 V , Bank 6 All J5, J6 M7, N6, N7, P6, P9, R8, R9, T8, AF35, AG35, CCO R6, T6 U8, V8 AJ35, AK35, AN35, AP35 V , Bank 7 All H5, H6 G6, H6, J6, K6, J8, K8, L8, M8, F35, G35, K35, CCO K7, L7 M9, N9 L35, N35, P35 V , Bank 0 XCV50 B4, B7 N/A N/A N/A REF (VREF pins are listed XCV100/150 ... + C6 A9, C6, E8 N/A N/A incrementally. Connect XCV200/300 ... + A3 ... + B4 N/A N/A all pins listed for both the required device and XCV400 N/A N/A A12, C11, D6, E8, all smaller devices G10 listed in the same XCV600 N/A N/A ... + B7 A33, B28, B30, package.) C23, C24, D33 Within each bank, if XCV800 N/A N/A ... + B10 ... + A26 input reference voltage is not required, all V REF XCV1000 N/A N/A N/A ... + D34 pins are general I/O. Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 12 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 V , Bank 1 XCV50 B9, C11 N/A N/A N/A REF (VREF pins are listed XCV100/150 ... + E11 A18, B13, E14 N/A N/A incrementally. Connect XCV200/300 ... + A14 ... + A19 N/A N/A all pins listed for both the required device and XCV400 N/A N/A A14, C20, C21, N/A all smaller devices D15, G16 listed in the same XCV600 N/A N/A ... + B19 B6, B8, B18, package.) D11, D13, D17 Within each bank, if XCV800 N/A N/A ... + A17 ... + B14 input reference voltage is not required, all V REF XCV1000 N/A N/A N/A ... + B5 pins are general I/O. V , Bank 2 XCV50 F13, H13 N/A N/A N/A REF (V pins are listed XCV100/150 ... + F14 F21, H18, K21 N/A N/A REF incrementally. Connect XCV200/300 ... + E13 ... + D22 N/A N/A all pins listed for both the required device and XCV400 N/A N/A F24, H23, K20, N/A all smaller devices M23, M26 listed in the same XCV600 N/A N/A ... + G26 G1, H4, J1, L2, package.) V5, W3 Within each bank, if XCV800 N/A N/A ... + K25 ... + N1 input reference voltage is not required, all V REF XCV1000 N/A N/A N/A ... + D2 pins are general I/O. V , Bank 3 XCV50 K16, L14 N/A N/A N/A REF (V pins are listed XCV100/150 ... + L13 N21, R19, U21 N/A N/A REF incrementally. Connect XCV200/300 ... + M13 ... + U20 N/A N/A all pins listed for both the required device and XCV400 N/A N/A R23, R25, U21, N/A all smaller devices W22, W23 listed in the same XCV600 N/A N/A ... + W26 AC1, AJ2, AK3, package.) AL4, AR1, Y1 Within each bank, if XCV800 N/A N/A ... + U25 ... + AF3 input reference voltage is not required, all V REF XCV1000 N/A N/A N/A ... + AP4 pins are general I/O. DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 13 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 V , Bank 4 XCV50 P9, T12 N/A N/A N/A REF (V pins are listed XCV100/150 ... + T11 AA13, AB16, N/A N/A REF incrementally. Connect AB19 all pins listed for both XCV200/300 ... + R13 ... + AB20 N/A N/A the required device and all smaller devices XCV400 N/A N/A AC15, AD18, N/A listed in the same AD21, AD22, package.) AF15 Within each bank, if XCV600 N/A N/A ... + AF20 AT19, AU7, input reference voltage AU17, AV8, is not required, all V REF AV10, AW11 pins are general I/O. XCV800 N/A N/A ... + AF17 ... + AV14 XCV1000 N/A N/A N/A ... + AU6 V , Bank 5 XCV50 T4, P8 N/A N/A N/A REF (V pins are listed XCV100/150 ... + R5 W8, Y10, AA5 N/A N/A REF incrementally. Connect XCV200/300 ... + T2 ... + Y6 N/A N/A all pins listed for both the required device and XCV400 N/A N/A AA10, AB8, AB12, N/A all smaller devices AC7, AF12 listed in the same XCV600 N/A N/A ... + AF8 AT27, AU29, package.) AU31, AV35, Within each bank, if AW21, AW23 input reference voltage XCV800 N/A N/A ... + AE10 ... + AT25 is not required, all V REF pins are general I/O. XCV1000 N/A N/A N/A ... + AV36 V , Bank 6 XCV50 J3, N1 N/A N/A N/A REF (V pins are listed XCV100/150 ... + M1 N2, R4, T3 N/A N/A REF incrementally. Connect XCV200/300 ... + N2 ... + Y1 N/A N/A all pins listed for both the required device and XCV400 N/A N/A AB3, R1, R4, U6, N/A all smaller devices V5 listed in the same XCV600 N/A N/A ... + Y1 AB35, AD37, package.) AH39, AK39, Within each bank, if AM39, AN36 input reference voltage XCV800 N/A N/A ... + U2 ... + AE39 is not required, all V REF pins are general I/O. XCV1000 N/A N/A N/A ... + AT39 Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 14 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 V , Bank 7 XCV50 C1, H3 N/A N/A N/A REF (V pins are listed XCV100/150 ... + D1 E2, H4, K3 N/A N/A REF incrementally. Connect XCV200/300 ... + B1 ... + D2 N/A N/A all pins listed for both the required device and XCV400 N/A N/A F4, G4, K6, M2, N/A all smaller devices M5 listed in the same XCV600 N/A N/A ... + H1 E38, G38, L36, package.) N36, U36, U38 Within each bank, if XCV800 N/A N/A ... + K1 ... + N38 input reference voltage is not required, all V REF XCV1000 N/A N/A N/A ... + F36 pins are general I/O. GND All A1, A16, B2, A1, A22, B2, A1, A26, B2, B9, A1, A2, A3, A37, B15, F6, F7, B21, C3, C20, B14, B18, B25, A38, A39, AA5, F10, F11, J9, J10, J11, C3, C24, D4, D23, AA35, AH4, G6, G7, G8, J12, J13, J14, E5, E22, J2, J25, AH5, AH35, G9, G10, K9, K10, K11, K10, K11, K12, AH36, AR5, G11, H7, K12, K13, K14, K13, K14, K15, AR12, AR19, H8, H9, H10, L9, L10, L11, K16, K17, L10, AR20, AR21, J7, J8, J9, L12, L13, L14, L11, L12, L13, AR28, AR35, J10, K6, K7, M9, M10, M11, L14, L15, L16, AT4, AT12, AT20, K8, K9, K10, M12, M13, M14, L17, M10, M11, AT28, AT36, K11, L6, L7, N9, N10, N11, M12, M13, M14, AU1, AU3, AU20, L10, L11, N12, N13, N14, M15, M16, M17, AU37, AU39, R2, R15, T1, P9, P10, P11, N2, N10, N11, AV1, AV2, AV38, T16 P12, P13, P14, N12, N13, N14, AV39, AW1, Y3, Y20, AA2, N15, N16, N17, AW2, AW3, AA21, AB1, P10, P11, P12, AW37, AW38, AB22 P13, P14, P15, AW39, B1, B2, P16, P17, P25, B38, B39, C1, R10, R11, R12, C3, C20, C37, R13, R14, R15, C39, D4, D12, R16, R17, T10, D20, D28, D36, T11, T12, T13, E5, E12, E19, T14, T15, T16, E20, E21, E28, T17, U10, U11, E35, M4, M5, U12, U13, U14, M35, M36, W5, U15, U16, U17, W35, Y3, Y4, Y5, V2, V25, AB5, Y35, Y36, Y37 AB22, AC4, AC23, AD3, AD24, AE2, AE9, AE13, AE18, AE25, AF1, AF26 DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 15 R Virtex™ 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 No Connect XCV800 N/A N/A A2, A3, A15, A25, N/A B1, B6, B11, B16, (No-connect pins are B21, B24, B26, listed incrementally. All C1, C2, C25, C26, pins listed for both the F2, F6, F21, F25, required device and all L2, L25, N25, P2, larger devices listed in T2, T25, AA2, the same package are AA6, AA21, AA25, no connects.) AD1, AD2, AD25, AE1, AE3, AE6, AE11, AE14, AE16, AE21, AE24, AE26, AF2, AF24, AF25 XCV600 N/A N/A same as above N/A XCV400 N/A N/A ... + A9, A10, A13, N/A A16, A24, AC1, AC25, AE12, AE15, AF3, AF10, AF11, AF13, AF14, AF16, AF18, AF23, B4, B12, B13, B15, B17, D1, D25, H26, J1, K26, L1, M1, M25, N1, N26, P1, P26, R2, R26, T1, T26, U26, V1 XCV300 N/A D4, D19, W4, N/A N/A W19 XCV200 N/A ... + A2, A6, A12, N/A N/A B11, B16, C2, D1, D18, E17, E19, G2, G22, L2, L19, M2, M21, R3, R20, U3, U18, Y22, AA1, AA3, AA11, AA16, AB7, AB12, AB21, XCV150 N/A ... + A13, A14, N/A N/A C8, C9, E13, F11, H21, J1, J4, K2, K18, K19, M17, N1, P1, P5, P22, R22, W13, W15, AA9, AA10, AB8, AB14 Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 16 1-800-255-7778 Production Product Specification R Virtex™ 2.5 V Field Programmable Gate Arrays Pinout Diagrams The following diagrams, CS144 Pin Function Diagram, Table 5: Pinout Diagram Symbols (Continued) page 17 through FG680 Pin Function Diagram, page 27, Symbol Pin Function illustrate the locations of special-purpose pins on Virtex ❿, ❶, ❷ M0, M1, M2 FPGAs. Table 5 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. ➉, ➀, ➁, D0/DIN, D1, D2, D3, D4, D5, D6, D7 ➂, Table 5: Pinout Diagram Symbols ➃, ➄, ➅, ➆ Symbol Pin Function B DOUT/BUSY ✳ General I/O DDONE ❄ Device-dependent general I/O, n/c on smaller devices P PROGRAM VV IINIT CCINT v Device-dependent V , n/c on smaller K CCLK CCINT devices WWRITE OV CCO SCS RV REF T Boundary-scan Test Access Port r Device-dependent V , remains I/O on REF + Temperature diode, anode smaller devices – Temperature diode, cathode G Ground n No connect Ø, 1, 2, 3 Global Clocks CS144 Pin Function Diagram Bank 0 Bank 1 A A GO✳✳✳ 3 2 ✳ V R T T O A B B T O✳✳✳ r V RGG ✳ O K B Bank 7 C C ✳✳ T R V✳G✳✳WB ✳ C Bank 2 ➉ D D ✳✳ r R G R O✳rR S ✳ r D E E R✳✳GG ➁ ✳ E ➀ F F G✳✳✳ R ➂ ✳ ✳ F CS144 G G✳✳ OVV GO ✳ G (Top view) H H ✳✳ R ✳ ✳ R➃ ✳ H J JGG ✳✳ r r ➅ ➄ J K K R✳✳ ✳ ✳ ✳Ø✳ ✳ ✳ R ✳ K ➆ Bank 6 L L ✳ ❶GGG RR RR G ✳ P I L Bank 3 M M ❿ O✳✳ ✳VV ✳ 1 ✳ ✳ D O M N NOOO ❷✳ r✳✳✳ V ✳ r G N Bank 5 Bank 4 Figure 1: CS144 Pin Function Diagram DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 17 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 R Virtex™ 2.5 V Field Programmable Gate Arrays TQ144 Pin Function Diagram ❶ G T R r G R GO V R G r R G ❿ O ✳✳✳✳✳✳✳✳✳ ✳✳✳✳✳✳✳✳✳✳ 1 O ❷ 108 2 T 107 ✳ 3 Bank 7 Bank 6 106 ✳ ✳ 4 105 ✳ ✳ 5 R R 104 6 103 ✳ ✳ 7 r r 102 8 101 ✳ ✳ 9 G G 100 10 V Bank 0 Bank 5 V 99 11 98 ✳ ✳ 12 97 ✳ ✳ 13 R R 96 14 95 ✳ ✳ 15 V V 94 TQ144 16 3 1 93 17 O O 92 (Top view) 18 G G 91 19 2 Ø 90 20 89 ✳ ✳ 21 88 ✳ ✳ 22 R R 87 23 86 ✳ ✳ 24 85 ✳ ✳ 25 V V 84 26 G Bank 1 Bank 4 G 83 27 82 ✳ ✳ 28 r r 81 29 80 ✳ ✳ 30 R R 79 31 78 ✳ ✳ 32 W 77 ✳ 33 S 76 ✳ 34 T Bank 2 Bank 3 G 75 35 G D 74 36 T O 73 OOKP BRRrr GG ➁ V ➃RR ➄G ➅ I ➉✳✳ ➀ ✳✳ ➂✳✳ ✳ ✳ ✳✳ ✳✳ ➆ Figure 2: TQ144 Pin Function Diagram Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 18 1-800-255-7778 Production Product Specification 37 144 38 143 39 142 40 141 41 140 42 139 43 138 44 137 45 136 46 135 47 134 48 133 49 132 50 131 51 130 52 129 53 128 54 127 55 126 56 125 57 124 58 123 59 122 60 121 61 120 62 119 63 118 64 117 65 116 66 115 67 114 68 113 69 112 70 111 71 110 72 109 R Virtex™ 2.5 V Field Programmable Gate Arrays PQ240/HQ240 Pin Function Diagram T ✳ ✳ G ✳ r G V ✳✳ G ✳ r 3 G ✳ ✳ R ✳ r ✳ O ✳ r R ✳ r W T T O ✳ r ✳ R r ✳ O ✳ r ✳ R ✳ V O 2 r ✳ G ✳✳ V G r ✳ G ✳ ✳ S G 1 G O Bank 0 Bank 1 179 T K 3 ✳ B ✳ ➉ 177 5 r ✳ 175 r ✳ 7 ✳ ✳ 173 G ✳ 9 R G R 171 ✳ 11 r ✳ 169 r r 13 ✳ r ➀ 167 G 15 O G Bank 7 Bank 2 165 V O 17 V ✳ 163 ✳ ➁ 19 ✳ r r 161 ✳ 21 ✳ ✳ 159 G ✳ 23 R G PQ240/HQ240 ✳ 157 R 25 ✳ ➂ 155 r ✳ (Top view) 27 r ✳ 153 ✳ ✳ 29 ✳ G O G 151 Pins are shown staggered 31 O ✳ 149 V for readability ✳ 33 r V ✳ 147 r 35 ✳ ✳ 145 R ➃ 37 G R 143 ✳ G 39 ✳ ✳ r 141 ✳ 41 r ✳ 139 ✳ Bank 6 Bank 3 ✳ 43 V ➄ 137 O V 45 G O 135 G ✳ 47 r ➅ 133 r r 49 ✳ r R 131 ✳ 51 G R 129 G ✳ 53 ✳ ✳ ✳ 127 r 55 r ✳ 125 ✳ ✳ 57 ✳ ➆ 123 ❶ Bank 5 Bank 4 I 59 G P O 121 ❿ ❷ ✳ r ✳ R r ✳ O ✳ r ✳ R ✳ V O Ø r ✳ G ✳✳ V G r ✳ G ✳ ✳ ✳ D O ✳ ✳ ✳ G ✳ r G V ✳✳ G ✳ r 1 G ✳ ✳ R ✳ r ✳ O ✳ r R ✳ r ✳ G Figure 3: PQ240/HQ240 Pin Function Diagram DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 19 61 239 63 237 65 235 67 233 69 231 71 229 73 227 75 225 77 223 79 221 81 219 83 217 85 215 87 213 89 211 91 209 93 207 95 205 97 203 99 201 101 199 103 197 105 195 107 193 109 191 111 189 113 187 115 185 117 183 119 181 R Virtex™ 2.5 V Field Programmable Gate Arrays BG256 Pin Function Diagram ATR r ✳ r ✳✳✳ ✳2 ✳✳✳✳✳✳R ✳WT A B ✳ r ✳ R ✳✳✳✳✳ 3 ✳RS ✳ ✳ r ✳ rK ✳ B C ✳✳ G✳✳✳✳✳✳ V ✳✳✳✳✳✳ TG ➉ R C D r✳✳ T G G V OOGGGGOO V G G B✳ D E ✳✳✳GG✳✳ ➀ E Bank 0 Bank 1 F ✳✳✳VV✳✳ r F G ✳✳ RO O r ➁ ✳ G BG256 H RO ✳✳ O✳✳✳ H Bank 7 Bank 2 J ✳✳✳ G GGGG GR ➂ ✳ J K ✳✳✳GG GGGG ✳✳✳ K L ✳✳ VG GGGG GV ✳✳ L M ✳✳RG GGGG GR ➃ ✳ M N ✳✳✳OO✳✳✳ N Bank 6 Bank 3 (Top View) P ✳✳✳OO r ➄ ✳ P R ✳✳ RV V✳✳ r R T r ✳ rGG✳✳ ➅ T Bank 5 Bank 4 U ✳✳ ❶ GG V OOGGGGOO V G G I ✳✳ U V ✳✳ G+ ✳✳ r✳✳ R V R✳ r ✳✳✳ G ➆ R V W ✳ ❷ – ✳ ✳rr ✳✳✳✳✳✳✳✳ ✳✳✳ D ✳ W Y ❿✳R1 ✳✳✳✳✳✳ Ø✳✳✳✳✳✳R ✳P Y DS003_18_100300 Figure 4: BG256 Pin Function Diagram Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 20 1-800-255-7778 Production Product Specification 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 R Virtex™ 2.5 V Field Programmable Gate Arrays BG352 Pin Function Diagram A G G ✳ ✳ G ✳ ✳ G ✳ O ✳ ✳ ✳ G ✳ R O ✳ G V ✳ G ✳ ✳ G G A B G O T ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ 2 ✳ V ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ O G B C ✳ ✳ K S ✳ ✳ ✳ ✳ R ✳ ✳ R ✳ V ✳ ✳ ✳ ✳ R ✳ R ✳ ✳ T ✳ ✳ C D ✳ r ➉ T W r O ✳ ✳ V ✳ V O 3 ✳ ✳ ✳ ✳ O ✳ r ✳ T ✳ ✳ R D E G R ✳ B ✳ r ✳ G E F ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ F Bank 1 Bank 0 G ➀ ✳ ✳ ✳ O ✳ ✳ R G H G R ✳ O ✳ ✳ ✳ G H J ✳ ✳ ➁ ✳ ✳ V ✳ ✳ J K O ✳ ✳ V ✳ ✳ ✳ O K Bank 2 Bank 7 L V ✳ ✳ ✳ ✳ ✳ V R L M ✳ ✳ ➂ R ✳ ✳ ✳ ✳ M N G ✳ ✳ ✳ O ✳ ✳ ✳ N BG352 P ✳ V ✳ O (Top View) ✳ ✳ V G P R ✳ ✳ ➃ R V R ✳ ✳ R T V ✳ ✳ ✳ ✳ ✳ ✳ ✳ T U O ✳ ✳ ➄ ✳ ✳ ✳ O U Bank 3 Bank 6 V ✳ ✳ ➅ R ✳ V ✳ ✳ V W G V ✳ ✳ O ✳ ✳ G W Y ✳ ✳ R O ✳ ✳ ✳ R Y AA ✳ ✳ ✳ ✳ ✳ ✳ R ✳ AA Bank 4 Bank 5 AB G ✳ ✳ ✳ ❶ ✳ ✳ G AB AC ✳ r ➆ P ✳ ✳ ✳ O ✳ V ✳ R ✳ O R ✳ ✳ R ✳ O ✳ ✳ ❷ ✳ ✳ ✳ AC AD ✳ I D ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ – ❿ ✳ r AD AE G O ✳ r R ✳ ✳ R ✳ ✳ ✳ ✳ Ø V ✳ ✳ ✳ ✳ V ✳ ✳ ✳ r + O G AE AF G G ✳ ✳ G ✳ ✳ G ✳ O V✳✳ G 1 V O ✳ G ✳ ✳ G ✳ ✳ G G AF DS003_19_100600 Figure 5: BG352 Pin Function Diagram DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 21 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 R Virtex™ 2.5 V Field Programmable Gate Arrays BG432 Pin Function Diagram A O G G✳✳✳ G✳ GVO✳ R G✳ 2 V G✳✳✳✳✳ O G G ✳✳ G G O A B GG TW✳✳ R ✳✳✳✳rr ✳✳ ✳✳✳✳✳✳ R r V ✳✳ V ✳✳ G G B C GO ➉ T ✳R V ✳ ✳R ✳✳✳V ✳✳✳rr V ✳✳✳✳ ✳✳✳✳OG ✳ C D ✳✳ BKS ✳✳✳✳ r O ✳✳✳✳ G 3 ✳✳✳ O R ✳ R ✳ R ✳ T T ✳✳ D E ✳✳ R ✳ ✳✳✳✳ E F V✳✳ ✳ RR ✳ V F Bank 1 Bank 0 G GR ✳ ✳ ✳✳✳ G G H r ✳✳✳ ✳✳✳✳ H J GR ✳✳ r ✳ RG J K ✳ ➁ V ➀ ✳✳ V ✳ K Bank 2 Bank 7 L OO ✳✳ OO ✳✳ L M ✳✳rr ✳ ✳✳✳ M N RV ✳✳ ✳✳ VR N P G ✳✳ ➂ ✳✳✳ G P R ✳✳ r ✳ ✳✳✳ r R BG432 T VG ✳✳ (Top View) GV ✳✳ T U ✳✳rr ✳ ✳✳✳ U V GR ✳ ➃ RG ✳✳ V W ✳✳ V ✳ ✳✳✳ V W Y ✳✳ r ✳ ✳✳ r ✳ Y AA O ✳✳ O O ✳✳ O AA AB ➄VR ➅ R✳✳ V AB Bank 3 Bank 6 AC G✳✳ r r ✳✳ G AC AD ✳✳✳ R ✳✳✳✳ AD AE G✳✳ ✳ ✳ V R G AE AF V ✳ R ✳ R ✳✳✳ AF Bank 4 Bank 5 AG ✳✳✳ ➆ ✳✳✳✳ AG AH ✳✳ P D ✳✳✳ V ✳✳ O ✳✳✳✳ G ✳✳ r ✳ O ✳ ✳ V ✳ ✳ – ❿ ❶✳ ✳ AH AJ GIO ✳✳✳ R ✳✳ V ✳ r ✳✳✳ V r R ✳✳✳✳✳✳RO ✳✳ ❷ ✳ G AJ AK GG ✳✳✳✳✳ r ✳✳✳✳V1V ✳ r ✳ ✳ ✳ ✳ VR ✳✳✳ R ✳ + GG AK Ø AL OG GR ✳✳ GR G ✳ O ✳ RG ✳ ✳ G ✳✳ O ✳ G r G ✳ ✳✳ G GO AL DS003_21_100300 Figure 6: BG432 Pin Function Diagram Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 22 1-800-255-7778 Production Product Specification 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 R Virtex™ 2.5 V Field Programmable Gate Arrays BG560 Pin Function Diagram ✳✳✳ ✳✳✳✳✳ ✳✳✳✳ ✳ A GS RG OGGO3G RG V O G O GO GG A B GO r ✳✳ G ✳✳ G ✳✳ VO VG ✳✳VOGG ✳✳✳ ✳✳✳V ✳✳GOT B ✳ ✳ ✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳ ✳ ✳✳✳✳✳✳ ✳ C GO K V V n O C ✳✳ ✳✳ ✳ ✳ ✳ ✳ ✳ ✳✳✳✳✳ ✳✳ ✳ ✳ DOT B WR rrR R2 R R rr O D EGO ✳✳ ➉T r ✳VV ✳ ✳ ✳ ✳R ✳✳✳✳✳rr ✳R ✳ ✳R ✳ T ✳ R ✳ ✳ E F ✳ V ✳✳✳ ✳✳✳ G ✳ F Bank 1 Bank 0 ✳✳✳ ✳✳ ✳ G GR R G G HOR ✳✳ ✳ ✳✳✳ V r H J V ✳✳✳✳ ✳✳✳ G ✳ J ✳✳ ➀ ✳✳ K G r RV O K Bank 2 Bank 7 ✳✳ ➁ ✳✳✳✳ L GR r L M O✳✳ V ✳ ✳✳✳✳ G M ✳✳✳ ✳✳ N V r V OV N ✳✳ ➂ ✳✳ ✳ P GRRG P R R O ✳✳✳ ✳✳✳ G ✳ R BG560 T G ✳✳✳✳ (Top View) ✳✳RO ✳ T ✳✳✳✳ ✳ ✳✳✳ UVV U VOR ✳✳ ✳ R ✳✳✳G V W ✳✳GR ➃ ✳✳✳O ✳ W ✳✳✳ ✳✳ Y GV VR G Y ✳✳✳ ✳ ✳✳✳ AA O r r AA AB G V ✳ ✳ ➄ ✳✳✳ V O AB ✳✳✳ ➅ ✳✳✳ ✳ AC n G AC Bank 3 Bank 6 ✳✳ ✳✳ AD OV R RV G AD AE ✳✳ G ✳ R R✳✳ r ✳ AE AF r ✳✳✳✳ ✳✳✳✳ O AF ✳✳✳ ✳✳ ✳ AG GV VG AG Bank 4 Bank 5 AH✳✳ G r I ✳ r ✳✳✳ AH AJ ✳✳✳ ➆ D ✳✳✳✳✳✳✳ V ✳✳✳ 1 R ✳✳✳✳✳✳ R ✳✳ + ❿ ✳✳✳ G AJ ✳ ✳ ✳✳ ✳✳ ✳ ✳✳✳ ✳✳ ✳✳✳✳✳✳✳ ❶ ✳ AK O R n V V r V V r – R O AK ✳ ✳✳✳ ✳ ✳✳✳ ✳ ✳✳✳✳✳✳✳✳ ✳ ALOR n R r R V Ø R V R V R O G AL AM P O G R ✳✳ G ✳✳✳ G ✳✳ R O ✳✳✳ G ✳ O ✳✳✳ G r ✳ G ✳ ✳✳ OG AM ✳✳✳✳✳✳✳✳✳ ✳✳✳✳ ❷ AN G G r O G O G O G GO G G r O V G O G AN DS003_22_100300 Figure 7: BG560 Pin Function Diagram DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 23 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 R Virtex™ 2.5 V Field Programmable Gate Arrays FG256 Pin Function Diagram Bank 0 Bank 1 G r r T G A A ✳ ✳✳✳✳✳✳✳✳✳✳ rGG R RR 3 S T B B ✳ ✳✳ ✳✳✳ ✳ R V T r 2 R W V B C C ✳ ✳ ✳✳✳✳ ✳ Bank 7 r T V V K Bank 2 D D ✳ ✳✳✳✳✳✳✳✳ ➉ ✳ VV OO rr E E ✳✳✳✳ ✳✳ ✳ ✳✳ ➀ GGOOGG R r F ➁ F ✳✳✳✳✳ ✳ ✳ GGGGG G G ✳✳✳✳✳ G✳✳✳✳➂ R OOGGGGOO R H H ✳✳ ✳ ✳✳✳ R OOGGGGOO J ➃ J ✳✳ ✳ ✳✳✳ GGGGGG R K K ✳✳✳✳✳ ✳✳✳✳ GGOOGG r R L L ✳✳✳✳✳ ✳ ✳✳ r V OO V r M ➄ M ✳✳✳ ✳✳ ✳✳ ✳✳ Bank 6 Bank 3 R r V Ø V I N ❿ ➅ N ✳✳✳ ✳✳✳✳ ➆ V + R R V P P ❶ P ✳ ✳✳✳ ✳✳✳✳ ✳ G – r 1 r D G R ❷ R ✳ ✳✳ ✳✳✳✳ ✳ G r R r R G T T ✳ ✳✳✳✳✳✳ ✳✳✳ Bank 5 Bank 4 FG256 (Top view) Figure 8: FG256 Pin Function Diagram Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 24 1-800-255-7778 Production Product Specification 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 R Virtex™ 2.5 V Field Programmable Gate Arrays FG456 Pin Function Diagram Bank 0 Bank 1 G R 2 R r WT G A A ❅✳✳✳❅❅ ✳✳ ✳ ❅❅✳✳✳ B G r R T G K B ✳ ✳ ✳✳✳✳✳✳❅❅ ✳ ✳✳ ✳✳✳ GG T R 3 S B C C ✳❅ ✳ ✳❅❅✳ ✳✳✳✳✳✳✳ ✳ r T n n r Bank 7 D D Bank 2 ❅ ✳✳✳✳✳✳✳✳✳✳ ✳✳✳❅ ➉ ✳ R V R R V E E ✳ ✳✳ ✳✳ ✳✳✳✳❅ ✳ ✳❅ ❅✳✳✳ V OOOO OOOO V R F F ✳✳✳✳✳ ❅✳ ✳✳✳ ✳ G O V V VOOOOVVV O G ✳❅✳✳✳ ✳✳✳✳❅ R O V V O R H ➁ H ✳✳✳ ✳ ✳ ❅ ➀ O V GGGGGG V O J J ❅✳✳❅✳ ✳✳✳✳✳ R OO GGGGGG OO R K ➂ K ✳❅ ✳✳ ❅❅ ✳ O GGGGGG O L L ✳❅✳✳✳✳ ✳✳❅✳✳✳ M O GGGGGG O M ✳❅✳✳✳✳ ❅✳✳✳❅✳ R OO GGGGGG OO R N ➃ N ❅ ✳✳✳ ✳✳✳ O V GGGGGG V O P P ❅✳✳✳❅ ✳✳✳✳❅ R O V V O R R ➄ R ✳✳❅ ✳ ✳ ❅ ❅ R O V V VOOOOVV V O ➅ T T ✳✳ ✳✳ ✳✳✳✳ U ❶ VOOOO OOOO V r R U ✳✳❅✳ ✳✳ ❅✳ ✳ V + V I V V ✳✳✳✳ ✳✳✳✳✳✳✳✳✳✳✳ ✳✳✳ Bank 6 Bank 3 n R Ø n P W W ✳✳✳ ✳✳✳ ✳✳✳ ❅✳❅✳✳✳ ✳✳ rGG – r R 1 D Y ❷ Y ✳ ✳✳✳ ✳✳✳✳✳✳✳ ➆❅ G R R G AA AA ❅ ❅✳ ✳✳✳❅❅❅✳ ✳✳ ❅✳✳✳✳ ✳ AB G ❿ R R r G AB ✳✳✳✳ ❅❅✳✳✳❅✳❅✳ ✳✳ ❅ Bank 5 Bank 4 FG456 (Top view) Figure 9: FG456 Pin Function Diagram Notes: Packages FG456 and FG676 are layout compatible. DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 25 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 R Virtex™ 2.5 V Field Programmable Gate Arrays FG676 Pin Function Diagram Bank 0 Bank 1 ✳✳✳✳✳ ❄ ❄ ✳ ❄ ❄ ✳✳✳✳✳✳ ❄ AGnn R Rn r nG A BnG ✳❄ ✳ nr ✳ Gr n ❄❄ G ❄ n ❄ Gr ✳ n ✳✳ nG n B CnnG ✳✳✳✳✳✳✳ R ✳ 2 ✳✳✳✳✳✳ RR W T G n n C D ❄✳ ✳ G ✳ R ✳✳✳✳✳✳✳✳ R ✳✳✳✳✳✳ TG K ❄✳ D E ✳✳✳✳ GT ✳ R ✳✳✳✳ 3 ✳✳✳✳✳✳✳ SG B ✳✳✳ E Bank 7 F ✳ n ✳ RT n ✳✳✳✳✳✳✳✳✳✳✳✳✳✳ n ➉ ✳ Rn ✳ F Bank 2 G ✳✳✳ R ✳✳ V ✳ ✳ R ✳✳✳✳✳ R ✳✳✳ V ✳✳✳✳✳rG ✳✳✳✳✳✳ ✳✳ ✳✳✳ ✳✳ ❄ Hr V OOOO OOOO V R H J ❄ G ✳✳✳✳✳ O VVV O O O O VVV O ✳✳✳✳✳ G ✳ J ✳✳✳✳ ✳ ✳ ✳ ❄ Kr R O V GGGGGGGG V O R ➁ ➀ r K ❄ ✳✳✳✳✳ ✳✳✳✳✳ ✳ L n O V GGGGGGGG V O n L M ❄ R ✳✳ R OOGGGGGGGGOO ✳✳ ➂ R ✳❄RM ✳✳ N ❄ G ✳✳✳ ✳✳✳ OGGGGGGGGO ✳✳✳✳✳✳ n ❄ N ❄ ✳✳✳✳✳✳ ✳✳✳✳✳✳ ❄ P n OGGGGGGGGO G P ❄✳ ✳✳✳ ✳✳✳ ❄ RR R OOGGGGGGGGOO R ➃ R R T ❄ n ✳✳✳✳✳ O V GGGGGGGG V O ✳✳✳✳✳ n ❄ T U ✳ r ✳✳✳ R ✳ O V GGGGGGGG V O ✳ R ✳ ➄ ✳ r ❄ U V ❄ G ✳✳ R ✳✳ O V V V OOOO V V V O ✳✳✳✳ ➅ G ✳ V Bank 6 W ✳✳✳✳✳✳ V OOOO ✳✳ OOOO V ✳✳ RR ✳✳ r W Bank 3 ❶ Yr ✳✳✳✳✳ V ✳✳✳✳✳✳✳✳✳✳✳ VI ✳✳✳✳✳ Y + ✳ ✳✳✳ ✳✳✳ ✳✳✳ ✳✳✳✳✳✳ ✳✳ ✳ AA n n R 0 nP n AA ✳✳ ✳ - ✳✳✳ ✳✳✳✳✳✳✳ ✳✳✳ AB R G ❷ R R1 DG ➆ AB ❄✳ ✳ ✳✳ ✳✳✳✳✳✳✳ ✳✳✳✳✳✳✳ ✳❄ ✳ AC G R R G AC AD n n G ✳✳✳✳✳✳✳✳✳✳✳✳✳ R ✳✳ RR ✳ G n ✳ AD ❿ AE n G n ✳✳ n ✳✳ Gr n ❄ Gn ❄ n ✳ G ✳✳ n ✳✳ nG n AE AF G n ❄ ✳ ✳✳✳ r ✳❄ ❄ R ❄❄ R ❄ r ❄✳ r ✳✳ ❄ nn G AF Bank 5 Bank 4 FG676 (Top view) fg676a Figure 10: FG676 Pin Function Diagram Notes: Packages FG456 and FG676 are layout compatible. Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 26 1-800-255-7778 Production Product Specification 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 R Virtex™ 2.5 V Field Programmable Gate Arrays FG680 Pin Function Diagram Bank 1 Bank 0 AGGG ✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳ 3 ✳✳✳✳✳ r ✳✳✳✳✳✳ R ✳✳✳ GGG A BGGTWrR ✳ R ✳✳✳✳✳ r ✳✳✳ R ✳✳✳✳✳✳✳✳✳ R ✳ R ✳✳✳✳✳✳✳ GG B CG GT ✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳ G ✳✳ RR ✳✳✳✳✳✳✳✳✳✳✳ TG ✳GC ➉ D ✳ r ✳ GS ✳✳✳✳✳ RG R ✳✳✳ R ✳✳ G2 ✳✳✳✳✳✳ G ✳✳✳✳ Rr ✳ G ✳✳✳ D E ✳✳ B K G OO V V OOGOO V V ✳✳ GGG ✳✳ V V OOGOO V V OOG T ✳ R ✳ E Bank 2 F ✳✳✳✳ O Or ✳✳✳ F Bank 7 GR ✳✳✳ O O ✳✳ R ✳ G H ✳✳✳ RV V ✳✳✳✳ H JR ✳✳✳ V V ✳✳✳✳ J K ✳✳✳✳ O O ✳✳✳✳ K L ✳ R ✳✳ O OR ✳✳✳ L M ✳✳✳ GG GG ✳✳✳ M Nr ✳✳✳ O OR ✳ r ✳ N P ✳✳ O O ✳✳✳✳ P ➁➀ R ➂ ✳✳✳ V V ✳✳✳✳ R T ✳✳✳✳ V V ✳✳✳✳ T U ✳✳✳✳✳ ✳ R ✳ R ✳ U V ✳✳✳✳ R ✳✳✳✳✳ V W ✳✳ R ✳ G G ✳✳✳✳ W YR ✳ GGG FG680 GGG ✳✳ Y AA ✳✳✳✳ G G ✳✳✳✳ AA (Top View) AB ✳✳✳✳✳ R ✳✳✳✳ AB Bank 7 AC R ✳✳✳✳ ✳✳✳✳✳ AC Bank 2 AD ✳✳ ✳ V V ✳ R ✳✳ AD ➃ AE ✳✳✳✳ V V ✳✳✳rAE AF ✳✳ r ✳ O O ✳✳✳✳ AF AG ✳ ➄ ✳✳ O O ✳✳✳✳ AG AH ✳✳ GG GG ✳✳RAH ➅ AJ ✳ R ✳✳ O O ✳✳✳✳ AJ AK ✳✳ R ✳ O O ✳✳✳RAK AL ✳✳✳ RV V ✳✳✳✳ AL AM ✳✳✳✳ V V ✳✳✳RAM AN ✳✳✳✳ O OR ✳✳✳ AN Bank 3 AP ✳✳✳ rO O ✳✳✳✳ AP Bank 6 AR R ✳✳ ➆ GOO V V OOGOO V V ✳✳ GGG ✳✳ V V OOGOO V V OOG ✳✳✳✳ AR AT ✳✳✳ GP ✳✳✳✳✳✳ G ✳✳✳✳✳✳ RG ✳✳✳✳ r ✳ RG ✳✳✳✳✳✳ G ✳rAT ❷ ❿ AU G I G ✳ Dr R ✳✳✳✳✳✳✳✳✳ R ✳✳ G ✳ 1 ✳✳✳✳✳✳ R ✳ R ✳✳✳ ✳ G GAU + ❶ AV G G ✳✳✳✳✳ R ✳ R ✳✳✳ r ✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳✳ Rr G G AV - AW GGG ✳✳✳✳✳✳✳ R ✳✳✳✳✳✳✳ 0 ✳ R ✳ R ✳✳✳✳✳✳✳✳✳✳✳✳✳ GGG AW Bank 4 Bank 5 fg680_12a Note: AA3, AA4, and AB2 are in Bank 2 Note: AA37 is in Bank 7 Figure 11: FG680 Pin Function Diagram DS003-4 (v2.8) July 19, 2002 www.xilinx.com Module 4 of 4 Production Product Specification 1-800-255-7778 27 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 R Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added T parameter, changed T to T . IJITCC OJIT OPHASE 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for V in CS144 package on p.43. CCO 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18.  Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. 09/00 2.3  Corrected Units column in table under IOB Input Switching Characteristics.  Added values to table under CLB SelectRAM Switching Characteristics.  Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18. 10/00 2.4  Corrected BG256 Pin Function Diagram.  Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. 04/02/01 2.5  Converted file to modularized format. See section Virtex Data Sheet, below.  Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.) 04/19/01 2.6  Clarified V pinout information and added AE19 pin for BG352 devices in Table 3. 07/19/01 2.7 CCINT  Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7.  Changed pinouts listed for GND in TQ144 devices (see Table 2). 07/19/02 2.8 Virtex Data Sheet The Virtex Data Sheet contains the following modules:  DS003-1, Virtex 2.5V FPGAs:  DS003-3, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)  DS003-2, Virtex 2.5V FPGAs:  DS003-4, Virtex 2.5V FPGAs: Functional Description (Module 2) Pinout Tables (Module 4) Module 4 of 4 www.xilinx.com DS003-4 (v2.8) July 19, 2002 28 1-800-255-7778 Production Product Specification