0 R Virtex-4 Data Sheet: DC and Switching Characteristics 00 DS302 (v2.2) June 8, 2007 Preliminary Product Specification Virtex-4 Electrical Characteristics Virtex™-4 FPGAs are available in -12, -11, and -10 speed This Virtex-4 Data Sheet is part of an overall set of docu- grades, with -12 having the highest performance. mentation on the Virtex-4 family of FPGAs that is available on the Xilinx Website: Virtex-4 DC and AC characteristics are specified for both commercial and industrial grades. Except the operatingVirtex-4 Family Overview, DS112 temperature range or unless otherwise noted, all the DCVirtex-4 User Guide, UG070 and AC electrical parameters are the same for a particular Virtex-4 Configuration Guide, UG071 speed grade (that is, the timing characteristics of a -10 XtremeDSP Design Considerations, UG073 speed grade industrial device are the same as for a -10 Virtex-4 Packaging Specification, UG075 speed grade commercial device). However, only selected PCB Designers Guide, UG072 speed grades and/or devices might be available in the industrial range.Virtex-4 RocketIO™ Multi-Gigabit Transceiver User Guide, UG076 All supply voltage and junction temperature specifications Tri-Mode Ethernet Media Access Controller, UG074 are representative of worst-case conditions. The parame- ters included are common to popular designs and typicalPowerPC™ 405 Processor Block Reference Guide, applications. UG018 All specifications are subject to change without notice. Virtex-4 DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description Units V Internal supply voltage relative to GND –0.5 to 1.32 V CCINT V Auxiliary supply voltage relative to GND –0.5 to 3.0 V CCAUX V Output drivers supply voltage relative to GND –0.5 to 3.75 V CCO V Key memory battery backup supply –0.5 to 4.05 V BATT V Input reference voltage –0.3 to 3.75 V REF I/O input voltage relative to GND –0.75 to 4.05 V (all user and dedicated I/Os) –0.95 to 4.4 I/O input voltage relative to GND (Commercial Temperature) V V IN (3,4) (restricted to maximum of 100 user I/Os) –0.85 to 4.3 (Industrial Temperature) 2.5V or below I/O input voltage relative to GND –0.75 to V + 0.5 V CCO (user and dedicated I/Os) Current applied to an I/O pin, powered or unpowered ±100 mA I IN Total current applied to all I/O pins, powered or unpowered ±200 mA © 2004-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 1 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings (Continued) Symbol Description Units Voltage applied to 3-state 3.3V output –0.75 to 4.05 V (all user and dedicated I/Os) –0.95 to 4.4 Voltage applied to 3-state 3.3V output (Commercial Temperature) V V TS (3,4) (restricted to maximum of 100 user I/Os) –0.85 to 4.3 (Industrial Temperature) 2.5V or below I/O input voltage relative to GND –0.75 to V + 0.5 V CCO (user and dedicated I/Os) Receive auxiliary supply voltage relative to analog ground, GNDA AVCCAUXRX –0.5 to 1.32 V (RocketIO pins) Transmit auxiliary supply voltage relative to analog ground, GNDA AVCCAUXTX –0.5 to 1.32 V (RocketIO pins) Management auxiliary supply voltage relative to analog ground, GNDA AVCCAUXMGT –0.5 to 3.0 V (RocketIO pins) V Terminal receive supply voltage relative to GND –0.5 to 3.0 V TRX V Terminal transmit supply voltage relative to GND –0.5 to 1.65 V TTX T Storage temperature (ambient) –65 to 150 °C STG (2) T Maximum soldering temperature +220 °C SOL (2) T Maximum junction temperature +125 °C J Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see the Virtex-4 Packaging Specifications on the Xilinx website. 3. When using more than 100 3.3V I/Os, refer to the Virtex-4 User Guide, Chapter 6, “3.3V I/O Design Guidelines,” 4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period. There are no bank restrictions. Table 2: Recommended Operating Conditions Symbol Description Min Max Units Internal supply voltage relative to GND, T =0°C to +85°C Commercial 1.14 1.26 V J V CCINT = –40°C to +100°C Industrial 1.14 1.26 V Internal supply voltage relative to GND, T J Auxiliary supply voltage relative to GND, T =0°C to +85°C Commercial 2.375 2.625 V J V CCAUX Auxiliary supply voltage relative to GND, T =–40°C to +100°C Industrial 2.375 2.625 V J Supply voltage relative to GND, T =0°C to +85°C Commercial 1.14 3.45 V J (1,3,4,5) V CCO Supply voltage relative to GND, T = –40°C to +100°C Industrial 1.14 3.45 V J 3.3V supply voltage relative to GND, T =0°C to +85°C Commercial GND – 0.20 3.45 V J = –40°C to +100°C Industrial GND – 0.20 3.45 V 3.3V supply voltage relative to GND, T J 2.5V and below supply voltage relative to GND, V IN Commercial GND – 0.20 V +0.2 V CCO T =0°C to +85°C J 2.5V and below supply voltage relative to GND, Industrial GND – 0.20 V +0.2 V CCO T =–40°C to +100°C J Commercial 10 mA Maximum current through any pin in a powered or unpowered I IN bank when forward biasing the clamp diode. Industrial 10 mA Battery voltage relative to GND, T =0°C to +85°CCommercial1.0 3.6 V J (2) V BATT Battery voltage relative to GND, T = –40°C to +100°C Industrial 1.0 3.6 V J DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 2 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 2: Recommended Operating Conditions (Continued) Symbol Description Min Max Units Commercial 1.14 1.26 V (6) AVCCAUXRX Auxiliary receive supply voltage relative to GNDA Industrial 1.14 1.26 V Commercial 1.14 1.26 V (6) AVCCAUXTX Auxiliary transmit supply voltage relative to GNDA Industrial 1.14 1.26 V Commercial 2.375 2.625 V AVCCAUXMGT Auxiliary management supply voltage relative to GNDA Industrial 2.375 2.625 V Commercial 0.25 2.5 V (7) V Terminal receive supply voltage relative to GND TRX Industrial 0.25 2.5 V Commercial 1.14 1.575 V V Terminal transmit supply voltage relative to GND TTX Industrial 1.14 1.575 V Notes: 1. Configuration data is retained even if V drops to 0V. CCO 2. V is required only when using bitstream encryption. If battery is not used, connect V to either ground or V . BATT BATT CCAUX 3. For 3.3V I/O operation, refer to the Virtex-4 User Guide. 4. Includes V of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V CCO 5. The configuration output supply voltage V is also known as V CC_CONFIG CCO_0 6. IMPORTANT! All unused RocketIO transceivers must be connected to power and GND. When using RocketIO transceivers, refer to the power filtering section of the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. Unused transceivers must be powered by an appropriate voltage level source. Passive filtering must meet the requirements discussed in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. 7. Internal AC coupling is enabled. Table 3: DC Characteristics Over Recommended Operating Conditions Data Rate Symbol Description (Gb/s) Min Typ Max Units Data retention V voltage CCINT V 0.9 V DRINT (below which configuration data might be lost) Data retention V voltage CCAUX V 2.0 V DRI (below which configuration data might be lost) I V current per pin 10 µA REF REF I Input or output leakage current per pin (sample-tested) 10 µA L C Input capacitance (sample-tested) 10 pF IN Pad pull-up (when selected) @ V =0V, V =3.3V 5 200 µA IN CCO Pad pull-up (when selected) @ V =0V, V =3.0V 5 125 µA IN CCO (1) I Pad pull-up (when selected) @ V =0V, V =2.5V 5 120 µA RPU IN CCO Pad pull-up (when selected) @ V =0V, V = 1.8V 5 60 µA IN CCO Pad pull-up (when selected) @ V =0V, V = 1.5V 5 40 µA IN CCO (1) I Pad pull-down (when selected) @ V =V 5100µA RPD IN CCO (1) I Battery supply current 75 nA BATT 6.5 292 427 mA 5.0 302 485 mA 4.25 291 446 mA (2) I Operating AVCCAUXRX supply current CCAUXRX 3.125 279 382 mA 1.25/2.5 263 351 mA 1.25 Digital RX 314 432 mA DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 3 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions (Continued) Data Rate Symbol Description (Gb/s) Min Typ Max Units 6.5 170 339 mA 5.0 180 355 mA 4.25 173 330 mA (2) I Operating AVCCAUXTX supply current CCAUXTX 3.125 165 307 mA 2.5 157 298 mA 1.25 151 295 mA (2) I Operating AVCCAUXMGT supply current 3 5 mA CCAUXMGT Operating I supply current when transmitter is AC coupled (2) TTX I 100 210 mA TTX or V =V TTX TRX Operating I supply current when receiver is AC coupled or (2,3) TRX I 12 24 mA TRX V =V TTX TRX n Temperature diode ideality factor 1.02 n P Power dissipation of PowerPC 405 processor block 0.45 mW/MHz CPU r Series resistance 2 Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. I numbers given per tile with both MGT devices operating with default settings. CC 3. Varies with AC / DC coupling Table 4: Quiescent Supply Current (1) Symbol Description Device Typ Max Units I Quiescent V supply current XC4VLX15 46 Note (6) mA CCINTQ CCINT XC4VLX25 77 Note (6) mA XC4VLX40 121 Note (6) mA XC4VLX60 167 Note (6) mA XC4VLX80 220 Note (6) mA XC4VLX100 292 Note (6) mA XC4VLX160 384 Note (6) mA XC4VLX200 489 Note (6) mA XC4VSX25 94 Note (6) mA XC4VSX35 140 Note (6) mA XC4VSX55 271 Note (6) mA XC4VFX12 47 Note (6) mA XC4VFX20 71 Note (6) mA XC4VFX40 139 Note (6) mA XC4VFX60 203 Note (6) mA XC4VFX100 311 Note (6) mA XC4VFX140 442 Note (6) mA DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 4 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 4: Quiescent Supply Current (Continued) (1) Symbol Description Device Typ Max Units I Quiescent V supply current XC4VLX15 1.25 Note (6) mA CCOQ CCO XC4VLX25 1.25 Note (6) mA XC4VLX40 1.25 Note (6) mA XC4VLX60 1.5 Note (6) mA XC4VLX80 1.5 Note (6) mA Note (6) XC4VLX100 1.75 mA Note (6) mA XC4VLX160 2.5 XC4VLX200 2.5 Note (6) mA Note (6) XC4VSX25 1.25 mA Note (6) mA XC4VSX35 1.25 XC4VSX55 1.5 Note (6) mA Note (6) XC4VFX12 1.25 mA Note (6) mA XC4VFX20 1.25 XC4VFX40 1.25 Note (6) mA Note (6) XC4VFX60 1.5 mA Note (6) mA XC4VFX100 1.75 XC4VFX140 2.5 Note (6) mA Note (6) I Quiescent V supply current XC4VLX15 31 mA CCAUXQ CCAUX Note (6) mA XC4VLX25 36 XC4VLX40 43 Note (6) mA Note (6) XC4VLX60 74 mA Note (6) mA XC4VLX80 83 XC4VLX100 95 Note (6) mA Note (6) XC4VLX160 133 mA Note (6) mA XC4VLX200 150 XC4VSX25 62 Note (6) mA Note (6) XC4VSX35 70 mA Note (6) mA XC4VSX55 91 XC4VFX12 31 Note (6) mA Note (6) XC4VFX20 35 mA Note (6) mA XC4VFX40 69 XC4VFX60 80 Note (6) mA Note (6) XC4VFX100 98 mA Note (6) mA XC4VFX140 143 (4) I Quiescent AVCCAUXRX supply current XC4VFX20 25 154 mA CCAUXRX XC4VFX60 35 154 mA XC4VFX100 50 154 mA DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 5 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 4: Quiescent Supply Current (Continued) (1) Symbol Description Device Typ Max Units (4) I XC4VFX20 10 44 mA Quiescent AVCCAUXTX supply current CCAUXTX XC4VFX60 15 44 mA XC4VFX100 20 44 mA (4,5) XC4VFX20 1 2 mA I Quiescent V supply current TTX TTX XC4VFX60 1 2 mA XC4VFX100 1 2 mA (4,5) XC4VFX20 1 2 mA I Quiescent V supply current TRX TRX XC4VFX60 1 2 mA XC4VFX100 1 2 mA (4) Quiescent V supply current XC4VFX20 1 2 mA I AUXMGT AUXMGT XC4VFX60 1 2 mA XC4VFX100 1 2 mA Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWER™ tool. 4. Given for entire die. Powered and unconfigured. 5. Unconnected (if channel is driven to voltage). 6. Use the XPower™ Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 6 R Virtex-4 Data Sheet: DC and Switching Characteristics Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current Table 5 shows the minimum current required by Virtex-4 during power-on to insure proper device initialization. The devices for proper power-on and configuration. actual current consumed depends on the power-on ramp If the current minimums shown in Table 5 are met, the rate of the power supply. device powers on properly after all three supplies have The power supplies can be turned on in any sequence, passed through their power-on reset threshold voltages. though the specifications shown in Table 5 are for the rec- Once initialized and configured, use the XPOWER™ tool to ommended power-on sequence of V , V , V . CCINT CCAUX CCO estimate current drain on these supplies. Xilinx does not specify the current for other power-on sequences. Table 5: Power-On Current for Virtex-4 Devices I I I CCINTMIN CCAUXMIN CCOMIN (1) (2) (1) (2) (1) (2) Device Typ Max Typ Max Typ Max Units XC4VLX15 110 750 60 100 50 75 mA XC4VLX25 160 1350 85 125 75 100 mA XC4VLX40 250 1500 110 150 75 105 mA XC4VLX60 300 1925 225 300 150 250 mA XC4VLX80 400 2550 280 350 150 275 mA XC4VLX100 500 3200 335 425 200 300 mA XC4VLX160 700 3700 500 600 250 400 mA XC4VLX200 850 3850 500 600 250 400 mA XC4VSX25 175 725 110 150 75 105 mA XC4VSX35 250 1350 165 200 100 150 mA XC4VSX55 400 2225 225 300 150 225 mA XC4VFX12 111 750 56 100 50 75 mA XC4VFX20 151 1100 56 100 75 125 mA XC4VFX40 244 1650 167 250 125 225 mA XC4VFX60 339 2250 222 350 150 275 mA XC4VFX100 511 3300 278 500 200 300 mA XC4VFX140 702 4250 500 825 250 375 mA Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. Maximum values are specified under worst-case process, voltage, and temperature conditions. Table 6: Power Supply Ramp Time Symbol Description Ramp Time Units V Internal supply voltage relative to GND 0.20 to 50.0 ms CCINT V Output drivers supply voltage relative to GND 0.20 to 50.0 ms CCO V Auxiliary supply voltage relative to GND 0.20 to 50.0 ms CCAUX DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 7 R Virtex-4 Data Sheet: DC and Switching Characteristics SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages. The selected standards are tested at a minimum V with IL IH CCO Values for I and I are guaranteed over the recom- the respective V and V voltage levels shown. Other OL OH OL OH mended operating conditions at the V and V test standards are sample tested. OL OH points. Only selected standards are tested. These are cho- sen to ensure that all standards meet their specifications. Table 7: Select IO DC Input and Output Levels V V V V I I IL IH OL OH OL OH IOSTANDARD Attribute V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL –0.2 0.8 2.0 3.45 0.4 2.4 Note(3) Note(3) LVCMOS33, –0.2 0.8 2.0 3.45 0.4 V –0.4 Note(3) Note(3) CCO LVDCI33 LVCMOS25, –0.3 0.7 1.7 V +0.3 0.4 V –0.4 Note(3) Note(3) CCO CCO LVDCI25 LVCMOS18, –0.3 35% V 65% V V +0.3 0.4 V –0.45 Note(4) Note(4) CCO CCO CCO CCO LVDCI18 LVCMOS15, –0.3 35% V 65% V V +0.3 0.4 V –0.45 Note(4) Note(4) CCO CCO CCO CCO LVDCI15 (5) PCI33_3 –0.2 30% V 50% V V 10% V 90% V 1.5 –0.5 CCO CCO CCO CCO CCO (5) PCI66_3 –0.2 30% V 50% V V 10% V 90% V 1.5 –0.5 CCO CCO CCO CCO CCO (5) PCI-X –0.2 35% V 50% V V 10% V 90% V 1.5 –0.5 CCO CCO CCO CCO CCO GTLP –0.3 V –0.1 V + 0.1 – 0.6 N/A 36 N/A REF REF GTL –0.3 V –0.05 V + 0.05 – 0.4 N/A 32 N/A REF REF (2) HSTL I –0.3 V –0.1 V +0.1 V +0.3 0.4 V –0.4 8 –8 REF REF CCO CCO (2) HSTL II –0.3 V –0.1 V +0.1 V +0.3 0.4 V – 0.4 16 –16 REF REF CCO CCO (2) HSTL III –0.3 V –0.1 V +0.1 V +0.3 0.4 V – 0.4 24 –8 REF REF CCO CCO (2) HSTL IV –0.3 V –0.1 V +0.1 V +0.3 0.4 V – 0.4 48 –8 REF REF CCO CCO 50% 50% (2) DIFF HSTL II –0.3 V +0.3 0.4 V –0.4 – – CCO CCO V –0.1 V +0.1 CCO CCO SSTL2 I –0.3 V –0.15 V +0.15 V +0.3 V –0.61 V + 0.61 8.1 –8.1 REF REF CCO TT TT SSTL2 II –0.3 V –0.15 V +0.15 V +0.3 V –0.81 V + 0.81 16.2 –16.2 REF REF CCO TT TT 50% 50% DIFF SSTL2 II –0.3 V +0.3 0.5 V –0.5 – – CCO CCO V –0.15 V +0.15 CCO CCO SSTL18 I –0.3 V – 0.125 V + 0.125 V +0.3 V –0.47 V + 0.47 6.7 –6.7 REF REF CCO TT TT SSTL18 II –0.3 V – 0.125 V +0.125 V +0.3 V –0.60 V + 0.60 13.4 –13.4 REF REF CCO TT TT 50% 50% DIFF SSTL18 II –0.3 V +0.3 0.4 V –0.4 – – CCO CCO V –0.125 V +0.125 CCO CCO Notes: 1. Tested according to relevant specifications. 2. Applies to both 1.5V and 1.8V HSTL. 3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 5. For more information on PCI33_3, PCI66_3, and PCIX refer to the Virtex-4 User Guide, SelectIO Resources, Chapter 6. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 8 R Virtex-4 Data Sheet: DC and Switching Characteristics LDT DC Specifications (LDT_25) Table 8: LDT DC Specifications Symbol DC Parameter Conditions Min Typ Max Units V Supply Voltage 2.38 2.5 2.63 V CCO (1,2) V Differential Output Voltage R = 100Ω across Q and Q signals 495 600 715 mV OD T Δ V Change in V Magnitude –15 15 mV OD OD V Output Common Mode Voltage R = 100Ω across Q and Q signals 495 600 715 mV OCM T Δ V Change in V Magnitude –15 15 mV OCM OCM V Input Differential Voltage 200 600 1000 mV ID Δ V Change in V Magnitude –15 15 mV ID ID V Input Common Mode Voltage 440 600 780 mV ICM Δ V Change in V Magnitude –15 15 mV ICM ICM Notes: 1. Recommended input maximum voltage not to exceed V +0.2V. CC0 2. Recommended input minimum voltage not to go below –0.5V. LVDS DC Specifications (LVDS_25) Table 9: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units V Supply Voltage 2.38 2.5 2.63 V CCO V Output High Voltage for Q and Q R = 100Ω across Q and Q signals 1.602 V OH T V Output Low Voltage for Q and Q R = 100Ω across Q and Q signals 0.898 V OL T (1,2) Differential Output Voltage V R = 100Ω across Q and Q signals 247 350 454 mV ODIFF T (Q – Q), Q = High (Q –Q), Q = High V Output Common-Mode Voltage R = 100Ω across Q and Q signals 1.125 1.250 1.375 V OCM T Differential Input Voltage (Q – Q), V 100 350 600 mV IDIFF Q = High (Q –Q), Q = High V Input Common-Mode Voltage 0.3 1.2 2.2 V ICM Notes: 1. Recommended input maximum voltage not to exceed V +0.2V. CC0 2. Recommended input minimum voltage not to go below –0.5V. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 9 R Virtex-4 Data Sheet: DC and Switching Characteristics Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units V Supply Voltage 2.38 2.5 2.63 V CCO V Output High Voltage for Q and Q R = 100Ω across Q and Q signals – – 1.785 V OH T V Output Low Voltage for Q and Q R = 100Ω across Q and Q signals 0.715 – – V OL T Differential Output Voltage (Q – Q), V R = 100Ω across Q and Q signals 440 – 820 mV ODIFF T Q = High (Q –Q), Q = High V Output Common-Mode Voltage R = 100Ω across Q and Q signals 1.125 1.250 1.375 V OCM T (1,2) Differential Input Voltage V Common-mode input voltage = 1.25V 100 – 1000 mV IDIFF (Q – Q), Q = High (Q –Q), Q = High V Input Common-Mode Voltage Differential input voltage = ±350 mV 0.3 1.2 2.2 V ICM Notes: 1. Recommended input maximum voltage not to exceed V +0.2V. CC0 2. Recommended input minimum voltage not to go below –0.5V. LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100Ω differential load mon-mode ranges. Table 11 summarizes the DC output only, i.e., a 100Ω resistor between the two receiver pins. specifications of LVPECL. For more information on using The V levels are 200 mV below standard LVPECL levels LVPECL, see the Virtex-4 User Guide: Chapter 6, SelectIO OH and are compatible with devices tolerant of lower com- Resources. Table 11: LVPECL DC Specifications Symbol DC Parameter Min Typ Max Units V Output High Voltage V – 1.025 1.545 V –0.88 V OH CC CC V Output Low Voltage V – 1.81 0.795 V –1.62 V OL CC CC V Input Common-Mode Voltage 0.6 2.2 V ICM (1,2) V Differential Input Voltage 0.100 1.5 V IDIFF Notes: 1. Recommended input maximum voltage not to exceed V +0.2V. CC0 2. Recommended input minimum voltage not to go below –0.5V. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 10 R Virtex-4 Data Sheet: DC and Switching Characteristics RocketIO DC Input and Output Levels Table 12 summarizes the DC input and output specifica- swing. Figure 2 shows the peak-to-peak differential output tions of the Virtex-4 RocketIO Multi-Gigabit Serial Trans- voltage. Consult the Virtex-4 RocketIO Multi-Gigabit Trans- ceivers. Figure 1 shows the single-ended output voltage ceiver User Guide for further details. Table 12: RocketIO DC Specifications DC Parameter Symbol Conditions Min Typ Max Units Peak-to-Peak Differential Input Voltage DV Internal AC Coupled 110 2400 mV IN Single-Ended Input Range SE Internal AC Coupled 0 V mV VIN TRX Internal AC Coupled 100 V –100 mV TRX Common Mode Input Voltage Range V ICM Bypassed Internal AC 800 mV (1) Coupled (2)(3) Single-Ended Output Voltage Swing V 450 725 mV OUT (3) Common Mode Output Voltage Range V 1000 mV TCM (2)(3) Peak-to-Peak Differential Output Voltage DV 900 1050 1400 mV PPOUT RX TBD Signal detect threshold RXOOB VDPP Electrical idle amplitude TXOOB TX 65 mV VDPP RocketIO MGT Clock DC Input Levels Peak-to-Peak Differential Input Voltage V 2 x | V – V | 100 600 2000 mV IDIFF MGTCLKP MGTCKLN Differential Input Resistance R 71 105 124 Ω IN Notes: 1. The maximum V is 1.26V when bypassing the internal AC coupled V . V must be less than or equal to AVCCAUXRX. TRX ICM TRX 2. The output swing and pre-emphasis levels are selected using the attributes discussed in Chapter 4: PMA Analog Considerations in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for details. 3. V is 1.5 ± 5%; different amplitudes possible with adjusted DAC values. TTX +V TXP DV OUT TXN 0 ds302_02_042105 Figure 1: Single-Ended Output Voltage Swing +V DV PPOUT 0 –V TXP–TXN ds302_03_042105 Figure 2: Peak-to-Peak Differential Output Voltage DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 11 R Virtex-4 Data Sheet: DC and Switching Characteristics Interface Performance Characteristics Table 13: Interface Performance Speed Grade Description -12 -11 -10 Networking Applications (1,2) SFI-4.1 (SDR LVDS Interface) 710 MHz 710 MHz 644 MHz (3) SPI-4.2 (DDR LVDS Interface) 1 Gb/s 1 Gb/s 800 Mb/s Memory Interfaces (8) DDR2 SDRAM (High-Performance SERDES Design) 600 Mb/s 533 Mb/s 500 Mb/s (5) DDR2 SDRAM (Low-Latency Direct Clocking Design) 420 Mb/s 410 Mb/s 400 Mb/s (6) QDR II SRAM (Low-Latency Direct Clocking Design) 550 Mb/s 500 Mb/s 400 Mb/s (4) DDR SDRAM (Low-Latency Direct Clocking Design) 344 Mb/s 336 Mb/s 330 Mb/s (7) RLDRAM II (Low-Latency Direct Clocking Design) 470 Mb/s 470 Mb/s 400 Mb/s Notes: 1. Input clocks above 622 MHz require AC coupling. See XAPP704, Virtex-4 High-Speed SDR LVDS Transceiver. 2. Performance defined using design implementation described in application note XAPP704,:Virtex-4 High-Speed SDR LVDS Transceiver. 3. Performance defined using design implementation described in application note XAPP700,:Dynamic Phase Alignment for Networking Applications or XAPP705, Virtex-4 High-Speed DDR LVDS Transceiver. 4. Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 FPGA Devices. 5. Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices. 6. Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices. 7. Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs. 8. Performance defined using design implementation described in application note XAPP721, High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES. Switching Characteristics Switching characteristics are specified on a per-speed- Table 14 correlates the current status of each Virtex-4 grade basis and can be designated as Advance, Prelimi- device with a corresponding speed specification version nary, or Production. Each designation is defined as follows: 1.65 designation. Advance Table 14: Virtex-4 Device Speed Grade Designations These specifications are based on simulations only and are Speed Grade Designations typically available soon after device design specifications Device Advance Preliminary Production are frozen. Although speed grades with this designation are XC4VLX15 -12, -11, -10 considered relatively stable and conservative, some XC4VLX25 -12, -11, -10 under-reporting might still occur. XC4VLX40 -12, -11, -10 Preliminary XC4VLX60 -12, -11, -10 These specifications are based on complete ES (engineer- XC4VLX80 -12, -11, -10 ing sample) silicon characterization. Devices and speed grades with this designation are intended to give a better XC4VLX100 -12, -11, -10 indication of the expected performance of production sili- XC4VLX160 -12, -11, -10 con. The probability of under-reporting delays is greatly XC4VLX200 -11, -10 reduced as compared to Advance data. XC4VSX25 -12, -11, -10 Production XC4VSX35 -12, -11, -10 These specifications are released once enough production XC4VSX55 -12, -11, -10 silicon of a particular device family member has been char- XC4VFX12 -12, -11, -10 acterized to provide full correlation between specifications XC4VFX20 -12, -11, -10 and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal XC4VFX40 -12, -11, -10 notification of any subsequent changes. Typically, the slow- XC4VFX60 -12, -11, -10 est speed grades transition to Production before faster XC4VFX100 -12 -11, -10 speed grades. XC4VFX140 -11, -10 DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 12 R Virtex-4 Data Sheet: DC and Switching Characteristics Since individual family members are produced at different All specifications are always representative of worst-case times, the migration from one category to another depends supply voltage and junction temperature conditions. completely on the status of the fabrication process for each device. Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing use the values reported by the static timing analyzer (TRCE parameters are derived from measuring internal test pat- in the Xilinx Development System) and back-annotate to the terns. Listed below are representative values. For more simulation net list. Unless otherwise noted, values apply to specific, more precise, and worst-case guaranteed data, all Virtex-4 devices. PowerPC Switching Characteristics Consult the PowerPC 405 Processor Block Reference Guide for further information. Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics Speed Grade -12 -11 -10 Description MinMax MinMax MinMax Units Characteristics when APU Not Used CPMC405CLOCK frequency 0 450 0 400 0 350 MHz (2) CPMDCRCLK 0450 0400 0350 MHz (2) CPMFCMCLK NA NA NA NA NA NA MHz (1) 0225 0200 0175 MHz JTAGC405TCK frequency (2) PLBCLK 0450 0400 0350 MHz (2) BRAMDSOCMCLK 0450 0400 0350 MHz (2) 0450 0400 0350 MHz BRAMISOCMCLK Characteristics when APU Used CPMC405CLOCK frequency 0 333 0 275 0 233 MHz (2) CPMDCRCLK 0333 0275 0233 MHz (2) 0333 0275 0233 MHz CPMFCMCLK (1) JTAGC405TCK frequency 0166.5 0137.5 0116.5 MHz (2) PLBCLK 0333 0275 0233 MHz (2) 0333 0275 0233 MHz BRAMDSOCMCLK (2) BRAMISOCMCLK 0333 0275 0233 MHz Notes: 1. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will be much less. 2. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent. 3. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 13 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 16: Processor Block Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (CPMC405CLOCK) T _CORECKI/ 0.60 0.65 0.74 PPCDCK Clock and Power Management control inputs ns Min T _CORECKI 0.20 0.20 0.23 PPCCKD T _RSTCHIP/ 0.60 0.65 0.74 PPCDCK Reset control inputs ns Min T _RSTCHIP 0.20 0.20 0.23 PPCCKD T _EXBUSHAK/ 0.60 0.65 0.74 PPCDCK Debug control inputs ns Min T _EXBUSHAK 0.20 0.20 0.23 PPCCKD T _TRCDIS/ 0.60 0.65 0.74 PPCDCK Trace control inputs ns Min T _TRCDIS 0.20 0.20 0.23 PPCCKD T _CINPIRQ/ 1.04 1.15 1.40 PPCDCK External Interrupt Controller control inputs ns Min T _CINPIRQ 0.20 0.20 0.23 PPCCKD Clock to Out Clock and Power Management control outputs T _CORESLP 1.35 1.51 1.74 ns Max PPCCKO Reset control outputs T _RSTCHIP 1.441.591.83 ns Max PPCCKO Debug control outputs T _DBGLDAPU 1.34 1.48 1.70 ns Max PPCCKO Trace control outputs T _TRCCYCLE 1.52 1.68 1.83 ns Max PPCCKO Clock CPMC405CLOCK minimum pulse width, High T 1.11 1.25 1.43 ns Min CPWH CPMC405CLOCK minimum pulse width, Low T 1.11 1.25 1.43 ns Min CPWL Table 17: Processor Block PLB Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (PLBCLK) T _ICUBUSY/ 0.60 0.66 0.76 PPCDCK Processor Local Bus (ICU/DCU) control inputs ns Min T _ICUBUSY 0.20 0.20 0.23 PPCCKD T _ICURDDB/ 0.90 1.00 1.15 PPCDCK Processor Local Bus (ICU/DCU) data inputs ns Min T _ICURDDB 0.20 0.20 0.23 PPCCKD Clock to Out Processor Local Bus (ICU/DCU) control outputs T _DCUABORT 1.61 1.78 2.05 ns Max PPCCKO Processor Local Bus (ICU/DCU) address bus outputs T _ICUABUS 1.66 1.85 2.13 ns Max PPCCKO Processor Local Bus (ICU/DCU) data bus outputs T _DCUWRDBUS 2.08 2.24 2.57 ns Max PPCCKO Table 18: Processor Block JTAG Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (JTAGC405TCK) T _JTGTDI 1.16 1.29 1.48 PPCDCK JTAG control inputs ns Min T _JTGTDI 0.20 0.20 0.23 PPCCKD T _JTGTRSTN 0.60 0.65 0.74 PPCDCK JTAG reset input ns Min T _JTGTRSTN 0.20 0.20 0.23 PPCCKD Clock to Out JTAG control outputs T _JTGTDO 1.681.792.14 ns Max PPCCKO DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 14 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (BRAMDSOCMCLK) T _DSOCMRDDB 0.60 0.65 0.74 PPCDCK Data-Side On-Chip Memory data bus inputs ns Min T _DSOCMRDDB 0.20 0.20 0.23 PPCCKD Clock to Out Data-Side On-Chip Memory control outputs T _BRAMBWR 2.07 2.30 2.65 ns Max PPCCKO Data-Side On-Chip Memory address bus outputs T _BRAMABUS 2.07 2.30 2.65 ns Max PPCCKO _IBRAMWRDBUS01 1.61 1.79 2.06 ns Max Data-Side On-Chip Memory data bus outputs T PPCCKO Table 20: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (BRAMISOCMCLK) T _ISOCMRDDB 0.74 0.82 0.94 PPCDCK Instruction-Side On-Chip Memory data bus inputs ns Min T _ISOCMRDDB 0.20 0.20 0.23 PPCCKD Clock to Out Instruction-Side On-Chip Memory control outputs T _IBRAMEN 3.04 3.37 3.88 ns Max PPCCKO Instruction-Side On-Chip Memory address bus outputs T _IBRAMRDABUS 1.67 1.85 2.13 ns Max PPCCKO _IBRAMWRDBUS 1.67 1.86 2.14 ns Max Instruction-Side On-Chip Memory data bus outputs T PPCCKO Table 21: Processor Block DCR Bus Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (CPMDCRCLOCK) T _EXDCRACK 0.12 0.13 0.15 PPCDCK Device Control Register Bus control inputs ns Min T _EXDCRACK 0.15 0.17 0.19 PPCCKD _EXDCRDBUSI 0.57 0.57 1.02 T PPCDCK Device Control Register Bus data inputs ns Min T _EXDCRDBUSI 0.16 0.16 0.27 PPCCKD Clock to Out Device Control Register Bus control outputs T _EXDCRRD 1.20 1.35 1.54 ns Max PPCCKO Device Control Register Bus address bus outputs T _EXDCRABUS 1.28 1.45 1.66 ns Max PPCCKO Device Control Register Bus data bus outputs T _EXDCRDBUSO 1.31 1.45 1.67 ns Max PPCCKO DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 15 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 22: Processor Block APU Interface Switching Characteristics Speed Grade Description Symbol -12 -11 -10 Units Setup and Hold Relative to Clock (CPMDFCMCLOCK) T _DCDCREN 0.33 0.36 0.42 PPCDCK APU bus control inputs ns Min T _DCDCREN 0.20 0.20 0.23 PPCCKD T _RESULT 0.61 0.67 0.78 PPCDCK APU bus data inputs ns Min T _RESULT 0.20 0.20 0.23 PPCCKD Clock to Out APU bus control outputs T _APUFCMDEC 1.53 1.75 2.00 ns Max PPCCKO APU bus data outputs T _RADATA 1.53 1.75 2.00 ns Max PPCCKO RocketIO Switching Characteristics Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information. Table 23: Maximum RocketIO Transceiver Performance Speed Grade Description -12 -11 -10 Units RocketIO Transceiver 6.5 6.5 3.125 Gb/s Table 24: RocketIO Reference Clock Switching Characteristics All Speed Grades Description Symbol Conditions Min Typ Max Units (1) Reference Clock frequency range F CLK 106 644 MHz GCLK (1) GREFCLK Reference Clock frequency range F CLK 106 320 MHz GREFCLK Reference Clock frequency tolerance F CLK –350 +350 ppm GTOL Reference Clock rise time T 20% – 80% 400 ps RCLK Reference Clock fall time T 20% – 80% 400 ps FCLK Reference Clock duty cycle T CLK 45 55 % DCREF (2) Reference Clock total jitter, peak-peak T CLK 40 ps GJTT Initial lock of the PLL from Clock recovery frequency acquisition time T 1ms LOCK startup (programmable) Lock to data after PLL has relocked to the reference clock. Clock recovery phase acquisition time T PHASE Includes lock to reference time (programmable) (3) Spread Spectrum Clocking 0% to –0.5% 30 33 kHz Notes: 1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval. 3. Tested with synchronous reference clock. T RCLK 80% 20% T FCLK ds302_04_042205 Figure 3: Reference Clock Timing Parameters DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 16 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 25: RocketIO Receiver Switching Characteristics Description Symbol Conditions Min Typ Max Units Serial data rate, -10 F 0.622 3.125 Gb/s GRX Serial data rate, -11 F 0.622 6.5 Gb/s GRX (2) (3) XAUI Receive Jitter Tolerance (8B/10B CJPAT) Rate (Gb/s) Mode Frequency Receive Deterministic Jitter Tolerance T 3.125 ACDR 0.37 DJTOL (6) Receive Total Jitter Tolerance T 3.125 ACDR 0.65 TJTOL (1) 3.125 ACDR f = 22.1 kHz 8.5 UI (7) Receive Sinusoidal Jitter Tolerance T 3.125 ACDR f = 1.875 MHz 0.10 SJTOL 3.125 ACDR f = 20 MHz 0.10 (3) General Receive Jitter Tolerance Rate (Gb/s) Mode Pattern (5) 6.5 ACDR PRBS7 0.65 (5) 5.0 ACDR PRBS7 0.65 (5) 4.25 ACDR PRBS7 0.65 3.125 ACDR PRBS7 0.60 (2,4) Receive deterministic jitter tolerance T 2.5 ACDR PRBS7 0.55 DJTOL 1.25 ACDR PRBS7 0.50 1.25 DCDR PRBS7 0.50 1.25 DCDR PRBS31 0.40 0.622 DCDR PRBS31 0.40 (1) UI (9) 6.5 ACDR PRBS7 0.65 (9) 5.0 ACDR PRBS7 0.65 (9) 4.25 ACDR PRBS7 0.65 (8) 3.125 ACDR PRBS7 0.50 (8) Sinusoidal jitter tolerance T 2.5 ACDR PRBS7 0.50 SJTOL (8) 1.25 ACDR PRBS7 0.50 (8) 1.25 DCDR PRBS7 0.55 (8) 1.25 DCDR PRBS31 0.35 (8) 0.622 DCDR PRBS31 0.55 RXUSRCLK frequency T For slower speed grades = MaxDataRate/32 250 MHz RX RXUSRCLK2 frequency T 250 MHz RX2 RXUSRCLK duty cycle T 40 60 % RXDC RXUSRCLK2 duty cycle T 40 60 % RX2DC Differential input skew T 20 ps ISKEW (2) Differential receive input sensitivity V 110 mV EYE On-chip AC coupling corner frequency Signal detect response time RXSIGDET 30 Responsetime Input capacitance at the Die C fF DIE Excess capacitance at the solder ball C fF BALL 6. Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter Notes: as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5. 1. UI = Unit Interval 7. SJ in addition to 0.55 UI of DJ +RJ. 2. Using receiver equalization setting of 111 (14 dB). 8. Jitter frequency = 5 MHz. 3. ACDR = Analog CDR and DCDR = Digital CDR. 9. Jitter frequency = 10 MHz. 4. Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency sinusoidal jitter (SJ). 5. Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ + 0.15 UI of RJ. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 17 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 26: RocketIO Transmitter Switching Characteristics Description Symbol Conditions Min Typ Max Units Serial data rate, -10 F 0.622 3.125 Gb/s GTX Serial data rate, -11 F 0.622 6.5 Gb/s GTX Data Rate (Gb/s) 0.50 TJ RJ PRBS7 6.5 0.35 0.30 DJ 0.45 TJ RJ PRBS7 5.0 0.30 0.25 DJ 0.40 TJ RJ PRBS7 4.25 0.25 0.21 DJ 0.28 TJ (3) (1) TX Jitter Generation RJ PRBS7 3.125 0.14 UI 0.14 DJ 0.25 TJ RJ PRBS7 2.5 0.18 0.12 DJ 0.12 TJ RJ PRBS7 1.25 0.10 0.06 DJ 0.08 TJ RJ PRBS31 0.622 0.06 0.04 DJ (2) TX rise time T 20% – 80% 90 ps RTX (2) TX fall time T 20% – 80% 90 ps FTX For slower speed grades = TXUSRCLK frequency 250 MHz MaxDataRate/32 TXUSRCLK2 frequency 250 MHz TXUSRCLK duty cycle T 40 60 % TXDC TXUSRCLK2 duty cycle T 40 60 % TX2DC Differential output skew T 12 20 ps ISKEW Electrical idle transition time TXOOB 15 ns Transition Notes: 1. UI = Unit Interval. 2. Default attributes, measured at 2.5 Gb/s. 3. Peak-to-Peak values measured relative to 1e-12 Error rate. Default attributes. TX feedback divider (TXPLLNDIVSEL) = 10. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 18 R Virtex-4 Data Sheet: DC and Switching Characteristics IOB Pad Input/Output/3-State Switching Characteristics Table 27 summarizes the values of standard-specific data T is described as the delay from the T pin to the IOB IOTP input delay adjustments, output delays terminating at pads pad through the output buffer of an IOB pad, when 3-state is (based on standard and 3-state delays. disabled. The delay varies depending on the SelectIO capa- bility of the output buffer. T is described as the delay from IOB pad through the IOPI input buffer to the I-pin of an IOB pad. The delay varies Table 28 summarizes the value of T . T is IOTPHZ IOTPHZ depending on the capability of the SelectIO input buffer. described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is T is described as the delay from the O pin to the IOB IOOP enabled (i.e., a high impedance state). pad through the output buffer of an IOB pad. The delay var- ies depending on the capability of the SelectIO output buffer. (1,2) Table 27: IOB Switching Characteristics T T T IOPI IOOP IOTP IOSTANDARD Speed Grade Speed Grade Speed Grade Units (1) Attribute -12 -11 -10 -12 -11 -10 -12 -11 -10 LVDS_25 1.00 1.15 1.28 1.61 1.71 1.85 1.61 1.71 1.85 ns RSDS_25 1.00 1.15 1.28 1.61 1.71 1.85 1.61 1.71 1.85 ns LVDSEXT_25 1.01 1.16 1.30 1.65 1.75 1.91 1.65 1.75 1.91 ns LDT_25 1.00 1.15 1.28 1.58 1.68 1.82 1.58 1.68 1.82 ns BLVDS_25 1.00 1.15 1.28 1.99 2.15 2.34 1.99 2.15 2.34 ns ULVDS_25 1.00 1.15 1.28 1.59 1.68 1.83 1.59 1.68 1.83 ns PCI33_3 0.76 0.87 0.97 2.52 2.76 3.02 2.52 2.76 3.02 ns (PCI, 33 MHz, 3.3V) PCI66_3 0.76 0.87 0.97 2.22 2.46 2.72 2.22 2.46 2.72 ns (PCI, 66 MHz, 3.3V) PCI-X 0.76 0.87 0.97 2.19 2.21 2.25 2.19 2.21 2.25 ns GTL 1.28 1.47 1.63 1.75 1.87 2.03 1.75 1.87 2.03 ns GTLP 1.31 1.51 1.68 1.75 1.87 2.03 1.75 1.87 2.03 ns HSTL_I 1.28 1.47 1.64 2.00 2.16 2.35 2.00 2.16 2.35 ns HSTL_II 1.28 1.47 1.64 1.83 1.96 2.13 1.83 1.96 2.13 ns HSTL_III 1.28 1.47 1.64 1.90 2.04 2.22 1.90 2.04 2.22 ns HSTL_IV 1.28 1.47 1.64 1.75 1.87 2.03 1.75 1.87 2.03 ns HSTL_I _18 1.26 1.44 1.60 1.89 2.03 2.21 1.89 2.03 2.21 ns HSTL_II _18 1.26 1.44 1.60 1.85 1.98 2.16 1.85 1.98 2.16 ns HSTL_III _18 1.26 1.44 1.60 1.80 1.93 2.09 1.80 1.93 2.09 ns HSTL_IV_18 1.26 1.44 1.60 1.77 1.89 2.06 1.77 1.89 2.06 ns SSTL2_I 1.31 1.51 1.68 2.06 2.23 2.43 2.06 2.23 2.43 ns SSTL2_II 1.31 1.51 1.68 1.85 1.98 2.16 1.85 1.98 2.16 ns LVTTL, Slow, 2 mA 0.76 0.87 0.97 5.66 6.37 7.03 5.66 6.37 7.03 ns LVTTL, Slow, 4 mA 0.76 0.87 0.97 4.10 4.57 5.04 4.10 4.57 5.04 ns LVTTL, Slow, 6 mA 0.76 0.87 0.97 4.00 4.46 4.91 4.00 4.46 4.91 ns LVTTL, Slow, 8 mA 0.76 0.87 0.97 4.00 4.46 4.91 4.00 4.46 4.91 ns DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 19 R Virtex-4 Data Sheet: DC and Switching Characteristics (1,2) Table 27: IOB Switching Characteristics (Continued) T T T IOPI IOOP IOTP IOSTANDARD Speed Grade Speed Grade Speed Grade Units (1) Attribute -12 -11 -10 -12 -11 -10 -12 -11 -10 LVTTL, Slow, 12 mA 0.76 0.87 0.97 3.26 3.61 3.96 3.26 3.61 3.96 ns LVTTL, Slow, 16 mA 0.76 0.87 0.97 2.87 3.16 3.46 2.87 3.16 3.46 ns LVTTL, Slow, 24 mA 0.76 0.87 0.97 2.60 2.85 3.12 2.60 2.85 3.12 ns LVTTL, Fast, 2 mA 0.76 0.87 0.97 3.96 4.41 4.86 3.96 4.41 4.86 ns LVTTL, Fast, 4 mA 0.76 0.87 0.97 2.87 3.16 3.46 2.87 3.16 3.46 ns LVTTL, Fast, 6 mA 0.76 0.87 0.97 2.51 2.74 3.00 2.51 2.74 3.00 ns LVTTL, Fast, 8 mA 0.76 0.87 0.97 2.34 2.55 2.79 2.34 2.55 2.79 ns LVTTL, Fast, 12 mA 0.76 0.87 0.97 2.09 2.26 2.47 2.09 2.26 2.47 ns LVTTL, Fast, 16 mA 0.76 0.87 0.97 2.09 2.26 2.47 2.09 2.26 2.47 ns LVTTL, Fast, 24 mA 0.76 0.87 0.97 1.88 2.02 2.20 1.88 2.02 2.20 ns LVCMOS33, Slow, 2 mA 0.76 0.87 0.97 6.98 7.88 8.73 6.98 7.88 8.73 ns LVCMOS33, Slow, 4 mA 0.76 0.87 0.97 4.92 5.52 6.09 4.92 5.52 6.09 ns LVCMOS33, Slow, 6 mA 0.76 0.87 0.97 4.07 4.54 5.00 4.07 4.54 5.00 ns LVCMOS33, Slow, 8 mA 0.76 0.87 0.97 3.25 3.59 3.95 3.25 3.59 3.95 ns LVCMOS33, Slow, 12 mA 0.76 0.87 0.97 2.83 3.11 3.42 2.83 3.11 3.42 ns LVCMOS33, Slow, 16 mA 0.76 0.87 0.97 2.11 2.28 2.49 2.11 2.28 2.49 ns LVCMOS33, Slow, 24 mA 0.76 0.87 0.97 2.11 2.28 2.49 2.11 2.28 2.49 ns LVCMOS33, Fast, 2 mA 0.76 0.87 0.97 5.98 6.73 7.44 5.98 6.73 7.44 ns LVCMOS33, Fast, 4 mA 0.76 0.87 0.97 3.55 3.93 4.33 3.55 3.93 4.33 ns LVCMOS33, Fast, 6 mA 0.76 0.87 0.97 2.93 3.23 3.55 2.93 3.23 3.55 ns LVCMOS33, Fast, 8 mA 0.76 0.87 0.97 2.09 2.25 2.46 2.09 2.25 2.46 ns LVCMOS33, Fast, 12 mA 0.76 0.87 0.97 1.93 2.08 2.27 1.93 2.08 2.27 ns LVCMOS33, Fast, 16 mA 0.76 0.87 0.97 1.79 1.91 2.08 1.79 1.91 2.08 ns LVCMOS33, Fast, 24 mA 0.76 0.87 0.97 1.79 1.91 2.08 1.79 1.91 2.08 ns LVCMOS25, Slow, 2 mA 0.69 0.80 0.88 4.77 5.34 5.89 4.77 5.34 5.89 ns LVCMOS25, Slow, 4 mA 0.69 0.80 0.88 4.09 4.56 5.02 4.09 4.56 5.02 ns LVCMOS25, Slow, 6 mA 0.69 0.80 0.88 3.53 3.92 4.31 3.53 3.92 4.31 ns LVCMOS25, Slow, 8 mA 0.69 0.80 0.88 3.53 3.92 4.31 3.53 3.92 4.31 ns LVCMOS25, Slow, 12 mA 0.69 0.80 0.88 2.90 3.19 3.50 2.90 3.19 3.50 ns LVCMOS25, Slow, 16 mA 0.69 0.80 0.88 2.75 3.02 3.31 2.75 2.02 3.31 ns LVCMOS25, Slow, 24 mA 0.69 0.80 0.88 2.33 2.54 2.77 2.33 2.54 2.77 ns LVCMOS25, Fast, 2 mA 0.69 0.80 0.88 3.20 3.54 3.89 3.20 3.54 3.89 ns LVCMOS25, Fast, 4 mA 0.69 0.80 0.88 2.66 2.92 3.19 2.66 2.92 3.19 ns LVCMOS25, Fast, 6 mA 0.69 0.80 0.88 2.36 2.57 2.81 2.36 2.57 2.81 ns LVCMOS25, Fast, 8 mA 0.69 0.80 0.88 2.13 2.31 2.52 2.13 2.31 2.52 ns LVCMOS25, Fast, 12 mA 0.69 0.80 0.88 2.06 2.23 2.43 2.06 2.23 2.43 ns DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 20 R Virtex-4 Data Sheet: DC and Switching Characteristics (1,2) Table 27: IOB Switching Characteristics (Continued) T T T IOPI IOOP IOTP IOSTANDARD Speed Grade Speed Grade Speed Grade Units (1) Attribute -12 -11 -10 -12 -11 -10 -12 -11 -10 LVCMOS25, Fast, 16 mA 0.69 0.80 0.88 1.89 2.03 2.21 1.89 2.03 2.21 ns LVCMOS25, Fast, 24 mA 0.69 0.80 0.88 1.83 1.96 2.13 1.83 1.96 2.13 ns LVCMOS18, Slow, 2 mA 0.97 1.12 1.25 4.77 5.34 5.89 4.77 5.34 5.89 ns LVCMOS18, Slow, 4 mA 0.97 1.12 1.25 3.56 3.95 4.35 3.56 3.95 4.35 ns LVCMOS18, Slow, 6 mA 0.97 1.12 1.25 3.29 3.64 4.00 3.29 3.64 4.00 ns LVCMOS18, Slow, 8 mA 0.97 1.12 1.25 3.10 3.42 3.76 3.10 3.42 3.76 ns LVCMOS18, Slow, 12 mA 0.97 1.12 1.25 3.09 3.41 3.74 3.09 3.41 3.74 ns LVCMOS18, Slow, 16 mA 0.97 1.12 1.25 2.94 3.24 3.55 2.94 3.24 3.55 ns LVCMOS18, Fast, 2 mA 0.97 1.12 1.25 3.20 3.54 3.89 3.20 3.54 3.89 ns LVCMOS18, Fast, 4 mA 0.97 1.12 1.25 2.52 2.75 3.02 2.52 2.75 3.02 ns LVCMOS18, Fast, 6 mA 0.97 1.12 1.25 2.29 2.49 2.72 2.29 2.49 2.72 ns LVCMOS18, Fast, 8 mA 0.97 1.12 1.25 2.13 2.31 2.52 2.13 2.31 2.52 ns LVCMOS18, Fast, 12 mA 0.97 1.12 1.25 2.01 2.17 2.36 2.01 2.17 2.36 ns LVCMOS18, Fast, 16 mA 0.97 1.12 1.25 1.94 2.09 2.27 1.94 2.09 2.27 ns LVCMOS15, Slow, 2 mA 1.05 1.20 1.34 5.33 5.99 6.61 5.33 5.99 6.61 ns LVCMOS15, Slow, 4 mA 1.05 1.20 1.34 4.21 4.70 4.88 4.21 4.70 4.88 ns LVCMOS15, Slow, 6 mA 1.05 1.20 1.34 3.49 3.87 4.26 3.49 3.87 4.26 ns LVCMOS15, Slow, 8 mA 1.05 1.20 1.34 3.49 3.87 4.26 3.49 3.87 4.26 ns LVCMOS15, Slow, 12 mA 1.05 1.20 1.34 3.11 3.43 3.77 3.11 3.43 3.77 ns LVCMOS15, Slow, 16 mA 1.05 1.20 1.34 2.92 3.21 3.53 2.92 3.21 3.53 ns LVCMOS15, Fast, 2 mA 1.05 1.20 1.34 3.42 3.79 4.17 3.42 3.79 4.17 ns LVCMOS15, Fast, 4 mA 1.05 1.20 1.34 2.76 3.03 3.32 2.76 3.03 3.32 ns LVCMOS15, Fast, 6 mA 1.05 1.20 1.34 2.46 2.69 2.94 2.46 2.69 2.94 ns LVCMOS15, Fast, 8 mA 1.05 1.20 1.34 2.28 2.48 2.71 2.28 2.48 2.71 ns LVCMOS15, Fast, 12 mA 1.05 1.20 1.34 2.12 2.29 2.50 2.12 2.29 2.50 ns LVCMOS15, Fast, 16 mA 1.05 1.20 1.34 2.06 2.23 2.43 2.06 2.23 2.43 ns LVDCI_33 0.76 0.87 0.97 2.61 2.86 3.13 2.61 2.86 3.13 ns LVDCI_25 0.69 0.80 0.88 2.52 2.76 3.02 2.52 2.76 3.02 ns LVDCI_18 0.97 1.12 1.25 2.47 2.69 2.95 2.47 2.69 2.95 ns LVDCI_15 1.05 1.20 1.34 2.45 2.68 2.93 2.45 2.68 2.93 ns LVDCI_DV2_25 0.69 0.80 0.88 1.93 2.08 2.27 1.93 2.08 2.27 ns LVDCI_DV2_18 0.97 1.12 1.25 1.95 2.09 2.28 1.95 2.09 2.28 ns LVDCI_DV2_15 1.05 1.20 1.34 2.18 2.36 2.58 2.18 2.36 2.58 ns GTL_DCI 1.18 1.36 1.51 1.75 1.87 2.03 1.75 1.87 2.03 ns GTLP_DCI 0.96 1.11 1.23 1.75 1.87 2.03 1.75 1.87 2.03 ns HSTL_I_DCI 1.28 1.47 1.64 2.00 2.16 2.35 2.00 2.16 2.35 ns DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 21 R Virtex-4 Data Sheet: DC and Switching Characteristics (1,2) Table 27: IOB Switching Characteristics (Continued) T T T IOPI IOOP IOTP IOSTANDARD Speed Grade Speed Grade Speed Grade Units (1) Attribute -12 -11 -10 -12 -11 -10 -12 -11 -10 HSTL_II_DCI 1.28 1.47 1.64 1.83 1.96 2.13 1.83 1.96 2.13 ns HSTL_III_DCI 1.28 1.47 1.64 1.90 2.04 2.22 1.90 2.04 2.22 ns HSTL_IV_DCI 1.28 1.47 1.64 1.75 1.87 2.03 1.75 1.87 2.03 ns HSTL_I_DCI_18 1.26 1.44 1.60 1.89 2.03 2.21 1.89 2.03 2.21 ns HSTL_II_DCI_18 1.26 1.44 1.60 1.85 1.98 2.16 1.85 1.98 2.16 ns HSTL_III_DCI_18 1.26 1.44 1.60 1.80 1.93 2.09 1.80 1.93 2.09 ns HSTL_IV_DCI_18 1.26 1.44 1.60 1.77 1.89 2.06 1.77 1.89 2.06 ns SSTL2_I_DCI 1.31 1.51 1.68 2.09 2.25 2.46 2.09 2.25 2.46 ns SSTL2_II_DCI 1.31 1.51 1.68 2.07 2.24 2.45 2.07 2.24 2.45 ns LVPECL_25 1.38 1.59 1.77 1.52 1.61 1.74 1.52 1.61 1.74 ns SSTL18_I 1.31 1.51 1.68 2.15 2.33 2.54 2.15 2.33 2.54 ns SSTL18_II 1.31 1.51 1.68 1.92 2.06 2.24 1.92 2.06 2.24 ns SSTL18_I_DCI 1.31 1.51 1.68 1.97 2.12 2.32 1.97 2.12 2.32 ns SSTL18_II_DCI 1.31 1.51 1.68 1.87 2.00 2.18 1.87 2.00 2.18 ns Notes: 1. The I/O standard is selected in the Xilinx ISE™ software tool using the IOSTANDARD attribute. 2. All I/O timing specifications are measured with V at –5% from nominal. CCO Table 28: IOB 3-state ON Output Switching Characteristics (T ) IOTPHZ Speed Grade Symbol Description -12 -11 -10 Units T T input to Pad high-impedance 0.88 1.01 1.12 ns IOTPHZ DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 22 R Virtex-4 Data Sheet: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 29: ILOGIC Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Setup/Hold 0.58 0.66 0.79 T / T CE1 pin Setup/Hold with respect to CLK ns ICE1CK ICKCE1 –0.23 –0.23 –0.23 0.16 0.19 0.23 T / T DLYCE pin Setup/Hold with respect to C ns ICECK ICKCE 0.11 0.13 0.16 –0.03 –0.02 –0.02 T / T DLYRST pin Setup/Hold with respect to C ns IRSTCK ICKRST 0.37 0.45 0.54 0.01 0.01 0.01 T / T DLYINC pin Setup/Hold with respect to C ns IINCCK ICKINC 0.36 0.43 0.51 1.15 1.33 1.59 T / T SR/REV pin Setup/Hold with respect to CLK ns ISRCK ICKSR –0.56 –0.56 –0.56 0.24 0.28 0.34 T / T D pin Setup/Hold with respect to CLK without Delay ns IDOCK IOCKD –0.10 –0.10 –0.10 D pin Setup/Hold with respect to CLK 6.64 7.63 8.84 ns (IOBDELAY_TYPE = DEFAULT) –5.99 –5.99 –5.99 T / T IDOCKD IOCKDD D pin Setup/Hold with respect to CLK 0.81 0.87 1.09 ns (1) (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) –0.63 –0.63 –0.63 Combinatorial T D pin to O pin propagation delay, no Delay 0.17 0.20 0.24 ns IDI D pin to O pin propagation delay 6.00 6.91 7.96 ns (IOBDELAY_TYPE = DEFAULT) T IDID D pin to O pin propagation delay 0.74 0.79 0.99 ns (1) (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) Sequential Delays T D pin to Q1 pin using flip-flop as a latch without Delay 0.50 0.59 0.71 ns IDLO D pin to Q1 pin using flip-flop as a latch 6.90 7.94 9.21 ns (IOBDELAY_TYPE = DEFAULT) T IDLOD D pin to Q1 pin using flip-flop as a latch 1.07 1.18 1.45 ns (1) (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) T CLK to Q outputs 0.53 0.60 0.72 ns ICKQ T CE1 pin to Q1 using flip-flop as a latch, propagation delay 0.90 1.06 1.27 ns ICE1Q SR/REV pin to OQ/TQ out 1.70 2.03 2.44 ns T RQ T Global Set/Reset to Q outputs 1.54 1.73 2.03 ns GSRQ Set/Reset ns, T Minimum Pulse Width, SR/REV inputs 0.53 0.59 0.70 RPW Min Notes: 1. Recorded at 0 tap value. Refer to Timing Report for other values. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 23 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 30: OLOGIC Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Setup/Hold 0.52 0.62 0.75 T / T D1/D2 pins Setup/Hold with respect to CLK ns ODCK OCKD –0.22 –0.22 –0.22 0.53 0.64 0.77 T / T OCE pin Setup/Hold with respect to CLK ns OOCECK OCKOCE –0.33 –0.33 –0.33 0.99 1.18 1.42 T / T SR/REV pin Setup/Hold with respect to CLK ns OSRCK OCKSR –0.55 –0.55 –0.55 0.52 0.62 0.75 T / T T1/T2 pins Setup/Hold with respect to CLK ns OTCK OCKT –0.22 –0.22 –0.22 0.53 0.64 0.77 T / T TCE pin Setup/Hold with respect to CLK ns OTCECK OCKTCE –0.33 –0.33 –0.33 Combinatorial D1 to OQ out 0.56 0.65 0.76 ns T ODQ T T1 to TQ out 0.56 0.65 0.76 ns OTQ Sequential Delays T REV pin to TQ out 1.14 1.37 1.64 ns IOSRON T CLK to OQ/TQ out 0.41 0.49 0.59 ns OCKQ T SR/REV pin to OQ/TQ out 1.14 1.37 1.64 ns RQ Global Set/Reset to Q outputs 1.54 1.73 2.03 ns T GSRQ Set/Reset T Minimum Pulse Width, SR/REV inputs 0.53 0.59 0.70 ns Min RPW DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 24 R Virtex-4 Data Sheet: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 31: ISERDES Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Setup/Hold for Control Lines 0.28 0.34 0.40 T / T BITSLIP pin Setup/Hold with respect to CLKDIV ns ISCCK_BITSLIP ISCKC_BITSLIP –0.20 –0.16 –0.13 0.48 0.57 0.69 (2) T / T CE pin Setup/Hold with respect to CLK (for CE1) ns ISCCK_CE ISCKC_CE –0.37 –0.30 –0.25 0.11 0.14 0.16 (2) T / T CE pin Setup/Hold with respect to CLKDIV (for CE2) ns ISCCK_CE2 ISCKC_CE2 –0.04 –0.03 –0.02 0.16 0.19 0.23 T / T DLYCE pin Setup/Hold with respect to CLKDIV ns ISCCK_DLYCE ISCKC_DLYCE 0.11 0.13 0.16 0.01 0.01 0.01 T / T DLYINC pin Setup/Hold with respect to CLKDIV ns ISCCK_DLYINC ISCKC_DLYINC 0.36 0.43 0.51 –0.03 –0.02 –0.02 T / T DLYRST pin Setup/Hold with respect to CLKDIV ns ISCCK_DLYRST ISCKC_DLYRST 0.37 0.45 0.54 T SR pin Setup with respect to CLKDIV 0.64 0.77 0.92 ns ISCCK_SR Setup/Hold for Data Lines D pin Setup/Hold with respect to CLK 0.24 0.28 0.34 ns (IOBDELAY = IBUF or NONE) –0.11 –0.11 –0.11 D pin Setup/Hold with respect to CLK 6.64 7.63 8.84 (IOBDELAY = IFD or BOTH, ns T / T –6.51 –6.51 –6.51 ISDCK_D ISCKD_D IOBDELAY_TYPE = DEFAULT) (1) D pin Setup/Hold with respect to CLK 0.81 0.87 1.08 (IOBDELAY = IFD or BOTH, ns –0.68 –0.68 –0.68 IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) D pin Setup/Hold with respect to CLK at DDR mode 0.24 0.28 0.34 ns (IOBDELAY = IBUF or NONE) –0.11 –0.11 –0.11 D pin Setup/Hold with respect to CLK at DDR mode 6.64 7.63 8.84 (IOBDELAY = IFD or BOTH, ns T / T –6.51 –6.51 –6.51 ISDCK_DDR ISCKD_DDR IOBDELAY_TYPE = DEFAULT) (1) D pin Setup/Hold with respect to CLK at DDR mode 0.81 0.87 1.08 (IOBDELAY = IFD or BOTH, ns –0.68 –0.68 –0.68 IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) Sequential Delays T CLKDIV to out at Q pin 0.59 0.71 0.85 ns ISCKO_Q Propagation Delays T D input to DO output pin (IOBDELAY = IFD) 0.17 0.20 0.24 ns ISDO_DO_IOBDELAY_IFD T D input to DO output pin (IOBDELAY = NONE) 0.17 0.20 0.24 ns ISDO_DO_IOBDELAY_NONE D input to DO output pin (IOBDELAY = BOTH, 6.00 6.91 7.96 ns IOBDELAY_TYPE = DEFAULT) T ISDO_DO_IOBDELAY_BOTH (1) D input to DO output pin (IOBDELAY = BOTH, 0.74 0.79 0.99 ns IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) D input to DO output pin (IOBDELAY = IBUF, 6.00 6.91 7.96 ns IOBDELAY_TYPE = DEFAULT) T ISDO_DO_IOBDELAY_IBUF (1) D input to DO output pin (IOBDELAY = IBUF, 0.74 0.79 0.99 ns IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) Notes: 1. Recorded at 0 tap value. Refer to Timing Report for other values. 2. T and T are reported as T / T in TRCE report. ISCCK_CE2 ISCKC_CE2 ISCCK_CE ISCKC_CE DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 25 R Virtex-4 Data Sheet: DC and Switching Characteristics Input Delay Switching Characteristics Table 32: Input Delay Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units T IDELAY Chain Delay Resolution 75 75 75 ps IDELAYRESOLUTION [(tap − 1) x 75 + 34] (2) T Cumulative delay at a given tap ps IDELAYTOTAL_ERR ± 0.07[(tap − 1) x 75 + 34] Reset to Ready for IDELAYCTRL T 3.00 3.00 3.00 µs IDELAYCTRLCO_RDY (Maximum) F REFCLK frequency 200 200 200 MHz IDELAYCTRL_REF (3) IDELAYCTRL_REF_PRECISION REFCLK precision ±10 ±10 ±10 MHz T Minimum Reset pulse width 50.0 50.0 50.0 ns IDELAYCTRL_RPW Pattern dependent period jitter in delay 00 0 Note (4) chain for clock pattern T IDELAYPAT_JIT Pattern dependent period jitter in delay 10 ± 2 10 ± 2 10 ± 2 Note (4) chain for random data pattern (PRBS 23) Notes: 1. Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics. 2. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps. 3. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 User Guide: Chapter 7, SelectIO Logic Resources. 4. Units in ps peak-to-peak per tap. Output Serializer/Deserializer Switching Characteristics Table 33: OSERDES Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Setup/Hold 0.35 0.42 0.50 T / T D input Setup/Hold with respect to CLKDIV ns OSDCK_D OSCKD_D –0.05 –0.04 –0.03 0.43 0.52 0.62 (1) T / T T input Setup/Hold with respect to CLK ns OSDCK_T OSCKD_T –0.16 –0.16 –0.16 0.35 0.42 0.50 (1) T / T T input Setup/Hold with respect to CLKDIV ns OSDCK_T2 OSCKD_T2 –0.05 –0.04 –0.03 0.45 0.53 0.64 T / T OCE input Setup/Hold with respect to CLK ns OSCCK_OCE OSCKC_OCE 0.01 0.02 0.03 T SR (Reset) input Setup with respect to CLKDIV 0.67 0.80 0.96 ns OSCCK_S 0.45 0.53 0.64 T / T TCE input Setup/Hold with respect to CLK ns OSCCK_TCE OSCKC_TCE 0.01 0.02 0.03 Sequential Delays T Clock to out from CLK to OQ 0.41 0.49 0.59 ns OSCKO_OQ T Clock to out from CLK to TQ 0.41 0.49 0.59 ns OSCKO_TQ Combinatorial T T input to TQ Out 0.56 0.65 0.76 ns OSDO_TTQ T Asynchronous Reset to OQ 1.14 1.37 1.64 ns OSCO_OQ T Asynchronous Reset to TQ 1.14 1.37 1.64 ns OSCO_TQ Notes: 1. T and T are reported as T / T in TRCE report. OSDCK_T2 OSCKD_T2 OSDCK_T OSCKD_T DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 26 R Virtex-4 Data Sheet: DC and Switching Characteristics CLB Switching Characteristics Table 34: CLB Switching Characteristics Speed Grade -12 -11 -10 (2) Symbol Description XC4VFX XC4VLX/SX ALL DEVICES Units Combinatorial Delays T 4-input function: F/G inputs to X/Y outputs 0.15 0.15 0.17 0.20 ns, Max ILO T 5-input function: F/G inputs to F5 output 0.36 0.35 0.40 0.46 ns, Max IF5 5-input function: F/G inputs to X output 0.44 0.43 0.49 0.57 ns, Max T IF5X T FXINA or FXINB inputs to YMUX output 0.30 0.30 0.34 0.39 ns, Max IF6Y T FXINA input to FX output via MUXFX 0.21 0.21 0.23 0.27 ns, Max INAFX FXINB input to FX output via MUXFX 0.21 0.20 0.23 0.26 ns, Max T INBFX T BX input to XMUX output 0.59 0.58 0.65 0.76 ns, Max BXX T BY input to YMUX output 0.43 0.43 0.48 0.56 ns, Max BYY (3) BX input to C output – Getting into carry chain 0.60 0.59 0.66 0.78 ns, Max T BXCY OUT (3) T BY input to C output – Getting into carry chain 0.49 0.48 0.54 0.63 ns, Max BYCY OUT (3) T C input to C output – Carry chain delay 0.07 0.07 0.08 0.09 ns, Max BYP IN OUT (3) F input to C output – Getting out from carry chain 0.45 0.44 0.50 0.58 ns, Max T OPCYF OUT (3) T G input to C output – Getting out from carry chain 0.44 0.43 0.48 0.57 ns, Max OPCYG OUT Sequential Delays T FF Clock CLK to XQ/YQ outputs 0.28 0.28 0.31 0.36 ns, Max CKO T Latch Clock CLK to XQ/YQ outputs 0.37 0.36 0.41 0.48 ns, Max CKLO Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK T / T 0.36 0.36 0.40 0.47 DICK CKDI BX/BY inputs ns, Min –0.09 –0.09 –0.09 –0.09 T / T 0.58 0.57 0.64 0.75 CECK CKCE CE input ns, Min –0.16 –0.16 –0.16 –0.16 T / T 0.42 0.41 0.46 0.54 FXCK CKFX FXINA/FXINB inputs ns, Min –0.14 –0.14 –0.14 –0.14 / T T 1.04 1.02 1.15 1.35 SRCK CKSR SR/BY inputs (synchronous) ns, Min –0.74 –0.73 –0.73 –0.73 T / T 0.52 0.51 0.57 0.67 CINCK CKCIN (3) C Data Inputs (DI) – Getting out from carry chain ns, Min IN –0.23 –0.23 –0.23 –0.23 Set/Reset T Minimum Pulse Width, SR/BY inputs 0.54 0.53 0.59 0.70 ns, Min RPW Delay from SR/BY inputs to XQ/YQ outputs T RQ 1.05 1.03 1.15 1.35 ns, Max (asynchronous) F Toggle Frequency (MHz) (for export control) 1181 1205 1205 1028 MHz TOG Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX -12 column. 3. These items are of interest for Carry Chain applications. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 27 R Virtex-4 Data Sheet: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) ) Table 35: CLB Distributed RAM Switching Characteristics Speed Grade -12 -11 -10 (2) Symbol Description ALL DEVICES Units XC4VFX XC4VLX/SX Sequential Delays (3) T Clock CLK to X outputs (WE active) 1.61 1.58 1.77 2.08 ns, Max SHCKO T Clock CLK to F5 output (WE active) 1.53 1.50 1.69 1.98 ns, Max SHCKOF5 Setup and Hold Times Before/After Clock CLK 1.26 1.23 1.46 1.80 T / T BX/BY data inputs (DI) ns, Min DS DH –0.90 –0.88 –0.88 –0.88 0.88 0.86 0.97 1.13 T / T F/G address inputs ns, Min AS AH –0.37 –0.37 –0.34 –0.29 1.10 1.08 1.21 1.42 T / T WE input (SR) ns, Min WS WH –0.48 –0.47 –0.47 –0.47 Clock CLK T Minimum Pulse Width, High 0.53 0.52 0.59 0.69 ns, Min WPH T Minimum Pulse Width, Low 0.55 0.54 0.60 0.70 ns, Min WPL T Minimum clock period to meet address write cycle time 0.76 0.74 0.84 0.98 ns, Min WC Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent XC4VLX/SX -12 column. 3. T also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path. SHCKO CLB Shift Register Switching Characteristics (SLICEM Only) ) Table 36: CLB Shift Register Switching Characteristics Speed Grade -12 -11 -10 (2) (3) Symbol Description ALL Units XC4VFX XC4VLX/SX XC4VFX XC4VLX/SX Sequential Delays T Clock CLK to X/Y outputs 2.12 2.08 2.19 2.19 2.57 ns, Max REG T Clock CLK to XB output via MC15 LUT output 1.83 1.73 1.90 1.84 2.16 ns, Max REGXB T Clock CLK to YB output via MC15 LUT output 1.84 1.74 1.92 1.85 2.17 ns, Max REGYB T Clock CLK to Shiftout 1.70 1.60 1.76 1.70 1.99 ns, Max CKSH T Clock CLK to F5 output 2.05 2.01 2.11 2.11 2.47 ns, Max REGF5 Setup and Hold Times Before/After Clock CLK 0.87 0.85 0.96 0.96 1.12 T / T WE input (SR) ns, Min WS WH –0.76 –0.76 –0.70 –0.70 –0.62 1.28 1.25 1.45 1.45 1.75 T / T BX/BY data inputs (DI) ns, Min DS DH –1.12 –1.11 –1.11 –1.11 –1.11 Clock CLK T Minimum Pulse Width, High 0.53 0.52 0.59 0.59 0.69 ns, Min WPH T Minimum Pulse Width, Low 0.55 0.54 0.60 0.60 0.70 ns, Min WPL Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent XC4VLX/SX -12 column. 3. The values in this column apply to all XC4VFX -11 parts. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 28 R Virtex-4 Data Sheet: DC and Switching Characteristics Block RAM and FIFO Switching Characteristics Table 37: Block RAM Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Sequential Delays (2) Clock CLK to DOUT output (without output register) 1.65 1.83 2.10 ns, Max T RCKO_DORA Clock CLK to DOUT output with ECC 3.00 3.33 3.83 ns, Max (without output register) (3) Clock CLK to DOUT output (with output register) 0.72 0.80 0.92 ns, Min T RCKO_DOA Clock CLK to DOUT output with ECC (with output 2.00 2.20 2.50 ns, Max register) Setup and Hold Times Before Clock CLK 0.34 0.37 0.43 T / T ADDR inputs ns, Min RCCK_ADDR RCKC_ADDR 0.26 0.28 0.33 0.18 0.20 0.23 (4) T / T DIN inputs ns, Min RDCK_DI RCKD_DI 0.26 0.28 0.33 0.41 0.45 0.52 (5) T / T EN input ns, Min RCCK_EN RCKC_EN 0.26 0.28 0.33 0.25 0.27 0.32 T /T CE input of output register ns, Min RCCK_REGCE RCKC_REGCE 0.26 0.28 0.33 0.25 0.27 0.32 T / T RST input ns, Min RCCK_SSR RCKC_SSR 0.26 0.28 0.33 0.59 0.65 0.75 T / T WEN input ns, Min RCCK_WE RCKC_WE 0.26 0.28 0.33 Maximum Frequency Write first and no change mode 500.00 450.45 400.00 MHz F MAX F Read first mode 500.00 450.45 400.00 MHz MAX CLK-to-CLK Read first mode 500.00 450.45 400.00 MHz Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. T includes T , T , and T as well as the B port equivalent timing parameters. RCKO_DORA RCKO_DOWA RCKO_DOPAR RCKO_DOPAW 3. T includes T as well as the B port equivalent timing parameters. RCKO_DOA RCKO_DOPA 4. T includes both A and B inputs as well as the parity inputs of A and B. RCKO_DI 5. Xilinx Block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable during the specified set-up time. Do not create an asynchronous input on an enabled port address. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 29 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 38: FIFO Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Sequential Delays (2) T Clock CLK to DO output 0.72 0.80 0.92 ns, Max FCKO_DO (3) T Clock CLK to FIFO flags outputs 0.93 1.04 1.19 ns, Max FCKO_FLAGS (4) Clock CLK to FIFO pointer outputs 1.16 1.29 1.48 ns, Max T FCKO_POINTERS Setup and Hold Times Before Clock CLK 0.18 0.20 0.23 (5) T / T DI input ns, Min FDCK_DI FCKD_DI 0.26 0.28 0.33 0.66 0.73 0.84 (6) T / T Enable inputs ns, Min FCCK_EN FCKC_EN 0.26 0.28 0.33 Reset Delays (7) T Reset RST to FLAGS 1.32 1.46 1.68 ns, Max FCO_FLAGS Maximum Frequency F FIFO in all modes 500.00 450.45 400.00 MHz MAX Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. T includes parity output (T ). FCKO_DO FCKO_DOP 3. T includes the following parameters: T , T , T , T , T , T FCKO_FLAGS FCKO_AEMPTY FCKO_AFULL FCKO_EMPTY FCKO_FULL FCKO_RDERR FCKO_WRERR. 4. T includes both T and T FCKO_POINTERS FCKO_RDCOUNT FCKO_WRCOUNT. 5. T includes parity inputs (T ). FDCK_DI FDCK_DIP 6. T includes both WRITE and READ enable. FCCK_EN 7. T includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT. FCO_FLAGS DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 30 R Virtex-4 Data Sheet: DC and Switching Characteristics XtremeDSP™ Switching Characteristics Table 39: XtremeDSP Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Setup and Hold of CE Pins 0.39 0.43 0.49 T / T Setup/Hold of all CE inputs of the DSP48 slice ns DSPCCK_CE DSPCKC_CE 0.09 0.10 0.12 0.32 0.36 0.40 T / T Setup/Hold of all RST inputs of the DSP48 slice ns DSPCCK_RST DSPCKC_RST 0.09 0.10 0.12 Setup and Hold Times of Data T / 0.25 0.28 0.32 DSPDCK_{AA, BB, CC} Setup/Hold of {A, B, C} input to {A, B, C} register ns T 0.23 0.26 0.29 DSPCKD_{AA, BB, CC} T / 1.82 2.03 2.28 DSPDCK_{AM, BM} Setup/Hold of {A, B} input to M register ns T 0.00 0.00 0.00 DSPCKD_{AM, BM} Sequential Delays Clock to out from P register to P output 0.64 0.71 0.79 ns T DSPCKO_PP T Clock to out from M register to P output 2.38 2.65 2.98 ns DSPCKO_PM Combinatorial {A, B} input to P output T 3.53 3.92 4.41 ns DSPDO_{AP, BP}L (LEGACY_MODE = MULT18X18) Maximum Frequency From {A, B} register to P register 317.46 285.71 253.94 MHz (LEGACY_MODE = MULT18X18) F MAX Fully Pipelined 500.00 450.05 400.00 MHz DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 31 R Virtex-4 Data Sheet: DC and Switching Characteristics Configuration Switching Characteristics Table 40: Configuration Switching Characteristics Speed Grade Symbol Description -12 -11 -10 Units Power-up Timing Characteristics Maximum time to configure device after (1) T 10 10 10 minutes CONFIG V has been applied. CCINT µs/frame, T Program Latency 0.5 0.5 0.5 PL Max T Power-on-Reset T +10 T +10 T +10 ms, Max POR PL PL PL T CCLK (output) delay 500 500 500 ns, Min ICCK Program Pulse Width 300 300 300 ns, Min T PROGRAM Master/Slave Serial Mode Programming Switching 0.5 0.5 0.5 T / T DIN Setup/Hold, slave mode ns, Min DCC CCD 1.0 1.0 1.0 0.5 0.5 0.5 T / T DIN Setup/Hold, master mode ns, Min DSCK SCKD 1.0 1.0 1.0 DOUT 7.5 7.5 7.5 ns, Max T CCO T High Time 2.0 2.0 2.0 ns, Min CCH T Low Time 2.0 2.0 2.0 ns, Min CCL Maximum Frequency, master mode with F 100 100 100 MHz, Max CC_SERIAL respect to nominal CCLK. Maximum Frequency, slave mode external F 100 100 100 MHz, Max MAX_SLAVE CCLK Frequency Tolerance, master mode with F ±50 ±50 ±50 % MCCTOL respect to nominal CCLK. SelectMAP Mode Programming Switching 2.0 2.0 2.0 T / T SelectMAP Setup/Hold ns, Min SMDCC SMCCD 0.0 0.0 0.0 1.0 1.0 1.0 T / T CS_B Setup/Hold ns, Min SMCSCC SMCCCS 0.5 0.5 0.5 6.0 6.0 6.0 T / T RDWR_B Setup/Hold ns, Min SMCCW SMWCC 1.0 1.0 1.0 T BUSY Propagation Delay 8.0 8.0 8.0 ns, Max SMCKBY Maximum Frequency, master mode with F 100 100 100 MHz, Max CC_SELECTMAP respect to nominal CCLK. Maximum Frequency, slave mode external F 100 100 100 MHz, Max MAX_SELECTMAP CCLK Frequency Tolerance, master mode with F ±50 ±50 ±50 % MCCTOL respect to nominal CCLK. T SelectMAP Readback Clock-to-Out 8.0 8.0 8.0 ns, Max SMCO DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 32 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 40: Configuration Switching Characteristics (Continued) Speed Grade Symbol Description -12 -11 -10 Units Boundary-Scan Port Timing Specifications T TMS and TDI Setup time before TCK 1.0 1.0 1.0 ns, Min TAPTCK T TMS and TDI Hold time after TCK 2.0 2.0 2.0 ns, Min TCKTAP T TCK falling edge to TDO output valid 6.0 6.0 6.0 ns, Max TCKTDO Maximum configuration TCK clock F 66 66 66 MHz, Max TCK frequency Maximum boundary-scan TCK clock F 50 50 50 MHz, Max TCKB frequency Dynamic Reconfiguration Port (DRP) for DCM CLKIN_FREQ_DLL_HF_MS_MAX Maximum frequency for DCLK 500 450 400 MHz, Max D_DCMADV_DADDR_DCLK_SETUP/ 0.54 0.63 0.72 DADDR Setup/Hold ns, Max D_DCMADV_DADDR_DCLK_HOLD 0.00 0.00 0.00 D_DCMADV_DI_DCLK_SETUP/ 0.54 0.63 0.72 DI Setup/Hold ns, Max D_DCMADV_DI_DCLK_HOLD 0.00 0.00 0.00 D_DCMADV_DEN_DCLK_SETUP/ 0.58 0.58 0.58 DEN Setup/Hold time ns, Max D_DCMADV_DEN_DCLK_HOLD 0.00 0.00 0.00 D_DCMADV_DWE_DCLK_SETUP/ 0.58 0.58 0.58 DWE Setup/Hold time ns, Max D_DCMADV_DWE_DCLK_HOLD 0.00 0.00 0.00 (2) D_DCMADV_DCLK_DO CLK to out of DO 00 0 ns, Max D_DCMADV_DCLK_DRDY CLK to out of DRDY 0.68 0.80 0.92 ns, Max Notes: 1. T and T must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters BCCCK_CE BCCKC_CE do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. DO will hold until next DRP operation. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 33 R Virtex-4 Data Sheet: DC and Switching Characteristics Clock Buffers and Networks Table 41: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol Description -12 -11 -10 Units 0.27 0.31 0.35 (1) T / T CE pins Setup/Hold ns BCCCK_CE BCCKC_CE 0.00 0.00 0.00 0.27 0.31 0.35 (1) T / T S pins Setup/Hold ns BCCCK_S BCCKC_S 0.00 0.00 0.00 BUFGCTRL delay 0.70 0.77 0.90 ns T BCCKO_O Maximum Frequency F Global clock tree 500 450 400 MHz MAX Notes: 1. T and T must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters BCCCK_CE BCCKC_CE do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. DCM and PMCD Switching Characteristics Table 42: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Speed Grade Symbol Description -12 -11 -10 Units Outputs Clocks (Low Frequency Mode) CLKOUT_FREQ_1X_LF_MS_MIN 32 32 32 MHz CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_LF_MS_MAX 150 150 150 MHz CLKOUT_FREQ_2X_LF_MS_MIN 64 64 64 MHz CLK2X, CLK2X180 CLKOUT_FREQ_2X_LF_MS_MAX 300 300 300 MHz CLKOUT_FREQ_DV_LF_MS_MIN 222 MHz CLKDV CLKOUT_FREQ_DV_LF_MS_MAX 100 100 100 MHz CLKOUT_FREQ_FX_LF_MS_MIN 32 32 32 MHz CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_MS_MAX 210 210 210 MHz Input Clocks (Low Frequency Mode) CLKIN_FREQ_DLL_LF_MS_MIN 32 32 32 MHz (1,3,4,5,6) CLKIN (using DLL outputs) CLKIN_FREQ_DLL_LF_MS_MAX 150 150 150 MHz CLKIN_FREQ_FX_LF_MS_MIN 111 MHz (2,3,4) CLKIN (using DFS outputs only) CLKIN_FREQ_FX_LF_MS_MAX 210 210 210 MHz PSCLK_FREQ_LF_MS_MIN 111 KHz PSCLK PSCLK_FREQ_LF_MS_MAX 500 450 400 MHz Outputs Clocks (High Frequency Mode) CLKOUT_FREQ_1X_HF_MS_MIN 150 150 150 MHz CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_HF_MS_MAX 500 450 400 MHz CLKOUT_FREQ_2X_HF_MS_MIN 300 300 300 MHz CLK2X, CLK2X180 CLKOUT_FREQ_2X_HF_MS_MAX 500 450 400 MHz CLKOUT_FREQ_DV_HF_MS_MIN 9.4 9.4 9.4 MHz CLKDV CLKOUT_FREQ_DV_HF_MS_MAX 333 300 267 MHz DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 34 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 42: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued) Speed Grade Symbol Description -12 -11 -10 Units CLKOUT_FREQ_FX_HF_MS_MIN 210 210 210 MHz CLKFX, CLKFX180 CLKOUT_FREQ_FX_HF_MS_MAX 350 315 300 MHz Input Clocks (High Frequency Mode) CLKIN_FREQ_DLL_HF_MS_MIN 150 150 150 MHz (1,3,4,5,6) CLKIN (using DLL outputs) CLKIN_FREQ_DLL_HF_MS_MAX 500 450 400 MHz CLKIN_FREQ_FX_HF_MS_MIN 50 50 50 MHz (2,3,4) CLKIN (using DFS outputs only) CLKIN_FREQ_FX_HF_MS_MAX 350 315 300 MHz PSCLK_FREQ_HF_MS_MIN 111 KHz PSCLK PSCLK_FREQ_HF_MS_MAX 500 450 400 MHz Notes: 1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to 55/45). 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs. Table 43: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode Speed Grade Symbol Description -12 -11 -10 Units Outputs Clocks (Low Frequency Mode) CLKOUT_FREQ_1X_LF_MR_MIN 19 19 19 MHz CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_LF_MR_MAX 40 36 32 MHz CLKOUT_FREQ_2X_LF_MR_MIN 38 38 38 MHz CLK2X, CLK2X180 CLKOUT_FREQ_2X_LF_MR_MAX 80 72 64 MHz CLKOUT_FREQ_DV_LF_MR_MIN 1.2 1.2 1.2 MHz CLKDV CLKOUT_FREQ_DV_LF_MR_MAX 26.7 24 21.3 MHz CLKOUT_FREQ_FX_LF_MR_MIN 19 19 19 MHz CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_MR_MAX 40 36 32 MHz Input Clocks (Low Frequency Mode) CLKIN_FREQ_DLL_LF_MR_MIN 19 19 19 MHz (1,3,4,5,6) CLKIN (using DLL outputs) CLKIN_FREQ_DLL_LF_MR_MAX 40 36 32 MHz CLKIN_FREQ_FX_LF_MR_MIN 111 MHz (2,3,4) CLKIN (using DFS outputs only) CLKIN_FREQ_FX_LF_MR_MAX 35 32 28 MHz PSCLK_FREQ_LF_MR_MIN 111 KHz PSCLK PSCLK_FREQ_LF_MR_MAX 262.50 236.30 210.00 MHz Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to 55/45). 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 35 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 44: Input Clock Tolerances Frequency Symbol Description Range Value Units Duty Cycle Input Tolerance (in %) CLKIN_PSCLK_PULSE_RANGE_1 PSCLK only < 1 MHz 25 - 75 % (1) CLKIN_PSCLK_PULSE_RANGE_1_50 1 – 50 MHz 25 - 75 % (1) CLKIN_PSCLK_PULSE_RANGE_50_100 50 – 100 MHz 30 - 70 % (1) CLKIN_PSCLK_PULSE_RANGE_100_200 PSCLK and CLKIN 100 – 200 MHz 40 - 60 % (1) CLKIN_PSCLK_PULSE_RANGE_200_400 200 – 400 MHz 45 - 55 % CLKIN_PSCLK_PULSE_RANGE_400 > 400 MHz 45 - 55 % Speed Grade -12 -11 -10 Input Clock Cycle-Cycle Jitter (Low Frequency Mode) (2,5,6) CLKIN_CYC_JITT_DLL_LF CLKIN (using DLL outputs) ±300 ±300 ±345 ps (3) CLKIN_CYC_JITT_FX_LF CLKIN (using DFS outputs) ±300 ±300 ±345 ps Input Clock Cycle-Cycle Jitter (High Frequency Mode) (2,5,6) CLKIN_CYC_JITT_DLL_HF CLKIN (using DLL outputs) ±150 ±150 ±173 ps (3) CLKIN_CYC_JITT_FX_HF CLKIN (using DFS outputs) ±150 ±150 ±173 ps Input Clock Period Jitter (Low Frequency Mode) (2,5,6) CLKIN_PER_JITT_DLL_LF CLKIN (using DLL outputs) ±1.0 ±1.0 ±1.15 ns (3) CLKIN_PER_JITT_FX_LF CLKIN (using DFS outputs) ±1.0 ±1.0 ±1.15 ns Input Clock Period Jitter (High Frequency Mode) (2,5,6) CLKIN_PER_JITT_DLL_HF CLKIN (using DLL outputs) ±1.0 ±1.0 ±1.15 ns (3) CLKIN_PER_JITT_FX_HF CLKIN (using DFS outputs) ±1.0 ±1.0 ±1.15 ns Feedback Clock Path Delay Variation CLKFB_DELAY_VAR_EXT CLKFB off-chip feedback ±1.0 ±1.0 ±1.15 ns Notes: 1. For boundary frequencies, use the more restrictive specifications. 2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 4. If both DLL and DFS outputs are used, follow the more restrictive specifications. 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 36 R Virtex-4 Data Sheet: DC and Switching Characteristics Output Clock Jitter Table 45: Output Clock Jitter Speed Grade Description Symbol Constraints -12 -11 -10 Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 ±100 ±100 ±100 ps CLK90 CLKOUT_PER_JITT_90 ±150 ±150 ±150 ps CLK180 CLKOUT_PER_JITT_180 ±150 ±150 ±150 ps CLK270 CLKOUT_PER_JITT_270 ±150 ±150 ±150 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ±200 ±200 ±200 ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 ±150 ±150 ±150 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ±300 ±300 ±300 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note (2) Note (2) Note (2) ps Notes: 1. PMCD outputs are not included in this table because they do not introduce jitter. 2. Values for this parameter are available from the architecture wizard. Output Clock Phase Alignment Table 46: Output Clock Phase Alignment Speed Grade Description Symbol Constraints -12 -11 -10 Units Phase Offset Between CLKIN and CLKFB CLKIN / CLKFB CLKIN_CLKFB_PHASE ±120 ±120 ±120 ps Phase Offset Between Any DCM Outputs All CLK outputs CLKOUT_PHASE ±140 ±140 ±140 ps Duty Cycle Precision (1) (3,4) DLL outputs CLKOUT_DUTY_CYCLE_DLL ±150 ±150 ±150 ps (2) (4) DFS outputs CLKOUT_DUTY_CYCLE_FX ±200 ±200 ±200 ps Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE. 4. The measured value includes the duty cycle distortion of the global clock tree. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 37 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 47: Miscellaneous Timing Parameters Speed Grade Symbol Description -12 -11 -10 Units Time Required to Achieve LOCK (2) T_LOCK_DLL_240 DLL output – Frequency range > 240 MHz 20 20 20 µs (1,2) T_LOCK_DLL_120_240 DLL output – Frequency range 120 - 240 MHz 63 63 63 µs (1,2) 225 225 225 µs T_LOCK_DLL_60_120 DLL output – Frequency range 60 - 120 MHz (1,2) T_LOCK_DLL_50_60 DLL output – Frequency range 50 - 60 MHz 325 325 325 µs (1,2) T_LOCK_DLL_40_50 DLL output – Frequency range 40 - 50 MHz 500 500 500 µs (1,2) 900 900 900 µs T_LOCK_DLL_30_40 DLL output – Frequency range 30 - 40 MHz (1,2) T_LOCK_DLL_24_30 DLL output – Frequency range 24 - 30 MHz 1250 1250 1250 µs (2) T_LOCK_DLL_30 DLL output – Frequency range < 30 MHz 1250 1250 1250 µs (3) 10 10 10 ms T_LOCK_FX_MAX DFS outputs T_LOCK_DLL_FINE_SHIFT Multiplication factor for DLL lock time with Fine Shift 2 2 2 Fine Phase Shifting FINE_SHIFT_RANGE_MS Absolute shifting range in maximum speed mode 7 7 7 ns FINE_SHIFT_RANGE_MR Absolute shifting range in maximum range mode 10 10 10 ns Delay Lines DCM_TAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 5 5 5 ps DCM_TAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 40 40 40 ps DCM_TAP_MR_MIN Tap delay resolution (Min) in maximum range mode 10 10 10 ps DCM_TAP_MR_MAX Tap delay resolution (Max) in maximum range mode 60 60 60 ps Input Signal Requirements Minimum duration that RST must be held asserted 200 200 200 ms (4) DCM_RESET (5) Maximum duration that RST can be held asserted. 10 10 10 sec Maximum duration that CLKIN and CLKFB can be DCM_INPUT_CLOCK_STOP 100 100 100 ms (6,7) stopped . Notes: 1. For boundary frequencies, choose the higher delay. 2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 4. CLKIN must be present and stable during the DCM_RESET. 5. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in answer record 21127 for support of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement. 6. For production step 1 LX and SX devices, use the design solutions described in answer record 21127 for support of longer durations of stopped clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support longer durations of stopped clocks. 7. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 38 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 48: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 Table 49: DCM Switching Characteristics Speed Grade Symbol Description Units -12 -11 -10 0.93 0.93 1.07 T / T PSEN Setup/Hold ns DMCCK_PSEN DMCKC_PSEN 0.00 0.00 0.00 0.93 0.93 1.07 T / T PSINCDEC Setup/Hold ns DMCCK_PSINCDEC DMCKC_PSINCDEC 0.00 0.00 0.00 T Clock to out of PSDONE 0.60 0.60 0.69 ns DMCKO_PSDONE Table 50: PMCD Switching Characteristic Speed Grade Symbol Description Units -12 -11 -10 0.60 0.60 0.60 T / T REL Setup/Hold for all outputs ns PMCCCK_REL PMCCKC_REL 0.00 0.00 0.00 T RST assertion to clock output deassertion 4.00 4.00 4.50 ns PMCCO_CLK{A1,B,C,D} T Max clock propagation delay of PMCD for all outputs 4.60 4.60 5.20 ns PMCCKO_CLK{A1,B,C,D} PMCD_CLK_SKEW Max phase between all outputs assuming all inputs ±150 ±150 ±150 ps (1) CLKIN_FREQ_PMCD_CLKA_MAX Max input/output frequency 500 450 400 MHz CLKIN_PSCLK_PULSE_RANGE Max duty cycle input tolerance (same as DCM) Note (2) PMCD_REL_HIGH_PULSE_MIN Min pulse width for REL 1.11 1.11 1.25 ns PMCD_RST_HIGH_PULSE_MIN Min pulse width for RST 1.11 1.11 1.25 ns Notes: 1. There is no minimum frequency for PMCD. 2. Refer to Table 44 parameter: CLKIN_PSCLK_PULSE_RANGE. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 39 R Virtex-4 Data Sheet: DC and Switching Characteristics System-Synchronous Switching Characteristics Virtex-4 Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 51. Values are expressed in nanoseconds unless otherwise noted. Table 51: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Speed Grade Symbol Description Device Units -12 -11 -10 LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM. T Global Clock and OFF with DCM XC4VLX15 2.43 2.81 3.25 ns ICKOFDCM XC4VLX25 2.60 2.95 3.36 ns XC4VLX40 2.54 2.91 3.32 ns XC4VLX60 2.69 3.05 3.45 ns XC4VLX80 2.88 3.27 3.72 ns XC4VLX100 2.94 3.33 3.79 ns XC4VLX160 2.94 3.35 3.82 ns XC4VLX200 N/A 3.51 4.02 ns XC4VSX25 2.65 2.99 3.39 ns XC4VSX35 2.81 3.18 3.60 ns XC4VSX55 2.83 3.20 3.62 ns XC4VFX12 2.43 2.78 3.18 ns XC4VFX20 2.54 2.88 3.26 ns XC4VFX40 2.87 3.25 3.67 ns XC4VFX60 2.92 3.31 3.77 ns XC4VFX100 3.16 3.58 4.06 ns XC4VFX140 N/A 3.79 4.30 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 40 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 52: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Speed Grade Symbol Description Device Units -12 -11 -10 LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM. T Global Clock and OFF without DCM XC4VLX15 6.42 7.22 8.14 ns ICKOF XC4VLX25 6.50 7.32 8.25 ns XC4VLX40 6.70 7.54 8.50 ns XC4VLX60 6.86 7.72 8.70 ns XC4VLX80 6.98 7.85 8.85 ns XC4VLX100 7.23 8.15 9.18 ns XC4VLX160 7.46 8.40 9.46 ns XC4VLX200 N/A 8.79 9.88 ns XC4VSX25 6.69 7.52 8.47 ns XC4VSX35 6.75 7.59 8.56 ns XC4VSX55 7.10 7.99 9.00 ns XC4VFX12 6.41 7.21 8.13 ns XC4VFX20 6.60 7.42 8.37 ns XC4VFX40 6.97 7.84 8.83 ns XC4VFX60 6.98 7.86 8.85 ns XC4VFX100 7.46 8.40 9.45 ns XC4VFX140 N/A 8.80 9.90 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 41 R Virtex-4 Data Sheet: DC and Switching Characteristics Virtex-4 Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 53. Values are expressed in nanoseconds unless otherwise noted. Table 53: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM Speed Grade Symbol Description Device Units -12 -11 -10 (1) Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. (2) T / T No Delay Global Clock and IFF with DCM 1.35 1.52 1.54 PSDCM PHDCM XC4VLX15 ns –0.72 –0.67 –0.62 1.28 1.50 1.58 XC4VLX25 ns –0.58 –0.57 –0.55 1.25 1.44 1.50 XC4VLX40 ns –0.55 –0.50 –0.46 1.25 1.47 1.55 XC4VLX60 ns –0.43 –0.40 –0.36 1.22 1.42 1.49 XC4VLX80 ns –0.26 –0.21 –0.15 1.27 1.48 1.56 XC4VLX100 ns –0.20 –0.14 –0.08 1.54 1.79 1.89 XC4VLX160 ns –0.20 –0.13 –0.05 1.90 2.00 XC4VLX200 N/A ns 0.03 0.15 1.25 1.47 1.55 XC4VSX25 ns –0.50 –0.48 –0.48 1.21 1.43 1.50 XC4VSX35 ns –0.41 –0.38 –0.34 1.25 1.47 1.55 XC4VSX55 ns –0.23 –0.18 –0.13 1.35 1.55 1.61 XC4VFX12 ns –0.71 –0.69 –0.69 1.25 1.48 1.56 XC4VFX20 ns –0.52 –0.51 –0.51 1.23 1.45 1.52 XC4VFX40 ns –0.18 –0.13 –0.08 1.17 1.37 1.44 XC4VFX60 ns –0.06 0.01 0.09 1.21 1.42 1.49 XC4VFX100 ns 0.11 0.20 0.31 1.68 1.76 XC4VFX140 N/A ns 0.21 0.31 Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. These measurements include: CLK0 DCM jitter IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 42 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 54: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM in Source-Synchronous Mode Speed Grade Symbol Description Device –12 –11 –10 Units (1) Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values (1,2) shown in IOB Switching Characteristics , page 19. (2) No Delay Global Clock and IFF with DCM in –0.33 –0.33 –0.33 T / PSDCM_0 XC4VLX15 ns Source-Synchronous Mode 0.73 0.88 1.03 T PHDCM_0 –0.29 –0.29 –0.29 XC4VLX25 ns 0.86 0.97 1.09 –0.37 –0.37 –0.37 XC4VLX40 ns 0.90 1.04 1.19 –0.32 –0.32 –0.32 XC4VLX60 ns 1.02 1.15 1.29 –0.38 –0.38 –0.38 XC4VLX80 ns 1.18 1.34 1.50 –0.31 –0.31 –0.31 XC4VLX100 ns 1.24 1.41 1.57 –0.31 –0.31 –0.31 XC4VLX160 ns 1.50 1.69 1.89 –0.31 –0.31 XC4VLX200 N/A ns 1.97 2.19 –0.32 –0.32 –0.32 XC4VSX25 ns 0.95 1.07 1.17 –0.37 –0.37 –0.37 XC4VSX35 ns 1.04 1.17 1.31 –0.32 –0.32 –0.32 XC4VSX55 ns 1.22 1.36 1.52 –0.26 –0.26 –0.26 XC4VFX12 ns 0.73 0.86 0.96 –0.31 –0.31 –0.31 XC4VFX20 ns 0.92 1.03 1.14 –0.35 –0.35 –0.35 XC4VFX40 ns 1.26 1.41 156 –0.43 –0.43 –0.43 XC4VFX60 ns 1.39 1.56 1.74 –0.38 –0.38 –0.38 XC4VFX100 ns 1.55 1.75 1.96 –0.44 –0.44 XC4VFX140 N/A ns 2.03 2.25 Notes: 1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 43 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 55: Global Clock Setup and Hold for LVCMOS25 Standard, Without DCM Speed Grade Symbol Description Device Units -12 -11 -10 (1) Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. T /T Full Delay 1.82 2.33 2.74 PSFD PHFD XC4VLX15 ns (2) Global Clock and IFF without DCM 0.11 0.19 0.39 1.79 2.30 2.70 XC4VLX25 ns 0.20 0.29 0.50 2.06 2.61 3.06 XC4VLX40 ns 0.13 0.22 0.44 2.39 2.99 3.50 XC4VLX60 ns 0.04 0.12 0.34 2.36 2.96 3.47 XC4VLX80 ns 0.16 0.26 0.49 4.85 5.83 6.76 XC4VLX100 ns –0.09 –0.09 –0.01 2.56 3.21 3.76 XC4VLX160 ns 0.46 0.59 0.88 3.57 4.17 XC4VLX200 N/A ns 0.64 0.95 2.12 2.68 3.14 XC4VSX25 ns 0.14 0.23 0.44 2.10 2.66 3.12 XC4VSX35 ns 0.21 0.30 0.52 1.99 2.53 2.97 XC4VSX55 ns 0.57 0.71 0.98 1.82 2.33 2.73 XC4VFX12 ns 0.12 0.20 0.39 1.75 2.26 2.65 XC4VFX20 ns 0.38 0.49 0.73 1.82 2.34 2.75 XC4VFX40 ns 0.64 0.78 1.05 2.42 3.03 3.54 XC4VFX60 ns 0.25 0.35 0.59 1.69 2.21 2.60 XC4VFX100 ns 1.11 1.31 1.64 2.80 3.28 XC4VFX140 N/A ns 1.26 1.61 Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. IFF = Input Flip-Flop or Latch 3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 44 R Virtex-4 Data Sheet: DC and Switching Characteristics ChipSync™ Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4 source-synchronous transmitter and receiver data-valid windows. Table 56: Duty Cycle Distortion and Clock-Tree Skew Speed Grade Symbol Description Device Units -12 -11 -10 (1) T Global Clock Tree Duty Cycle Distortion All 150 150 150 ps DCD_CLK (2) Global Clock Tree Skew XC4VLX15 120 120 120 ps T CKSKEW XC4VLX25 200 200 200 ps XC4VLX40 270 270 270 ps XC4VLX60 380 380 380 ps XC4VLX80 ps XC4VLX100 600 600 600 ps XC4VLX160 ps XC4VLX200 1160 1160 1160 ps XC4VSX25 250 250 250 ps XC4VSX35 310 310 310 ps XC4VSX55 485 485 485 ps XC4VFX12 90 90 90 ps XC4VFX20 220 220 220 ps XC4VFX40 ps XC4VFX60 395 395 395 ps XC4VFX100 ps XC4VFX140 ps T I/O clock tree duty cycle distortion All 100 100 100 ps DCD_BUFIO I/O clock tree skew across one clock region All 50 50 50 ps T I/O clock tree skew across multiple clock regions All 50 50 50 ps BUFIOSKEW T Regional clock tree duty cycle distortion All 250 250 250 ps DCD_BUFR I/O clock tree MAX frequency All 710 710 644 MHz T BUFIO_MAX_FREQ T Regional clock tree MAX frequency All 300 250 250 MHz BUFR_MAX_FREQ Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The T value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists CKSKEW for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 45 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 57: Package Skew Symbol Description Device Package Value Units (1) T Package Skew SF363 80 ps PKGSKEW XC4VLX15 FF668 120 ps SF363 90 ps XC4VLX25 FF668 110 ps FF668 110 ps XC4VLX40 FF1148 150 ps FF668 130 ps XC4VLX60 FF1148 140 ps XC4VLX80 FF1148 155 ps FF1148 140 ps XC4VLX100 FF1513 180 ps FF1148 145 ps XC4VLX160 FF1513 180 ps XC4VLX200 FF1513 180 ps XC4VSX25 FF668 90 ps XC4VSX35 FF668 100 ps XC4VSX55 FF1148 145 ps SF363 90 ps XC4VFX12 FF668 100 ps XC4VFX20 FF672 110 ps FF672 ps XC4VFX40 FF1152 ps FF672 110 ps XC4VFX60 FF1152 170 ps FF1152 ps XC4VFX100 FF1517 ps XC4VFX140 FF1517 ps Notes: 1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball (7.1 ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 46 R Virtex-4 Data Sheet: DC and Switching Characteristics Table 58: Sample Window Speed Grade Symbol Description Device Units -12 -11 -10 (1) T Sampling Error at Receiver Pins All 450 500 550 ps SAMP (2) T Sampling Error at Receiver Pins using BUFIO All 350 400 450 ps SAMP_BUFIO Notes: 1. This parameter indicates the total sampling error of Virtex-4 DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of Virtex-4 DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. Table 59: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out Speed Grade Symbol Description Units -12 -11 -10 Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO –0.45 –0.45 –0.44 T /T Setup/Hold of I/O clock across multiple clock regions ns PSCS PHCS 0.97 1.08 1.17 Pin-to-Pin Clock-to-Out Using BUFIO T Clock-to-Out of I/O clock across multiple clock regions 4.10 4.54 5.02 ns ICKOFCS Production Stepping Table 60: JTAG ID Code by Step Device Step 0 Step 1 Step 2 The Virtex-4 stepping identification system denotes the capability improvement of production released devices. By XC4VLX15 35 definition, devices from one stepping are functional super- XC4VLX25 9A sets of previous devices. Bitstreams compiled for a device XC4VLX40 with an earlier stepping are guaranteed to operate correctly 35 in subsequent device steppings. XC4VLX60 2 or 3 4 or 5 New device steppings can be shipped in place of earlier XC4VLX80 35 device steppings. Existing production designs are guaran- XC4VLX100 2 or 3 4 or 5 teed on new device steppings. To take advantage of the capabilities of a newer device stepping, customers are able XC4VLX160 0 or 3 4 or 5 to order a new stepping version and compile a new bit- XC4VLX200 0 or 3 2 or 5 stream. XC4VSX25 24 Production devices are marked with a stepping version, with XC4VSX35 24 the exception of some step 1 devices. Designs should be compiled with a CONFIG STEPPING parameter set to a XC4VSX55 24 specific stepping version. This parameter is set in the UCF XC4VFX12 0 or 2 - file: XC4VFX20 26 - CONFIG STEPPING = “#”; (where # is the stepping XC4VFX40 - version) XC4VFX60 28 - Table 60 shows the JTAG ID code by step. XC4VFX100 06 - XC4VFX140 0- Notes: 1. Shaded cells represent devices not produced at that stepping. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 47 R Virtex-4 Data Sheet: DC and Switching Characteristics Current Virtex-4 Production Devices Table 61 summarizes the current production LX and SX device stepping. Table 61: Current LX and SX Production Devices LX/SX Device Stepping Step 1 Step 2 Example Ordering Code XC4VLX60-10FF672C XC4VLX60-10FF672CS2 Device steppings shipped when ordered per Example Ordering Step 1 or Step 2 Step 2 Code T requirement is removed CONFIG DCM_RESET requirement is removed (1) Capability ImprovementsDCM_INPUT_CLOCK_STOP requirement is removed by a macro (automatically inserted by ISE software) CONFIG STEPPING parameter “1” “2” (must be set in UCF file) Minimum Software Required ISE 7.1i SP4 ISE 7.1i SP4 Minimum Speed Specification 1.58 1.58 Required. Notes: 1. See LX and SX Errata for details on LX and SX Step 1 and ES silicon. Table 62 summarizes the current production FX device stepping. Table 62: Current FX Production Devices FX Device Stepping Step 0 Step 1 Example Ordering Code XC4VFX60-10FF1152C XC4VFX60-10FF1152CS1 Device steppings shipped when ordered per Example Ordering Step 0 or Step 1 Step 1 Code Capability Improvements See FX Errata for details CONFIG STEPPING parameter “0” “0” or “1” (must be set in UCF file) Minimum Software Required ISE 8.1i SP2 ISE 8.1i SP2 Minimum Speed Specification 1.58 1.58 Required Revision History The following table shows the revision history for this document. Date Version Revisions 08/02/04 1.0 Initial Xilinx release. Printed Handbook version. 09/09/04 1.1 Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table 39. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 48 R Virtex-4 Data Sheet: DC and Switching Characteristics Date Version Revisions 01/18/05 1.2 Added parameters to Tables 4 and 5. Removed System Monitor and ADC parameters. 02/01/05 1.3 Changed parameters in Tables 1, 2, 3, 7, and 11. Added Interface Performance Characteristics section. Added Switching Characteristics section and Table 14. Added parameters to the following tables: 4–6, 14, 16–30, 32–40, and 46. 02/24/05 1.4 Changed the notes in Table 2. Added Set/Reset parameters to Table 29 and Table 30. Changed description in Table 32. Changed Set/Reset in Table 34. Changed PSCLK units in Table 42. Added parameters to Table 43. Changed DCM_TAP_MS_MIN in Table 47. 05/19/05 1.5 Added RocketIO and PowerPC parameters to Table 1, Table 2, and Table 3. Removed conditions from V and V in Table 9. Revised Table 13. Added RocketIO DC Input IDIFF ICM and Output Levels section. Added PowerPC Switching Characteristics section. Added RocketIO Switching Characteristics section. Removed Table 31 from version 1.4. Revised Table 32. Along with changes to Table 40 and Table 47, there are three new requirements to ensure maximum operating frequencies for the DCM. Added parameters to Table 51, Table 52, Table 53, Table 55, Table 56, Table 57, Table 58, Table 59. 06/17/05 1.6 Revised V and V in Table 1 and Note 4. Revised typical P specification in Table 3. IN TS CPU Revised symbols and values in the Processor tables: Table 16 through Table 22. Revised T in Table 24. Corrected the CLKOUT_FREQ_FX_HF_MS_MIN in Table 42, the DCREF CLKOUT_FREQ_FX_LF_MR_MIN in Table 43, and the “Input Clock Period Jitter” in Table 44. Corrected units in Table 56. 06/27/05 1.7 Changed V and V for LVCMOS15 in Table 7. Revised Table 14. Replaced value for V IL IH EYE in Table 25. Added Note 4 to Table 47. Added Table 54: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM in Source-Synchronous Mode. Added value for XC4VLX160-FF1513 in Table 57. Added values for -12 speed specifications to most of the tables. Revised the -10 and -11 speeds in most of the switching characteristics tables. 08/06/05 1.8 Updated to speed specification v1.56. Added V note to Table 2. Clarified design CC_CONFIG information in Table 13. Corrected T in Table 40. Added DRP configuration timing PROGRAM for DCMs to Table 40. Added global clock tree maximum frequency to Table 41. Corrected CLKOUT_FREQ_FX_LF_MS_MIN in Table 42. Added footnotes 3 and 4 to Table 42 and Table 43. Added more data to the T in Table 56. CKSKEW 08/29/05 1.9 Corrected V in Table 8. Revised Table 11. Added RocketIO MGT Clock DC Input OCM Levels to Table 12. Revised SFI-4.1 performance values in Table 13. Added software tools requirements ISE7.1i SP4, to description above Table 14. Added -11X speed grade to Table 14 and Table 23. Edited Table 15 and Table 16. Edited Table 24. Added note 2 to Table 25, and moved RXOOB to Table 12. Added conditions to T and T in VDPP DJ RJ Table 26. Moved TXOOB to Table 12. Added RSDS to Table 27. Added note 4 to VDPP Table 46. Added Production Stepping section. 09/28/05 1.10 Table 2: Removed Note 1. Recommended maximum voltage drop for V is 10 mV/ms. CCAUX 02/03/06 1.11 Revised the speed specification requirements in Switching Characteristics, page 12, with parameter changes in Table 51 and Table 53. Added Note 7 to Table 2. Added to the I RPU and I specifications in Table 3. Changed LVCMOS18 to meet the JEDEC specification in RPD Table 7. Inserted notes into Table 8, Table 9, and Table 10. Corrected note 1 in Table 11. In Table 12, revised Common Mode Input Voltage Range (V ) typical from 800 mV to ICM 600 mV and added a new Note 1. Also in Table 12, changed Common Mode Voltage specification from 95mV to 950mV. Changed performance numbers in Table 23. Removed the typical specification for T from Table 26. Added note 2 to Table 27. In Table 32, added DJ maximum to T , and a new parameter T . Revised Note 1 in IDELAYCTRLCO_RDY IDELAYPAT_JIT Table 40. Added note 5 to Table 42. Revised notes 3 and 5 in Table 47. Changed the CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in Table 50. Changed the T specification in Table 56. Changed the information in the Production BUFIO_MAX_FREQ Stepping and Current Virtex-4 Production Devices sections. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 49 R Virtex-4 Data Sheet: DC and Switching Characteristics Date Version Revisions 03/22/06 1.12 Modified second paragraph in Power-On Power Supply Requirements. Added/Changed numbers for I , I , and I and added Note 2 (Table 5). Changed the CCINTMIN CCAUXMIN CCOMIN, typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to 800 MV in Table 12. Added three DC parameters to Table 12, Input Common-Mode Voltage (V ), Peak-to-Peak Differential Input Voltage (V ), and Differential Input Resistance ICMC IDIFF (R ). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in Table 13. Added Note 3 IN to Table 15. Reduced the maximum frequency from 322 MHz to 250 MHz (in Table 25 and Table 26). Added Note 5 to Table 37. 06/01/06 1.13 Changed V and V values and added notes to Table 1, page 1. Removed -11X speed IN TS grade from Table 14. Updated to speed specification v1.60. Removed -11X speed grade, changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in Table 23, page 16. Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference Clock total jitter, peak-peak (T ) in Table 24, page 16. Changed the max value for Serial GJTT data rate F to 6.5 Gb/s. Deleted first condition and changed second condition to GTX 2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (T ) and deleted first DJ condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output random jitter (T ), both in Table 26, page 18. RJ 06/23/06 1.14.1 Virtex-4 Electrical Characteristics, page 1: removed paragraph on that introduced the -11x for XC4VFX devices. Table 3, page 3: added new values for I , I , CCAUXRX CCAUXTX I , I , I , and new notes 2 and 3. Table 4, page 4: added new symbols and CCCAUXMGT TTX TRX for values I , I , I , I ,I and new notes 4 and 5. Table 12, CCAUXRX CCAUXTX TTX TRX AUMGT page 11: changed DC parameters and values and added note. Table 14: changed speed designations for the XC4VFX devices. Table 24, page 16 and Table 25, page 17, for most characteristics: changed conditions, speed grade (typ and max) values, and units. Table 26, page 18, for most characteristics: changed conditions, speed grade (typ and max) values, and units. Updated notes. Table 40, page 32: removed the Tcnfig symbol, values, and note 1. Note 2 is now Note 1, and the reference has also been changed. Table 47, page 38: removed Input Signal Requirements. Table 51, page 40, Table 52, page 41, Table 53, page 42, Table 54, page 43, and Table 55, page 44: corrected large speed numbers to N/A. 08/23/06 1.15 Table 24, page 16: changed value for Reference Clock Rise/Fall Time (T ; T ) from RCLK FCLK 65 ps Typ to 400 ps Max. Table 32, page 26: changed the speeds specification for the -12, -11, and -10 Speed Grades for T , deleted row for IDELAYRESOLUTION T and added row for T . Table 36, page 28: changed IDELAYRESOLUTION_ERR IDELAYTOTAL_ERR the speeds specification for -12 Speed Grades, Sequential Delay characteristics: T , REG T , T , T , and T . Table 62, page 48: added stepping information for REGXB REGYB CKSH REGF5 Virtex-4 FX devices. 09/07/06 1.16 Added 2.5V rows to V and V (Table 1, page 1). Updated value DV from 200 mV to IN IN TS 110 mV in Table 12, page 11. Updated speed grade specifications for XCV4FX devices in Table 14. Updated jitter tolerance and V in Table 25, page 17. Corrected equation for EYE T in Table 32, page 26. IDELAYTOTAL_ERR 10/06/06 1.17SPEED SPECIFICATION version for this data sheet release: v1.62. Table 1: Removed former note 3 on V . IN Table 14: Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11 devices to Production status. Table 15: Expanded to break out processor clock specifications into Characteristics when APU Not Used and Characteristics when APU Used. Removed specs for CPMFCMCLK, not available. Table 25, Table 26: Updated RX and TX jitter data and notes. Table 36: Modified T , T , and T timing parameters to comply with REGXB REGYB CKSH v1.62 speed specification. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 50 R Virtex-4 Data Sheet: DC and Switching Characteristics Date Version Revisions 12/11/06 2.0SPEED SPECIFICATION version for this data sheet release: v1.62. Table 1: Modified Note (3) referring to 3.3V I/O design guidelines. Added I IN parameters. Table 2: Corrected recommended V range to 0.25V – 2.5V. Added I parameters. TRX IN Table 7: Added LVDCI attributes with LVCMOS. Table 13: Added Note (1) for SDR LVDS Interface requiring AC coupling above 622 MHz. Added DDR2 SDRAM (High-Performance SERDES Design) with reference to XAPP721. Updated all specification values. Pin-to-Pin Performance and Register-to-Register Performance tables (formerly Table 13 and Table 14) deleted. Table 14: XC4VFX12 changed to Production status. Table 15: Added APU-used max characteristics for -12 devices. Table 24: Added values for Spread-Spectrum Clocking and footnote. Table 26: Changed symbol for jitter parameters from T , R , and D to TJ, RJ, and DJ J J J respectively. Table 29: Added Note (1) to refer to Timing Report for non-zero tap values. Made DLY setup/hold parameters relative to C, not CLKDIV. Table 31: Amended Note (1) to refer to Timing Report for non-zero tap values. Table 32: Added Note (1) to refer to XAPP707 for details on IDELAY timing characteristics. Changed T from 74 ps to 75 ps to match Timing IDELAYRESOLUTION Analyzer. Modified formula for T to use 75 ps resolution. IDELAYTOTAL_ERR Table 37: Added CLK-to-DOUT parameters for “with ECC” case. Added CLK-to-CLK parameter. Table 40, Table 41, Table 56: Added configuration parameter values for -12 speed grade. Table 42: Added F for -12 speed grade. MAX Table 42, Table 43, Table 44: Added Note (6) stating that CLKIN values for DLL only also apply to DLL and DFS together. Table 43, Table 44: Replicated Note (5) from Table 42 and applied to all CLKIN with DLL parameters. Table 44, Table 47: Added notes to clarify boundary-frequency cases. Table 45: Modified Note (1) to point to the architecture wizard for CLKFX output jitter. Added Note (2) to indicate that PMCD outputs introduce no jitter. Table 47: Removed T_LOCK_FX_MIN parameter. Added DCM_RESET. Table 50: Added Note (1), no minimum frequency for PMCD. Table 61: Added Note (1) to refer to LX and SX Errata for capability improvements. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 51 R Virtex-4 Data Sheet: DC and Switching Characteristics Date Version Revisions 03/27/07 2.1SPEED SPECIFICATION version for this data sheet release: v1.64. Table 4: Added Note (6) regarding max quiescent supply current. Table 5: Filled in missing power-on current values for FX devices. Table 24: Added new parameter F . Added Min value for Spread Spectrum GREFCLK Clocking frequency. Corrected “Conditions”. Table 26: Revised Notes (2) and (3). Table 34, Table 35: Added column/values for XC4VFX -12. Table 36: Added columns/values for XC4VFX -11 and -12. Corrected XC4VLX/SX -11 and -12 values for T , T , and T . REGXB REGYB CKSH Table 40: Restored parameter T and footnote (1) from earlier revision. Added CONFIG new parameter T (SelectMAP Readback Clock-to-Out). SMCO Table 47: Restorerd DCM_RESET Minimum and DCM_INPUT_CLOCK_STOP parameters from earlier revision. Added Notes (4) through (7) to these parameters. Table 57: Removed FF1760 package. Not supported. Table 60: Added FX devices and JTAG IDs. 06/08/07 2.2SPEED SPECIFICATION version for this data sheet release: v1.65. Table 14: Promoted -12 speed grade devices of XC4VFX12, XC4VFX20, and XC4VFX60 to Production status. Table 34: Removed parameter T . Not meaningful because pin should always ISCCK_REV be connected to GND. Table 40: Added parameter F . for maximum Slave SelectMAP mode MAX_SELECTMAP external configuration clock frequency. Table 60: Filled in Step 1 values for XC4VFX20, XC4VFX60, and XC4VFX100. Table 62: Added Step 1 data. DS302 (v2.2) June 8, 2007 www.xilinx.com Preliminary Product Specification 52