1 R Virtex-II Platform FPGAs: Complete Data Sheet DS031 (v3.4) March 1, 2005 Product Specification Module 1: Module 3: Introduction and Overview DC and Switching Characteristics 7pages 43 pages Summary of FeaturesElectrical Characteristics General DescriptionPerformance Characteristics ArchitectureSwitching Characteristics Device/Package Combinations and Maximum I/OPin-to-Pin Output Parameter Guidelines Ordering ExamplesPin-to-Pin Input Parameter Guidelines DCM Timing Parameters Module 2: Source-Synchronous Switching Characteristics Functional Description Module 4: 41 pages Pinout Information Detailed Description 226 pages - Input/Output Blocks (IOBs) - Digitally Controlled Impedance (DCI)Pin Definitions - Configurable Logic Blocks (CLBs) Pinout Tables - 18-Kb Block SelectRAM™ Resources - CS144/CSG144 Chip-Scale BGA Package - 18-Bit x 18-Bit Multipliers - FG256/FGG256 Fine-Pitch BGA Package - Global Clock Multiplexer Buffers - FG456/FGG456 Fine-Pitch BGA Package - Digital Clock Manager (DCM) - FG676/FGG676 Fine-Pitch BGA Package Routing - BG575/BGG575 Standard BGA Package Creating a Design - BG728/BGG728 Standard BGA Package - FF896 Flip-Chip Fine-Pitch BGA PackageConfiguration - FF1152 Flip-Chip Fine-Pitch BGA Package - FF1517 Flip-Chip Fine-Pitch BGA Package - BF957Flip-Chip BGA Package IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume. © 2000–2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031 (v3.4) March 1, 2005 www.xilinx.com Product Specification 1 7 R Virtex-II Platform FPGAs: Introduction and Overview DS031-1 (v3.4) March 1, 2005 Product Specification Summary of Virtex-II™ Features Industry First Platform FPGA Solution - PCI-X compatible (133 MHz and 66 MHz) at 3.3V - PCI compliant (66 MHz and 33 MHz) at 3.3VIP-Immersion Architecture - CardBus compliant (33 MHz) at 3.3V - Densities from 40K to 8M system gates - Differential Signaling - 420 MHz internal clock speed (Advance Data) · 840 Mb/s Low-Voltage Differential Signaling I/O - 840+ Mb/s I/O (Advance Data) (LVDS) with current mode drivers SelectRAM™ Memory Hierarchy · Bus LVDS I/O - 3 Mb of dual-port RAM in 18 Kbit block SelectRAM · Lightning Data Transport (LDT) I/O with current resources driver buffers - Up to 1.5 Mb of distributed SelectRAM resources · Low-Voltage Positive Emitter-Coupled Logic High-Performance Interfaces to External Memory (LVPECL) I/O · Built-in DDR input and output registers - DRAM interfaces · SDR / DDR SDRAM - Proprietary high-performance SelectLink · Network FCRAM Technology · Reduced Latency DRAM · High-bandwidth data path · Double Data Rate (DDR) link - SRAM interfaces · Web-based HDL generation methodology · SDR / DDR SRAM · QDR™ SRAM Supported by Xilinx Foundation™ and Alliance - CAM interfaces Series™ Development Systems Arithmetic Functions - Integrated VHDL and Verilog design flows - Compilation of 10M system gates designs - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains - Internet Team Design (ITD) tool SRAM-Based In-System ConfigurationFlexible Logic Resources - Up to 93,184 internal registers / latches with Clock - Fast SelectMAP configuration Enable - Triple Data Encryption Standard (DES) security - Up to 93,184 look-up tables (LUTs) or cascadable option (Bitstream Encryption) 16-bit shift registers - IEEE 1532 support - Wide multiplexers and wide-input function support - Partial reconfiguration - Horizontal cascade chain and sum-of-products - Unlimited reprogrammability support - Readback capability - Internal 3-state bussing0.15 µm 8-Layer Metal Process with 0.12 µm High-Performance Clock Management Circuitry High-Speed Transistors - Up to 12 DCM (Digital Clock Manager) modules 1.5V (V ) Core Power Supply, Dedicated 3.3V CCINT · Precise clock de-skew V Auxiliary and V I/O Power Supplies CCAUX CCO · Flexible frequency synthesis IEEE 1149.1 Compatible Boundary-Scan Logic · High-resolution phase shifting Support - 16 global clock multiplexer buffers Flip-Chip and Wire-Bond Ball Grid Array (BGA) Active Interconnect Technology Packages in Three Standard Fine Pitches (0.80 mm, - Fourth generation segmented routing structure 1.00 mm, and 1.27 mm) - Predictable, fast routing delay, independent of Wire-Bond BGA Devices Available in Pb-Free fanout Packaging (www.xilinx.com/pbfree) SelectIO™-Ultra Technology 100% Factory Tested - Up to 1,108 user I/Os - 19 single-ended and six differential standards - Programmable sink current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards © 2000–2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 1 R Virtex-II Platform FPGAs: Introduction and Overview Table 1: Virtex-II Field-Programmable Gate Array Family Members CLB (1 CLB = 4 slices = Max 128 bits) SelectRAM Blocks Maximum System Array Distributed Multiplier 18 Kbit Max RAM Max I/O (1) Device Gates Row x Col. Slices RAM Kbits Blocks Blocks (Kbits) DCMs Pads XC2V40 40K 8 x 8 256 8 4 4 72 4 88 XC2V80 80K 16 x 8 512 16 8 8 144 4 120 XC2V250 250K 24 x 16 1,536 48 24 24 432 8 200 XC2V500 500K 32 x 24 3,072 96 32 32 576 8 264 XC2V1000 1M 40 x 32 5,120 160 40 40 720 8 432 XC2V1500 1.5M 48 x 40 7,680 240 48 48 864 8 528 XC2V2000 2M 56 x 48 10,752 336 56 56 1,008 8 624 XC2V3000 3M 64 x 56 14,336 448 96 96 1,728 12 720 XC2V4000 4M 80 x 72 23,040 720 120 120 2,160 12 912 XC2V6000 6M 96 x 88 33,792 1,056 144 144 2,592 12 1,104 XC2V8000 8M 112 x 104 46,592 1,456 168 168 3,024 12 1,108 Notes: 1. See details in Table 2, “Maximum Number of User I/O Pads”. General Description The Virtex-II family is a platform FPGA developed for high Wire-bond packages CS, FG, and BG are optionally avail- performance from low-density to high-density designs that abe in Pb-free versions CSG, FGG, and BGG. See Virtex-II are based on IP cores and customized modules. The family Ordering Examples, page 6. delivers complete solutions for telecommunication, wire- Table 2 shows the maximum number of user I/Os available. less, networking, video, and DSP applications, including The Virtex-II device/package combination table (Table 6 at PCI, LVDS, and DDR interfaces. the end of this section) details the maximum number of I/Os The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal for each device and package using wire-bond or flip-chip process and the Virtex-II architecture are optimized for high technology. speed with low power consumption. Combining a wide vari- Table 2: Maximum Number of User I/O Pads ety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances pro- Device Wire-Bond Flip-Chip grammable logic design capabilities and is a powerful alter- XC2V40 88 - native to mask-programmed gates arrays. As shown in Table 1, the Virtex-II family comprises 11 members, ranging XC2V80 120 - from 40K to 8M system gates. XC2V250 200 - Packaging XC2V500 264 - Offerings include ball grid array (BGA) packages with XC2V1000 328 432 0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra- XC2V1500 392 528 ditional wire-bond interconnects, flip-chip interconnect is used in some of the BGA offerings. The use of flip-chip XC2V2000 - 624 interconnect offers more I/Os than is possible in wire-bond XC2V3000 516 720 versions of the similarpackages. Flip-chip construction XC2V4000 - 912 offers the combination of high pin count with high thermal capacity. XC2V6000 - 1,104 XC2V8000 - 1,108 DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 2 R Virtex-II Platform FPGAs: Introduction and Overview Architecture Virtex-II Array Overview Virtex-II devices are user-programmable gate arrays with Programmable I/O blocks provide the interface between various configurable elements. The Virtex-II architecture is package pins and the internal configurable logic. Most optimized for high-density and high-performance logic popular and leading-edge I/O standards are supported by designs. As shown in Figure 1, the programmable device is the programmable IOBs. comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs). DCM DCM IOB Global Clock Mux Configurable Logic Programmable I/Os CLB Block SelectRAM Multiplier DS031_28_100900 Figure 1: Virtex-II Architecture Overview The internal configurable logic includes four major elements configuration and can be reloaded to change the functions organized in a regular array. of the programmable elements. Configurable Logic Blocks (CLBs) provide functional Virtex-II Features elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state This section briefly describes Virtex-II features. buffers) associated with each CLB element drive Input/Output Blocks (IOBs) dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large IOBs are programmable and can be categorized as follows: 18 Kbit storage elements of dual-port RAM. Input block with an optional single-data-rate or Multiplier blocks are 18-bit x 18-bit dedicated double-data-rate (DDR) register multipliers. Output block with an optional single-data-rate or DDR DCM (Digital Clock Manager) blocks provide register, and an optional 3-state buffer, to be driven self-calibrating, fully digital solutions for clock directly or through a single or DDR register distribution delay compensation, clock multiplication Bidirectional block (any combination of input and output and division, coarse- and fine-grained clock phase configurations) shifting. These registers are either edge-triggered D-type flip-flops A new generation of programmable routing resources called or level-sensitive latches. Active Interconnect Technology interconnects all of these elements. The general routing matrix (GRM) is an array of IOBs support the following single-ended I/O standards: routing switches. Each programmable element is tied to a LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) switch matrix, allowing multiple connections to the general PCI-X compatible (133 MHz and 66 MHz) at 3.3V routing matrix. The overall programmable interconnection is PCI compliant (66 MHz and 33 MHz) at 3.3V hierarchical and designed to support high-speed designs. CardBus compliant (33 MHz) at 3.3V All programmable elements, including the routing GTL and GTLP resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 3 R Virtex-II Platform FPGAs: Introduction and Overview HSTL (Class I, II, III, and IV) A multiplier block is associated with each SelectRAM mem- ory block. The multiplier block is a dedicated 18 x 18-bit SSTL (3.3V and 2.5V, Class I and II) multiplier and is optimized for operations based on the block AGP-2X SelectRAM content on one port. The 18 x 18 multiplier can The digitally controlled impedance (DCI) I/O feature auto- be used independently of the block SelectRAM resource. matically provides on-chip termination for each I/O element. Read/multiply/accumulate operations and DSP filter struc- tures are extremely efficient. The IOB elements also support the following differential sig- naling I/O standards: Both the SelectRAM memory and the multiplier resource are connected to four switch matrices to access the general LVDS routing resources. BLVDS (Bus LVDS) ULVDS Global Clocking LDT The DCM and global clock multiplexer buffers provide a LVPECL complete solution for designing high-speed clocking schemes. Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the Up to 12 DCM blocks are available. To generate de-skewed routing resources. internal or external clocks, each DCM can be used to elimi- nate clock distribution delay. The DCM also provides 90-, Configurable Logic Blocks (CLBs) 180-, and 270-degree phase-shifted versions of its output CLB resources include four slices and two 3-state buffers. clocks. Fine-grained phase shifting offers high-resolution Each slice is equivalent and contains: phase adjustments in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clockTwo function generators (F & G) output frequency equal to any M/D ratio of the input clock Two storage elements frequency, where M and D are two integers. For the exact Arithmetic logic gates timing parameters, see Virtex-II Electrical Characteristics. Large multiplexers Virtex-II devices have 16 global clock MUX buffers, with up Wide function capability to eight clock nets per quadrant. Each global clock MUX Fast carry look-ahead chain buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. Each DCM block isHorizontal cascade chain (OR gate) able to drive up to four of the 16 global clock MUX buffers. The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-bit shift registers, or as 16-bit Routing Resources distributed SelectRAM memory. The IOB, CLB, block SelectRAM, multiplier, and DCM ele- In addition, the two storage elements are either edge-trig- ments all use the same interconnect scheme and the same gered D-type flip-flops or level-sensitive latches. access to the global routing matrix. Timing models are shared, greatly improving the predictability of the perfor- Each CLB has internal fast interconnect and connects to a mance of high-speed designs. switch matrix to access general routing resources. There are a total of 16 global clock lines, with eight available Block SelectRAM Memory per quadrant. In addition, 24 vertical and horizontal long The block SelectRAM memory resources are 18Kb of lines per row or column as well as massive secondary and dual-port RAM, programmable from 16K x 1 bit to 512 x 36 local routing resources provide fast interconnect. Virtex-II bits, in various depth and width configurations. Each port is buffered interconnects are relatively unaffected by net totally synchronous and independent, offering three fanout and the interconnect layout is designed to minimize "read-during-write" modes. Block SelectRAM memory is crosstalk. cascadable to implement large embedded storage blocks. Horizontal and vertical routing resources for each row or Supported memory configurations for dual-port and sin- column include: gle-port modes are shown in Table 3. 24 long lines Table 3: Dual-Port And Single-Port Configurations 120 hex lines 40 double lines 16K x 1 bit 2K x 9 bits 16 direct connect lines (total in all four directions) 8K x 2 bits 1K x 18 bits 4K x 4 bits 512 x 36 bits DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 4 R Virtex-II Platform FPGAs: Introduction and Overview SelectRAM, and block SelectRAM memory resources can Boundary Scan be read back. This capability is useful for real-time debug- Boundary scan instructions and associated data registers ging. support a standard methodology for accessing and config- The Integrated Logic Analyzer (ILA) core and software pro- uring Virtex-II devices that complies with IEEE standards vides a complete solution for accessing and verifying 1149.1 — 1993 and 1532. A system mode and a test mode Virtex-II devices. are implemented. In system mode, a Virtex-II device per- forms its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan Virtex-II Device/Package Combinations test instructions control the I/O pins for testing purposes. and Maximum I/O The Virtex-II Test Access Port (TAP) supports BYPASS, Wire-bond and flip-chip packages are available. Table 4 and PRELOAD, SAMPLE, IDCODE, and USERCODE non-test Table 5 show the maximum possible number of user I/Os in instructions. The EXTEST, INTEST, and HIGHZ test instruc- wire-bond and flip-chip packages, respectively. Table 6 tions are also supported. shows the number of available user I/Os for all device/pack- Configuration age combinations. Virtex-II devices are configured by loading data into internalCS denotes wire-bond chip-scale ball grid array (BGA) configuration memory, using the following five modes: (0.80 mm pitch). CSG denotes Pb-free wire-bond chip-scale ball grid Slave-serial mode array (BGA) (0.80 mm pitch). Master-serial mode FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). Slave SelectMAP mode FGG denotes Pb-free wire-bond fine-pitch BGA (1.00 Master SelectMAP mode mm pitch). Boundary-Scan mode (IEEE 1532) BG denotes standard BGA (1.27 mm pitch). A Data Encryption Standard (DES) decryptor is available BGG denotes Pb-free standard BGA (1.27 mm pitch). on-chip to secure the bitstreams. One or two triple-DES key FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). sets can be used to optionally encrypt the configuration BF denotes flip-chip BGA (1.27 mm pitch). information. The number of I/Os per package include all user I/Os except Readback and Integrated Logic Analyzer the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, Configuration data stored in Virtex-II configuration memory DXP, and RSVD) and VBATT. can be read back for verification. Along with the configura- tion data, the contents of all flip-flops/latches, distributed Table 4: Wire-Bond Packages Information CS144/ FG256/ FG456/ FG676/ BG575/ BG728/ (1) Package CSG144 FGG256 FGG456 FGG676 BGG575 BGG728 Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27 Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35 I/Os 92 172 324 484 408 516 Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1). Table 5: Flip-Chip Packages Information Package FF896 FF1152 FF1517 BF957 Pitch (mm) 1.00 1.00 1.00 1.27 Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40 I/Os 624 824 1,108 684 DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 5 R Virtex-II Platform FPGAs: Introduction and Overview Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) Available I/Os XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V (1,2) Package 40 80 250 500 1000 1500 2000 3000 4000 6000 8000 CS144/CSG144 88 92 92 ----- --- FG256/FGG256 88 120 172 172 172 - - - - - - FG456/FGG456 - - 200 264 324 - - - - - - FG676/FGG676 - - - - - 392 456 484 - - - FF896 - - - - 432 528 624 - - - - FF1152 - - - ---- 720 824 824 824 FF1517 - - - ----- 9121,1041,108 BG575/BGG575 - - - - 328 392 408 - - - - BG728/BGG728 - - - ---- 516 --- BF957 - - - - - - 624 684 684 684 - Notes: 1. All devices in a particular package are pinout (footprint) compatible. In addition, the FG456/FGG456 and FG676/FGG676 packages are compatible, as are the FF896 and FF1152 packages. 2. Wire-bond packages CS144, FG256, FG456, FG676, BG575, and BG728 are also available in Pb-free versions CSG144, FGG256, FGG456, FGG676, BGG575, and BGG728. See Virtex-II Ordering Examples for details on how to order. Virtex-II Ordering Examples Example: XC2V1000-5FG456C Device Type Temperature Range C = Commercial (Tj = 0˚C to +85˚C) I = Industrial (Tj = –40˚C to +100˚C) Speed Grade Number of Pins (-4, -5, -6) Package Type DS031_35_033001 Figure 2: Virtex-II Ordering Example. Regular Package Example: XC2V3000-6BGG728C Device Type Temperature Range C = Commercial (Tj = 0˚C to +85˚C) I = Industrial (Tj = –40˚C to +100˚C) Number of Pins Speed Grade Pb-Free Package (-4, -5, -6) Package Type DS031_35a_061804 Figure 3: Virtex-II Ordering Example. Pb-Free Package DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 6 R Virtex-II Platform FPGAs: Introduction and Overview Revision History This section records the change history for this module of the data sheet. Date Version Revision 11/07/00 1.0 Early access draft. 12/06/00 1.1 Initial release. 01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics sections. 01/25/01 1.3 The data sheet was divided into four modules (per the current style standard). 04/02/01 1.5 Skipped v1.4 to sync up modules. Reverted to traditional double-column format. 07/30/01 1.6 Made minor changes to items listed under Summary of Virtex-II™ Features. 10/02/01 1.7 Minor edits. 07/16/02 1.8 Updated Virtex-II Device/Package Combinations shown in Table 6. 09/26/02 1.9 Updated Table 2 and Table 6 to reflect supported Virtex-II Device/Package Combinations. 08/01/03 2.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3. 03/29/04 2.0.1 Recompiled for backward compatibility with Acrobat 4 and above. No content changes. 06/24/04 3.3 Added references to available Pb-free wire-bond packages. (Revision number advanced to level of complete data sheet.) 03/01/05 3.4 No changes in Module 1 for this revision. Virtex-II Data Sheet The Virtex-II Data Sheet contains the following modules: Virtex-II Platform FPGAs: Introduction and Overview Virtex-II Platform FPGAs: DC and Switching (Module 1) Characteristics (Module 3) Virtex-II Platform FPGAs: Functional Description Virtex-II Platform FPGAs: Pinout Information (Module 2) (Module 4) DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 7 4 0 R Virtex-II Platform FPGAs: Functional Description DS031-2 (v3.4) March 1, 2005 Product Specification Detailed Description Input/Output Blocks (IOBs) Table 1: Supported Single-Ended I/O Standards Board Virtex-II™ I/O blocks (IOBs) are provided in groups of two IOSTANDARD Output Input Input Termination or four on the perimeter of each device. Each IOB can be Attribute V V V Voltage (V ) CCO CCO REF TT used as input and/or output for single-ended I/Os. Two (3) LVTTL 3.3 3.3 N/R N/R IOBs can be used as a differential pair. A differential pair is always connected to the same switch matrix, as shown in LVCMOS33 3.3 3.3 N/R N/R Figure 1. LVCMOS25 2.5 2.5 N/R N/R IOB blocks are designed for high performances I/Os, sup- LVCMOS18 1.8 1.8 N/R N/R porting 19 single-ended standards, as well as differential LVCMOS15 1.5 1.5 N/R N/R signaling with LVDS, LDT, Bus LVDS, and LVPECL. PCI33_3 3.3 3.3 N/R N/R PCI66_3 3.3 3.3 N/R N/R IOB PCI-X 3.3 3.3 N/R N/R PAD4 Differential Pair GTL Note (1) Note (1) 0.8 1.2 IOB GTLP Note (1) Note (1) 1.0 1.5 PAD3 Switch HSTL_I 1.5 N/R 0.75 0.75 Matrix IOB HSTL_II 1.5 N/R 0.75 0.75 PAD2 Differential Pair HSTL_III 1.5 N/R 0.9 1.5 IOB HSTL_IV 1.5 N/R 0.9 1.5 PAD1 HSTL_I_18 1.8 N/R 0.9 0.9 DS031_30_101600 HSTL_II_18 1.8 N/R 0.9 0.9 Figure 1: Virtex-II Input/Output Tile HSTL_III _18 1.8 N/R 1.1 1.8 Note: Differential I/Os must use the same clock. HSTL_IV_18 1.8 N/R 1.1 1.8 Supported I/O Standards (2) SSTL18_I 1.8 N/R 0.9 0.9 Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out- puts that support a wide variety of I/O signaling standards. SSTL18_II 1.8 N/R 0.9 0.9 In addition to the internal supply voltage (V =1.5V), CCINT SSTL2_I 2.5 N/R1.25 1.25 output driver supply voltage (V ) is dependent on the I/O CCO SSTL2_II 2.5 N/R 1.25 1.25 standard (see Table 1 and Table 2). An auxiliary supply voltage (V = 3.3 V) is required, regardless of the I/OSSTL3_I 3.3 N/R 1.5 1.5 CCAUX standard used. For exact supply voltage absolute maximum SSTL3_II 3.3 N/R 1.5 1.5 ratings, see DC Input and Output Levels in Module 3. AGP-2X/AGP 3.3 N/R 1.32 N/R All of the user IOBs have fixed-clamp diodes to V and to CCO Notes: ground. As outputs, these IOBs are not compatible or com- 1. V of GTL or GTLP should not be lower than the termination CCO pliant with 5V I/O standards. As inputs, these IOBs are not voltage or the voltage seen at the I/O pad. Example: If the pin High level is 1.5V, connect V to 1.5V. normally 5V tolerant, but can be used with 5V I/O standards CCO 2. SSTL18_I is not a JEDEC-supported standard. when external current-limiting resistors are used. For more 3. N/R = no requirement. details, see the “5V Tolerant I/Os“ Tech Topic at www.xil- inx.com. Table 3 lists supported I/O standards with Digitally Con- trolled Impedance. See Digitally Controlled Impedance (DCI), page 8. © 2000–2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 1 R Virtex-II Platform FPGAs: Functional Description Logic Resources Table 2: Supported Differential Signal I/O Standards IOB blocks include six storage elements, as shown in Output Input Input Output I/O Standard V V V V Figure 2. CCO CCO REF OD (1) LVPECL_33 3.3 N/R N/R 0.490 - 1.220 LDT_25 2.5 N/R N/R 0.500 - 0.700 IOB LVDS_33 3.3 N/R N/R 0.250 - 0.400 Input DDR mux LVDS_25 2.5 N/R N/R 0.250 - 0.400 Reg LVDSEXT_33 3.3 N/R N/R 0.440 - 0.820 OCK1 Reg LVDSEXT_25 2.5 N/R N/R 0.440 - 0.820 ICK1 BLVDS_25 2.5 N/R N/R 0.250 - 0.450 Reg ULVDS_25 2.5 N/R N/R 0.500 - 0.700 3-State OCK2 Reg Notes: ICK2 1. N/R = no requirement. DDR mux Table 3: Supported DCI I/O Standards Reg I/O Output Input Input Termination OCK1 Standard V V V Type CCO CCO REF PAD (1) (4) LVDCI_33 3.3 3.3 N/R Series Reg (1) LVDCI_DV2_33 3.3 3.3 N/R Series Output OCK2 (1) LVDCI_25 2.5 2.5 N/R Series (1) LVDCI_DV2_25 2.5 2.5 N/R Series DS031_29_100900 (1) LVDCI_18 1.8 1.8 N/R Series (1) Figure 2: Virtex-II IOB Block LVDCI_DV2_18 1.8 1.8 N/R Series (1) LVDCI_15 1.5 1.5 N/R Series Each storage element can be configured either as an (1) LVDCI_DV2_15 1.5 1.5 N/R Series edge-triggered D-type flip-flop or as a level-sensitive latch. GTL_DCI 1.2 1.2 0.8 Single On the input, output, and 3-state path, one or two DDR reg- GTLP_DCI 1.5 1.5 1.0 Single isters can be used. HSTL_I_DCI 1.5 1.5 0.75 Split Double data rate is directly accomplished by the two regis- HSTL_II_DCI 1.5 1.5 0.75 Split ters on each path, clocked by the rising edges (or falling edges) from two different clock nets. The two clock signals HSTL_III_DCI 1.5 1.5 0.9 Single are generated by the DCM and must be 180 degrees out of HSTL_IV_DCI 1.5 1.5 0.9 Single phase, as shown in Figure 3. There are two input, output, HSTL_I_DCI_18 1.8 1.8 0.9 Split and 3-state data signals, each being alternately clocked HSTL_II_DCI_18 1.8 1.8 0.9 Split out. HSTL_III_DCI_18 1.8 1.8 1.1 Single HSTL_IV_DCI_18 1.8 1.8 1.1 Single (3) SSTL18_I_DCI 1.8 1.8 0.9 Split SSTL18_II_DCI 1.8 1.8 0.9 Split (2) SSTL2_I_DCI 2.5 2.5 1.25 Split (2) SSTL2_II_DCI 2.5 2.5 1.25 Split (2) SSTL3_I_DCI 3.3 3.3 1.5 Split (2) SSTL3_II_DCI 3.3 3.3 1.5 Split LVDS_25_DCI 2.5 2.5 N/R Split LVDSEXT_25_DCI 2.5 2.5 N/R Split Notes: 1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. These are SSTL compatible. 3. SSTL18_I is not a JEDEC-supported standard. 4. N/R = no requirement. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 2 R Virtex-II Platform FPGAs: Functional Description DCM 180° 0° FDDR FDDR D1 D1 Q1 Q1 CLOCK CLK1 CLK1 DDR MUXQQ DDR MUX D2 D2 Q2 Q2 CLK2 CLK2 (50/50 duty cycle clock) DS031_26_100900 Figure 3: Double Data Rate Registers The DDR mechanism shown in Figure 3 can be used to mir- For each storage element, the SRHIGH, SRLOW, INIT0, ror a copy of the clock on the output. This is useful for prop- and INIT1 attributes are independent. Synchronous or agating a clock along the data that has an identical delay. It asynchronous set / reset is consistent in an IOB block. is also useful for multiple clock generation, where there is a All the control signals have independent polarity. Any unique clock driver for every clock load. Virtex-II devices inverter placed on a control input is automatically absorbed. can produce many copies of a clock with very little skew. Each register or latch (independent of all other registers or Each group of two registers has a clock enable signal (ICE latches) (see Figure 4) can be configured as follows: for the input registers, OCE for the output registers, and No set or reset TCE for the 3-state registers). The clock enable signals are Synchronous set active High by default. If left unconnected, the clock enable Synchronous reset for that storage element defaults to the active state. Synchronous set and reset Each IOB block has common synchronous or asynchro- Asynchronous set (preset) nous set and reset (SR and REV signals). Asynchronous reset (clear) SR forces the storage element into the state specified by the Asynchronous set and reset (preset and clear) SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”. The synchronous reset overrides a set, and an asynchro- SRLOW forces a logic “0”. When SR is used, a second input nous clear overrides a preset. (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition. The ini- tial state after configuration or global initialization state is defined by a separate INIT0 and INIT1 attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 3 R Virtex-II Platform FPGAs: Functional Description (O/T) 1 Attribute INIT1 INIT0 FF SRHIGH LATCH SRLOW Q1 D1 (O/T) CE CE (O/T) CLK1 CK1 SR REV SR Shared FF1 by all (OQ or TQ) DDR MUX registers REV FF2 FF LATCH D2 Q2 CE Attribute INIT1 (O/T) CLK2 CK2 INIT0 SR REV SRHIGH SRLOW Reset Type SYNC ASYNC (O/T) 2 DS031_25_110300 Figure 4: Register / Latch Configuration in an IOB Block Input/Output Individual Options V CCO Each device pad has optional pull-up and pull-down in all SelectI/O-Ultra configurations. Each device pad has Clamp OBUF optional weak-keeper in LVTTL, LVCMOS, and PCI Diode SelectI/O-Ultra configurations, as illustrated in Figure 5. Weak Values of the optional pull-up and pull-down resistors are in V CCO Keeper the range 10 - 60 KΩ, which is the specification for V CCO Program 10KΩ – when operating at 3.3V (from 3.0 to 3.6V only). The clamp 60KΩ Current diode is always present, even when power is not. The optional weak-keeper circuit is connected to each user PAD I/O pad. When selected, the circuit monitors the voltage on V CCO the pad and weakly drives the pin High or Low. If the pin is 10KΩ – connected to a multiple-source signal, the weak-keeper 60KΩ holds the signal in its last state if all drivers are disabled. V = 3.3V CCAUX Maintaining a valid logic level in this way eliminates bus Program V = 1.5V CCINT chatter. An enabled pull-up or pull-down overrides the Delay weak-keeper circuit. DS031_23_022205 IBUF LVTTL sinks and sources current up to 24 mA. The current Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra is programmable for LVTTL and LVCMOS SelectI/O-Ultra Standards standards (see Table 4). Drive-strength and slew-rate con- trols for each output driver, minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew-rate controls are not available. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 4 R Virtex-II Platform FPGAs: Functional Description Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source) SelectI/O-Ultra Programmable Current (Worst-Case Guaranteed Minimum) LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a Figure 6 shows the SSTL2, SSTL3, and HSTL configura- Input Path tions. HSTL can sink current up to 48 mA. (HSTL IV) The Virtex-II IOB input path routes input signals directly to internal logic and / or through an optional input flip-flop or V CCO latch, or through the DDR input registers. An optional delay element at the D-input of the storage element eliminates Clamp OBUF pad-to-pad hold time. The delay is matched to the internal Diode clock-distribution delay of the Virtex-II device, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, V . The need to supply V imposes REF REF PAD constraints on which standards can be used in the same bank. See I/O banking description. Output Path The output path includes a 3-state output buffer that drives V = 3.3V CCAUX the output signal onto the pad. The output and / or the V = 1.5V V CCINT REF 3-state signal can be routed to the buffer directly from the DS031_24_100900 internal logic or through an output / 3-state flip-flop or latch, Figure 6: SSTL or HSTL SelectI/O-Ultra Standards or through the DDR output / 3-state registers. Each output driver can be individually programmed for a All pads are protected against damage from electrostatic wide range of low-voltage signaling standards. In most sig- discharge (ESD) and from over-voltage transients. Virtex-II naling standards, the output High voltage depends on an uses two memory cells to control the configuration of an I/O externally supplied V voltage. The need to supply V CCO CCO as an input. This is to reduce the probability of an I/O con- imposes constraints on which standards can be used in the figured as an input from flipping to an output when sub- same bank. See I/O banking description. jected to a single event upset (SEU) in space applications. I/O Banking Prior to configuration, all outputs not involved in configura- tion are forced into their high-impedance state. The Some of the I/O standards described above require V CCO pull-down resistors and the weak-keeper circuits are inac- and V voltages. These voltages are externally supplied REF tive. The dedicated pin HSWAP_EN controls the pull-up and connected to device pins that serve groups of IOB resistors prior to configuration. By default, HSWAP_EN is blocks, called banks. Consequently, restrictions exist about set high, which disables the pull-up resistors on user I/O which I/O standards can be combined within a given bank. pins. When HSWAP_EN is set low, the pull-up resistors are Eight I/O banks result from dividing each edge of the FPGA activated on user I/O pins. into two banks, as shown in Figure 7 and Figure 8. Each All Virtex-II IOBs support IEEE 1149.1 compatible boundary bank has multiple V pins, all of which must be con- CCO scan testing. nected to the same voltage. This voltage is determined by the output standards in use. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 5 R Virtex-II Platform FPGAs: Functional Description devices, some V pins used in larger devices do not con- CCO nect within the package. These unconnected pins can be left unconnected externally, or, if necessary, they can be Bank 0 Bank 1 connected to V to permit migration to a larger device. CCO Rules for Combining I/O Standards in the Same Bank The following rules must be obeyed to combine different input, output, and bi-directional standards in the same bank: 1. Combining output standards only. Output standards with the same output V requirement can be CCO Bank 5 Bank 4 combined in the same bank. Compatible example: SSTL2_I and LVDS_25_DCI outputs ug002_c2_014_112900 Incompatible example: Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond SSTL2_I (output V = 2.5V) and CCO LVCMOS33 (output V = 3.3V) outputs Packages (CS/CSG, FG/FGG, & BG/BGG) CCO 2. Combining input standards only. Input standards Some input standards require a user-supplied threshold with the same input V and input V requirements CCO REF voltage (V ), and certain user-I/O pins are automatically REF can be combined in the same bank. configured as V inputs. Approximately one in six of the REF Compatible example: I/O pins in the bank assume this role. LVCMOS15 and HSTL_IV inputs Incompatible example: LVCMOS15 (input V = 1.5V) and CCO LVCMOS18 (input V = 1.8V) inputs CCO Bank 1 Bank 0 Incompatible example: HSTL_I_DCI_18 (V = 0.9V) and REF HSTL_IV_DCI_18 (V = 1.1V) inputs REF 3. Combining input standards and output standards. Input standards and output standards with the same input V and output V requirement can be CCO CCO combined in the same bank. Compatible example: LVDS_25 output and HSTL_I input Bank 4 Bank 5 Incompatible example: LVDS_25 output (output V = 2.5V) and CCO ds031_66_112900 HSTL_I_DCI_18 input (input V = 1.8V) CCO Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip 4. Combining bi-directional standards with input or Packages (FF & BF) output standards. When combining bi-directional I/O with other standards, make sure the bi-directional V pins within a bank are interconnected internally, and REF standard can meet rules 1 through 3 above. consequently only one V voltage can be used within REF 5. Additional rules for combining DCI I/O standards. each bank. However, for correct operation, all V pins in REF the bank must be connected to the external reference volt- a. No more than one Single Termination type (input or age source. output) is allowed in the same bank. Incompatible example: The V and the V pins for each bank appear in the CCO REF HSTL_IV_DCI input and HSTL_III_DCI input device pinout tables. Within a given package, the number of V and V pins can vary depending on the size of b. No more than one Split Termination type (input or REF CCO device. In larger devices, more I/O pins convert to V output) is allowed in the same bank. REF pins. Since these are always a superset of the V pins Incompatible example: REF used for smaller devices, it is possible to design a PCB that HSTL_I_DCI input and HSTL_II_DCI input permits migration to a larger device if necessary. The implementation tools will enforce these design rules. All V pins for the largest device anticipated must be con- REF Table 5 summarizes all standards and voltage supplies. nected to the V voltage and not used for I/O. In smaller REF DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 6 Bank 2 Bank 3 Bank 6 Bank 7 Bank 2 Bank 3 Bank 6 Bank 7 R Virtex-II Platform FPGAs: Functional Description Table 5: Summary of Voltage Supply Requirements for Table 5: Summary of Voltage Supply Requirements for All Input and Output Standards (Continued) All Input and Output Standards V V Termination Type V V Termination Type CCO REF CCO REF I/O Standard Output Input Input Output Input I/O Standard Output Input Input Output Input (1) HSTL_III_18 1.1 N/R N/R LVDS_33 N/R N/R N/R HSTL_IV_18 1.1 N/R N/R LVDSEXT_33 N/R N/R N/R HSTL_I_18 0.9 N/R N/R LVPECL_33 N/R N/R N/R N/R N/R HSTL_II_18 0.9 N/R N/R SSTL3_I 1.5 N/R N/R SSTL18_I 0.9 N/R N/R SSTL3_II 1.5 N/R N/R SSTL18_II 0.9 N/R N/R AGP 1.32 N/R N/R LVCMOS18 N/R N/R N/R LVTTL N/R N/R N/R LVDCI_18 1.8 N/R Series N/R LVCMOS33 3.3 N/R N/R N/R LVDCI_DV2_18 N/R Series N/R LVDCI_33 N/R Series N/R HSTL_III_DCI_18 1.1 N/R Single LVDCI_DV2_33 N/R Series N/R HSTL_IV_DCI_18 1.8 1.1 Single Single PCI33_3 3.3 N/R N/R N/R HSTL_I_DCI_18 0.9 N/R Split PCI66_3 N/R N/R N/R HSTL_II_DCI_18 0.9 Split Split PCIX N/R N/R N/R SSTL18_I_DCI 0.9 N/R Split SSTL3_I_DCI 1.5 N/R Split SSTL18_II_DCI 0.9 Split Split SSTL3_II_DCI 1.5 Split Split HSTL_III 0.9 N/R N/R LVDS_25 N/R N/R N/R HSTL_IV 0.9 N/R N/R LVDSEXT_25 N/R N/R N/R N/R HSTL_I 0.75 N/R N/R LDT_25 N/R N/R N/R HSTL_II 0.75 N/R N/R ULVDS_25 N/R N/R N/R N/R LVCMOS15 N/R N/R N/R BLVDS_25 N/R N/R N/R LVDCI_15 N/R Series N/R SSTL2_I 1.25 N/R N/R 1.5 LVDCI_DV2_15 N/R Series N/R SSTL2_II 1.25 N/R N/R 2.5 GTLP_DCI 1 Single Single LVCMOS25 N/R N/R N/R 1.5 HSTL_III_DCI 0.9 N/R Single LVDCI_25 N/R Series N/R HSTL_IV_DCI 0.9 Single Single LVDCI_DV2_25 N/R Series N/R HSTL_I_DCI 0.75 N/R Split LVDS_25_DCI N/R N/R Split 2.5 HSTL_II_DCI 0.75 Split Split LVDSEXT_25_DC N/R N/R Split I GTL_DCI 1.2 1.2 0.8 Single Single SSTL2_I_DCI 1.25 N/R Split GTLP 1N/R N/R N/R N/R SSTL2_II_DCI 1.25 Split Split GTL 0.8 N/R N/R Notes: 1. N/R = no requirement. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 7 R Virtex-II Platform FPGAs: Functional Description Digitally Controlled Impedance (DCI) Controlled Impedance Drivers (Series Term.) DCI can be used to provide a buffer with a controlled output Today’s chip output signals with fast edge rates require ter- impedance. It is desirable for this output impedance to mination to prevent reflections and maintain signal integrity. match the transmission line impedance (Z ). Virtex-II input High pin count packages (especially ball grid arrays) can 0 buffers also support LVDCI and LVDCI_DV2 I/O standards. not accommodate external termination resistors. Virtex-II XCITE DCI provides controlled impedance drivers IOB and on-chip termination for single-ended and differential I/Os. This eliminates the need for external resistors, and Z Z improves signal integrity. The DCI feature can be used on any IOB by selecting one of the DCI I/O standards. When applied to inputs, DCI provides input parallel termina- Virtex-II DCI tion. When applied to outputs, DCI provides controlled V = 3.3 V, 2.5 V, 1.8 V or 1.5 V CCO DS031_51_110600 impedance drivers (series termination) or output parallel termination. Figure 10: Internal Series Termination DCI operates independently on each I/O bank. When a DCI Table 6: SelectI/O-Ultra Controlled Impedance Buffers I/O standard is used in a particular I/O bank, external refer- ence resistors must be connected to two dual-function pins V DCI DCI Half Impedance CCO on the bank. These resistors, voltage reference of N transis- 3.3 V LVDCI_33 LVDCI_DV2_33 tor (VRN) and the voltage reference of P transistor (VRP) 2.5 V LVDCI_25 LVDCI_DV2_25 are shown in Figure 9. 1.8 V LVDCI_18 LVDCI_DV2_18 1.5 V LVDCI_15 LVDCI_DV2_15 1 Bank DCI Controlled Impedance Drivers (Parallel) DCI DCI also provides on-chip termination for SSTL3, SSTL2, HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or DCI transmitters on bidirectional lines. Table 7 and Table 8 list the on-chip parallel terminations DCI available in Virtex-II devices. V must be set according to CCO V CCO Table 3. Note that there is a V requirement for GTL_DCI CCO and GTLP_DCI, due to the on-chip termination resistor. R (1%) REF Table 7: SelectI/O-Ultra Buffers With On-Chip Parallel VRN Termination VRP IOSTANDARD Attribute R (1%) REF I/O Standard External On-Chip Description Termination Termination GND (1) SSTL3 Class I SSTL3_I SSTL3_I_DCI DS031_50_101200 (1) SSTL3 Class II SSTL3_II SSTL3_II_DCI Figure 9: DCI in a Virtex-II Bank (1) SSTL2 Class I SSTL2_I SSTL2_I_DCI (1) When used with a terminated I/O standard, the value of SSTL2 Class II SSTL2_II SSTL2_II_DCI resistors are specified by the standard (typically 50Ω). HSTL Class I HSTL_I HSTL_I_DCI When used with a controlled impedance driver, the resistors HSTL Class II HSTL_II HSTL_II_DCI set the output impedance of the driver within the specified range (25Ω to 100Ω). For all series and parallel termina- HSTL Class III HSTL_III HSTL_III_DCI tions listed in Table 6 and Table 7, the reference resistors HSTL Class IV HSTL_IV HSTL_IV_DCI must have the same value for any given bank. One percent GTL GTL GTL_DCI resistors are recommended. GTLP GTLP GTLP_DCI The DCI system adjusts the I/O impedance to match the Notes: two external reference resistors, or half of the reference 1. SSTL-compatible resistors, and compensates for impedance changes due to voltage and/or temperature fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 8 R Virtex-II Platform FPGAs: Functional Description Table 8: SelectI/O-Ultra Differential Buffers With On-Chip Termination IOSTANDARD Attribute I/O Standard Description External Termination On-Chip Termination LVDS 2.5V LVDS_25 LVDS_25_DCI LVDS Extended 2.5V LVDSEXT_25 LVDSEXT_25_DCI Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the Virtex-II Platform FPGA User Guide. HSTL_I HSTL_II HSTL_III HSTL_IV V /2 V /2 V /2 V V V CCO CCO CCO CCO CCO CCO R RR R RR Conventional Z Z Z Z 0 0 0 0 V V /2 V /2 CCO CCO CCO V V V DCI Transmit CCO CCO CCO R 2R R Conventional R RR Z Z 0 0 Receive Z Z 0 0 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V /2 V CCO V CCO CCO V V V Conventional CCO CCO CCO 2R 2R R Transmit R R R Z Z 0 0 DCI Receive Z Z 0 0 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V V V CCO CCO CCO V V V CCO CCO CCO 2R 2R 2R DCI Transmit R R R Z Z 0 0 DCI Receive Z Z 0 0 2R 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V V V V CCO CCO CCO CCO 2R 2R R R Z Z 0 0 Bidirectional N/A N/A 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Reference VRN = VRP = R = Z VRN = VRP = R = Z VRN = VRP = R = Z VRN = VRP = R = Z Resistor 0 0 0 0 Recommended 50 Ω 50 Ω 50 Ω 50 Ω (1) Z 0 DS031_65a_100201 Note: 1. Z is the recommended PCB trace impedance. 0 Figure 11: HSTL DCI Usage Examples DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 9 R Virtex-II Platform FPGAs: Functional Description Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O standards. For a complete list, see the Virtex-II Platform FPGA User Guide. SSTL2_I SSTL2_II SSTL3_I SSTL3_II V /2 V /2 CCO CCO V /2 V /2 V /2 V /2 CCO CCO CCO CCO R R RR RR Conventional Z Z 0 0 Z Z 0 0 R/2 R/2 R/2 R/2 V /2 CCO V V /2 V V /2 CCO CCO CCO CCO V /2 CCO (1) DCI Transmit (1) (1) 25Ω 25Ω 25Ω (1) R R R 2R 2R 25Ω Conventional R Z Z Receive 0 Z 0 0 Z 0 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V V V V V V CCO CCO/2 CCO CCO CCO/2 CCO Conventional 2R R 2R 2R R 2R Transmit Z Z Z Z 0 0 0 0 DCI Receive R/2 R/2 R/2 R/2 2R 2R 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V CCO V V V V CCO CCO CCO V CCO CCO (1) (1) (1) (1) 2R 25Ω 25Ω 25Ω 2R 25Ω 2R 2R 2R 2R DCI Transmit Z 0 Z Z Z 0 0 0 DCI Receive 2R 2R 2R 2R 2R 2R Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI V V CCO CCO V V CCO CCO (1) (1) 25Ω 25Ω 2R 2R 2R 2R Z Z 0 0 Bidirectional N/A N/A 2R 2R 2R 2R (1) (1) 25Ω 25Ω Virtex-II DCI Virtex-II DCI Virtex-II DCI Virtex-II DCI Reference Resistor VRN = VRP = R = Z VRN = VRP = R = Z VRN = VRP = R = Z VRN = VRP = R = Z 0 0 0 0 Recommended 50 Ω 50 Ω 50 Ω 50 Ω (2) Z 0 Notes: 1. The SSTL-compatible 25Ω series resistor is accounted for in the DCI buffer, and it is not DCI controlled. DS031_65b_112502 2. Z is the recommended PCB trace impedance. 0 Figure 12: SSTL DCI Usage Examples DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 10 R Virtex-II Platform FPGAs: Functional Description Figure 13 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list, see the Virtex-II Platform FPGA User Guide. LVDS_DCI and LVDSEXT_DCI Receiver Z 0 Conventional 2R Z 0 Virtex-II LVDS V CCO 2R Z 0 2R Conventional Transmit V CCO DCI Receive 2R Z 0 2R Virtex-II LVDS DCI Reference VRN = VRP = R = Z Resistor 0 Recommended 50 Ω Z 0 NOTE: Only LVDS25_DCI is supported (V = 2.5V only) CCO DS031_65c_022103 Figure 13: LVDS DCI Usage Examples DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 11 R Virtex-II Platform FPGAs: Functional Description Configurable Logic Blocks (CLBs) The Virtex-II configurable logic blocks (CLB) are organized Configurations in an array and are used to build combinatorial and synchro- Look-Up Table nous logic designs. Each CLB element is tied to a switch Virtex-II function generators are implemented as 4-input matrix to access the general routing matrix, as shown in look-up tables (LUTs). Four independent inputs are pro- Figure 14. A CLB element comprises 4 similar slices, with vided to each of the two function generators in a slice (F and fast local feedback within the CLB. The four slices are split G). These function generators are each capable of imple- in two columns of two slices with two independent carry menting any arbitrarily defined boolean function of four logic chains and one common shift chain. inputs. The propagation delay is therefore independent of the function implemented. Signals from the function gener- COUT TBUF X0Y1 ators can exit the slice (X or Y output), can input the XOR TBUF X0Y0 Slice dedicated gate (see arithmetic logic), or input the carry-logic X1Y1 multiplexer (see fast look-ahead carry logic), or feed the D input of the storage element, or go to the MUXF5 (not Slice X1Y0 shown in Figure 16). COUT Switch Matrix In addition to the basic LUTs, the Virtex-II slice contains SHIFT logic (MUXF5 and MUXFX multiplexers) that combines CIN Slice X0Y1 function generators to provide any function of five, six, Fast seven, or eight inputs. The MUXFX are either MUXF6, Slice Connects MUXF7 or MUXF8 according to the slice considered in the X0Y0 to neighbors CLB. Selected functions up to nine inputs (MUXF5 multi- plexer) can be implemented in one slice. The MUXFX can DS031_32_101600 CIN also be a MUXF6, MUXF7, or MUXF8 multiplexers to map Figure 14: Virtex-II CLB Element any functions of six, seven, or eight inputs and selected wide logic functions. Slice Description Register/Latch Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and The storage elements in a Virtex-II slice can be configured two storage elements. As shown in Figure 15, each 4-input either as edge-triggered D-type flip-flops or as level-sensi- function generator is programmable as a 4-input LUT, 16 tive latches. The D input can be directly driven by the X or Y bits of distributed SelectRAM memory, or a 16-bit vari- output via the DX or DY input, or by the slice inputs bypass- able-tap shift register element. ing the function generators via the BX or BY input. The clock enable signal (CE) is active High by default. If left The output from the function generator in each slice drives unconnected, the clock enable for that storage element both the slice output and the D input of the storage element. defaults to the active state. Figure 16 shows a more detailed view of a single slice. In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR and BY slice inputs). SR forces the storage element into the state speci- RAM16 ORCY fied by the attribute SRHIGH or SRLOW. SRHIGH forces a MUXFx logic “1” when SR is asserted. SRLOW forces a logic “0”. When SR is used, a second input (BY) forces the storage SRL16 element into the opposite state. The reset condition is pre- CY Register LUT dominant over the set condition. (See Figure 17.) G The initial state after configuration or global initial state is RAM16 defined by a separate INIT0 and INIT1 attribute. By default, MUXF5 setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. For each slice, set and reset SRL16 can be set to be synchronous or asynchronous. Virtex-II Register CY LUT devices also have the ability to set INIT0 and INIT1 inde- F pendent of SRHIGH and SRLOW. Arithmetic Logic The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage elements in one DS031_31_100900 slice. All of the control signals have independent polarity. Any Figure 15: Virtex-II Slice Configuration inverter placed on a control input is automatically absorbed. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 12 R Virtex-II Platform FPGAs: Functional Description SHIFTIN COUT ORCY SOPIN SOPOUT 0 Dual-Port YBMUX YB Shift-Reg MUXCY 1 A4 G4 1 0 LUT A3 G3 RAM A2 G2 ROM A1 G1 D GYMUX WG4 WG4 Y G WG3 WG3 WG2 WG2 DY MC15 XORG WG1 WG1 FF WS DI LATCH ALTDIG DYMUX DQ G2 Q PROD Y MULTAND G1 CE CE CYOG CLK CK BY 1 SR REV 0 BY SLICEWE[2:0] WSG SHIFTOUT SR WE[2:0] DIG WE CLK MUXCY 0 1 WSF CE Shared between CLK x & y Registers SR CIN DS031_01_112502 Figure 16: Virtex-II Slice (Top Half) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 13 R Virtex-II Platform FPGAs: Functional Description Distributed SelectRAM memory modules are synchronous FFY (write) resources. The combinatorial read access time is FF extremely fast, while the synchronous write simplifies LATCH high-speed designs. A synchronous read can be imple- DY mented with a storage element in the same slice. The dis- YQ DQ tributed SelectRAM memory and the storage element share Attribute CE the same clock input. A Write Enable (WE) input is active INIT1 CK High, and is driven by the SR input. INIT0 SR REV Table 9 shows the number of LUTs (2 per slice) occupied SRHIGH BY SRLOW by each distributed SelectRAM configuration. FFX Table 9: Distributed SelectRAM Configurations FF LATCH RAM Number of LUTs DX D Q XQ 16 x 1S 1 Attribute CE CE 16 x 1D 2 INIT1 CK CLK INIT0 SR REV 32 x 1S 2 SRHIGH SRLOW 32 x 1D 4 SR Reset Type 64 x 1S 4 SYNC BX 64 x 1D 8 ASYNC DS031_22_110600 128 x 1S 8 Figure 17: Register / Latch Configuration in a Slice Notes: 1. S = single-port configuration; D = dual-port configuration The set and reset functionality of a register or a latch can be configured as follows: For single-port configurations, distributed SelectRAM mem-No set or reset ory has one address port for synchronous writes and asyn-Synchronous set chronous reads. Synchronous reset Synchronous set and reset For dual-port configurations, distributed SelectRAM mem- Asynchronous set (preset) ory has one port for synchronous writes and asynchronous Asynchronous reset (clear) reads and another port for asynchronous reads. The func- tion generator (LUT) has separated read address inputsAsynchronous set and reset (preset and clear) (A1, A2, A3, A4) and write address inputs (WG1/WF1, The synchronous reset has precedence over a set, and an WG2/WF2, WG3/WF3, WG4/WF4). asynchronous clear has precedence over a preset. In single-port mode, read and write addresses share the Distributed SelectRAM Memory same address bus. In dual-port mode, one function genera- Each function generator (LUT) can implement a 16 x 1-bit tor (R/W port) is connected with shared read and write synchronous RAM resource called a distributed SelectRAM addresses. The second function generator has the A inputs element. The SelectRAM elements are configurable within (read) connected to the second read-only port address and a CLB to implement the following: the W inputs (write) shared with the first read/write port address.Single-Port 16 x 8 bit RAM Single-Port 32 x 4 bit RAM Single-Port 64 x 2 bit RAM Single-Port 128 x 1 bit RAM Dual-Port 16 x 4 bit RAM Dual-Port 32 x 2 bit RAM Dual-Port 64 x 1 bit RAM DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 14 R Virtex-II Platform FPGAs: Functional Description Figure 18, Figure 19, and Figure 20 illustrate various exam- ple configurations. RAM 16x1D RAM 16x1S dual_port RAM 4 DPRA[3:0] G[4:1] D DPO 4 RAM A[3:0] WG[4:1] 4 D Output A[3:0] A[4:1] WS DI 4 WG[4:1] Registered (BY) D Q D Output WS DI (BY) WSG D (optional) WSG WE CK (SR) WE WE WCLK CK dual_port RAM DS031_02_100900 4 A[3:0] G[4:1] D SPO Figure 18: Distributed SelectRAM (RAM16x1S) WG[4:1] WS DI RAM 32x1S WSG (BX) A[4] (SR) RAM WE WE 4 WCLK CK D A[3:0] G[4:1] WG[4:1] WS DI DS031_04_110100 (BY) D Figure 20: Dual-Port Distributed SelectRAM WSG (RAM16x1D) WE0 (SR) Output WE WE WCLK CK Similar to the RAM configuration, each function generator Registered D Q F5MUX WSF Output (LUT) can implement a 16 x 1-bit ROM. Five configurations are available: ROM16x1, ROM32x1, ROM64x1, WS DI ROM128x1, and ROM256x1. The ROM elements are cas- RAM (optional) D 4 cadable to implement wider or/and deeper ROM. ROM con- F[4:1] tents are loaded at configuration. Table 10 shows the WF[4:1] number of LUTs occupied by each configuration. Table 10: ROM Configuration DS031_03_110100 ROM Number of LUTs Figure 19: Single-Port Distributed SelectRAM 16 x 1 1 (RAM32x1S) 32 x 1 2 64 x 1 4 128 x 1 8 (1 CLB) 256 x 1 16 (2 CLBs) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 15 R Virtex-II Platform FPGAs: Functional Description Shift Registers Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a 1 Shift Chain in CLB clock input (CLK) and an optional clock enable, as shown in DI D IN FF Figure 21. A dynamic read access is performed through the SRLC16 4-bit address bus, A[3:0]. The configurable 16-bit shift reg- MC15 ister cannot be set or reset. The read is asynchronous, how- ever the storage element or flip-flop is available to DI implement a synchronous read. The storage element D FF SRLC16 should always be used with a constant address. For exam- MC15 ple, when building an 8-bit shift register and configuring the SLICE S3 addresses to point to the 7th bit, the 8th bit can be the SHIFTOUT flip-flop. The overall system performance is improved by using the superior clock-to-out of the flip-flops. SHIFTIN DI D FF SRLC16 SRLC16 SHIFTIN MC15 SHIFT-REG 4 DI D Output D FF A[3:0] A[4:1] SRLC16 MC15 Registered MC15 D Q Output SLICE S2 WS DI D(BY) SHIFTOUT (optional) WSG CE (SR) WE SHIFTIN CLK CK DI D FF SRLC16 MC15 SHIFTOUT DS031_05_110600 Figure 21: Shift Register Configurations DI D FF SRLC16 An additional dedicated connection between shift registers MC15 SLICE S1 allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary LUT output. (See SHIFTOUT Figure 22.) Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining SHIFTIN and the MUXF5, MUXF6, and MUXF7 multiplexers allow up DI D to a 128-bit shift register with addressable access to be FF SRLC16 implemented in one CLB. MC15 DI D FF SRLC16 MC15 SLICE S0 CLB OUT CASCADABLE OUT DS031_06_110200 Figure 22: Cascadable Shift Register DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 16 R Virtex-II Platform FPGAs: Functional Description Multiplexers Each Virtex-II slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX multiplexer implements Virtex-II function generators and associated multiplexers the MUXF6, MUXF7, or MUXF8, as shown in Figure 23. can implement the following: Each CLB element has two MUXF6 multiplexers, one 4:1 multiplexer in one slice MUXF7 multiplexer and one MUXF8 multiplexer. Examples 8:1 multiplexer in two slices of multiplexers are shown in the Virtex-II Platform FPGA 16:1 multiplexer in one CLB element (4 slices) User Guide. Any LUT can implement a 2:1 multiplexer. 32:1 multiplexer in two CLB elements (8 slices) MUXF8 combines G Slice S3 the two MUXF7 outputs (Two CLBs) F MUXF6 combines the two MUXF5 G Slice S2 outputs from slices S2 and S3 F MUXF7 combines the two MUXF6 G Slice S1 outputs from slices S0 and S2 F MUXF6 combines the two MUXF5 G Slice S0 outputs from slices S0 and S1 F CLB DS031_08_100201 Figure 23: MUXF5 and MUXFX multiplexers Fast Lookahead Carry Logic be used to cascade function generators for implementing wide logic functions. Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II CLB has two separate carry Arithmetic Logic chains, as shown in the Figure 24. The arithmetic logic includes an XOR gate that allows a The height of the carry chains is two bits per slice. The carry 2-bit full adder to be implemented within a slice. In addition, chain in the Virtex-II device is running upward. The dedi- a dedicated AND (MULT_AND) gate (shown in Figure 16) cated carry path and carry multiplexer (MUXCY) can also improves the efficiency of multiplier implementation. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 17 F5 F5 F6 F7 F5 F5 F6 F8 R Virtex-II Platform FPGAs: Functional Description COUT COUT to S0 of the next CLB to CIN of S2 of the next CLB MUXCY OI FF LUT (First Carry Chain) SLICE S3 MUXCY OI FF LUT CIN COUT MUXCY OI FF LUT SLICE S2 MUXCY OI FF MUXCY LUT OI FF LUT SLICE S1 MUXCY OI FF LUT CIN COUT (Second Carry Chain) MUXCY OI FF LUT SLICE S0 MUXCY OI FF LUT CIN CIN CLB DS031_07_110200 Figure 24: Fast Carry Logic Path DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 18 R Virtex-II Platform FPGAs: Functional Description Sum of Products large, flexible SOP chains. One input of each ORCY is con- nected through the fast SOP chain to the output of the previ- Each Virtex-II slice has a dedicated OR gate named ORCY, ous ORCY in the same slice row. The second input is ORing together outputs from the slices carryout and the ORCY connected to the output of the top MUXCY in the same slice, from an adjacent slice. The ORCY gate with the dedicated as shown in Figure 25. Sum of Products (SOP) chain are designed for implementing ORCY ORCY ORCY ORCY SOP 4 4 4 4 LUT LUT LUT LUT MUXCY MUXCY MUXCY MUXCY Slice 1 Slice 3 Slice 1 Slice 3 4 4 4 4 LUT LUT LUT LUT MUXCY MUXCY MUXCY MUXCY 4 4 4 4 LUT LUT LUT LUT MUXCY MUXCY MUXCY MUXCY Slice 0 Slice 2 Slice 0 Slice 2 4 4 4 4 LUT LUT LUT LUT MUXCY MUXCY MUXCY MUXCY V V V V CC CC CC CC CLB CLB ds031_64_110300 Figure 25: Horizontal Cascade Chain LUTs and MUXCYs can implement large AND gates or LUT and MUXCY resources configured as a 16-input AND other combinatorial logic functions. Figure 26 illustrates gate. OUT 4 MUXCY 01 LUT “0” Slice 4 MUXCY 01 LUT “0” 16 AND OUT 4 MUXCY 01 LUT “0” Slice 4 MUXCY 01 LUT V CC DS031_41_110600 Figure 26: Wide-Input AND Gate (16 Inputs) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 19 R Virtex-II Platform FPGAs: Functional Description Locations / Organization 3-State Buffers Four horizontal routing resources per CLB are provided for Introduction on-chip 3-state busses. Each 3-state buffer has access Each Virtex-II CLB contains two 3-state drivers (TBUFs) alternately to two horizontal lines, which can be partitioned that can drive on-chip busses. Each 3-state buffer has its as shown in Figure 28. The switch matrices corresponding own 3-state control pin and its own input pin. to SelectRAM memory and multiplier or I/O blocks are Each of the four slices have access to the two 3-state buff- skipped. ers through the switch matrix, as shown in Figure 27. Number of 3-State Buffers TBUFs in neighboring CLBs can access slice outputs by Table 11 shows the number of 3-state buffers available in direct connects. The outputs of the 3-state buffers drive hor- each Virtex-II device. The number of 3-state buffers is twice izontal routing resources used to implement 3-state busses. the number of CLB elements. Table 11: Virtex-II 3-State Buffers TBUF 3-State Buffers Total Number Device per Row of 3-State Buffers TBUF Slice S3 XC2V40 16 128 Switch Slice XC2V80 16 256 Matrix S2 XC2V250 32 768 Slice S1 XC2V500 48 1,536 Slice XC2V1000 64 2,560 S0 XC2V1500 80 3,840 DS031_37_060700 XC2V2000 96 5,376 Figure 27: Virtex-II 3-State Buffers XC2V3000 112 7,168 The 3-state buffer logic is implemented using AND-OR logic XC2V4000 144 11,520 rather than 3-state drivers, so that timing is more predict- XC2V6000 176 16,896 able and less load dependant especially with larger devices. XC2V8000 208 23,296 3 - state lines Programmable Switch Switch connection matrix matrix CLB-II CLB-II DS031_09_032700 Figure 28: 3-State Buffer Connection to Horizontal Lines CLB/Slice Configurations Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be implemented in one of the configurations listed. Table 13 shows the available resources in all CLBs. Table 12: Logic Resources in One CLB Arithmetic & SOP Distributed Shift Slices LUTs Flip-Flops MULT_ANDs Carry-Chains Chains SelectRAM Registers TBUF 4 8 8 8 2 2 128 bits 128 bits 2 DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 20 R Virtex-II Platform FPGAs: Functional Description Table 13: Virtex-II Logic Resources Available in All CLBs CLB Array: Number Number Max Distributed Number Number Number Row x of of SelectRAM or Shift of of of SOP (1) (1) Device Column Slices LUTs Register (bits) Flip-Flops Carry-Chains Chains XC2V40 8 x 8 256 512 8,192 512 16 16 XC2V80 16 x 8 512 1,024 16,384 1,024 16 32 XC2V250 24 x 16 1,536 3,072 49,152 3,072 32 48 XC2V500 32 x 24 3,072 6,144 98,304 6,144 48 64 XC2V1000 40 x 32 5,120 10,240 163,840 10,240 64 80 XC2V1500 48 x 40 7,680 15,360 245,760 15,360 80 96 XC2V2000 56 x 48 10,752 21,504 344,064 21,504 96 112 XC2V3000 64 x 56 14,336 28,672 458,752 28,672 112 128 XC2V4000 80 x 72 23,040 46,080 737,280 46,080 144 160 XC2V6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192 XC2V8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224 Notes: 1. The carry-chains and SOP chains can be split or cascaded. tions for single- and dual-port modes are shown in 18 Kbit Block SelectRAM Resources Table 14. Introduction Table 14: Dual- and Single-Port Configurations Virtex-II devices incorporate large amounts of 18 Kbit block 16K x 1 bit 2K x 9 bits SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures imple- 8K x 2 bits 1K x 18 bits mented in CLBs. Each Virtex-II block SelectRAM is an 18 4K x 4 bits 512 x 36 bits Kbit true dual-port RAM with two independently clocked and independently controlled synchronous ports that access a Single-Port Configuration common storage area. Both ports are functionally identical. CLK, EN, WE, and SSR polarities are defined through con- As a single-port RAM, the block SelectRAM has access to figuration. the 18 Kbit memory locations in any of the 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit Each port has the following types of inputs: Clock and Clock memory locations in any of the 16K x 1-bit, 8K x 2-bit, or Enable, Write Enable, Set/Reset, and Address, as well as 4K x 4-bit configurations. The advantage of the 9-bit, 18-bit separate Data/parity data inputs (for write) and Data/parity and 36-bit widths is the ability to store a parity bit for each data outputs (for read). eight bits. Parity bits must be generated or checked exter- Operation is synchronous; the block SelectRAM behaves nally in user logic. In such cases, the width is viewed as 8 + like a register. Control, address and data inputs must (and 1, 16 + 2, or 32 + 4. These extra parity bits are stored and need only) be valid during the set-up time window prior to a behave exactly as the other bits, including the timing rising (or falling, a configuration option) clock edge. Data parameters. Video applications can use the 9-bit ratio of outputs change as a result of the same clock edge. Virtex-II block SelectRAM memory to advantage. Configuration Each block SelectRAM cell is a fully synchronous memory The Virtex-II block SelectRAM supports various configura- as illustrated in Figure 29. Input data bus and output data tions, including single- and dual-port RAM and various bus widths are identical. data/address aspect ratios. Supported memory configura- DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 21 R Virtex-II Platform FPGAs: Functional Description Dual-Port Configuration 18 Kbit Block SelectRAM As a dual-port RAM, each port of block SelectRAM has access to a common 18 Kbit memory resource. These are DI fully synchronous ports with independent control signals for DIP each port. The data widths of the two ports can be config- ADDR ured independently, providing built-in bus-width conversion. WE Table 15 illustrates the different configurations available on EN ports A and B. SSR DO DOP CLK If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18 Kbit block is accessi- DS031_10_071602 ble from port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the Figure 29: 18 Kbit Block SelectRAM Memory in 16 K-bit block is accessible from Port A or Port B. All other Single-Port Mode configurations result in one port having access to an 18 Kbit memory block and the other port having access to a 16 K-bit subset of the memory block equal to 16 Kbits. Table 15: Dual-Port Mode Configurations Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2 Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 4K x 4 4K x 4 4K x 4 4K x 4 Port B 4K x 4 2K x 9 1K x 18 512 x 36 Port A 2K x 9 2K x 9 2K x 9 Port B 2K x 9 1K x 18 512 x 36 Port A 1K x 18 1K x 18 Port B 1K x 18 512 x 36 Port A 512 x 36 Port B 512 x 36 DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 22 R Virtex-II Platform FPGAs: Functional Description Each block SelectRAM cell is a fully synchronous memory, falling clock edge causes the data to be loaded into the as illustrated in Figure 30. The two ports have independent memory cell addressed. inputs and outputs and are independently clocked. A write operation performs a simultaneous read operation. Three different options are available, selected by configura- 18 Kbit Block SelectRAM tion: DIA 1. “WRITE_FIRST” DIPA The “WRITE_FIRST” option is a transparent mode. The ADDRA same clock edge that writes the data input (DI) into the WEA memory also transfers DI into the output registers DO ENA as shown in Figure 31. SSRA DOA DOPA CLKA Internal Data_in DO DI Data_out = Data_in Memory DIB DIPB ADDRB CLK WEB ENB WE SSRB DOB CLKB DOPB Data_in New DS031_11_071602 Address aa Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode RAM Contents Old New Port Aspect Ratios Data_out New Table 16 shows the depth and the width aspect ratios for the DS031_14_102000 18 Kbit block SelectRAM. Virtex-II block SelectRAM also includes dedicated routing resources to provide an efficient Figure 31: WRITE_FIRST Mode interface with CLBs, block SelectRAM, and multipliers. 2. “READ_FIRST” Table 16: 18 Kbit Block SelectRAM Port Aspect Ratio The “READ_FIRST” option is a read-before-write Width Depth Address Bus Data Bus Parity Bus mode. 1 16,384 ADDR[13:0] DATA[0] N/A The same clock edge that writes data input (DI) into the 2 8,192 ADDR[12:0] DATA[1:0] N/A memory also transfers the prior content of the memory cell addressed into the data output registers DO, as 4 4,096 ADDR[11:0] DATA[3:0] N/A shown in Figure 32. 9 2,048 ADDR[10:0] DATA[7:0] Parity[0] 18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0] Internal Data_in DO DI Prior stored data 36 512 ADDR[8:0] DATA[31:0] Parity[3:0] Memory Read/Write Operations CLK The Virtex-II block SelectRAM read operation is fully syn- chronous. An address is presented, and the read operation WE is enabled by control signals WEA and WEB in addition to Data_in New ENA or ENB. Then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into Address aa output registers. RAM Contents Old New The write operation is also fully synchronous. Data and address are presented, and the write operation is enabled Data_out Old by control signals WEA or WEB in addition to ENA or ENB. DS031_13_102000 Then, again depending on the clock input mode, a rising or Figure 32: READ_FIRST Mode DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 23 R Virtex-II Platform FPGAs: Functional Description 3. “NO_CHANGE” Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the output register The “NO_CHANGE” option maintains the content of the value after device configuration (INIT) and SSR is asserted output registers, regardless of the write operation. The (SRVAL). Both attributes (INIT_B and SRVAL) are available clock edge during the write mode has no effect on the for each port when a block SelectRAM resource is config- content of the data output register DO. When the port is ured as dual-port RAM. configured as “NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown Locations in Figure 33. Virtex-II SelectRAM memory blocks are located in either four or six columns. The number of blocks per column depends of the device array size and is equivalent to the Internal Data_in DO number of CLBs in a column divided by four. Column loca- DI No change during write Memory tions are shown in Table 18. Table 18: SelectRAM Memory Floor Plan CLK SelectRAM Blocks WE Device Columns Per Column Total Data_in New XC2V40 2 2 4 Address aa XC2V80 2 4 8 XC2V250 4 6 24 RAM Contents Old New XC2V500 4 8 32 Data_out Last Read Cycle Content (no change) XC2V1000 4 10 40 DS031_12_102000 XC2V1500 4 12 48 Figure 33: NO_CHANGE Mode XC2V2000 4 14 56 Control Pins and Attributes XC2V3000 6 16 96 Virtex-II SelectRAM memory has two independent ports with the control signals described in Table 17. All control XC2V4000 6 20 120 inputs including the clock have an optional inversion. XC2V6000 6 24 144 Table 17: Control Functions XC2V8000 6 28 168 Control Signal Function CLK Read and Write Clock EN Enable affects Read, Write, Set, Reset WE Write Enable SSR Set DO register to SRVAL (attribute) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 24 R Virtex-II Platform FPGAs: Functional Description SelectRAM Blocks SelectRAM Blocks SelectRAM Blocks ds031_38_101000 Figure 34: Block SelectRAM (2-column, 4-column, and 6-column) Table 19: Virtex-II SelectRAM Memory Available Total Amount of SelectRAM Memory Table 19 shows the amount of block SelectRAM memory Total SelectRAM Memory available for each Virtex-II device. The 18 Kbit SelectRAM Device Blocks in Kbits in Bits blocks are cascadable to implement deeper or wider single- or dual-port memory resources. XC2V3000 96 1,728 1,769,472 Table 19: Virtex-II SelectRAM Memory Available XC2V4000 120 2,160 2,211,840 Total SelectRAM Memory XC2V6000 144 2,592 2,654,208 Device Blocks in Kbits in Bits XC2V8000 168 3,024 3,096,576 XC2V40 4 72 73,728 18-Bit x 18-Bit Multipliers XC2V80 8 144 147,456 Introduction XC2V250 24 432 442,368 A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple- XC2V500 32 576 589,824 ment signed multiplier. Virtex-II devices incorporate many embedded multiplier blocks. These multipliers can be asso- XC2V1000 40 720 737,280 ciated with an 18 Kbit block SelectRAM resource or can be XC2V1500 48 864 884,736 used independently. They are optimized for high-speed operations and have a lower power consumption compared XC2V2000 56 1,008 1,032,192 to an 18-bit x 18-bit multiplier in slices. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 25 2 CLB column 2 CLB columns 2 CLB columns 2 CLB column n CLB columns 2 CLB columns n CLB columns 2 CLB columns 2 CLB columns 2 CLB columns n CLB columns n CLB columns 2 CLB columns 2 CLB columns n CLB columns n CLB columns 2 CLB columns 2 CLB columns R Virtex-II Platform FPGAs: Functional Description Each SelectRAM memory and multiplier block is tied to four Configuration switch matrices, as shown in Figure 35. The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-bit-wide inputs, and the output is 36 bits. Figure 36 shows a multiplier block. Switch Multiplier Block Matrix A[17:0] Switch MULT 18 x 18 Matrix P[35:0] 18-Kbit block SelectRAM B[17:0] Switch Matrix DS031_40_100400 Figure 36: Multiplier Block Switch Locations / Organization Matrix Multiplier organization is identical to the 18 Kbit SelectRAM DS031_33_101000 organization, because each multiplier is associated with an 18 Kbit block SelectRAM resource. Figure 35: SelectRAM and Multiplier Blocks In addition to the built-in multiplier blocks, the CLB elements Association With Block SelectRAM Memory have dedicated logic to implement efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs)). The interconnect is designed to allow SelectRAM memory and multiplier blocks to be used at the same time, but some Table 20: Multiplier Floor Plan interconnect is shared between the SelectRAM and the Multipliers multiplier. Thus, SelectRAM memory can be used only up to 18 bits wide when the multiplier is used, because the multi- Device Columns Per Column Total plier shares inputs with the upper data bits of the XC2V40 2 2 4 SelectRAM memory. This sharing of the interconnect is optimized for an XC2V80 2 4 8 18-bit-wide block SelectRAM resource feeding the multi- XC2V250 4 6 24 plier. The use of SelectRAM memory and the multiplier with an accumulator in LUTs allows for implementation of a dig- XC2V500 4 8 32 ital signal processor (DSP) multiplier-accumulator (MAC) XC2V1000 4 10 40 function, which is commonly used in finite and infinite impulse response (FIR and IIR) digital filters. XC2V1500 4 12 48 XC2V2000 4 14 56 XC2V3000 6 16 96 XC2V4000 6 20 120 XC2V6000 6 24 144 XC2V8000 6 28 168 DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 26 18 x 18 Multiplier R Virtex-II Platform FPGAs: Functional Description Multiplier Blocks Multiplier Blocks Multiplier Blocks DS031_39_101000 Figure 37: Multipliers (2-column, 4-column, and 6-column) Global Clock Multiplexer Buffers Virtex-II devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads are on the top edge of the device, in the middle of the array, and eight are 8 clock pads on the bottom edge, as illustrated in Figure 38. The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in Virtex-II devices. Like the clock pads, eight global clock multiplexer Virtex-II buffers are on the top edge of the device and eight are on Device the bottom edge. Each global clock buffer can either be driven by the clock pad to distribute a clock directly to the device, or driven by 8 clock pads the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 29. Each global clock buffer can also be driven by local interconnects. The DCM has DS031_42_022305 clock output(s) that can be connected to global clock buffer Figure 38: Virtex-II Clock Pads inputs, as shown in Figure 39. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 27 2 CLB column 2 CLB columns 2 CLB columns 2 CLB column n CLB columns 2 CLB columns n CLB columns 2 CLB columns 2 CLB columns 2 CLB columns n CLB columns n CLB columns 2 CLB columns 2 CLB columns n CLB columns n CLB columns 2 CLB columns 2 CLB columns R Virtex-II Platform FPGAs: Functional Description Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in Clock Clock Pad Pad CLBs and IOBs, and SelectRAM blocks. I Eight global clocks can be used in each quadrant of the Virtex-II device. Designers should consider the clock distri- CLKIN bution detail of the device prior to pin-locking and floorplan- Clock Buffer ning (see the Virtex-II User Guide). DCM Figure 40 shows clock distribution in Virtex-II devices. CLKOUT In each quadrant, up to eight clocks are organized in clock 0 I rows. A clock row supports up to 16 CLB rows (eight up and Clock Distribution eight down). For the largest devices a new clock row is Clock Buffer added, as necessary. To reduce power consumption, any unused clock branches remain static. 0 Global clocks are driven by dedicated clock buffers (BUFG), which can also be used to gate the clock (BUFGCE) or to mul- Clock Distribution tiplex between two independent clock inputs (BUFGMUX). DS031_43_101000 Figure 39: Virtex-II Clock Distribution Configurations 8 BUFGMUX NE NW 8 8 BUFGMUX NW NE 8 8 max 16 Clocks 16 Clocks 8 8 SE SW SE 8 BUFGMUX SW 8 BUFGMUX DS031_45_120200 Figure 40: Virtex-II Clock Distribution The most common configuration option of this element is as them can be used in either of two modes, selected by con- a buffer. A BUFG function in this (global buffer) mode, is figuration: rising clock edge or falling clock edge. shown in Figure 41. This section describes the rising clock edge option. For the opposite option, falling clock edge, just change all "rising" BUFG references to "falling" and all "High" references to "Low", except for the description of the CE or S levels. The rising I O clock edge option uses the BUFGCE and BUFGMUX prim- itives. The falling clock edge option uses the BUFGCE_1 DS031_61_101200 and BUFGMUX_1 primitives. Figure 41: Virtex-II BUFG Function BUFGCE The Virtex-II global clock buffer BUFG can also be config- If the CE input is active (High) prior to the incoming rising ured as a clock enable/disable circuit (Figure 42), as well as clock edge, this Low-to-High-to-Low clock pulse passes a two-input clock multiplexer (Figure 43). A functional through the clock buffer. Any level change of CE during the description of these two options is provided below. Each of incoming clock High time has no effect. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 28 R Virtex-II Platform FPGAs: Functional Description until CLK1 transitions High to Low. BUFGCE When CLK1 transitions from High to Low, the output switches to CLK1. I O No glitches or short pulses can appear on the output. CE DS031_62_101200 Wait for Low Figure 42: Virtex-II BUFGCE Function S If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through I0 the clock buffer, and the output stays Low. Any level change Switch of CE during the incoming clock High time has no effect. CE I1 must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this OUT setup time requirement can result in an undefined runt pulse output. DS031_46_020604 BUFGMUX Figure 44: Clock Multiplexer Waveform Diagram BUFGMUX can switch between two unrelated, even asyn- chronous clocks. Basically, a Low on S selects the I0 input, Local Clocking a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and In addition to global clocks, there are local clock resources Low time is never shorter than the shortest High or Low time in the Virtex-II devices. There are more than 72 local clocks of either input clock. As long as the presently selected clock in the Virtex-II family. These resources can be used for is High, any level change of S has no effect . many different applications, including but not limited to memory interfaces. For example, even using only the left BUFGMUX and right I/O banks, Virtex-II FPGAs can support up to 50 local clocks for DDR SDRAM. These interfaces can operate I0 beyond 200 MHz on Virtex-II devices. O I1 Digital Clock Manager (DCM) The Virtex-II DCM offers a wide range of powerful clock S management features. DS031_63_112900 Clock De-skew: The DCM generates new system Figure 43: Virtex-II BUFGMUX Function clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, thus If the presently selected clock is Low while S changes, or if eliminating clock distribution delays. it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transitionFrequency Synthesis: The DCM generates a wide from High to Low. At that instant, the new clock starts driv- range of output clock frequencies, performing very ing the output. flexible clock multiplication and division. The two clock inputs can be asynchronous with regard toPhase Shifting: The DCM provides both coarse phase each other, and the S input can change at any time, except shifting and fine-grained phase shifting with dynamic for a short setup time prior to the rising edge of the presently phase shift control. selected clock (I0 or I1). Violating this setup time require- The DCM utilizes fully digital delay lines allowing robust ment can result in an undefined runt pulse output. high-precision control of clock phase and frequency. It also utilizes fully digital feedback systems, operating dynami- All Virtex-II devices have 16 global clock multiplexer buffers. cally to compensate for temperature and voltage variations Figure 44 shows a switchover from I0 to I1. during operation. The current clock is CLK0. Up to four of the nine DCM clock outputs can drive inputs to S is activated High. global clock buffers or global clock multiplexer buffers If CLK0 is currently High, the multiplexer waits for simultaneously (see Figure 45). All DCM clock outputs can CLK0 to go Low. simultaneously drive general routing resources, including Once CLK0 is Low, the multiplexer output stays Low routes to output buffers. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 29 R Virtex-II Platform FPGAs: Functional Description can be generated for board-level routing. All DCM output DCM clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. CLK0 CLKIN To achieve clock de-skew, the CLKFB input must be con- CLK90 CLKFB nected, and its source must be either CLK0 or CLK2X. Note CLK180 that CLKFB must always be connected, unless only the CLKFX CLK270 RST or CLKFX180 outputs are used and de-skew is not required. CLK2X CLK2X180 Frequency Synthesis DSSEN CLKDV The DCM provides flexible methods for generating new PSINCDEC clock frequencies. Each method has a different operating CLKFX PSEN CLKFX180 frequency range and different AC characteristics. The PSCLK CLK2X and CLK2X180 outputs double the clock frequency. LOCKED The CLKDV output creates divided output clocks with divi- STATUS[7:0] sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, clock signal PSDONE 8, 9, 10, 11, 12, 13, 14, 15, and 16. control signal The CLKFX and CLKFX180 outputs can be used to pro- DS031_67_112900 duce clocks at the following frequency: Figure 45: Digital Clock Manager FREQ = (M/D) * FREQ CLKFX CLKIN The DCM can be configured to delay the completion of the where M and D are two integers. Specifications for M and D Virtex-II configuration process until after the DCM has are provided under DCM Timing Parameters in Module 3. achieved lock. This guarantees that the chip does not begin By default, M=4 and D=1, which results in a clock output fre- operating until after the system clocks generated by the quency four times faster than the clock input frequency DCM have stabilized. (CLKIN). The DCM has the following general control signals: CLK2X180 is phase shifted 180 degrees relative to CLK2X. RST input pin : resets the entire DCM CLKFX180 is phase shifted 180 degrees relative to CLKFX. LOCKED output pin: asserted High when all enabled All frequency synthesis outputs automatically have 50/50 DCM circuits have locked. duty cycles (with the exception of the CLKDV output when STATUS output pins (active High): shown in Table 21. performing a non-integer divide in high-frequency mode). Table 21: DCM Status Pins Note that CLK2X and CLK2X180 are not available in high-frequency mode. Status Pin Function 0 Phase Shift Overflow Phase Shifting 1 CLKIN Stopped The DCM provides additional control over clock skew through either coarse or fine-grained phase shifting. The 2 CLKFX Stopped CLK0, CLK90, CLK180, and CLK270 outputs are each 3N/A phase shifted by ¼ of the input clock period relative to each 4N/A other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. 5N/A Fine-phase adjustment affects all nine DCM output clocks. 6N/A When activated, the phase shift between the rising edges of 7N/A CLKIN and CLKFB is a specified fraction of the input clock period. Clock De-Skew In variable mode, the PHASE_SHIFT value can also be The DCM de-skews the output clocks relative to the input dynamically incremented or decremented as determined by clock by automatically adjusting a digital delay line. Addi- PSINCDEC synchronously to PSCLK, when the PSEN tional delay is introduced so that clock edges arrive at inter- input is active. Figure 46 illustrates the effects of fine-phase nal registers and block RAMs simultaneously with the clock shifting. For more information on DCM features, see the edges arriving at the input clock pad. Alternatively, external Virtex-II User Guide. clocks, which are also de-skewed relative to the input clock, DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 30 R Virtex-II Platform FPGAs: Functional Description CLKIN CLKOUT_PHASE_SHIFT = NONE CLKFB CLKIN CLKOUT_PHASE_SHIFT = FIXED CLKFB (PS/256) x PERIOD (PS/256) x PERIOD CLKIN CLKIN (PS negative) (PS positive) CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB (PS/256) x PERIOD (PS/256) x PERIOD CLKIN CLKIN DS031_48_101201 (PS negative) (PS positive) Figure 46: Fine-Phase Shifting Effects Table 22 lists fine-phase shifting control pins, when used in The reason for the difference between fixed and variable variable mode. modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets Table 22: Fine-Phase Shifting Control Pins the "zero phase skew" point as the middle of the delay line, Control Pin Direction Function thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after PSINCDEC in Increment or decrement configuration, the entire delay line is available for insertion PSEN in Enable ± phase shift into either the CLKIN or CLKFB path (to create either posi- PSCLK in Clock for phase shift tive or negative skew). PSDONE out Active when completed Taking both of these components into consideration, the fol- lowing are some usage examples: Two separate components of the phase shift range must be If PERIOD = 2 * FINE_SHIFT_RANGE, then CLKIN understood: PHASE_SHIFT in fixed mode is limited to ± 128, and in PHASE_SHIFT attribute range variable mode it is limited to ± 64. FINE_SHIFT_RANGE DCM timing parameter rangeIf PERIOD = FINE_SHIFT_RANGE, then CLKIN PHASE_SHIFT in fixed mode is limited to ± 255, and in The PHASE_SHIFT attribute is the numerator in the following variable mode it is limited to ± 128. equation: If PERIOD ≤ 0.5 * FINE_SHIFT_RANGE, then CLKIN Phase Shift (ns) = (PHASE_SHIFT/256) * PERIOD CLKIN PHASE_SHIFT is limited to ± 255 in either mode. The full range of this attribute is always -255 to +255, but its Operating Modes practical range varies with CLKIN frequency, as con- strained by the FINE_SHIFT_RANGE component, which rep- The frequency ranges of DCM input and output clocks resents the total delay achievable by the phase shift delay depend on the operating mode specified, either line. Total delay is a function of the number of delay taps low-frequency mode or high-frequency mode, according to used in the circuit. Across process, voltage, and tempera- Table 23. (For actual values, see Virtex-II Switching Char- ture, this absolute range is guaranteed to be as specified acteristics in Module 3). The CLK2X, CLK2X180, CLK90, under DCM Timing Parameters in Module 3. and CLK270 outputs are not available in high-frequency mode. Absolute range (fixed mode) = ± FINE_SHIFT_RANGE High or low-frequency mode is selected by an attribute. Absolute range (variable mode) = ± FINE_SHIFT_RANGE/2 Table 23: DCM Frequency Ranges Low-Frequency Mode High-Frequency Mode Output Clock CLKIN Input CLK Output CLKIN Input CLK Output CLK0, CLK180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF CLK90, CLK270 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF NA NA CLK2X, CLK2X180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF NA NA CLKDV CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF CLKFX, CLKFX180 CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 31 R Virtex-II Platform FPGAs: Functional Description Routing routing resources are segmented to offer the advantages of DCM Locations/Organization a hierarchical solution. Virtex-II logic features like CLBs, Virtex-II DCMs are placed on the top and bottom of each IOBs, block RAM, multipliers, and DCMs are all connected block RAM and multiplier column. The number of DCMs to an identical switch matrix for access to global routing depends on the device size, as shown in Table 24. resources, as shown in Figure 47. Table 24: DCM Organization Device Columns DCMs Switch XC2V40 2 4 Switch Matrix CLB XC2V80 2 4 Matrix XC2V250 4 8 Switch XC2V500 4 8 Matrix XC2V1000 4 8 18Kb MULT Switch IOB BRAM 18 x 18 XC2V1500 4 8 Matrix Switch XC2V2000 4 8 Matrix XC2V3000 6 12 XC2V4000 6 12 Switch DCM Switch Matrix XC2V6000 6 12 Matrix XC2V8000 6 12 DS031_55_022205 Figure 47: Active Interconnect Technology Active Interconnect Technology Local and global Virtex-II routing resources are optimized Each Virtex-II device can be represented as an array of for speed and timing predictability, as well as to facilitate IP switch matrixes with logic blocks attached, as illustrated in cores implementation. Virtex-II Active Interconnect Tech- Figure 48. nology is a fully buffered programmable routing matrix. All Switch Switch Switch Switch Switch IOB IOB IOB DCM Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB Matrix Matrix Matrix Matrix Matrix DS031_34_022205 Figure 48: Routing Resources DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 32 SelectRAM Multiplier R Virtex-II Platform FPGAs: Functional Description Place-and-route software takes advantage of this regular their endpoints. Double-line signals can be accessed array to deliver optimum system performance and fast com- either at the endpoints or at the midpoint (one block from the source). pile times. The segmented routing resources are essential to guarantee IP cores portability and to efficiently handle anThe direct connect lines route signals to neighboring incremental design flow that is based on modular imple- blocks: vertically, horizontally, and diagonally. mentations. Total design time is reduced due to fewer andThe fast connect lines are the internal CLB local shorter design iterations. interconnections from LUT outputs to LUT inputs. Hierarchical Routing Resources Dedicated Routing Most Virtex-II signals are routed using the global routing In addition to the global and local routing resources, dedi- resources, which are located in horizontal and vertical rout- cated signals are available. ing channels between each switch matrix. There are eight global clock nets per quadrant (see As shown in Figure 49, Virtex-II has fully buffered program- Global Clock Multiplexer Buffers). mable interconnections, with a number of resources Horizontal routing resources are provided for on-chip counted between any two adjacent switch matrix rows or 3-state busses. Four partitionable bus lines are columns. Fanout has minimal impact on the performance of provided per CLB row, permitting multiple busses each net. within a row. (See 3-State Buffers.) The long lines are bidirectional wires that distribute Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-chain MUXCY signals across the device. Vertical and horizontal long lines span the full height and width of the device. output signals vertically to the adjacent slice. (See CLB/Slice Configurations.) The hex lines route signals to every third or sixth block away in all four directions. Organized in a staggered One dedicated SOP chain per slice row (two per CLB pattern, hex lines can only be driven from one end. row) propagate ORCY output logic signals horizontally Hex-line signals can be accessed either at the endpoints to the adjacent slice. (See Sum of Products.) or at the midpoint (three blocks from the source). One dedicated shift-chain per CLB connects the output The double lines route signals to every first or second of LUTs in shift-register mode to the input of the next block away in all four directions. Organized in a LUT in shift-register mode (vertically) inside the CLB. staggered pattern, double lines can be driven only at (See Shift Registers, page 16.) 24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines 16 Direct Connections (total in all four directions) 8 Fast Connects Figure 49: Hierarchical Routing Resources DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 33 R Virtex-II Platform FPGAs: Functional Description Creating a Design Creating Virtex-II designs is easy with Xilinx Integrated Syn- To enable designers to leverage existing investments in thesis Environment (ISE) development systems, which sup- EDA tools, and to ensure high performance design flows, port advanced design capabilities, including ProActive Xilinx jointly develops tools with leading EDA vendors, Timing Closure, integrated logic analysis, and the fastest including: place and route runtimes in the industry. ISE solutions ® Aldec enable designers to get the performance they need, quickly ® Cadence and easily. ® Exemplar ® As a result of the ongoing cooperative development effortsMentor Graphics ® between Xilinx and EDA Alliance partners, designers canModel Technology take advantage of the benefits provided by EDA technolo- ® Synopsys gies in the programmable logic design process. Xilinx ® Synplicity development systems are available in a number of easy to Complete information on Alliance Series partners and their use configurations, collectively known as the ISE Series. associated design flows is available at www.xilinx.com on the Xilinx Alliance Series web page. ISE Alliance The ISE Foundation product offers schematic entry and The ISE Alliance solution is designed to plug and play within HDL design capabilities as part of an integrated design an existing design environment. Built using industry standard solution - enabling one-stop shopping. These capabilities data formats and netlists, these stable, flexible products are powerful, easy to use, and they support the full portfolio enable Alliance EDA partners to deliver their best design of Xilinx programmable logic devices. HDL design capabil- automation capabilities to Xilinx customers, along with the ities include a color-coded HDL editor with integrated lan- time to market benefits of ProActive Timing Closure. guage templates, state diagram entry, and Core generation capabilities. ISE Foundation Synthesis The ISE Foundation solution delivers the benefits of true HDL-based design in a seamlessly integrated design envi- The ISE Alliance product is engineered to support ronment. An intuitive project navigator, as well as powerful advanced design flows with the industry's best synthesis HDL design and two HDL synthesis tools, ensure that tools. Advanced design methodologies include: high-quality results are achieved quickly and easily. The Physical Synthesis ISE Foundation product includes: Incremental synthesis State Diagram entry using Xilinx StateCAD RTL floorplanning Automatic HDL Testbench generation using Xilinx Direct physical mapping HDLBencher The ISE Foundation product seamlessly integrates synthesis HDL Simulation using ModelSim XE capabilities purchased directly from Exemplar, Synopsys, and Synplicity. In addition, it includes the capabilities of Xilinx Design Flow Synthesis Technology. Virtex-II design flow proceeds as follows: A benefit of having two seamlessly integrated synthesis Design Entry engines within an ISE design flow is the ability to apply alter- Synthesis native sets of optimization techniques on designs, helping to Implementation ensure that designers can meet even the toughest timing Verification requirements. Most programmable logic designers iterate through these Design Implementation steps several times in the process of completing a design. The ISE Series development systems include Xilinx tim- Design Entry ing-driven implementation tools, frequently called “place and route” or “fitting” software. This robust suite of tools All Xilinx ISE development systems support the mainstream enables the creation of an intuitive, flexible, tightly inte- EDA design entry capabilities, ranging from schematic grated design flow that efficiently bridges “logical” and design to advanced HDL design methodologies. Given the “physical” design domains. This simplifies the task of defin- high densities of the Virtex-II family, designs are created ing a design, including its behavior, timing requirements, most efficiently using HDLs. To further improve their time to and optional layout (or floorplanning), as well as simplifying market, many Xilinx customers employ incremental, modu- the task of analyzing reports generated during the imple- lar, and Intellectual Property (IP) design techniques. When mentation process. properly used, these techniques further accelerate the logic design process. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 34 R Virtex-II Platform FPGAs: Functional Description The Virtex-II implementation process is comprised of Syn- robust capability that is enabled by Xilinx exclusive hierar- thesis, translation, mapping, place and route, and configu- chical floorplanning capabilities. Another powerful design ration file generation. While the tools can be run capability only available in the Xilinx design flow is “Modular individually, many designers choose to run the entire imple- Design”, part of the Xilinx suite of team design tools, which mentation process with the click of a button. To assist those enables autonomous design, implementation, and verifica- who prefer to script their design flows, Xilinx provides Xflow, tion of design modules. an automated single command line process. Incremental Synthesis Design Verification Xilinx unique hierarchical floorplanning capabilities enable In addition to conventional design verification using static designers to create a programmable logic design by isolat- timing analysis or simulation techniques, Xilinx offers pow- ing design changes within one hierarchical “logic block”, and erful in-circuit debugging techniques using ChipScope ILA perform synthesis, verification and implementation pro- (Integrated Logic Analysis). The reconfigurable nature of cesses on that specific logic block. By preserving the logic in Xilinx FPGAs means that designs can be verified in real unchanged portions of a design, Xilinx incremental design time without the need for extensive sets of software simula- makes the high-density design process more efficient. tion vectors. Xilinx hierarchical floorplanning capabilities can be speci- For simulation, the system extracts post-layout timing infor- fied using the high-level floorplanner or a preferred RTL mation from the design database, and back-annotates this floorplanner (see the Xilinx web site for a list of supported information into the netlist for use by the simulator. The EDA partners). When used in conjunction with one of the back annotation features a variety of patented Xilinx tech- EDA partners’ floorplanners, higher performance results niques, resulting in the industry’s most powerful simulation can be achieved, as many synthesis tools use this more flows. Alternatively, timing-critical portions of a design can predictable detailed physical implementation information to be verified using the Xilinx static timing analyzer or a third establish more aggressive and accurate timing estimates party static timing analysis tool like Synopsys Prime when performing their logic optimizations. Time™, by exporting timing data in the STAMP data format. Modular Design For in-circuit debugging, ChipScope ILA enables designers Xilinx innovative modular design capabilities take the incre- to analyze the real-time behavior of a device while operat- mental design process one step further by enabling the ing at full system speeds. Logic analysis commands and designer to delegate responsibility for completing the captured data are transferred between the ChipScope soft- design, synthesis, verification, and implementation of a ware and ILA cores within the Virtex-II FPGA, using industry hierarchical “logic block” to an arbitrary number of design- standard JTAG protocols. These JTAG transactions are ers - assigning a specific region within the target FPGA for driven over an optional download cable (MultiLINX or exclusive use by each of the team members. JTAG), connecting the Virtex device in the target system to This team design capability enables an autonomous a PC or workstation. approach to design modules, changing the hand-off point to ChipScope ILA was designed to look and feel like a logic the lead designer or integrator from “my module works in analyzer, making it easy to begin debugging a design simulation” to “my module works in the FPGA”. This unique immediately. Modifications to the desired logic analysis can design methodology also leverages the Xilinx hierarchical be downloaded directly into the system in a matter of min- floorplanning capabilities and enables the Xilinx (or EDA utes. partner) floorplanner to manage the efficient implementa- Other Unique Features of Virtex-II Design Flow tion of very high-density FPGAs. Xilinx design flows feature a number of unique capabilities. Among these are efficient incremental HDL design flows; a DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 35 R Virtex-II Platform FPGAs: Functional Description Configuration Virtex-II devices are configured by loading application spe- DIN input pin a short time before each rising edge of the cific configuration data into the internal configuration mem- externally generated CCLK. ory. Configuration is carried out using a subset of the device Multiple FPGAs can be daisy-chained for configuration from pins, some of which are dedicated, while others can be a single source. After a particular FPGA has been config- re-used as general purpose inputs and outputs once config- ured, the data for the next device is routed internally to the uration is complete. DOUT pin. The data on the DOUT pin changes on the fall- Depending on the system design, several configuration ing edge of CCLK. modes are supported, selectable via mode pins. The mode Slave-serial mode is selected by applying <111> to the pins M2, M1 and M0 are dedicated pins. The M2, M1, and mode pins (M2, M1, M0). A weak pull-up on the mode pins M0 mode pins should be set at a constant DC voltage level, makes slave serial the default mode if the pins are left either through pull-up or pull-down resistors, or tied directly unconnected. to ground or V . The mode pins should not be toggled CCAUX Master-Serial Mode during and after configuration. In master-serial mode, the CCLK pin is an output pin. It is An additional pin, HSWAP_EN is used in conjunction with the Virtex-II FPGA device that drives the configuration clock the mode pins to select whether user I/O pins have pull-ups on the CCLK pin to a Xilinx Serial PROM which in turn feeds during configuration. By default, HSWAP_EN is tied High bit-serial data to the DIN input. The FPGA accepts this data (internal pull-up) which shuts off the pull-ups on the user I/O on each rising CCLK edge. After the FPGA has been pins during configuration. When HSWAP_EN is tied Low, loaded, the data for the next device in a daisy-chain is pre- user I/Os have pull-ups during configuration. Other dedi- sented on the DOUT pin after the falling CCLK edge. cated pins are CCLK (the configuration clock pin), DONE, PROG_B, and the boundary-scan pins: TDI, TDO, TMS, The interface is identical to slave serial except that an inter- and TCK. Depending on the configuration mode chosen, nal oscillator is used to generate the configuration clock CCLK can be an output generated by the FPGA, or an input (CCLK). A wide range of frequencies can be selected for accepting an externally generated clock. The configuration CCLK which always starts at a slow default frequency. Con- pins and boundary scan pins are independent of the V . CCO figuration bits then switch CCLK to a higher frequency for The auxiliary power supply (V ) of 3.3V is used for CCAUX the remainder of the configuration. these pins. All configuration pins are LVTTL 12 mA. (See Slave SelectMAP Mode Virtex-II DC Characteristics in Module 3.) The SelectMAP mode is the fastest configuration option. A persist option is available which can be used to force the Byte-wide data is written into the Virtex-II FPGA device with configuration pins to retain their configuration function even a BUSY flag controlling the flow of data. An external data after device configuration is complete. If the persist option is source provides a byte stream, CCLK, an active Low Chip not selected then the configuration pins with the exception Select (CS_B) signal and a Write signal (RDWR_B). If of CCLK, PROG_B, and DONE can be used as user I/O in BUSY is asserted (High) by the FPGA, the data must be normal operation. The persist option does not apply to the held until BUSY goes Low. Data can also be read using the boundary-scan related pins. The persist feature is valuable SelectMAP mode. If RDWR_B is asserted, configuration in applications which employ partial reconfiguration or data is read out of the FPGA as part of a readback opera- reconfiguration on the fly. tion. Configuration Modes After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be Virtex-II supports the following five configuration modes: retained to permit high-speed 8-bit readback using the per- Slave-Serial Mode sist option. Master-Serial Mode Multiple Virtex-II FPGAs can be configured using the Slave SelectMAP Mode SelectMAP mode, and be made to start-up simultaneously. Master SelectMAP Mode To configure multiple devices in this way, wire the individual Boundary-Scan (JTAG, IEEE 1532) Mode CCLK, Data, RDWR_B, and BUSY pins of all the devices in A detailed description of configuration modes is provided in parallel. The individual devices are loaded separately by the Virtex-II User Guide. deasserting the CS_B pin of each device in turn and writing the appropriate data. Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data Master SelectMAP Mode in bit-serial form from a serial PROM or other serial source This mode is a master version of the SelectMAP mode. The of configuration data. The CCLK pin on the FPGA is an device is configured byte-wide on a CCLK supplied by the input in this mode. The serial bitstream must be setup at the DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 36 R Virtex-II Platform FPGAs: Functional Description Virtex-II FPGA device. Timing is similar to the Slave Serial- dard for In-System Configurable (ISC) devices. The IEEE MAP mode except that CCLK is supplied by the Virtex-II 1532 standard is backward compliant with the IEEE FPGA. 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-System Configurable (ISC) devices is intended Boundary-Scan (JTAG, IEEE 1532) Mode to be programmed, reprogrammed, or tested on the board In boundary-scan mode, dedicated pins are used for config- via a physical and logical protocol. uring the Virtex-II device. The configuration is done entirely Configuration through the boundary-scan port is always through the IEEE 1149.1 Test Access Port (TAP). Virtex-II available, independent of the mode selection. Selecting the device configuration using Boundary scan is compliant with boundary-scan mode simply turns off the other modes. IEEE 1149.1-1993 standard and the new IEEE 1532 stan- Table 25: Virtex-II Configuration Mode Pin Settings (1) (2) Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial D OUT Master Serial 0 0 0 Out 1 Yes Slave Serial 1 1 1 In 1 Yes Master SelectMAP 011 Out 8 No Slave SelectMAP 1 1 0 In 8 No Boundary Scan 1 0 1 N/A 1 No Notes: 1. The HSWAP_EN pin controls the pull-ups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pull-ups are used. 2. Daisy chaining is possible only in modes where Serial D is used. For example, in SelectMAP modes, the first device does NOT OUT support daisy chaining of downstream devices. Table 26 lists the total number of bits required to configure and V (bank 4) is greater than 1.5V. Once the POR CCO each device. voltages have been reached, the three-phase process begins. Table 26: Virtex-II Bitstream Lengths First, the configuration memory is cleared. Next, con- Device # of Configuration Bits figuration data is loaded into the memory, and finally, the XC2V40 338,976 logic is activated by a start-up process. Configuration is automatically initiated on power-up unless XC2V80 598,816 it is delayed by the user. The INIT_B pin can be held Low XC2V250 1,593,632 using an open-drain driver. An open-drain is required since INIT_B is a bidirectional open-drain pin that is held Low by a XC2V500 2,560,544 Virtex-II FPGA device while the configuration memory is XC2V1000 4,082,592 being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is XC2V1500 5,170,208 delayed by preventing entry into the phase where data is loaded. XC2V2000 6,812,960 The configuration process can also be initiated by asserting XC2V3000 10,494,368 the PROG_B pin. The end of the memory-clearing phase is XC2V4000 15,659,936 signaled by the INIT_B pin going High, and the completion of the entire process is signaled by the DONE pin going XC2V6000 21,849,504 High. The Global Set/Reset (GSR) signal is pulsed after the last frame of configuration data is written but before the XC2V8000 26,194,208 start-up sequence. The GSR signal resets all flip-flops on the device. Configuration Sequence The default start-up sequence is that one CCLK cycle after The configuration of Virtex-II devices is a three-phase pro- DONE goes High, the global 3-state signal (GTS) is cess after Power On Reset or POR. POR occurs when released. This permits device outputs to turn on as neces- V is greater than 1.2V, V is greater than 2.5V, CCINT CCAUX sary. One CCLK cycle later, the Global Write Enable (GWE) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 37 R Virtex-II Platform FPGAs: Functional Description signal is released. This permits the internal storage ele- The keys are stored in the FPGA by JTAG instruction and ments to begin changing state in response to the logic and retained by a battery connected to the V pin, when the BATT the user clock. device is not powered. Virtex-II devices can be configured with the corresponding encrypted bitstream, using any of The relative timing of these events can be changed via con- the configuration modes described previously. figuration options in software. In addition, the GTS and GWE events can be made dependent on the DONE pins of A detailed description of how to use bitstream encryption is multiple devices all going High, forcing the devices to start provided in the Virtex-II Platform FPGA User Guide. For synchronously. The sequence can also be paused at any devices that support this feature, please contact your sales stage, until lock has been achieved on any or all DCMs, as representative for specific ordering part number. well as the DCI. Partial Reconfiguration Readback Partial reconfiguration of Virtex-II devices can be accom- In this mode, configuration data from the Virtex-II FPGA plished in either Slave SelectMAP mode or Boundary-Scan device can be read back. Readback is supported only in the mode. Instead of resetting the chip and doing a full configu- SelectMAP (master and slave) and Boundary Scan mode. ration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. Data is Along with the configuration data, it is possible to read back loaded on a column basis, with the smallest load unit being the contents of all registers, distributed SelectRAM, and a configuration “frame” of the bitstream (device size depen- block RAM resources. This capability is used for real-time dent). debugging. For more detailed configuration information, see the Virtex-II Platform FPGA User Guide. Partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, Bitstream Encryption or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. Virtex-II devices have an on-chip decryptor using one or two sets of three keys for triple-key Data Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the configuration data (bitstream) with a tri- ple-key DES determined by the designer. Revision History This section records the change history for this module of the data sheet. Date Version Revision 11/07/00 1.0 Early access draft. 12/06/00 1.1 Initial release. Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II 01/15/01 1.2 Switching Characteristics sections. The data sheet was divided into four modules (per the current style standard). A note was 01/25/01 1.3 added to Table 1. Under Input/Output Individual Options, the range of values for optional pull-up and pull-down resistors was changed to 10 - 60 KΩ from 50 - 100 KΩ. 04/02/01 1.5 Skipped v1.4 to sync up modules. Reverted to traditional double-column format. Added Table 6 . Changed definition of multiply and divide integer ranges under Digital Clock Manager 07/30/01 1.6 (DCM). Made numerous minor edits throughout this module. Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock 10/02/01 1.7 Multiplexer Buffers, Digital Clock Manager (DCM), and Creating a Design. 10/12/01 1.8Made clarifying edits under Digital Clock Manager (DCM). DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 38 R Virtex-II Platform FPGAs: Functional Description Date Version Revision 11/29/01 1.9Changed bitstream lengths for each device in Table 26. 07/16/02 2.0Updated compatible input standards listed in Table 6. Changed number of resources available to the XC2V40 device in Table 13. 09/26/02 2.1 Clarified Power On Reset information under Configuration Sequence. 12/06/02 2.1.1Cosmetic edits. Added qualification note to Figure 13, page 11. Corrected sentence in section Input/Output Individual Options, page 4, to read “The 05/07/03 2.1.2 optional weak-keeper circuit is connected to each user I/O pad.” Corrected typographical errors in Table 3 for names of HSTL_[x]_DCI_18 standards. Removed Compatible Output Standards and Compatible Input Standards tables. Added new Table 5, Summary of Voltage Supply Requirements for All Input and 06/19/03 2.2 Output Standards. This table replaces deleted I/O standards tables. Added section Rules for Combining I/O Standards in the Same Bank, page 6. 08/01/03 3.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3. 10/14/03 3.1Added section Local Clocking, page 29. Table 1, page 1: - Added SSTL18_I and SSTL18_II. - Corrected names of 1.8V HSTL_I-IV standards to “HSTL_I-IV_18”. - Corrected Input V for HSTL_III-IV_18 from 1.08V to 1.1V. REF - Changed “N/A” to “N/R” (no requirement). Table 2, page 2: - Changed “N/A” to “N/R” (no requirement). Table 3, page 2: - Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI, LVDS_25_DCI, and LVDSEXT_25_DCI. - Corrected Input V for HSTL_III-IV_18 from 1.08V to 1.1V. REF Sections Slave-Serial Mode and Master-Serial Mode, page 36: Changed "rising" to "falling" edge with respect to DOUT. Added verbiage to section Bitstream Encryption, page 38: “For devices that support this feature, please contact your sales representative for specific ordering part number.” 03/29/04 3.2Table 2, page 2, and Table 5, page 7: Removed LVDS_33_DCI and LVDSEXT_33_DCI from tables. Table 26, page 37: Updated bitstream lengths. Section BUFGMUX, page 29: Corrected the definition of the "presently selected clock" to be I0 or I1. Corrected signal names in Figure 44 and associated text from CLK0 and CLK1 to I0 and I1. Recompiled for backward compatibility with Acrobat 4 and above. 06/24/04 3.3Table 1, page 1: Added example to Footnote (1) regarding V rules for GTL and CCO GTLP. Added reference to Pb-free package types in Figure 7, page 6. 03/01/05 3.4Reassigned heading hierarchies for better agreement with content. Table 2: Corrected V output voltages. OD Table 26: Updated bitstream lengths. DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 39 R Virtex-II Platform FPGAs: Functional Description Virtex-II Data Sheet The Virtex-II Data Sheet contains the following modules: Virtex-II Platform FPGAs: Introduction and Overview Virtex-II Platform FPGAs: DC and Switching (Module 1) Characteristics (Module 3) Virtex-II Platform FPGAs: Functional Description Virtex-II Platform FPGAs: Pinout Information (Module 2) (Module 4) DS031-2 (v3.4) March 1, 2005 www.xilinx.com Module 2 of 4 Product Specification 40 4 4 R Virtex-II Platform FPGAs: DC and Switching Characteristics DS031-3 (v3.4) March 1, 2005 Product Specification Virtex-II Electrical Characteristics Virtex-II™ devices are provided in -6, -5, and -4 speed commercial device). However, only selected speed grades grades, with -6 having the highest performance. and/or devices might be available in the industrial range. Virtex-II DC and AC characteristics are specified for both All supply voltage and junction temperature specifications commercial and industrial grades. Except the operating are representative of worst-case conditions. The parame- temperature range or unless otherwise noted, all the DC ters included are common to popular designs and typical and AC electrical parameters are the same for a particular applications. Contact Xilinx for design considerations speed grade (that is, the timing characteristics of a -4 speed requiring more detailed information. grade industrial device are the same as for a -4 speed grade All specifications are subject to change without notice. Virtex-II DC Characteristics Table 1: Absolute Maximum Ratings (1) Symbol Description Units V Internal supply voltage relative to GND –0.5 to 1.65 V CCINT V Auxiliary supply voltage relative to GND –0.5 to 4.0 V CCAUX V Output drivers supply voltage relative to GND –0.5 to 4.0 V CCO V Key memory battery backup supply –0.5 to 4.0 V BATT V Input reference voltage –0.5 to V + 0.5 V REF CCO (3) V Input voltage relative to GND (user and dedicated I/Os) –0.5 to V + 0.5 V IN CCO V Voltage applied to 3-state output (user and dedicated I/Os) –0.5 to 4.0 V TS T Storage temperature (ambient) –65 to +150 °C STG All regular FF/BF flip-chip and +220 °C FG/BG/CS wire-bond packages Pb-free FGG456, FGG676, BGG575, (2) T Maximum soldering temperature +250 °C SOL and BGG728 wire-bond packages Pb-free FGG256 and CSG144 +260 °C wire-bond packages (2) T Maximum junction temperature +125 °C J Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see the Device Packaging and Thermal Characteristics Guide information on the Xilinx website. 3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the device is not PCI compliant. © 2000–2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 1 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 2: Recommended Operating Conditions Symbol Description Temperature Range and Grade Min Max Units T =0 °C to +85°C Commercial 1.425 1.575 V J V Internal supply voltage relative to GND CCINT T =–40°C to +100°C Industrial 1.425 1.575 V J T =0 °C to +85°C Commercial 3.135 3.465 V J V Auxiliary supply voltage relative to GND CCAUX T =–40°C to +100°C Industrial 3.135 3.465 V J T =0 °C to +85°C Commercial 1.2 3.6 V J V Supply voltage relative to GND CCO T =–40°C to +100°C Industrial 1.2 3.6 V J T =0 °C to +85°C Commercial 1.0 3.6 V J (1) V Battery voltage relative to GND BATT T =–40°C to +100°C Industrial 1.0 3.6 V J Notes: 1. If battery is not used, connect V to GND or V . BATT CCAUX 2. Recommended maximum voltage droop for V is 10 mV/ms. CCAUX 3. The thresholds for Power On Reset are V > 1.2V, V > 2.5V, and V (Bank 4) > 1.5 V. CCINT CCAUX CCO 4. Limit the noise at the power supply to be within 200 mV peak-to-peak. 5. For power bypassing guidelines, see XAPP623 at www.xilinx.com. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Device Min Max Units V Data retention V voltage All 1.2 V DRINT CCINT V Data retention V voltage All 2.5 V DRI CCAUX I V current per pin All –10 +10 μA REF REF I Input leakage current All –10 +10 μA L C Input capacitance All 10 pF IN Note (1) I Pad pull-up (when selected) @ V = 0 V, V = 3.3 V (sample tested) All 250 μA RPU IN CCO I Pad pull-down (when selected) @ V = 3.6 V (sample tested) All Note (1) 250 μA RPD IN I Battery supply current All (Note 2) nA BATT Notes: 1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 2. Battery supply current (I ): BATT Device Device Unpowered Powered Units 25°C: < 50 < 10 nA 85°C: N/A < 10 nA DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 2 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 4: Quiescent Supply Current Symbol Description Device Min Typical Max Units XC2V40 3 125 XC2V80 5 125 XC2V250 8 150 XC2V500 10 200 XC2V1000 12 250 I Quiescent V supply current XC2V1500 15 350 mA CCINTQ CCINT XC2V2000 20 400 XC2V3000 27 500 XC2V4000 35 650 XC2V6000 45 800 XC2V8000 60 1100 XC2V40 1 2 XC2V80 1 2 XC2V250 1 2 XC2V500 1 2 XC2V1000 1 2 (1,2) I Quiescent V supply current XC2V1500 2 4 mA CCOQ CCO XC2V2000 2 4 XC2V3000 2 4 XC2V4000 2 4 XC2V6000 2 4 XC2V8000 2 4 XC2V40 5 25 XC2V80 5 25 XC2V250 5 25 XC2V500 5 25 XC2V1000 5 25 (1,2) I Quiescent V supply current XC2V1500 7.5 50 mA CCAUXQ CCAUX XC2V2000 7.5 50 XC2V3000 10 75 XC2V4000 10 75 XC2V6000 12.5 100 XC2V8000 12.5 100 Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 2. If DCI or differential signaling is used, more accurate values can be obtained by using the Power Estimator or XPOWER™. 3. Data are retained even if V drops to 0 V. CCO 4. Values specified for quiescent supply current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade values by 1.25. If any V bank powers up before V , then each bank Power-On Power Supply Requirements CCO CCAUX draws up to 300 mA, worst case, until the V powers CCAUX Xilinx FPGAs require a certain amount of supply current (2) up. This does not harm the device. If the current is limited during power-on to insure proper device operation. The to the minimum value above, or larger, the device powers on actual current consumed depends on the power-on ramp properly after all three supplies have passed through their rate of the power supply. power-on reset threshold voltages. The V , V , and V power supplies shall each CCINT CCAUX CCO Once initialized and configured, use the power calculator to ramp on, monotonically, no faster than 200 μs and no slower estimate current drain on these supplies. than 50 ms. Ramp on is defined as: 0 V to minimum sup- DC Notes: ply voltages. 1. If the V ramp rate is longer than 10 ms, then V must CCINT CCINT Table 5 shows the minimum current required by Virtex-II be applied before V and V . The device will not be CCO CCAUX damaged if this requirement is violated, but configuration will devices for proper power on and configuration. probably fail. (1) Power supplies can be turned on in any sequence. 2. The 300 mA is transient current (peak); it eventually disappears even if V does not power up. CCAUX DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 3 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 5: Minimum Power On Current Required for Virtex-II Devices Device (mA) XC2V40, XC2V80, XC2V250, XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 I 200 250 350 400 500 650 800 1100 CCINTMIN I 100 100 100 100 100 100 100 100 CCAUXMIN I 50 50 100 100 100 100 100 100 CCOMIN Notes: 1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade values by 1.25. 2. I values listed here apply to the entire device (all banks). CCOMIN General Power Supply Requirements Proper decoupling of all FPGA power supplies is sessential. tion are provided in Xilinx Answer Record 13756, available Consult Xilinx Application Note XAPP623 for detailed infor- at www.support.xilinx.com. mation on power distribution system design. V can share a power plane with 3.3V V , but only if CCAUX CCO V powers critical resources in the FPGA. Thus, V does not have excessive noise. Using simultaneously CCAUX CCO V is especially susceptible to power supply noise. switching output (SSO) limits are essential for keeping CCAUX power supply noise to a minimum. Refer to XAPP689, “Man- Changes in V voltage outside of 200 mV peak to peak CCAUX aging Ground Bounce in Large FPGAs,” to determine the should take place at a rate no faster than 10 mV per milli- number of simultaneously switching outputs allowed per second. Techniques to help reduce jitter and period distor- bank at the package level. DC Input and Output Levels Values for V and V are recommended input voltages. sen to ensure that all standards meet their specifications. IL IH Values for I and I are guaranteed over the recom- The selected standards are tested at minimum V with OL OH CCO mended operating conditions at the V and V test the respective V and V voltage levels shown. Other OL OH OL OH points. Only selected standards are tested. These are cho- standards are sample tested. Table 6: DC Input and Output Levels V V V V I I Input/Output IL IH OL OH OL OH Standard V, Min V, Max V, Min V, Max V, Max V, Min mA mA (1) LVTTL – 0.5 0.8 2.0 3.6 0.4 2.4 24 – 24 LVCMOS33 – 0.5 0.8 2.0 3.6 0.4 V –0.4 24 – 24 CCO LVCMOS25 – 0.5 0.7 1.7 2.7 0.4 V –0.4 24 –24 CCO LVCMOS18 – 0.5 35% V 65% V 1.95 0.4 V –0.4 16 –16 CCO CCO CCO LVCMOS15 – 0.5 35% V 65% V 1.7 0.4 V –0.4 16 –16 CCO CCO CCO PCI33_3 – 0.5 30% V 50% V V + 0.5 10% V 90% V Note 2 Note 2 CCO CCO CCO CCO CCO PCI66_3 – 0.5 30% V 50% V V + 0.5 10% V 90% V Note 2 Note 2 CCO CCO CCO CCO CCO PCI–X – 0.5 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 GTLP – 0.5 V –0.1 V + 0.1 V + 0.5 0.6 n/a 36 n/a REF REF CCO GTL – 0.5 V –0.05 V + 0.05 V + 0.5 0.4 n/a 40 n/a REF REF CCO HSTL I – 0.5 V –0.1 V + 0.1 V + 0.5 0.4 V –0.4 8 – 8 REF REF CCO CCO HSTL II – 0.5 V –0.1 V + 0.1 V + 0.5 0.4 V –0.4 16 –16 REF REF CCO CCO HSTL III – 0.5 V –0.1 V + 0.1 V + 0.5 0.4 V –0.4 24 –8 REF REF CCO CCO HSTL IV – 0.5 V –0.1 V + 0.1 V + 0.5 0.4 V –0.4 48 –8 REF REF CCO CCO DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 4 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 6: DC Input and Output Levels (Continued) V V V V I I Input/Output IL IH OL OH OL OH Standard V, Min V, Max V, Min V, Max V, Max V, Min mA mA SSTL3 I – 0.5 V –0.2 V + 0.2 V + 0.5 V –0.6 V + 0.6 8 – 8 REF REF CCO REF REF SSTL3 II – 0.5 V –0.2 V + 0.2 V + 0.5 V –0.8 V + 0.8 16 – 16 REF REF CCO REF REF SSTL2 I – 0.5 V –0.15 V + 0.15 V + 0.5 V –0.65 V + 0.65 7.6 – 7.6 REF REF CCO REF REF SSTL2 II – 0.5 V –0.15 V + 0.15 V + 0.5 V –0.80 V + 0.80 15.2 – 15.2 REF REF CCO REF REF AGP – 0.5 V –0.2 V + 0.2 V + 0.5 10% V 90% V Note 2 Note 2 REF REF CCO CCO CCO Notes: 1. V and V for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA. OL OH 2. Tested according to the relevant specifications. 3. LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis. LDT Differential Signal DC Specifications (LDT_25) Table 7: LDT DC Specifications DC Parameter Symbol Conditions Min Typ Max Units Differential Output Voltage V R = 100 Ω across Q and Q signals 500 600 700 mV OD T Change in V Magnitude Δ V –15 15 mV OD OD Output Common Mode Voltage V R = 100 Ω across Q and Q signals 560 600 640 mV OCM T Change in V Magnitude Δ V –15 15 mV OS OCM Input Differential Voltage V 200 600 1000 mV ID Change in V Magnitude Δ V –15 15 mV ID ID Input Common Mode Voltage V 500 600 700 mV ICM Change in V Magnitude Δ V –15 15 mV ICM ICM LVDS DC Specifications (LVDS_33 & LVDS_25) Table 8: LVDS DC Specifications DC Parameter Symbol Conditions Min Typ Max Units Supply Voltage V 3.3 or 2.5 V CCO Output High Voltage for Q and Q V R = 100 Ω across Q and Q signals 1.575 V OH T Output Low Voltage for Q and Q V R = 100 Ω across Q and Q signals 0.925 V OL T Differential Output Voltage (Q – Q), V R = 100 Ω across Q and Q signals 250 350 400 mV ODIFF T Q = High (Q –Q), Q = High Output Common-Mode Voltage V R = 100 Ω across Q and Q signals 1.125 1.2 1.375 V OCM T Differential Input Voltage (Q – Q), V Common-mode input voltage = 1.25 V 100 350 N/A mV IDIFF Q = High (Q –Q), Q = High Input Common-Mode Voltage V Differential input voltage = ±350 mV 0.2 1.25 V – 0.5 V ICM CCO DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 5 R Virtex-II Platform FPGAs: DC and Switching Characteristics Extended LVDS DC Specifications (LVDSEXT_33 & LVDSEXT_25) Table 9: Extended LVDS DC Specifications DC Parameter Symbol Conditions Min Typ Max Units Supply Voltage V 3.3 or 2.5 V CCO Output High voltage for Q and Q V R = 100 Ω across Q and Q signals 1.785 V OH T Output Low voltage for Q and Q V R = 100 Ω across Q and Q signals 0.705 V OL T Differential output voltage (Q – Q), V R = 100 Ω across Q and Q signals 440 820 mV ODIFF T Q = High (Q –Q), Q = High Output common-mode voltage V R = 100 Ω across Q and Q signals 1.125 1.200 1.375 V OCM T Differential input voltage (Q – Q), V Common-mode input voltage = 1.25 V 100 350 N/A mV IDIFF Q = High (Q –Q), Q = High Input common-mode voltage V Differential input voltage = ±350 mV 0.2 1.25 V – 0.5 V ICM CCO LVPECL DC Specifications These values are valid when driving a 100 Ω differential common-mode ranges. Table 10 summarizes the DC output load only, i.e., a 100 Ω resistor between the two receiver specifications of LVPECL. For more information on using pins. The V levels are 200 mV below standard LVPECL LVPECL, see the Virtex-II User Guide. OH levels and are compatible with devices tolerant of lower Table 10: LVPECL DC Specifications DC Parameter Min Max Min Max Min Max Units V 3.0 3.3 3.6 V CCO V 1.8 2.11 1.92 2.28 2.13 2.41 V OH V 0.96 1.27 1.06 1.43 1.30 1.57 V OL V 1.49 2.72 1.49 2.72 1.49 2.72 V IH V 0.86 2.125 0.86 2.125 0.86 2.125 V IL Differential Input Voltage 0.3 – 0.3 – 0.3 – V DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 6 R Virtex-II Platform FPGAs: DC and Switching Characteristics Virtex-II Performance Characteristics This section provides the performance characteristics of Table 11 provides pin-to-pin values (in nanoseconds) some common functions and designs implemented in including IOB delays; that is, delay through the device from Virtex-II devices. The numbers reported here are worst-case input pin to output pin. In the case of multiple inputs and out- values; they have all been fully characterized. Note that puts, the worst delay is reported. these values are subject to the same guidelines as Virtex-II Switching Characteristics, page 9 (speed files). Table 11: Pin-to-Pin Performance Description Device Used & Speed Grade Pin-to-Pin (with I/O delays) Units Basic Functions 16-bit Address Decoder XC2V1000 -5 6.3 ns 32-bit Address Decoder XC2V1000 -5 7.7 ns 64-bit Address Decoder XC2V1000 -5 9.3 ns 4:1 MUX XC2V1000 -5 5.7 ns 8:1 MUX XC2V1000 -5 6.5 ns 16:1 MUX XC2V1000 -5 6.7 ns 32:1 MUX XC2V1000 -5 8.7 ns Combinatorial (pad to LUT to pad) XC2V1000 -5 5.0 ns Memory Block RAM Pad to setup 1.6 ns 9.5 ns Clock to Pad Distributed RAM Pad to setup XC2V1000 -5 2.7 ns Clock to Pad XC2V1000 -5 5.1 (no clk skew) ns Table 12 shows internal (register-to-register) performance. Values are reported in MHz. Table 12: Register-to-Register Performance Device Used & Speed Register-to-Register Description Grade Performance Units Basic Functions 16-bit Address Decoder XC2V1000 -5 398 MHz 32-bit Address Decoder XC2V1000 -5 291 MHz 64-bit Address Decoder XC2V1000 -5 274 MHz 4:1 MUX XC2V1000 -5 563 MHz 8:1 MUX XC2V1000 -5 454 MHz 16:1 MUX XC2V1000 -5 414 MHz 32:1 MUX XC2V1000 -5 323 MHz Register to LUT to Register XC2V1000 -5 613 MHz DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 7 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 12: Register-to-Register Performance (Continued) Device Used & Speed Register-to-Register Description Grade Performance Units 8-bit Adder XC2V1000 -5 292 MHz 16-bit Adder XC2V1000 -5 239 MHz 64-bit Adder XC2V1000 -5 114 MHz 64-bit Counter XC2V1000 -5 114 MHz 64-bit Accumulator XC2V1000 -5 110 MHz Multiplier 18x18 (with Block RAM inputs) XC2V1000 -5 88 MHz Multiplier 18x18 (with Register inputs) XC2V1000 -5 105 MHz Memory Block RAM Single-Port 4096 x 4 bits 278 MHz Single-Port 2048 x 9 bits 277 MHz 270 MHz Single-Port 1024 x 18 bits Single-Port 512 x 36 bits 253 MHz Dual-Port A:4096 x 4 bits & B:1024 x 18 bits 257 MHz 259 MHz Dual-Port A:1024 x 18 bits & B:1024 x 18 bits Dual-Port A:2048 x 9 bits & B: 512 x 36 bits 250 MHz Distributed RAM Single-Port 32 x 8-bit XC2V1000 -5 387 MHz Single-Port 64 x 8-bit XC2V1000 -5 335 MHz Single-Port 128 x 8-bit XC2V1000 -5 266 MHz Dual-Port 16 x 8 XC2V1000 -5 409 MHz Dual-Port 32 x 8 XC2V1000 -5 311 MHz Dual-Port 64 x 8 XC2V1000 -5 294 MHz Shift Registers N/A MHz 128-bit SRL 256-bit SRL N/A MHz FIFOs (Async. in Block RAM) 1024 x 18-bit Read 279 MHz 1024 x 18-bit Write 172 MHz FIFOs (Sync. in SRL) 128 x 8-bit N/A MHz N/A MHz 128 x 16-bit DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 8 R Virtex-II Platform FPGAs: DC and Switching Characteristics Virtex-II Switching Characteristics Switching characteristics in this document are specified on Testing of Switching Characteristics a per-speed-grade basis and can be designated as All devices are 100% functionally tested. Internal timing Advance, Preliminary, or Production. Note that Virtex-II Per- parameters are derived from measuring internal test pat- formance Characteristics, page7 are subject to these terns. Listed below are representative values. For more guidelines as well. Each designation is defined as follows: specific, more precise, and worst-case guaranteed data, Advance: These speed files are based on simulations only use the values reported by the Xilinx static timing analyzer and are typically available soon after device design specifi- and back-annotate to the simulation net list. Unless other- cations are frozen. Although speed grades with this desig- wise noted, values apply to all Virtex-II devices. nation are considered relatively stable and conservative, some under-reporting might still occur. IOB Input Switching Characteristics Preliminary: These speed files are based on complete ES Input delays associated with the pad are specified for (engineering sample) silicon characterization. Devices and LVTTL levels. For other standards, adjust the delays with speed grades with this designation are intended to give a the values shown in IOB Input Switching Characteristics better indication of the expected performance of production Standard Adjustments, page 11. silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Table 13: Virtex-II Device Speed Grade Designations Production: These speed files are released once enough Speed Grade Designations production silicon of a particular device family member has been characterized to provide full correlation between Device Advance Preliminary Production speed files and devices over numerous production lots. XC2V40 -6, -5, -4 There is no under-reporting of delays, and customers XC2V80 -6, -5, -4 receive formal notification of any subsequent changes. Typ- XC2V250 -6, -5, -4 ically, the slowest speed grades transition to Production before faster speed grades. XC2V500 -6, -5, -4 Since individual family members are produced at different XC2V1000 -6, -5, -4 times, the migration from one category to another depends XC2V1500 -6, -5, -4 completely on the status of the fabrication process for each XC2V2000 -6, -5, -4 device. Table 13 correlates the current status of each XC2V3000 -6, -5, -4 Virtex-II device with a corresponding speed grade designa- tion. XC2V4000 -6, -5, -4 XC2V6000 -6, -5, -4 All specifications are always representative of worst-case supply voltage and junction temperature conditions. XC2V8000 -5, -4 Table 14: IOB Input Switching Characteristics Speed Grade Description Symbol Device -6 -5 -4 Units Propagation Delays 0.69 0.76 0.88 Pad to I output, no delay T All ns, Max IOPI Pad to I output, with delay T XC2V40 1.92 2.11 2.43 ns, Max IOPID XC2V80 1.92 2.11 2.43 ns, Max XC2V250 1.92 2.11 2.43 ns, Max XC2V500 1.92 2.11 2.43 ns, Max XC2V1000 1.92 2.11 2.43 ns, Max XC2V1500 1.92 2.11 2.43 ns, Max XC2V2000 1.92 2.11 2.43 ns, Max XC2V3000 1.97 2.16 2.49 ns, Max XC2V4000 1.97 2.16 2.49 ns, Max XC2V6000 2.10 2.31 2.66 ns, Max XC2V8000 2.31 2.66 ns, Max DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 9 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 14: IOB Input Switching Characteristics (Continued) Speed Grade Description Symbol Device -6 -5 -4 Units Propagation Delays Pad to output IQ via transparent 0.83 0.91 1.05 T All ns, Max IOPLI latch, no delay T XC2V40 3.23 3.55 4.09 ns, Max Pad to output IQ via transparent IOPLID latch, with delay XC2V80 3.23 3.55 4.09 ns, Max XC2V250 3.23 3.55 4.09 ns, Max XC2V500 3.23 3.55 4.09 ns, Max XC2V1000 3.23 3.55 4.09 ns, Max XC2V1500 3.23 3.55 4.09 ns, Max XC2V2000 3.23 3.55 4.09 ns, Max XC2V3000 3.32 3.65 4.20 ns, Max XC2V4000 3.32 3.65 4.20 ns, Max XC2V6000 3.60 3.95 4.55 ns, Max XC2V8000 3.95 4.55 ns, Max 0.67 0.77 Clock CLK to output IQ T All ns, Max IOCKIQ Setup and Hold Times With Respect to Clock at IOB Input Register 0.84/–0.36 0.92/–0.39 1.06/–0.45 Pad, no delay T /T All ns, Min IOPICK IOICKP T /T XC2V40 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min Pad, with delay IOPICKD IOICKPD XC2V80 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V250 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V500 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V1000 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V1500 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V2000 3.24/–2.04 3.57/–2.24 4.10/–2.58 ns, Min XC2V3000 3.33/–2.10 3.67/–2.31 4.22/–2.66 ns, Min XC2V4000 3.33/–2.10 3.67/–2.31 4.22/–2.66 ns, Min XC2V6000 3.61/–2.29 3.97/–2.52 4.56/–2.90 ns, Min XC2V8000 3.97/–2.52 4.56/–2.90 ns, Min ICE input T /T All 0.21/ 0.04 0.24/ 0.04 ns, Min IOICECK IOCKICE SR input (IFF, synchronous) T All 0.27 0.30 0.34 ns, Min IOSRCKI Set/Reset Delays SR input to IQ (asynchronous) T All 1.11 1.22 1.40 ns, Max IOSRIQ T All 5.44 5.98 6.88 ns, Max GSR to output IQ GSRQ Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 10 R Virtex-II Platform FPGAs: DC and Switching Characteristics IOB Input Switching Characteristics Standard Adjustments Table 15 gives all standard-specific data input delay adjustments. Table 15: IOB Input Switching Characteristics Standard Adjustments Speed Grade IOSTANDARD Timing Description Attribute Parameter -6 -5 -4 Units LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL T 0.00 0.00 0.00 ns ILVTTL LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS33 T 0.00 0.00 0.00 ns ILVCMOS33 LVCMOS, 2.5V LVCMOS25 T 0.11 0.11 0.12 ns ILVCMOS25 LVCMOS, 1.8V LVCMOS18 T 0.42 0.43 0.49 ns ILVCMOS18 LVCMOS, 1.5V LVCMOS15 T 0.98 1.00 1.15 ns ILVCMOS15 LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 T 0.60 0.60 0.69 ns ILVDS_25 LVDS, 3.3V LVDS_33 T 0.60 0.60 0.69 ns ILVDS_33 LVDSEXT (Extended Mode), 2.5V LVDSEXT_25 T 0.68 0.69 0.79 ns ILVDSEXT_25 LVDSEXT, 3.3V LVDSEXT_33 T 0.56 0.56 0.65 ns ILVDSEXT_33 ULVDS (Ultra LVDS), 2.5V ULVDS_25 T 0.48 0.49 0.56 ns IULVDS_25 BLVDS (Bus LVDS), 2.5V BLVDS_25 T 0.68 0.69 0.79 ns IBLVDS_25 LDT (HyperTransport), 2.5V LDT_25 T 0.48 0.49 0.56 ns ILDT_25 LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V LVPECL_33 T 0.60 0.60 0.69 ns ILVPECL_33 PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 T 0.00 0.00 0.00 ns IPCI33_3 PCI, 66 MHz, 3.3V PCI66_3 T 0.00 0.00 0.00 ns IPCI66_3 PCI-X, 133 MHz, 3.3V PCIX T 0.00 0.00 0.00 ns IPCIX GTL (Gunning Transceiver Logic) GTL T 0.42 0.42 0.48 ns IGTL GTL Plus GTLP T 0.42 0.42 0.48 ns IGTLP HSTL (High-Speed Transceiver Logic), Class I HSTL_I T 0.42 0.42 0.48 ns IHSTL_I HSTL, Class II HSTL_II T 0.42 0.42 0.48 ns IHSTL_II HSTL, Class III HSTL_III T 0.42 0.42 0.48 ns IHSTL_III HSTL, Class IV HSTL_IV T 0.42 0.42 0.48 ns IHSTL_IV HSTL, Class I, 1.8V HSTL_I_18 T 0.42 0.42 0.48 ns IHSTL_I_18 HSTL, Class II, 1.8V HSTL_II_18 T 0.42 0.42 0.48 ns IHSTL_II_18 HSTL, Class III, 1.8V HSTL_III_18 T 0.42 0.42 0.48 ns IHSTL_III_18 HSTL, Class IV, 1.8V HSTL_IV_18 T 0.42 0.42 0.48 ns IHSTL_IV_18 SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I T 0.42 0.42 0.48 ns ISSTL18_I SSTL, Class II, 1.8V SSTL18_II T 0.42 0.42 0.48 ns ISSTL18_II SSTL, Class I, 2.5V SSTL2_I T 0.42 0.42 0.48 ns ISSTL2_I SSTL, Class II, 2.5V SSTL2_II T 0.42 0.42 0.48 ns ISSTL2_II SSTL, Class I, 3.3V SSTL3_I T 0.35 0.35 0.40 ns ISSTL3_I SSTL, Class II, 3.3V SSTL3_ II T 0.35 0.35 0.40 ns ISSTL3_II AGP-2X/AGP (Accelerated Graphics Port) AGP T 0.35 0.35 0.40 ns IAGP LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI_33 T 0.00 0.00 0.00 ns ILVDCI_33 LVDCI, 2.5V LVDCI_25 T 0.11 0.11 0.12 ns ILVDCI_25 LVDCI, 1.8V LVDCI_18 T 0.42 0.43 0.49 ns ILVDCI_18 LVDCI, 1.5V LVDCI_15 T 0.98 1.00 1.14 ns ILVDCI_15 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 11 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued) Speed Grade IOSTANDARD Timing Description Attribute Parameter -6 -5 -4 Units LVDCI, 3.3V, Half-Impedance LVDCI_DV2_33 T 0.00 0.00 0.00 ns ILVDCI_DV2_33 LVDCI, 2.5V, Half-Impedance LVDCI_DV2_25 T 0.11 0.11 0.12 ns ILVDCI_DV2_25 LVDCI, 1.8V, Half-Impedance LVDCI_DV2_18 T 0.42 0.43 0.49 ns ILVDCI_DV2_18 LVDCI, 1.5V, Half-Impedance LVDCI_DV2_15 T 0.98 1.00 1.14 ns ILVDCI_DV2_15 HSLVDCI (High-Speed Low-Voltage DCI), 1.5V HSLVDCI_15 T 0.42 0.42 0.48 ns IHSLVDCI_15 HSLVDCI, 1.8V HSLVDCI_18 T 0.52 0.53 0.60 ns IHSLVDCI_18 HSLVDCI, 2.5V HSLVDCI_25 T 0.42 0.42 0.48 ns IHSLVDCI_25 HSLVDCI, 3.3V HSLVDCI_33 T 0.42 0.42 0.48 ns IHSLVDCI_33 GTL (Gunning Transceiver Logic) with DCI GTL_DCI T 0.42 0.42 0.48 ns IGTL_DCI GTL Plus with DCI GTLP_DCI T 0.42 0.42 0.48 ns IGTLP_DCI HSTL (High-Speed Transceiver Logic), Class I, with DCI HSTL_I_DCI T 0.42 0.42 0.48 ns IHSTL_I_DCI HSTL, Class II, with DCI HSTL_II_DCI T 0.42 0.42 0.48 ns IHSTL_II_DCI HSTL, Class III, with DCI HSTL_III_DCI T 0.42 0.42 0.48 ns IHSTL_III_DCI HSTL, Class IV, with DCI HSTL_IV_DCI T 0.42 0.42 0.48 ns IHSTL_IV_DCI HSTL, Class I, 1.8V, with DCI HSTL_I_DCI_18 T 0.42 0.42 0.48 ns IHSTL_I_DCI_18 HSTL, Class II, 1.8V, with DCI HSTL_II_DCI_18 T 0.42 0.42 0.48 ns IHSTL_II_DCI_18 HSTL, Class III, 1.8V, with DCI HSTL_III_DCI_18 T 0.42 0.42 0.48 ns IHSTL_III_DCI_18 HSTL, Class IV, 1.8V, with DCI HSTL_IV_DCI_18 T 0.42 0.42 0.48 ns IHSTL_IV_DCI_18 SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI SSTL18_I_DCI T 0.42 0.42 0.48 ns ISSTL18_I_DCI SSTL, Class II, 1.8V, with DCI SSTL18_II_DCI T 0.42 0.42 0.48 ns ISSTL18_II_DCI SSTL, Class I, 2.5V, with DCI SSTL2_I_DCI T 0.42 0.42 0.48 ns ISSTL2_I_DCI SSTL, Class II, 2.5V, with DCI SSTL2_II_DCI T 0.42 0.42 0.48 ns ISSTL2_II_DCI SSTL, Class I, 3.3V, with DCI SSTL3_I_DCI T 0.35 0.35 0.40 ns ISSTL3_I_DCI SSTL, Class II, 3.3V, with DCI SSTL3_II_DCI T 0.35 0.35 0.40 ns ISSTL3_II_DCI LVDS (Low-Voltage Differential Signaling), 2.5V, with DCI LVDS_25_DCI T 0.60 0.60 0.69 ns ILVDS_25_DCI LVDS, 3.3V, with DCI LVDS_33_DCI T 0.60 0.60 0.69 ns ILVDS_33_DCI LVDSEXT (LVDS Extended Mode), 2.5V, with DCI LVDSEXT_25_DCI T 0.58 0.59 0.79 ns ILVDSEXT_25_DCI LVDSEXT, 3.3V, with DCI LVDSEXT_33_DCI T 0.56 0.56 0.65 ns ILVDSEXT_33_DCI Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 18. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 12 R Virtex-II Platform FPGAs: DC and Switching Characteristics IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14. Table 16: IOB Output Switching Characteristics Speed Grade Description Symbol Units -6 -5 -4 Propagation Delays O input to Pad T 1.43 1.51 1.74 ns, Max IOOP O input to Pad via transparent latch T 1.72 1.83 2.11 ns, Max IOOLP 3-State Delays (1) T input to Pad high-impedance T 0.51 0.56 0.64 ns, Max IOTHZ T input to valid data on Pad T 1.38 1.45 1.67 ns, Max IOTP (1) T input to Pad high-impedance via transparent latch T 0.80 0.88 1.01 ns, Max IOTLPHZ T input to valid data on Pad via transparent latch T 1.67 1.77 2.04 ns, Max IOTLPON (1) GTS to Pad high impedance T 4.73 5.20 5.98 ns, Max GTS Sequential Delays Clock CLK to Pad T 1.76 1.87 2.15 ns, Max IOCKP (1) Clock CLK to Pad high-impedance (synchronous) T 0.95 1.04 1.20 ns, Max IOCKHZ Clock CLK to valid data on Pad (synchronous) T 1.82 1.94 2.22 ns, Max IOCKON Setup and Hold Times Before/After Clock CLK O input T /T 0.31/–0.08 0.34/–0.09 0.39/–0.11 ns, Min IOOCK IOCKO OCE input T /T 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min IOOCECK IOCKOCE SR input (OFF) T /T 0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, Min IOSRCKO IOCKOSR 3–State Setup Times, T input T /T 0.28/–0.06 0.31/–0.07 0.35/–0.08 ns, Min IOTCK IOCKT 3–State Setup Times, TCE input T /T 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min IOTCECK IOCKTCE 3–State Setup Times, SR input (TFF) T /T 0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, Min IOSRCKT IOCKTSR Set/Reset Delays Minimum Pulse Width, SR input (asynchronous) T 0.61 0.67 0.77 ns, Min RPW SR input to Pad (asynchronous) T 2.41 2.59 2.98 ns, Max IOSRP (1) SR input to Pad high-impedance (asynchronous) T 1.52 1.67 1.92 ns, Max IOSRHZ SR input to valid data on Pad (asynchronous) T 2.39 2.56 2.95 ns, Max IOSRON GSR to Pad T 5.44 5.98 6.88 ns, Max IOGSRQ Notes: 1. The 3-state turn-off delays should not be adjusted. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 13 R Virtex-II Platform FPGAs: DC and Switching Characteristics IOB Output Switching Characteristics Standard Adjustments Table 17 gives all standard-specific adjustments for output delays terminating at pads, based on standard capacitive load, C . Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, REF adjust the delays by the values shown. Table 17: IOB Output Switching Characteristics Standard Adjustments Speed Grade IOSTANDARD Timing Description Attribute Parameter -6 -5 -4 Units LVTTL (Low-Voltage Transistor-Transistor Logic), Slow, 2 mA LVTTL_S2 T 9.42 9.71 10.68 ns OLVTTL_S2 LVTTL, Slow, 4 mA LVTTL_S4 T 5.77 5.95 6.55 ns OLVTTL_S4 LVTTL, Slow, 6 mA LVTTL_S6 T 4.11 4.24 4.66 ns OLVTTL_S6 LVTTL, Slow, 8 mA LVTTL_S8 T 2.87 2.96 3.26 ns OLVTTL_S8 LVTTL, Slow, 12 mA LVTTL_S12 T 2.32 2.39 2.63 ns OLVTTL_S12 LVTTL, Slow, 16 mA LVTTL_S16 T 1.70 1.75 1.93 ns OLVTTL_S16 LVTTL, Slow, 24 mA LVTTL_S24 T 1.26 1.30 1.43 ns OLVTTL_S24 LVTTL, Fast, 2 mA LVTTL_F2 T 6.52 6.72 7.39 ns OLVTTL_F2 LVTTL, Fast, 4 mA LVTTL_F4 T 2.80 2.88 3.17 ns OLVTTL_F4 LVTTL, Fast, 6 mA LVTTL_F6 T 1.57 1.62 1.78 ns OLVTTL_F6 LVTTL, Fast, 8 mA LVTTL_F8 T 0.46 0.48 0.52 ns OLVTTL_F8 LVTTL, Fast, 12 mA LVTTL_F12 T 0.00 0.00 0.00 ns OLVTTL_F12 LVTTL, Fast, 16 mA LVTTL_F16 T –0.13 –0.14 –0.15 ns OLVTTL_F16 LVTTL, Fast, 24 mA LVTTL_F24 T –0.22 –0.23 –0.26 ns OLVTTL_F24 LVCMOS (Low-Voltage CMOS), 3.3V, Slow, 2 mA LVCMOS33_S2 T 7.67 7.91 8.70 ns OLVCMOS33_S2 LVCMOS, 3.3V, Slow, 4 mA LVCMOS33_S4 T 4.37 4.50 4.95 ns OLVCMOS33_S4 LVCMOS, 3.3V, Slow, 6 mA LVCMOS33_S6 T 3.34 3.44 3.78 ns OLVCMOS33_S6 LVCMOS, 3.3V, Slow, 8 mA LVCMOS33_S8 T 2.29 2.36 2.60 ns OLVCMOS33_S8 LVCMOS, 3.3V, Slow, 12 mA LVCMOS33_S12 T 1.91 1.97 2.16 ns OLVCMOS33_S12 LVCMOS, 3.3V, Slow, 16 mA LVCMOS33_S16 T 1.24 1.27 1.40 ns OLVCMOS33_S16 LVCMOS, 3.3V, Slow, 24 mA LVCMOS33_S24 T 1.18 1.22 1.34 ns OLVCMOS33_S24 LVCMOS, 3.3V, Fast, 2 mA LVCMOS33_F2 T 5.82 6.00 6.60 ns OLVCMOS33_F2 LVCMOS, 3.3V, Fast, 4 mA LVCMOS33_F4 T 2.48 2.55 2.81 ns OLVCMOS33_F4 LVCMOS, 3.3V, Fast, 6 mA LVCMOS33_F6 T 1.28 1.31 1.45 ns OLVCMOS33_F6 LVCMOS, 3.3V, Fast, 8 mA LVCMOS33_F8 T 0.48 0.49 0.54 ns OLVCMOS33_F8 LVCMOS, 3.3V, Fast, 12 mA LVCMOS33_F12 T 0.27 0.28 0.31 ns OLVCMOS33_F12 LVCMOS, 3.3V, Fast, 16 mA LVCMOS33_F16 T –0.14 –0.14 –0.15 ns OLVCMOS33_F16 LVCMOS, 3.3V, Fast, 24 mA LVCMOS33_F24 T –0.21 –0.21 –0.23 ns OLVCMOS33_F24 LVCMOS, 2.5V, Slow, 2 mA LVCMOS25_S2 T 9.11 9.39 10.33 ns OLVCMOS25_S2 LVCMOS, 2.5V, Slow, 4 mA LVCMOS25_S4 T 5.00 5.16 5.67 ns OLVCMOS25_S4 LVCMOS, 2.5V, Slow, 6 mA LVCMOS25_S6 T 4.53 4.67 5.13 ns OLVCMOS25_S6 LVCMOS, 2.5V, Slow, 8 mA LVCMOS25_S8 T 3.86 3.98 4.38 ns OLVCMOS25_S8 LVCMOS, 2.5V, Slow, 12 mA LVCMOS25_S12 T 2.84 2.93 3.22 ns OLVCMOS25_S12 LVCMOS, 2.5V, Slow, 16 mA LVCMOS25_S16 T 2.36 2.43 2.67 ns OLVCMOS25_S16 LVCMOS, 2.5V, Slow, 24 mA LVCMOS25_S24 T 2.00 2.06 2.27 ns OLVCMOS25_S24 LVCMOS, 2.5V, Fast, 2 mA LVCMOS25_F2 T 4.06 4.18 4.60 ns OLVCMOS25_F2 LVCMOS, 2.5V, Fast, 4 mA LVCMOS25_F4 T 1.15 1.18 1.30 ns OLVCMOS25_F4 LVCMOS, 2.5V, Fast, 6 mA LVCMOS25_F6 T 0.72 0.74 0.81 ns OLVCMOS25_F6 LVCMOS, 2.5V, Fast, 8 mA LVCMOS25_F8 T 0.33 0.34 0.37 ns OLVCMOS25_F8 LVCMOS, 2.5V, Fast, 12 mA LVCMOS25_F12 T 0.02 0.02 0.03 ns OLVCMOS25_F12 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 14 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade IOSTANDARD Timing Description Attribute Parameter -6 -5 -4 Units LVCMOS, 2.5V, Fast, 16 mA LVCMOS25_F16 T –0.18 –0.19 –0.21 ns OLVCMOS25_F16 LVCMOS, 2.5V, Fast, 24 mA LVCMOS25_F24 T –0.35 –0.36 –0.40 ns OLVCMOS25_F24 LVCMOS, 1.8V, Slow, 2 mA LVCMOS18_S2 T 15.62 16.10 17.71 ns OLVCMOS18_S2 LVCMOS, 1.8V, Slow, 4 mA LVCMOS18_S4 T 10.20 10.51 11.57 ns OLVCMOS18_S4 LVCMOS, 1.8V, Slow, 6 mA LVCMOS18_S6 T 7.52 7.75 8.53 ns OLVCMOS18_S6 LVCMOS, 1.8V, Slow, 8 mA LVCMOS18_S8 T 6.87 7.08 7.78 ns OLVCMOS18_S8 LVCMOS, 1.8V, Slow, 12 mA LVCMOS18_S12 T 5.54 5.71 6.28 ns OLVCMOS18_S12 LVCMOS, 1.8V, Slow, 16 mA LVCMOS18_S16 T 5.31 5.47 6.02 ns OLVCMOS18_S16 LVCMOS, 1.8V, Fast, 2 mA LVCMOS18_F2 T 5.55 5.72 6.30 ns OLVCMOS18_F2 LVCMOS, 1.8V, Fast, 4 mA LVCMOS18_F4 T 1.89 1.95 2.15 ns OLVCMOS18_F4 LVCMOS, 1.8V, Fast, 6 mA LVCMOS18_F6 T 0.83 0.85 0.94 ns OLVCMOS18_F6 LVCMOS, 1.8V, Fast, 8 mA LVCMOS18_F8 T 0.70 0.72 0.80 ns OLVCMOS18_F8 LVCMOS, 1.8V, Fast, 12 mA LVCMOS18_F12 T 0.26 0.27 0.30 ns OLVCMOS18_F12 LVCMOS, 1.8V, Fast, 16 mA LVCMOS18_F16 T 0.23 0.23 0.26 ns OLVCMOS18_F16 LVCMOS, 1.5V, Slow, 2 mA LVCMOS15_S2 T 18.96 19.55 21.50 ns OLVCMOS15_S2 LVCMOS, 1.5V, Slow, 4 mA LVCMOS15_S4 T 12.77 13.17 14.48 ns OLVCMOS15_S4 LVCMOS, 1.5V, Slow, 6 mA LVCMOS15_S6 T 12.05 12.42 13.66 ns OLVCMOS15_S6 LVCMOS, 1.5V, Slow, 8 mA LVCMOS15_S8 T 9.75 10.06 11.06 ns OLVCMOS15_S8 LVCMOS, 1.5V, Slow, 12 mA LVCMOS15_S12 T 9.04 9.32 10.25 ns OLVCMOS15_S12 LVCMOS, 1.5V, Slow, 16 mA LVCMOS15_S16 T 8.21 8.46 9.31 ns OLVCMOS15_S16 LVCMOS, 1.5V, Fast, 2 mA LVCMOS15_F2 T 5.09 5.25 5.78 ns OLVCMOS15_F2 LVCMOS, 1.5V, Fast, 4 mA LVCMOS15_F4 T 2.01 2.07 2.27 ns OLVCMOS15_F4 LVCMOS, 1.5V, Fast, 6 mA LVCMOS15_F6 T 1.46 1.51 1.66 ns OLVCMOS15_F6 LVCMOS, 1.5V, Fast, 8 mA LVCMOS15_F8 T 0.93 0.96 1.05 ns OLVCMOS15_F8 LVCMOS, 1.5V, Fast, 12 mA LVCMOS15_F12 T 0.74 0.77 0.84 ns OLVCMOS15_F12 LVCMOS, 1.5V, Fast, 16 mA LVCMOS15_F16 T 0.67 0.69 0.75 ns OLVCMOS15_F16 LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 T –0.31 –0.32 –0.36 ns OLVDS_25 LVDS, 3.3V LVDS_33 T –0.25 –0.26 –0.29 ns OLVDS_33 LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 T –0.18 –0.19 –0.21 ns OLVDSEXT_25 LVDSEXT, 3.3V LVDSEXT_33 T –0.17 –0.18 –0.19 ns OLVDSEXT_33 ULVDS (Ultra LVDS), 2.5V ULVDS_25 T –0.20 –0.21 –0.23 ns OULVDS_25 BLVDS (Bus LVDS), 2.5V BLVDS_25 T 0.67 0.69 0.76 ns OBLVDS_25 LDT (HyperTransport), 2.5V LDT_25 T –0.20 –0.21 –0.23 ns OLDT_25 LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V LVPECL_33 T 0.29 0.30 0.33 ns OLVPECL_33 PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 T 1.15 1.19 1.31 ns OPCI33_3 PCI, 66 MHz, 3.3V PCI66_3 T –0.01 –0.01 –0.01 ns OPCI66_3 PCI-X, 133 MHz, 3.3V PCIX T –0.01 –0.01 –0.01 ns OPCIX GTL (Gunning Transceiver Logic) GTL T –0.31 –0.32 –0.36 ns OGTL GTL Plus GTLP T –0.17 –0.18 –0.20 ns OGTLP HSTL (High-Speed Transceiver Logic), Class I HSTL_I T 0.26 0.27 0.29 ns OHSTL_I HSTL, Class II HSTL_II T –0.15 –0.16 –0.17 ns OHSTL_II HSTL, Class III HSTL_III T –0.17 –0.17 –0.19 ns OHSTL_III HSTL, Class IV HSTL_IV T –0.40 –0.41 –0.45 ns OHSTL_IV HSTL, Class I, 1.8V HSTL_I_18 T 0.03 0.03 0.04 ns OHSTL_I_18 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 15 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade IOSTANDARD Timing Description Attribute Parameter -6 -5 -4 Units HSTL, Class II, 1.8V HSTL_II_18 T –0.17 –0.18 –0.20 ns OHSTL_II_18 HSTL, Class III, 1.8V HSTL_III_18 T –0.16 –0.16 –0.18 ns OHSTL_III_18 HSTL, Class IV, 1.8V HSTL_IV_18 T –0.39 –0.40 –0.44 ns OHSTL_IV_18 SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I T 0.20 0.20 0.22 ns OSSTL18_I SSTL, Class II, 1.8V SSTL18_II T –0.05 –0.05 –0.06 ns OSSTL18_II SSTL, Class I, 2.5V SSTL2_I T 0.21 0.22 0.24 ns OSSTL2_I SSTL, Class II, 2.5V SSTL2_II T –0.15 –0.16 –0.18 ns OSSTL2_II SSTL, Class I, 3.3V SSTL3_I T 0.29 0.30 0.33 ns OSSTL3_I SSTL, Class II, 3.3V SSTL3_II T –0.05 –0.05 –0.05 ns OSSTL3_II AGP-2X/AGP (Accelerated Graphics Port) AGP T –0.27 –0.28 –0.31 ns OAGP LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI_33 T 0.74 0.77 0.84 ns OLVDCI_33 LVDCI, 2.5V LVDCI_25 T 0.78 0.80 0.88 ns OLVDCI_25 LVDCI, 1.8V LVDCI_18 T 0.84 0.87 0.95 ns OLVDCI_18 LVDCI, 1.5V LVDCI_15 T 1.82 1.88 2.06 ns OLVDCI_15 LVDCI, 3.3V, Half-Impedance LVDCI_DV2_33 T 0.12 0.12 0.13 ns OLVDCI_DV2_33 LVDCI, 2.5V, Half-Impedance LVDCI_DV2_25 T 0.03 0.03 0.03 ns OLVDCI_DV2_25 LVDCI, 1.8V, Half-Impedance LVDCI_DV2_18 T 0.42 0.43 0.48 ns OLVDCI_DV2_18 LVDCI, 1.5V, Half-Impedance LVDCI_DV2_15 T 1.20 1.23 1.36 ns OLVDCI_DV2_15 HSLVDCI (High-Speed Low-Voltage DCI), 1.5V HSLVDCI_15 T 1.82 1.88 2.06 ns OHSLVDCI_15 HSLVDCI, 1.8V HSLVDCI_18 T 1.05 1.08 1.24 ns OHSLVDCI_18 HSLVDCI, 2.5V HSLVDCI_25 T 0.78 0.80 0.88 ns OHSLVDCI_25 HSLVDCI, 3.3V HSLVDCI_33 T 0.74 0.77 0.84 ns OHSLVDCI_33 GTL (Gunning Transceiver Logic) with DCI GTL_DCI T –0.31 –0.32 –0.35 ns OGTL_DCI GTL Plus with DCI GTLP_DCI T –0.15 –0.16 –0.17 ns OGTLP_DCI HSTL (High-Speed Transceiver Logic), Class I, with DCI HSTL_I_DCI T 0.23 0.23 0.26 ns OHSTL_I_DCI HSTL, Class II, with DCI HSTL_II_DCI T 0.06 0.06 0.07 ns OHSTL_II_DCI HSTL, Class III, with DCI HSTL_III_DCI T –0.17 –0.18 –0.20 ns OHSTL_III_DCI HSTL, Class IV, with DCI HSTL_IV_DCI T –0.46 –0.47 –0.52 ns OHSTL_IV_DCI HSTL, Class I, 1.8V, with DCI HSTL_I_DCI_18 T 0.05 0.05 0.06 ns OHSTL_I_DCI_18 HSTL, Class II, 1.8V, with DCI HSTL_II_DCI_18 T –0.03 –0.03 –0.03 ns OHSTL_II_DCI_18 HSTL, Class III, 1.8V, with DCI HSTL_III_DCI_18 T –0.14 –0.14 –0.16 ns OHSTL_III_DCI_18 HSTL, Class IV, 1.8V, with DCI HSTL_IV_DCI_18 T –0.41 –0.42 –0.47 ns OHSTL_IV_DCI_18 SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI SSTL18_I_DCI T 0.36 0.37 0.40 ns OSSTL18_I_DCI SSTL, Class II, 1.8V, with DCI SSTL18_II_DCI T 0.06 0.06 0.07 ns OSSTL18_II_DCI SSTL, Class I, 2.5V, with DCI SSTL2_I_DCI T 0.12 0.13 0.14 ns OSSTL2_I_DCI SSTL, Class II, 2.5V, with DCI SSTL2_II_DCI T –0.10 –0.10 –0.11 ns OSSTL2_II_DCI SSTL, Class I, 3.3V, with DCI SSTL3_I_DCI T 0.15 0.16 0.17 ns OSSTL3_I_DCI SSTL, Class II, 3.3V, with DCI SSTL3_II_DCI T 0.08 0.08 0.09 ns OSSTL3_II_DCI DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 16 R Virtex-II Platform FPGAs: DC and Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 18 shows the test setup parameters used for measuring Input standard adjustments (see Table 15, page 11). Table 18: Input Delay Measurement Methodology IOSTANDARD V V MEAS REF (1,2) (1,2) V V Description Attribute L H (1,4,5) (1,3,5) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL 0 3.0 1.4 – LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 0 3.3 1.65 – LVCMOS, 2.5V LVCMOS25 0 2.5 1.25 – LVCMOS, 1.8V LVCMOS18 0 1.8 0.9 – LVCMOS, 1.5V LVCMOS15 0 1.5 0.75 – PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 Per PCI Specification – PCI, 66 MHz, 3.3V PCI66_3 Per PCI Specification – PCI-X, 133 MHz, 3.3V PCIX Per PCI-X Specification – GTL (Gunning Transceiver Logic) GTL V –0.2 V +0.2 V 0.80 REF REF REF GTL Plus GTLP V –0.2 V +0.2 V 1.0 REF REF REF HSTL (High-Speed Transceiver Logic), Class I & II HSTL_I, HSTL_II V –0.5 V +0.5 V 0.75 REF REF REF HSTL, Class III & IV HSTL_III, HSTL_IV V –0.5 V +0.5 V 0.90 REF REF REF HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V –0.5 V +0.5 V 0.90 REF REF REF HSTL, Class III & IV, 1.8V HSTL_III_18, HSTL_IV_18 V –0.5 V +0.5 V 1.08 REF REF REF SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL3_I, SSTL3_II V –1.00 V +1.00 V 1.5 REF REF REF SSTL, Class I & II, 2.5V SSTL2_I, SSTL2_II V –0.75 V +0.75 V 1.25 REF REF REF SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V –0.5 V +0.5 V 0.90 REF REF REF V – V + AGP REF REF AGP-2X/AGP (Accelerated Graphics Port) AGP V REF Spec (0.2 xV ) (0.2 xV ) CCO CCO LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 1.2 LVDS, 3.3V LVDS_33 1.2 – 0.125 1.2 + 0.125 1.2 LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 1.2 – 0.125 1.2 + 0.125 1.2 LVDSEXT, 3.3V LVDSEXT_33 1.2 – 0.125 1.2 + 0.125 1.2 ULVDS (Ultra LVDS), 2.5V ULVDS_25 0.6 – 0.125 0.6 + 0.125 0.6 LDT (HyperTransport), 2.5V LDT_25 0.6 – 0.125 0.6 + 0.125 0.6 LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V LVPECL_33 1.6 – 0.3 1.6 + 0.3 1.6 Notes: 1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same as for the corresponding non-DCI standards. 2. Input waveform switches between V and V . L H 3. Measurements are made at typical, minimum, and maximum V values. Reported delays reflect worst case of these measurements. V values REF REF listed are typical. See Virtex-II Platform FPGA User Guide for min/max specifications. 4. Input voltage level from which measurement starts. 5. Note that this is an input voltage reference that bears no relation to the V / V parameters found in IBIS models and/or noted in Figure 1. REF MEAS DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 17 R Virtex-II Platform FPGAs: DC and Switching Characteristics 4. Record the time to V . Output Delay Measurements MEAS 5. Compare the results of steps 2 and 4. The increase or Output delays are measured using a Tektronix P6245 decrease in delay should be added to or subtracted TDS500/600 probe (< 1 pF) across approximately 4" of FR4 from the I/O Output Standard Adjustment value microstrip trace. Standard termination was used for all test- (Table 17) to yield the actual worst-case propagation ing. (See Virtex-II Platform FPGA User Guide for details.) delay (clock-to-input) of the PCB trace. The propagation delay of the 4" trace is characterized sep- arately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown V REF in Figure 1. Measurements and test conditions are reflected in the IBIS FPGA Output R models except where the IBIS format precludes it. (IBIS REF models can be found on the web at http://support.xil- inx.com/support/sw_ibis.htm.) Parameters V , R , REF REF C , and V fully describe the test conditions for each REF MEAS V MEAS I/O standard. The most accurate prediction of propagation (voltage level at which delay measurement is taken) delay in any given application can be obtained through IBIS C simulation, using the following method: REF (probe capacitance) 1. Simulate the output driver of choice into the generalized test setup, using values from Table 19. ds083-3_06a_092503 2. Record the time to V . MEAS Figure 1: Generalized Test Setup 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. Table 19: Output Delay Measurement Methodology (1) IOSTANDARD R C V V REF REF MEAS REF Description Attribute (Ω) (pF) (V) (V) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0 LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS33 1M 0 1.65 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 (2) PCI33_3 (rising edge) 25 10 0.94 0 PCI (Peripheral Component Interface), 33 MHz, 3.3V (2) PCI33_3 (falling edge) 25 10 2.03 3.3 (2) PCI66_3 (rising edge) 25 10 0.94 0 PCI, 66 MHz, 3.3V (2) PCI66_3 (falling edge) 25 10 2.03 3.3 (3) PCIX (rising edge) 25 10 0.94 PCI-X, 133 MHz, 3.3V (3) PCIX (falling edge 25 10 2.03 3.3 GTL (Gunning Transceiver Logic) GTL 25 0 0.8 1.2 GTL Plus GTLP 25 0 1.0 1.5 HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 V 0.75 REF HSTL, Class II HSTL_II 25 0 V 0.75 REF HSTL, Class III HSTL_III 50 0 0.9 1.5 HSTL, Class IV HSTL_IV 25 0 0.9 1.5 HSTL, Class I, 1.8V HSTL_I_18 50 0 V 0.9 REF HSTL, Class II, 1.8V HSTL_II_18 25 0 V 0.9 REF HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8 HSTL, Class IV, 1.8V HSTL_IV_18 25 0 1.1 1.8 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 18 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 19: Output Delay Measurement Methodology (1) IOSTANDARD R C V V REF REF MEAS REF Description Attribute (Ω) (pF) (V) (V) SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 V 0.9 REF SSTL, Class II, 1.8V SSTL18_II 25 0 V 0.9 REF SSTL, Class I, 2.5V SSTL2_I 50 0 V 1.25 REF SSTL, Class II, 2.5V SSTL2_II 25 0 V 1.25 REF SSTL, Class I, 3.3V SSTL3_I 50 0 V 1.5 REF SSTL, Class II, 3.3V SSTL3_II 25 0 V 1.5 REF AGP-2X/AGP (rising edge) 50 0 0.94 0 AGP-2X/AGP (Accelerated Graphics Port) AGP-2X/AGP (falling edge) 50 0 2.03 3.3 LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 50 0 V 1.2 REF LVDS, 3.3V LVDSEXT_25 50 0 V 1.2 REF LVDSEXT (LVDS Extended Mode), 2.5V LVDS_33 50 0 V 1.2 REF LVDSEXT, 3.3V LVDSEXT_33 50 0 V 1.2 REF BLVDS (Bus LVDS), 2.5V BLVDS_25 1M 0 1.2 0 LDT (HyperTransport), 2.5V LDT_25 50 0 V 0.6 REF LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V LVPECL_33 1M 0 1.23 0 LVDCI/HSLVDCI LVDCI_33, HSLVDCI_33 1M 0 1.65 0 (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0 LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 1M 0 0.9 0 LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 1M 0 0.75 0 HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI 50 0 V 0.75 REF HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 50 0 0.9 1.5 HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18 50 0 V 0.9 REF HSTL, Class III & IV, 1.8V, with DCI HSTL_III_DCI_18, HSTL_IV_DCI_18 50 0 1.1 1.8 SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 V 0.9 REF SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 V 1.25 REF SSTL, Class I & II, 3.3V, with DCI SSTL3_I_DCI, SSTL3_II_DCI 50 0 V 1.5 REF GTL (Gunning Transceiver Logic) with DCI GTL_DCI 50 0 0.8 1.2 GTL Plus with DCI GTLP_DCI 50 0 1.0 1.5 Notes: 1. C is the capacitance of the probe, nominally 0 pF. REF 2. Per PCI specifications. 3. Per PCI-X specifications. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 19 R Virtex-II Platform FPGAs: DC and Switching Characteristics Clock Distribution Switching Characteristics Table 20: Clock Distribution Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Global Clock Buffer I input to O output T 0.47 0.52 0.59 ns, Max GIO Global Clock Buffer S input Setup/Hold T /T 0.55/ 0 0.61/ 0 0.70/ 0 ns, Max GSI GIS to I1 an I2 inputs CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used (see Figure 16 in Module 2). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 21: CLB Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Combinatorial Delays 4-input function: F/G inputs to X/Y outputs T 0.35 0.39 0.44 ns, Max ILO 5-input function: F/G inputs to F5 output T 0.57 0.63 0.72 ns, Max IF5 5-input function: F/G inputs to X output T 0.76 0.83 0.95 ns, Max IF5X FXINA or FXINB inputs to Y output via MUXFX T 0.36 0.39 0.45 ns, Max IFXY FXINA input to FX output via MUXFX T 0.26 0.28 0.32 ns, Max INAFX FXINB input to FX output via MUXFX T 0.26 0.28 0.32 ns, Max INBFX SOPIN input to SOPOUT output via ORCY T 0.35 0.38 0.44 ns, Max SOPSOP Incremental delay routing through transparent latch to T 0.41 0.45 0.51 ns, Max IFNCTL XQ/YQ outputs Sequential Delays FF Clock CLK to XQ/YQ outputs T 0.45 0.50 0.57 ns, Max CKO Latch Clock CLK to XQ/YQ outputs T 0.54 0.59 0.68 ns, Max CKLO Setup and Hold Times Before/After Clock CLK BX/BY inputs T /T 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min DICK CKDI DY inputs T /T 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min DYCK CKDY DX inputs T /T 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min DXCK CKDX CE input T /T 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min CECK CKCE SR/BY inputs (synchronous) T T 0.21/–0.02 0.23/–0.03 0.26/–0.03 ns, Min SRCK/ SCKR Clock CLK Minimum Pulse Width, High T 0.61 0.67 0.77 ns, Min CH Minimum Pulse Width, Low T 0.61 0.67 0.77 ns, Min CL Set/Reset Minimum Pulse Width, SR/BY inputs (asynchronous) T 0.61 0.67 0.77 ns, Min RPW Delay from SR/BY inputs to XQ/YQ outputs T 1.06 1.17 1.34 ns, Max RQ (asynchronous) Toggle Frequency (MHz) (for export control) F 820 750 650 MHz TOG DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 20 R Virtex-II Platform FPGAs: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics Table 22: CLB Distributed RAM Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Sequential Delays Clock CLK to X/Y outputs (WE active) in 16 x 1 mode T 1.63 1.79 2.05 ns, Max SHCKO16 Clock CLK to X/Y outputs (WE active) in 32 x 1 mode T 1.97 2.17 2.49 ns, Max SHCKO32 Clock CLK to F5 output T 1.77 1.94 2.23 ns, Max SHCKOF5 Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) T /T 0.53/–0.09 0.58/–0.10 0.67/–0.11 ns, Min DS DH F/G address inputs T /T 0.40/ 0.00 0.44/ 0.00 0.50/ 0.00 ns, Min AS AH SR input (WS) T /T 0.42/–0.01 0.46/–0.01 0.53/–0.01 ns, Min WES WEH Clock CLK Minimum Pulse Width, High T 0.57 0.63 0.72 ns, Min WPH Minimum Pulse Width, Low T 0.57 0.63 0.72 ns, Min WPL Minimum clock period to meet address write cycle time T 1.14 1.25 1.44 ns, Min WC CLB Shift Register Switching Characteristics Table 23: CLB Shift Register Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Sequential Delays Clock CLK to X/Y outputs T 2.31 2.54 2.92 ns, Max REG Clock CLK to X/Y outputs T 2.65 2.92 3.35 ns, Max REG32 Clock CLK to XB output via MC15 LUT output T 2.23 2.46 2.82 ns, Max REGXB Clock CLK to YB output via MC15 LUT output T 2.18 2.40 2.75 ns, Max REGYB Clock CLK to Shiftout T 1.92 2.11 2.43 ns, Max CKSH Clock CLK to F5 output T 2.45 2.69 3.09 ns, Max REGF5 Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) T /T 0.53/–0.07 0.58/–0.08 0.67/–0.09 ns, Min SRLDS SRLDH SR input (WS) T /T 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min WSS WSH Clock CLK Minimum Pulse Width, High T 0.57 0.63 0.72 ns, Min SRPH Minimum Pulse Width, Low T 0.57 0.63 0.72 ns, Min SRPL DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 21 R Virtex-II Platform FPGAs: DC and Switching Characteristics Multiplier Switching Characteristics Table 24: Multiplier Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Propagation Delay to Output Pin Input to Pin 35 T 4.66 8.50 10.36 ns, Max MULT_P35 Input to Pin 34 T 4.57 8.33 10.15 ns, Max MULT_P34 Input to Pin 33 T 4.47 8.16 9.95 ns, Max MULT_P33 Input to Pin 32 T 4.37 7.99 9.74 ns, Max MULT_P32 Input to Pin 31 T 4.28 7.82 9.53 ns, Max MULT_P31 Input to Pin 30 T 4.18 7.65 9.33 ns, Max MULT_P30 Input to Pin 29 T 4.08 7.48 9.12 ns, Max MULT_P29 Input to Pin 28 T 3.99 7.31 8.91 ns, Max MULT_P28 Input to Pin 27 T 3.89 7.14 8.70 ns, Max MULT_P27 Input to Pin 26 T 3.79 6.97 8.50 ns, Max MULT_P26 Input to Pin 25 T 3.69 6.80 8.29 ns, Max MULT_P25 Input to Pin 24 T 3.60 6.63 8.08 ns, Max MULT_P24 Input to Pin 23 T 3.50 6.46 7.88 ns, Max MULT_P23 Input to Pin 22 T 3.40 6.29 7.67 ns, Max MULT_P22 Input to Pin 21 T 3.31 6.12 7.46 ns, Max MULT_P21 Input to Pin 20 T 3.21 5.95 7.26 ns, Max MULT_P20 Input to Pin 19 T 3.11 5.78 7.05 ns, Max MULT_P19 Input to Pin 18 T 3.02 5.61 6.84 ns, Max MULT_P18 Input to Pin 17 T 2.92 5.44 6.63 ns, Max MULT_P17 Input to Pin 16 T 2.82 5.27 6.43 ns, Max MULT_P16 Input to Pin 15 T 2.72 5.10 6.22 ns, Max MULT_P15 Input to Pin 14 T 2.63 4.93 6.01 ns, Max MULT_P14 Input to Pin 13 T 2.53 4.76 5.81 ns, Max MULT_P13 Input to Pin 12 T 2.43 4.59 5.60 ns, Max MULT_P12 Input to Pin 11 T 2.34 4.42 5.39 ns, Max MULT_P11 Input to Pin 10 T 2.24 4.25 5.19 ns, Max MULT_P10 Input to Pin 9 T 2.14 4.08 4.98 ns, Max MULT_P9 Input to Pin 8 T 2.05 3.91 4.77 ns, Max MULT_P8 Input to Pin 7 T 1.95 3.74 4.56 ns, Max MULT_P7 Input to Pin 6 T 1.85 3.57 4.36 ns, Max MULT_P6 Input to Pin 5 T 1.75 3.40 4.15 ns, Max MULT_P5 Input to Pin 4 T 1.66 3.23 3.94 ns, Max MULT_P4 Input to Pin 3 T 1.56 3.06 3.74 ns, Max MULT_P3 Input to Pin 2 T 1.46 2.89 3.53 ns, Max MULT_P2 Input to Pin 1 T 1.37 2.72 3.32 ns, Max MULT_P1 Input to Pin 0 T 1.27 2.55 3.12 ns, Max MULT_P0 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 22 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 25: Pipelined Multiplier Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Setup and Hold Times Before/After Clock Data Inputs T /T 3.00/ 0.00 3.45/ 0.00 3.89/ 0.00 ns, Max MULIDCK MULCKID Clock Enable T /T 0.72/ 0.00 0.80/ 0.00 0.86/ 0.00 ns, Max MULIDCK_CE MULCKID_CE Reset T /T 0.72/ 0.00 0.80/ 0.00 0.86/ 0.00 ns, Max MULIDCK_RST MULCKID_RST Clock to Output Pin Clock to Pin 35 T 3.05 6.91 8.12 ns, Max MULTCK_P35 Clock to Pin 34 T 2.95 6.75 7.93 ns, Max MULTCK_P34 Clock to Pin 33 T 2.85 6.59 7.74 ns, Max MULTCK_P33 Clock to Pin 32 T 2.76 6.43 7.56 ns, Max MULTCK_P32 Clock to Pin 31 T 2.66 6.27 7.37 ns, Max MULTCK_P31 Clock to Pin 30 T 2.56 6.11 7.19 ns, Max MULTCK_P30 Clock to Pin 29 T 2.47 5.95 7.00 ns, Max MULTCK_P29 Clock to Pin 28 T 2.37 5.79 6.81 ns, Max MULTCK_P28 Clock to Pin 27 T 2.27 5.63 6.63 ns, Max MULTCK_P27 Clock to Pin 26 T 2.17 5.47 6.44 ns, Max MULTCK_P26 Clock to Pin 25 T 2.08 5.31 6.26 ns, Max MULTCK_P25 Clock to Pin 24 T 1.98 5.15 6.07 ns, Max MULTCK_P24 Clock to Pin 23 T 1.88 4.99 5.88 ns, Max MULTCK_P23 Clock to Pin 22 T 1.79 4.83 5.70 ns, Max MULTCK_P22 Clock to Pin 21 T 1.69 4.67 5.51 ns, Max MULTCK_P21 Clock to Pin 20 T 1.59 4.51 5.33 ns, Max MULTCK_P20 Clock to Pin 19 T 1.50 4.35 5.14 ns, Max MULTCK_P19 Clock to Pin 18 T 1.40 4.19 4.95 ns, Max MULTCK_P18 Clock to Pin 17 T 1.30 4.03 4.77 ns, Max MULTCK_P17 Clock to Pin 16 T 1.20 3.87 4.58 ns, Max MULTCK_P16 Clock to Pin 15 T 1.11 3.71 4.40 ns, Max MULTCK_P15 Clock to Pin 14 T 1.01 3.55 4.21 ns, Max MULTCK_P14 Clock to Pin 13 T 0.91 3.39 4.02 ns, Max MULTCK_P13 Clock to Pin 12 T 0.91 3.23 3.84 ns, Max MULTCK_P12 Clock to Pin 11 T 0.91 3.07 3.65 ns, Max MULTCK_P11 Clock to Pin 10 T 0.91 2.91 3.47 ns, Max MULTCK_P10 Clock to Pin 9 T 0.91 2.75 3.28 ns, Max MULTCK_P9 Clock to Pin 8 T 0.91 2.59 3.09 ns, Max MULTCK_P8 Clock to Pin 7 T 0.91 2.43 2.91 ns, Max MULTCK_P7 Clock to Pin 6 T 0.91 2.27 2.72 ns, Max MULTCK_P6 Clock to Pin 5 T 0.91 2.11 2.54 ns, Max MULTCK_P5 Clock to Pin 4 T 0.91 1.95 2.35 ns, Max MULTCK_P4 Clock to Pin 3 T 0.91 1.79 2.16 ns, Max MULTCK_P3 Clock to Pin 2 T 0.91 1.63 1.98 ns, Max MULTCK_P2 Clock to Pin 1 T 0.91 1.47 1.79 ns, Max MULTCK_P1 Clock to Pin 0 T 0.91 1.31 1.61 ns, Max MULTCK_P0 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 23 R Virtex-II Platform FPGAs: DC and Switching Characteristics Enhanced Multiplier Switching Characteristics Table 26 and Table 27 provide timing information for enhanced Virtex-II multiplier blocks, available in stepping revisions of Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales representative. Table 26: Enhanced Multiplier Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Propagation Delay to Output Pin Input to Pin 35 T 4.66 5.14 5.91 ns, Max MULT1_P35 Input to Pin 34 T 4.57 5.03 5.79 ns, Max MULT1_P34 Input to Pin 33 T 4.47 4.93 5.66 ns, Max MULT1_P33 Input to Pin 32 T 4.37 4.82 5.54 ns, Max MULT1_P32 Input to Pin 31 T 4.28 4.71 5.42 ns, Max MULT1_P31 Input to Pin 30 T 4.18 4.61 5.29 ns, Max MULT1_P30 Input to Pin 29 T 4.08 4.50 5.17 ns, Max MULT1_P29 Input to Pin 28 T 3.99 4.39 5.05 ns, Max MULT1_P28 Input to Pin 27 T 3.89 4.28 4.92 ns, Max MULT1_P27 Input to Pin 26 T 3.79 4.18 4.80 ns, Max MULT1_P26 Input to Pin 25 T 3.69 4.07 4.68 ns, Max MULT1_P25 Input to Pin 24 T 3.60 3.96 4.56 ns, Max MULT1_P24 Input to Pin 23 T 3.50 3.86 4.43 ns, Max MULT1_P23 Input to Pin 22 T 3.40 3.75 4.31 ns, Max MULT1_P22 Input to Pin 21 T 3.31 3.64 4.19 ns, Max MULT1_P21 Input to Pin 20 T 3.21 3.54 4.06 ns, Max MULT1_P20 Input to Pin 19 T 3.11 3.43 3.94 ns, Max MULT1_P19 Input to Pin 18 T 3.02 3.32 3.82 ns, Max MULT1_P18 Input to Pin 17 T 2.92 3.21 3.69 ns, Max MULT1_P17 Input to Pin 16 T 2.82 3.11 3.57 ns, Max MULT1_P16 Input to Pin 15 T 2.72 3.00 3.45 ns, Max MULT1_P15 Input to Pin 14 T 2.63 2.89 3.33 ns, Max MULT1_P14 Input to Pin 13 T 2.53 2.79 3.20 ns, Max MULT1_P13 Input to Pin 12 T 2.43 2.68 3.08 ns, Max MULT1_P12 Input to Pin 11 T 2.34 2.57 2.96 ns, Max MULT1_P11 Input to Pin 10 T 2.24 2.47 2.83 ns, Max MULT1_P10 Input to Pin 9 T 2.14 2.36 2.71 ns, Max MULT1_P9 Input to Pin 8 T 2.05 2.25 2.59 ns, Max MULT1_P8 Input to Pin 7 T 1.95 2.14 2.46 ns, Max MULT1_P7 Input to Pin 6 T 1.85 2.04 2.34 ns, Max MULT1_P6 Input to Pin 5 T 1.75 1.93 2.22 ns, Max MULT1_P5 Input to Pin 4 T 1.66 1.82 2.10 ns, Max MULT1_P4 Input to Pin 3 T 1.56 1.72 1.97 ns, Max MULT1_P3 Input to Pin 2 T 1.46 1.61 1.85 ns, Max MULT1_P2 Input to Pin 1 T 1.37 1.50 1.73 ns, Max MULT1_P1 Input to Pin 0 T 1.27 1.40 1.60 ns, Max MULT1_P0 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 24 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 27: Enhanced Pipelined Multiplier Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Setup and Hold Times Before/After Clock Data Inputs T /T 3.00/0.00 3.45/0.00 3.89/0.00 ns, Max MULIDCK MULCKID Clock Enable T /T 0.72/0.00 0.80/0.00 0.86/0.00 ns, Max MULIDCK_CE MULCKID_CE Reset T /T 0.72/0.00 0.80/0.00 0.86/0.00 ns, Max MULIDCK_RST MULCKID_RST Clock to Output Pin Clock to Pin 35 T 3.05 3.25 3.74 ns, Max MULTCK1_P35 Clock to Pin 34 T 2.95 3.14 3.61 ns, Max MULTCK1_P34 Clock to Pin 33 T 2.85 3.04 3.49 ns, Max MULTCK1_P33 Clock to Pin 32 T 2.76 2.93 3.37 ns, Max MULTCK1_P32 Clock to Pin 31 T 2.66 2.82 3.25 ns, Max MULTCK1_P31 Clock to Pin 30 T 2.56 2.72 3.12 ns, Max MULTCK1_P30 Clock to Pin 29 T 2.47 2.61 3.00 ns, Max MULTCK1_P29 Clock to Pin 28 T 2.37 2.50 2.88 ns, Max MULTCK1_P28 Clock to Pin 27 T 2.27 2.40 2.75 ns, Max MULTCK1_P27 Clock to Pin 26 T 2.17 2.29 2.63 ns, Max MULTCK1_P26 Clock to Pin 25 T 2.08 2.18 2.51 ns, Max MULTCK1_P25 Clock to Pin 24 T 1.98 2.07 2.38 ns, Max MULTCK1_P24 Clock to Pin 23 T 1.88 1.97 2.26 ns, Max MULTCK1_P23 Clock to Pin 22 T 1.79 1.86 2.14 ns, Max MULTCK1_P22 Clock to Pin 21 T 1.69 1.75 2.02 ns, Max MULTCK1_P21 Clock to Pin 20 T 1.59 1.65 1.89 ns, Max MULTCK1_P20 Clock to Pin 19 T 1.50 1.54 1.77 ns, Max MULTCK1_P19 Clock to Pin 18 T 1.40 1.43 1.65 ns, Max MULTCK1_P18 Clock to Pin 17 T 1.30 1.33 1.52 ns, Max MULTCK1_P17 Clock to Pin 16 T 1.20 1.22 1.40 ns, Max MULTCK1_P16 Clock to Pin 15 T 1.11 1.11 1.28 ns, Max MULTCK1_P15 Clock to Pin 14 T 1.01 1.00 1.15 ns, Max MULTCK1_P14 Clock to Pin 13 T 0.91 1.00 1.15 ns, Max MULTCK1_P13 Clock to Pin 12 T 0.91 1.00 1.15 ns, Max MULTCK1_P12 Clock to Pin 11 T 0.91 1.00 1.15 ns, Max MULTCK1_P11 Clock to Pin 10 T 0.91 1.00 1.15 ns, Max MULTCK1_P10 Clock to Pin 9 T 0.91 1.00 1.15 ns, Max MULTCK1_P9 Clock to Pin 8 T 0.91 1.00 1.15 ns, Max MULTCK1_P8 Clock to Pin 7 T 0.91 1.00 1.15 ns, Max MULTCK1_P7 Clock to Pin 6 T 0.91 1.00 1.15 ns, Max MULTCK1_P6 Clock to Pin 5 T 0.91 1.00 1.15 ns, Max MULTCK1_P5 Clock to Pin 4 T 0.91 1.00 1.15 ns, Max MULTCK1_P4 Clock to Pin 3 T 0.91 1.00 1.15 ns, Max MULTCK1_P3 Clock to Pin 2 T 0.91 1.00 1.15 ns, Max MULTCK1_P2 Clock to Pin 1 T 0.91 1.00 1.15 ns, Max MULTCK1_P1 Clock to Pin 0 T 0.91 1.00 1.15 ns, Max MULTCK1_P0 DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 25 R Virtex-II Platform FPGAs: DC and Switching Characteristics Block SelectRAM Switching Characteristics Table 28: Block SelectRAM Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Sequential Delays Clock CLK to DOUT output T 2.10 2.31 2.65 ns, Max BCKO Setup and Hold Times Before Clock CLK ADDR inputs T /T 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, Min BACK BCKA DIN inputs T /T 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, Min BDCK BCKD EN input T /T 0.95/–0.46 1.04/–0.50 1.20/–0.58 ns, Min BECK BCKE RST input T /T 1.31/–0.71 1.44/–0.78 1.65/–0.90 ns, Min BRCK BCKR WEN input T /T 0.57/–0.19 0.63/–0.21 0.72/–0.25 ns, Min BWCK BCKW Clock CLK CLKA to CLKB setup time for different ports T 1.0 1.0 1.0 ns, min BCCS Minimum Pulse Width, High T 1.17 1.29 1.48 ns, Min BPWH Minimum Pulse Width, Low T 1.17 1.29 1.48 ns, Min BPWL TBUF Switching Characteristics Table 29: TBUF Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Combinatorial Delays IN input to OUT output T 0.45 0.50 0.58 ns, Max IO TRI input to OUT output high-impedance T 0.44 0.48 0.55 ns, Max OFF TRI input to valid data on OUT output T 0.44 0.48 0.55 ns, Max ON DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 26 R Virtex-II Platform FPGAs: DC and Switching Characteristics Configuration Timing Configuration Memory Clearing Parameters Power-up timing of configuration signals is shown in Figure 2; corresponding timing characteristics are listed in Table 30. V CC 1 T POR PROG_B T 2 PL INIT_B 3 T ICCK CCLK (Output or Input) M0, M1, M2* (Required) *Can be either 0 or 1, but must not toggle during and after configuration. ds083-3_07_012004 Figure 2: Configuration Power-Up Timing Table 30: Power-Up Timing Characteristics Figure Description References Symbol Value Units Power-on reset 1 T T + 2 ms, max POR PL Program latency 2 T 4 μs per frame, max PL 0.5 μs, min CCLK (output) delay 3 T ICCK 4.0 μs, max Program pulse width T 300 ns, min PROGRAM Notes: 1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to ground or V . The mode pins should not be toggled during and after configuration. CCAUX Master/Slave Serial Mode Parameters Clock timing for Slave Serial configuration programming is shown in Figure 3, with Master Serial clock timing shown in Figure 4. Programming parameters for both Slave and Master modes are given in Table 31. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 27 R Virtex-II Platform FPGAs: DC and Switching Characteristics Serial DIN 1 T 2 T 5 T DCC CCD CCL CCLK 4 T CCH 3 T CCO Serial DOUT ds083-3_08_111104 Figure 3: Slave Serial Mode Timing Sequence CCLK (Output) 2 T CKDS 1 T DSCK Serial DIN Serial DOUT ds083-3_09_111104 Figure 4: Master Serial Mode Timing Sequence . Table 31: Master/Slave Serial Mode Timing Characteristics Figure Description References Symbol Value Units DIN setup/hold, slave mode (Figure 3)1/2 T /T 5.0/0.0 ns, min DCC CCD DIN setup/hold, master mode (Figure 4)1/2 T /T 5.0/0.0 ns, min DSCK CKDS DOUT 3 T 12.0 ns, max CCO High time 4 T 5.0 ns, min CCH CCLK Low time 5 T 5.0 ns, min CCL Maximum start-up frequency F 50 MHz, max CC_STARTUP (1) Maximum frequency F 66 MHz, max CC_SERIAL Frequency tolerance, master mode with +45% respect to nominal –30% Notes: 1. If no provision is made in the design to adjust the frequency of CCLK, F should not exceed F . CC_SERIAL CC_STARTUP Master/Slave SelectMAP Parameters Figure 5 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the Virtex-II Pro Platform FPGA User Guide. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 28 R Virtex-II Platform FPGAs: DC and Switching Characteristics CCLK 3 4 T T CS_B SMCSCC SMCCCS 5 6 T SMWCC RDWR_B T SMCCW 2 1 T SMCCD T SMDCC DATA[0:7] 7 T SMCKBY BUSY No Write Write No Write Write ds083-3_10_012004 Figure 5: SelectMAP Mode Data Loading Sequence (Generic) Table 32: SelectMAP Mode Write Timing Characteristics Figure Description References Symbol Value Units DATA[0:7] setup/hold 1/2 T /T 5.0/0.0 ns, min SMDCC SMCCD CS_B setup/hold 3/4 T /T 7.0/0.0 ns, min SMCSCC SMCCCS RDWR_B setup/hold 5/6 T /T 7.0/0.0 ns, min SMCCW SMWCC CCLK BUSY propagation delay 7 T 12.0 ns, max SMCKBY Maximum start-up frequency F 50 MHz, max CC_STARTUP Maximum frequency F 50 MHz, max CC_SELECTMAP Maximum frequency with no handshake F 50 MHz, max CCNH DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 29 R Virtex-II Platform FPGAs: DC and Switching Characteristics JTAG Test Access Port Switching Characteristics Characterization data for some of the most commonly requested timing parameters shown in Figure 6 is listed in Table 33. FI TMS TDI 1 2 T T TAPTCK TCKTAP TCK 3 T TCKTDO TDO Data Valid Data to be captured Data Valid Data to be driven out ds083-3_11_012104 Figure 6: Virtex-II Pro Boundary Scan Port Timing Waveforms Table 33: Boundary-Scan Port Timing Specifications Figure Description References Symbol Value Units TMS and TDI setup time 1 T 5.5 ns, min TAPTCK TMS and TDI hold times 2 T 0.0 ns, min TCKTAP TCK Falling edge to TDO output valid 3 T 10.0 ns, max TCKTDO Maximum frequency F 33.0 MHz, max TCK DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 30 R Virtex-II Platform FPGAs: DC and Switching Characteristics Virtex-II Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM Table 34: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM Speed Grade Description Symbol Device -6 -5 -4 Units LVTTL Global Clock Input to Output delay using Output flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14. Global Clock and OFF with DCM T XC2V40 1.10 1.28 1.48 ns ICKOFDCM XC2V80 1.10 1.28 1.48 ns XC2V250 1.10 1.28 1.48 ns XC2V500 1.10 1.28 1.48 ns XC2V1000 1.10 1.28 1.48 ns XC2V1500 1.10 1.28 1.48 ns XC2V2000 1.10 1.28 1.48 ns XC2V3000 1.19 1.38 1.59 ns XC2V4000 1.19 1.38 1.59 ns XC2V6000 1.64 1.88 2.17 ns XC2V8000 1.88 2.17 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% V threshold with test setup shown in Figure 1. For other I/O standards, see Table 19. CC DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 31 R Virtex-II Platform FPGAs: DC and Switching Characteristics Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM Table 35: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM Speed Grade Description Symbol Device -6 -5 -4 Units LVTTL Global Clock Input to Output Delay using Output flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14. Global Clock and OFF without DCM T XC2V40 3.46 3.58 3.69 ns ICKOF XC2V80 3.62 3.58 3.69 ns XC2V250 3.79 3.88 4.47 ns XC2V500 3.85 3.88 4.47 ns XC2V1000 4.02 4.28 4.62 ns XC2V1500 4.16 4.28 4.62 ns XC2V2000 4.30 4.43 5.10 ns XC2V3000 4.49 4.64 5.34 ns XC2V4000 4.82 4.99 5.74 ns XC2V6000 5.19 5.38 5.93 ns XC2V8000 6.09 7.00 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% V threshold with test setup shown in Figure 1. For other I/O standards, see Table 19. CC DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 32 R Virtex-II Platform FPGAs: DC and Switching Characteristics Virtex-II Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Setup and Hold for LVTTL Standard, With DCM Table 36: Global Clock Setup and Hold for LVTTL Standard, With DCM Speed Grade Description Symbol Device -6 -5 -4 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 11. No Delay T /T XC2V40 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns PSDCM PHDCM Global Clock and IFF with DCM XC2V80 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns XC2V250 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns XC2V500 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns XC2V1000 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns XC2V1500 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns XC2V2000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns XC2V3000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns XC2V4000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns XC2V6000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns XC2V8000 1.70/–0.90 1.96/–0.76 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 33 R Virtex-II Platform FPGAs: DC and Switching Characteristics Global Clock Setup and Hold for LVTTL Standard, Without DCM , Table 37: Global Clock Setup and Hold for LVTTL Standard, Without DCM Speed Grade Description Symbol Device -6 -5 -4 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL (2) Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 11. Full Delay T /T XC2V40 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns PSFD PHFD (1) Global Clock and IFF without DCM XC2V80 2.10/ 0.00 2.10/ 0.00 2.21/ 0.00 ns XC2V250 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V1000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V1500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V2000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V3000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns XC2V4000 2.00/ 0.00 2.00/ 0.00 2.30/ 0.00 ns XC2V6000 1.92/ 0.50 1.92/ 0.50 2.21/ 0.50 ns XC2V8000 2.38/ 0.00 2.60/ 0.00 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. These values are parametrically measured. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 34 R Virtex-II Platform FPGAs: DC and Switching Characteristics DCM Timing Parameters All devices are 100% functionally tested. Because of the dif- across the recommended operating conditions. All output ficulty in directly measuring many internal timing parame- jitter and phase specifications are determined through sta- ters, those parameters are derived from benchmark timing tistical measurement at the package pins. patterns. The following guidelines reflect worst-case values Operating Frequency Ranges e Table 38: Operating Frequency Ranges Speed Grade Constraint Unit Description Symbol s -6 -5 -4 s Output Clocks (Low Frequency Mode) CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_LF_Min 24.00 24.00 24.00 MHz CLKOUT_FREQ_1X_LF_Max 230.00 210.00 180.00 MHz CLK2X, CLK2X180 CLKOUT_FREQ_2X_LF_Min 48.00 48.00 48.00 MHz CLKOUT_FREQ_2X_LF_Max 450.00 420.00 360.00 MHz CLKDV CLKOUT_FREQ_DV_LF_Min 1.50 1.50 1.50 MHz CLKOUT_FREQ_DV_LF_Max 150.00 140.00 120.00 MHz CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_Min 24.00 24.00 24.00 MHz CLKOUT_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz Input Clocks (Low Frequency Mode) (1,3,4) CLKIN (using DLL outputs) CLKIN_FREQ_DLL_LF_Min 24.00 24.00 24.00 MHz CLKIN_FREQ_DLL_LF_Max 230.00 210.00 180.00 MHz (2,3,4) CLKIN (using CLKFX outputs) CLKIN_FREQ_FX_LF_Min 1.00 1.00 1.00 MHz CLKIN_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz PSCLK PSCLK_FREQ_LF_Min 0.01 0.01 0.01 MHz PSCLK_FREQ_LF_Max 450.00 420.00 360.00 MHz Output Clocks (High Frequency Mode) CLK0, CLK180 CLKOUT_FREQ_1X_HF_Min 48.00 48.00 48.00 MHz CLKOUT_FREQ_1X_HF_Max 450.00 420.00 360.00 MHz CLKDV CLKOUT_FREQ_DV_HF_Min 3.00 3.00 3.00 MHz CLKOUT_FREQ_DV_HF_Max 300.00 280.00 240.00 MHz CLKFX, CLKFX180 CLKOUT_FREQ_FX_HF_Min 210.00 210.00 210.00 MHz CLKOUT_FREQ_FX_HF_Max 350.00 320.00 270.00 MHz Input Clocks (High Frequency Mode) (1,3,4) CLKIN (using DLL outputs) CLKIN_FREQ_DLL_HF_Min 48.00 48.00 48.00 MHz CLKIN_FREQ_DLL_HF_Max 450.00 420.00 360.00 MHz (2,3,4) CLKIN (using CLKFX outputs) CLKIN_FRQ_FX_HF_Min 50.00 50.00 50.00 MHz CLKIN_FRQ_FX_HF_Max 350.00 320.00 270.00 MHz PSCLK PSCLK_FREQ_HF_Min 0.01 0.01 0.01 MHz PSCLK_FREQ_HF_Max 450.00 420.00 360.00 MHz Notes: 1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values. 4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5% (45/55 to 55/45). DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 35 R Virtex-II Platform FPGAs: DC and Switching Characteristics Input Clock Tolerances Table 39: Input Clock Tolerances Speed Grade -6 -5 -4 Constraints Description Symbol F Min Max Min Max Min Max Units CLKIN Input Clock Low/High Pulse Width PSCLK PSCLK_PULSE < 1MHz 25.00 25.00 25.00 ns 1 – 10 MHz 25.00 25.00 25.00 ns 10 – 25 MHz 10.00 10.00 10.00 ns 25 – 50 MHz 5.00 5.00 5.00 ns 50 – 100 MHz 3.00 3.00 3.00 ns 100 – 150 MHz 2.40 2.40 2.40 ns PSCLK_PULSE and (3) PSCLK and CLKIN 150 – 200 MHz 2.00 2.00 2.00 ns CLKIN_PULSE 200 – 250 MHz 1.80 1.80 1.80 ns 250 – 300 MHz 1.50 1.50 1.50 ns 300 – 350 MHz 1.30 1.30 1.30 ns 350 – 400 MHz 1.15 1.15 1.15 ns > 400 MHz 1.05 1.05 1.05 ns Input Clock Cycle-Cycle Jitter (Low Frequency Mode) (1) CLKIN (using DLL outputs) CLKIN_CYC_JITT_DLL_LF ±300 ±300 ±300 ps (2) CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_LF ±300 ±300 ±300 ps Input Clock Cycle-Cycle Jitter (High Frequency Mode) (1) CLKIN (using DLL outputs) CLKIN_CYC_JITT_DLL_HF ±150 ±150 ±150 ps (2) CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_HF ±150 ±150 ±150 ps Input Clock Period Jitter (Low Frequency Mode) (1) CLKIN (using DLL outputs) CLKIN_PER_JITT_DLL_LF ±1 ±1 ±1 ns (2) CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_LF ±1 ±1 ±1 ns Input Clock Period Jitter (High Frequency Mode) (1) CLKIN (using DLL outputs) CLKIN_PER_JITT_DLL_HF ±1 ±1 ±1 ns (2) CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_HF ±1 ±1 ±1 ns Feedback Clock Path Delay Variation CLKFB off-chip feedback CLKFB_DELAY_VAR_EXT ±1 ±1 ±1 ns Notes: 1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within ±5% (45/55 to 55/45). DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 36 R Virtex-II Platform FPGAs: DC and Switching Characteristics Output Clock Jitter Table 40: Output Clock Jitter Speed Grade Description Symbol Constraints -6 -5 -4 Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 ±100 ±100 ±100 ps CLK90 CLKOUT_PER_JITT_90 ±150 ±150 ±150 ps CLK180 CLKOUT_PER_JITT_180 ±150 ±150 ±150 ps CLK270 CLKOUT_PER_JITT_270 ±150 ±150 ±150 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ±200 ±200 ±200 ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 ±150 ±150 ±150 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ±300 ±300 ±300 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note 1 Note 1 Note 1 ps Notes: 1. Values for this parameter are available at www.xilinx.com. Output Clock Phase Alignment Table 41: Output Clock Phase Alignment Speed Grade Description Symbol Constraints -6 -5 -4 Units Phase Offset Between CLKIN and CLKFB CLKIN/CLKFB CLKIN_CLKFB_PHASE ±50 ±50 ±50 ps Phase Offset Between Any DCM Outputs All CLK outputs CLKOUT_PHASE ±140 ±140 ±140 ps Duty Cycle Precision (1) (2) DLL outputs CLKOUT_DUTY_CYCLE_DLL ±150 ±150 ±150 ps CLKFX outputs CLKOUT_DUTY_CYCLE_FX ±100 ±100 ±100 ps Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. 3. Specification also applies to PSCLK. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 37 R Virtex-II Platform FPGAs: DC and Switching Characteristics Miscellaneous Timing Parameters Table 42: Miscellaneous Timing Parameters Constraints Description Symbol F Speed Grade Units CLKIN -6 -5 -4 Time Required to Achieve LOCK (1) Using DLL outputs LOCK_DLL LOCK_DLL_60 > 60MHz 20.0 20.0 20.0 μs LOCK_DLL_50_60 50 - 60 MHz 25.0 25.0 25.0 μs LOCK_DLL_40_50 40 - 50 MHz 50.0 50.0 50.0 μs LOCK_DLL_30_40 30 - 40 MHz 90.0 90.0 90.0 μs LOCK_DLL_24_30 24 - 30 MHz 120.0 120.0 120.0 μs Using CLKFX outputs LOCK_FX_MIN 10.0 10.0 10.0 ms LOCK_FX_MAX 10.0 10.0 10.0 ms Additional lock time with LOCK_DLL_FINE_SHIFT 50.0 50.0 50.0 μs fine-phase shifting Fine-Phase Shifting Absolute shifting range FINE_SHIFT_RANGE 10.0 10.0 10.0 ns Delay Lines Tap delay resolution DCM_TAP_MIN 30.0 30.0 30.0 ps DCM_TAP_MAX 60.0 60.0 60.0 ps Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. Specification also applies to PSCLK. Frequency Synthesis Table 43: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 Parameter Cross Reference Table 44: Parameter Cross Reference Libraries Guide Data Sheet DLL_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_{1X|2X|DV}_LF DFS_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_FX_LF DLL_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_DLL_LF DFS_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_FX_LF DLL_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_{1X|DV}_HF DFS_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_FX_HF DLL_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_DLL_HF DFS_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_FX_HF DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 38 R Virtex-II Platform FPGAs: DC and Switching Characteristics Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II source-synchronous transmitter and receiver data-valid windows. Table 45: Duty Cycle Distortion and Clock-Tree Skew Speed Grade Description Symbol Device -6 -5 -4 Units (1) Duty Cycle Distortion T All 140 140 140 ps DCD_CLK0 T All 50 50 50 ps DCD_CLK180 (2) Clock Tree Skew T XC2V40 50 50 60 ps CKSKEW XC2V80 50 50 60 ps XC2V250 50 50 60 ps XC2V500 50 50 60 ps XC2V1000 80 80 90 ps XC2V1500 80 80 90 ps XC2V2000 100 100 110 ps XC2V3000 100 100 110 ps XC2V4000 400 400 450 ps XC2V6000 500 500 550 ps XC2V8000 600 650 ps Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. T applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O. DCD_CLK0 T applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element DCD_CLK180 in the I/O. 2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. Table 46: Package Skew Description Symbol Device/Package Value Units (1) Package Skew T XC2V1000 / FF896 130 ps PKGSKEW XC2V3000 / FF1152 115 ps XC2V3000 / BF957 130 ps XC2V4000 / FF1152 130 ps XC2V4000 / FF1517 200 ps XC2V4000 / BF957 140 ps XC2V6000 / FF1152 90 ps XC2V6000 / FF1517 105 ps XC2V6000 / BF957 105 ps Notes: 1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball (7.1ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 39 R Virtex-II Platform FPGAs: DC and Switching Characteristics Table 47: Sample Window Speed Grade Description Symbol Device -6 -5 -4 Units (1) Sampling Error at Receiver Pins T XC2V40 500 500 550 ps SAMP XC2V80 500 500 550 ps XC2V250 500 500 550 ps XC2V500 500 500 550 ps XC2V1000 500 500 550 ps XC2V1500 500 500 550 ps XC2V2000 500 500 550 ps XC2V3000 500 500 550 ps XC2V4000 500 500 550 ps XC2V6000 500 500 550 ps XC2V8000 500 550 ps Notes: 1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 and CLK180 DCM jitter - Worst-case Duty-Cycle Distortion - T DCD_CLK180 - DCM accuracy (phase offset) - DCM phase shift resolution. These measurements do not include package or clock tree skew. Table 48: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration Speed Grade Description Symbol Device -6 -5 -4 Units Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Input Switching Characteristics Standard Adjustments, page 11. No Delay T / XC2V40 0.2/0.5 0.2/0.5 0.2/0.5 ns PSDCM T PHDCM Global Clock and IFF with DCM XC2V80 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V250 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V500 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V1000 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V1500 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V2000 0.2/0.5 0.2/0.5 0.2/0.5 ns XC2V3000 0.2/0.5 0.2/0.5 0.2/0.6 ns XC2V4000 0.2/0.5 0.2/0.6 0.2/0.6 ns XC2V6000 0.2/0.5 0.2/0.6 0.2/0.6 ns XC2V8000 0.2/0.6 0.2/0.7 ns Notes: 1. IFF = Input Flip-Flop 2. The timing values were measured using the fine-phase adjustment feature of the DCM. 3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 40 R Virtex-II Platform FPGAs: DC and Switching Characteristics Source Synchronous Timing Budgets This section describes how to use the parameters provided in the Source-Synchronous Switching Characteristics section to develop system-specific timing budgets. The following analysis provides information necessary for determining Virtex-II contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol Interference or PCB skew. Virtex-II Transmitter Data-Valid Window (T ) Virtex-II Receiver Data-Valid Window (R ) X X T is the minimum aggregate valid data period for a R is the required minimum aggregate valid data period for X X source-synchronous data bus at the pins of the device and a source-synchronous data bus at the pins of the device is calculated as follows: and is calculated as follows: (1) (2) (1) (2) (3) T = Data Period - [Jitter + Duty Cycle Distortion + R = [TSAMP + TCKSKEW + TPKGSKEW ] X X (3) (4) TCKSKEW + TPKGSKEW ] Notes: Notes: 1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. 1. Jitter values and accumulation methodology to be provided in The characterization methodology uses the DCM to capture a future release of this document. The absolute period jitter the DDR input registers’ edges of operation. These values found in the DCM Timing Parameters section of the measurements include: particular DCM output clock used to clock the IOB FF can be used for a best case analysis. - CLK0 and CLK180 DCM jitter in a quiet system 2. This value depends on the clocking methodology used. See - Worst-case duty-cycle distortion Note1 for Table 45. - DCM accuracy (phase offset) 3. This value represents the worst-case clock-tree skew - DCM phase shift resolution. observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to These measurements do not include package or clock tree skew. each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer 2. This value represents the worst-case clock-tree skew tools to evaluate clock skew specific to your application. observable between sequential I/O elements. Significantly 4. These values represent the worst-case skew between any two less clock-tree skew exists for I/O registers that are close to balls of the package: shortest flight time to longest flight time each other and fed by the same or adjacent clock-tree from Pad to Ball. branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. 3. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball. Revision History This section records the change history for this module of the data sheet. Date Version Revision 11/07/00 1.0 Early access draft. 12/06/00 1.1 Initial release. 01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics sections. 01/25/01 1.3The data sheet was divided into four modules (per the current style standard). Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Table 18, “Delay Measurement Methodology” 04/23/01 1.5Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Added T symbol to Table 23. REG32 Skipped v1.4 to sync with other modules. Reverted to traditional double-column format. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 41 R Virtex-II Platform FPGAs: DC and Switching Characteristics Date Version Revision 07/30/01 1.6Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Added values to the Virtex-II Pin-to-Pin Output Parameter Guidelines and Virtex-II Pin-to-Pin Input Parameter Guidelines tables. Added Frequency Synthesis table. 10/02/01 1.7Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Updated the speed grade designations used in data sheets, and added Table 13, which shows the current speed grade designation for each device. 10/05/01 1.8Corrected the speed grade designation for the XC2V1000 device in Table 13. 10/12/01 1.9Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. 11/28/01 2.0Updated values in Table 3, Table 4, Table 5, Virtex-II Performance Characteristics, and Virtex-II Switching Characteristics tables. 01/03/02 2.1Updated values in Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables, based on values extracted from speedsfile version 1.96. Changed the speed grade designation for the XC2V6000 device in Table 13. 07/16/02 2.2Updated values in Table 4, "Quiescent Supply Current." Updated values in Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables, based on values extracted from speedsfile version 1.111. Added Enhanced Multiplier Switching Characteristics section. Added footnote to Table 37, "Global Clock Setup and Hold for LVTTL Standard, Without DCM." Added Source-Synchronous Switching Characteristics section. 09/26/02 2.3Removed mention of MIL-M-38510/605 specification. Added footnotes to Table 2 and Table 6. 12/06/02 2.4Revised SSTL2 values in Table 6 to match the latest JEDEC specification. Added footnote regarding V PCI compliance to Table 1. IN Added footnote regarding CLKOUT_DUTY_CYCLE_DLL to Table 41. 05/07/03 2.5Updated values in Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables, based on values extracted from speedsfile version 1.114. Table 4, Quiescent Supply Current, and Table 5, Minimum Power On Current Required for Virtex-II Devices: Added parameters for XC2V8000 device. Table 16, IOB Output Switching Characteristics: Changed parameter designator T to T . IOTON IOTP Table 26, Enhanced Multiplier Switching Characteristics: Corrected all parameter designators from T to T in order to correspond with designators MULT_P[nn] MULT1_P[nn] used in speedsfile. Table 27, Enhanced Pipelined Multiplier Switching Characteristics: Corrected all parameter designators from T to T in order to correspond MULTCK_P[nn] MULTCK1_P[nn] with designators used in speedsfile. Removed old Table 19, Standard Capacitive Loads. Added Figure 1, page 17, showing test configuration for measuring I/O standard adjustments. 06/19/03 2.5.1Removed footnotes in Table 34 and Table 36 that stated DCM jitter was included in the measurements. DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 42 R Virtex-II Platform FPGAs: DC and Switching Characteristics Date Version Revision 08/01/03 3.0Table 13: All Virtex-II devices and speed grades now Production. Updated values in Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables, based on values extracted from speedsfile version 1.116. Table 34 and Table 35: Revised test setup footnote to refer to Figure 1. Previously specified a capacitive load parameter. Figure 1: Added note to figure regarding termination resistors. 10/14/03 3.1Table 1: Changed T description from “Operating junction temperature” to “Maximum J junction temperature”. In section General Power Supply Requirements, replaced reference to Answer Record 11713 with reference to XAPP689 regarding handling of simultaneously switching outputs (SSO). In section I/O Standard Adjustment Measurement Methodology: - Table 18 renamed Input Delay Measurement Methodology. Added footnotes. - Added new Table 19, Output Delay Measurement Methodology. - Replaced Figure 1, Generalized Test Setup, with new drawing. - Revised and extended text describing output delay measurement procedure. Table 45, Table 47, and Table 48: All Source-Synchronous parameters for all devices now available in these tables. XC2V8000 is no longer offered in the -6 speed grade. The following tables containing parameters or other references to this device/grade combination were corrected accordingly: Table 13, Table 14, Table 34, Table 35, Table 36, Table 37, Table 45, Table 47, and Table 48. Table 39: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing Footnote (2) to new Footnote (3). 03/29/04 3.2Table 4: - For XC2V40, added Maximum quiescent supply current specifications. - For all devices, updated Typical specifications for I and I . CCINTQ CCAUXQ Section Power-On Power Supply Requirements, page 3: Added Footnote (1) qualifying statement that power supplies can be turned on in any sequence. Added section Configuration Timing, page 27. This section includes new timing diagrams as well as parameter specification tables formerly included in the Virtex-II Platform FPGA User Guide. Table 20, Clock Distribution Switching Characteristics: Added parameter T /T GSI GIS (Global Clock Buffer S Input Setup/Hold to I1 and I2 Inputs). Table 38, Operating Frequency Ranges: Added Footnote (4) to all four CLKIN parameters. Recompiled for backward compatibility with Acrobat 4 and above. 06/24/04 3.3Table 1: Added T parameters for Pb-free package devices. SOL DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 43 R Virtex-II Platform FPGAs: DC and Switching Characteristics Date Version Revision 03/01/05 3.4Updated values in Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables, based on values extracted from speedsfile version 1.120. Table 2: Corrected Footnote (1) to require connecting V to V or GND if BATT CCAUX battery is not used. Table 3: Corrected "V current per bank" to "V current per pin." REF REF Section Power-On Power Supply Requirements: Added word “monotonically” to description of supply voltage ramp-on requirements. Added sentence to footnote (1) indicating that if the stated requirements are violated, no damage to the device will result, but configuration will probably fail. Figure 3 and Figure 4: Corrected to show DOUT transitions driven by falling edge of CCLK. Table 15, Table 17, Table 18, and Table 19: Restructured these I/O-related tables to include descriptions, as well as the actual IOSTANDARD attributes (used in Xilinx ISE™ software) for all I/O standards. Table 15: Added data for the following I/O standards: SSTL18_I, SSTL18_II, SSTL18_I_DCI, SSTL18_II_DCI, HSTL_I_18, HSTL_II_18, HSTL_III_18, HSTL_IV_18, LVDSEXT_25, LVDSEXT_33, BLVDS_25, LVDS_25_DCI, LVDS_33_DCI, LVDSEXT_25_DCI, LVDSEXT_33_DCI, HSLVDCI_15, HSLVDCI_18, HSLVDCI_25, HSLVDCI_33. Rearranged I/O standards in a more logical order. Table 16: Added parameter T (Minimum Pulse Width, SR Input). RPW Table 17: Added data for the following I/O standards: SSTL18_I, SSTL18_II, SSTL18_I_DCI, SSTL18_II_DCI, HSLVDCI_15, HSLVDCI_18, HSLVDCI_25, HSLVDCI_33. Changed “Csl” to “C ” to agree with Figure 1 and Table 19. REF Rearranged I/O standards in a more logical order. Table 18: Added data for the following I/O standards: SSTL18_I, SSTL18_II, HSTL_I_18, HSTL_II_18, HSTL_III_18, HSTL_IV_18. Added footnote defining equivalents for DCI standards. Table 19: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C ) values. REF Added HSLVDCI callouts to LVDCI parameter rows (same values). Table 28: Added parameter T , CLKA to CLKB Setup Time. BCCS Table 31: Added Footnote (1) indicating that F should not exceed CC_SERIAL F if no provision is made to adjust the speed of CCLK. CC_STARTUP Table 33: T corrected from a “Min” to a “Max” specification. TCKTDO Virtex-II Data Sheet The Virtex-II Data Sheet contains the following modules: Virtex-II Platform FPGAs: Introduction and Overview Virtex-II Platform FPGAs: DC and Switching (Module 1) Characteristics (Module 3) Virtex-II Platform FPGAs: Functional Description Virtex-II Platform FPGAs: Pinout Information (Module 2) (Module 4) DS031-3 (v3.4) March 1, 2005 www.xilinx.com Module 3 of 4 Product Specification 44 2 2 R Virtex-II Platform FPGAs: 6 Pinout Information DS031-4 (v3.4) March 1, 2005 Product Specification This document provides Virtex-II™ Device/Package Combi-BG728/BGG728 Standard BGA Package nations, Maximum I/Os Available, and Virtex-II Pin Defini-FF896 Flip-Chip Fine-Pitch BGA Package tions, followed by pinout tables for the following packages:FF1152 Flip-Chip Fine-Pitch BGA Package FF1517 Flip-Chip Fine-Pitch BGA Package CS144/CSG144 Chip-Scale BGA Package BF957 Flip-Chip BGA PackageFG256/FGG256 Fine-Pitch BGA Package FG456/FGG456 Fine-Pitch BGA Package For device pinout diagrams and layout guidelines, refer to FG676/FGG676 Fine-Pitch BGA Package the Virtex-II Platform FPGA User Guide. ASCII package pinout files are also available for download from the XilinxBG575/BGG575 Standard BGA Package website (www.xilinx.com). Virtex-II Device/Package Combinations and Maximum I/Os Available Wire-bond and flip-chip packages are available. Table 1 andFGG denotes Pb-free wire-bond fine-pitch BGA (1.00 mm pitch). Table 2 show the maximum number of user I/Os possible in wire-bond and flip-chip packages, respectively. BG denotes standard BGA (1.27 mm pitch). BGG denotes Pb-free standard BGA (1.27 mm pitch). Table 3 shows the number of user I/Os available for all FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). device/package combinations. BF denotes flip-chip BGA (1.27 mm pitch). CS denotes wire-bond chip-scale ball grid array (BGA) The number of I/Os per package include all user I/Os except (0.80 mm pitch). the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, CSG denotes Pb-free wire-bond chip-scale ball grid PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, array (BGA) (0.80 mm pitch). DXP, AND RSVD). FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). Table 1: Wire-Bond Packages Information CS144/ FG256/ FG456/ FG676/ BG575/ BG728/ (1) Package CSG144 FGG256 FGG456 FGG676 BGG575 BGG728 Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27 Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35 I/Os 92 172 324 484 408 516 Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1). Table 2: Flip-Chip Packages Information Package FF896 FF1152 FF1517 BF957 Pitch (mm) 1.00 1.00 1.00 1.27 Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40 I/Os 624 824 1,108 684 © 2000–2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 1 R Virtex-II Platform FPGAs: Pinout Information Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os Available I/Os XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V Package 40 80 250 500 1000 1500 2000 3000 4000 6000 8000 CS144 88 92 92 - - - - - - - - FG256 88 120 172 172 172 - - - - - - FG456 - - 200 264 324 - - - - - - FG676 - - - - - 392 456 484 - - - FF896 - - - - 432 528 624 - - - - FF1152 - - - - - - - 720 824 824 824 FF1517 - - - - - - - - 912 1,104 1,108 BG575 - - - - 328 392 408 - - - - BG728 - - - - - - -516 - - - BF957 - - - - - - 624 684 684 684 - All of the devices supported in a particular package are Virtex-II Pin Definitions pinout compatible and are listed in the same table (one This section describes the pinouts for Virtex-II devices in the table per package). In addition, the FG456 and FG676 following packages: packages are compatible, as are the FF896 and FF1152 CS144: wire-bond chip-scale ball grid array (BGA) of packages. Pins that are not available for the smallest 0.80 mm pitch devices are listed in right-hand columns. FG256, FG456, and FG676: wire-bond fine-pitch BGA Each device is split into eight I/O banks to allow for flexibility of 1.00 mm pitch in the choice of I/O standards (see the Virtex-II Data Sheet). Global pins, including JTAG, configuration, andFF896, FF1152, FF1517: flip-chip fine-pitch BGA of power/ground pins, are listed at the end of each table. 1.00 mm pitch Table 4 provides definitions for all pin types. BG575 and BG728: wire-bond BGA of 1.27 mm pitch The FG256 pinouts (Table 6) is included as an example. All BF957: flip-chip BGA of 1.27 mm pitch Virtex-II pinout tables are available on the distribution CD-ROM, or on the web (at http://www.xilinx.com). DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 2 R Virtex-II Platform FPGAs: Pinout Information Pin Definitions Table 4 provides a description of each pin type listed in Virtex-II pinout tables. Table 4: Virtex-II Pin Definitions Pin Name Direction Description User I/O Pins IO_LXXY_# Input/Output/ All user I/O pins are capable of differential signalling and can implement LVDS, Bidirectional ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7) Dual-Function Pins IO_LXXY_#/ZZZ The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN – D7, RDWR_B, or CS_B With /ZZZ: D0/DIN, D1, D2, Input/OutputIn SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. D3, D4, D5, D6, D7In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after configuration. CS_B Input In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. RDWR_B Input In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. BUSY/DOUT OutputIn SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. INIT_B Bidirectional When Low, this pin indicates that the configuration memory is being cleared. When (open-drain) held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. The pin becomes a user I/O after configuration. GCLKx (S/P) Input/Output These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. VRP Input This pin is for the DCI voltage reference resistor of P transistor (per bank). VRN Input This pin is for the DCI voltage reference resistor of N transistor (per bank). ALT_VRP Input This is the alternative pin for the DCI voltage reference resistor of P transistor. ALT_VRN Input This is the alternative pin for the DCI voltage reference resistor of N transistor. V Input These are input threshold voltage pins. They become user I/Os when an external REF threshold voltage is not needed (per bank). (1) Dedicated Pins CCLK Input/Output Configuration clock. Output in Master mode or Input in Slave mode. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 3 R Virtex-II Platform FPGAs: Pinout Information Table 4: Virtex-II Pin Definitions (Continued) Pin Name Direction Description PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. DONE Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. M2, M1, M0 Input Configuration mode selection. HSWAP_EN Input Enable I/O pull-ups during configuration. TCK Input Boundary Scan Clock. TDI Input Boundary Scan Data Input. TDO Output Boundary Scan Data Output. TMS Input Boundary Scan Mode Select. PWRDWN_B Input Active Low power-down pin (unsupported). Driving this pin Low can adversely affect (unsupported) device operation and configuration. PWRDWN_B is internally pulled High, which is its default state. It does not require an external pull-up. Other Pins DXN, DXP N/A Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). V Input Decryptor key memory backup supply. Connect V to V or GND if battery is BATT BATT CCAUX not used. RSVD N/A Reserved pin - do not connect. V Input Power-supply pins for the output drivers (per bank). CCO V Input Power-supply pins for auxiliary circuits. CCAUX V Input Power-supply pins for the internal core logic. CCINT GND Input Ground. Notes: 1. All dedicated pins (JTAG and configuration) are powered by V (independent of the bank V voltage). CCAUX CCO DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 4 R Virtex-II Platform FPGAs: Pinout Information CS144/CSG144 Chip-Scale BGA Package As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144/CSG144 package. Pins in the XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the No Connect column. Following this table are the CS144/CSG144 Chip-Scale BGA Package Specifications (0.80mm pitch). Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description Pin Number No Connect in the XC2V40 0 IO_L01N_0 B3 0 IO_L01P_0 A3 0 IO_L02N_0 C4 0 IO_L02P_0 B4 0 IO_L03N_0/VRP_0 A4 0 IO_L03P_0/VRN_0 D5 0 IO_L94N_0/VREF_0 A5 0 IO_L94P_0 D6 0 IO_L95N_0/GCLK7P C6 0 IO_L95P_0/GCLK6S B6 0 IO_L96N_0/GCLK5P A6 0 IO_L96P_0/GCLK4S D7 1 IO_L96N_1/GCLK3P A7 1 IO_L96P_1/GCLK2S B7 1 IO_L95N_1/GCLK1P A8 1 IO_L95P_1/GCLK0S B8 1 IO_L94N_1 C8 1 IO_L94P_1/VREF_1 D8 1 IO_L03N_1/VRP_1 C9 1 IO_L03P_1/VRN_1 D9 1 IO_L02N_1 A10 1 IO_L02P_1 B10 1 IO_L01N_1 C10 1 IO_L01P_1 D10 2 IO_L01N_2 C13 2 IO_L01P_2 D11 2 IO_L02N_2/VRP_2 D12 2 IO_L02P_2/VRN_2 D13 2 IO_L03N_2 E10 2 IO_L03P_2/VREF_2 E11 2 IO_L93N_2 E13 NC 2 IO_L93P_2/VREF_2 F11 NC 2 IO_L94N_2 F12 2 IO_L94P_2 G10 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 5 R Virtex-II Platform FPGAs: Pinout Information Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description Pin Number No Connect in the XC2V40 2 IO_L96N_2 G11 2 IO_L96P_2 G13 3 IO_L96N_3 G12 3 IO_L96P_3 H12 3 IO_L94N_3 H11 3 IO_L94P_3 J13 3 IO_L03N_3/VREF_3 J10 3 IO_L03P_3 K13 3 IO_L02N_3/VRP_3 K12 3 IO_L02P_3/VRN_3 K11 3 IO_L01N_3 K10 3 IO_L01P_3 L13 (1) 4 IO_L01N_4/BUSY/DOUT M11 4 IO_L01P_4/INIT_B N11 (1) 4 IO_L02N_4/D0/DIN L10 4 IO_L02P_4/D1 M10 4 IO_L03N_4/D2/ALT_VRP_4 N10 4 IO_L03P_4/D3/ALT_VRN_4 K9 4 IO_L94N_4/VREF_4 N9 4 IO_L94P_4 K8 4 IO_L95N_4/GCLK3S L8 4 IO_L95P_4/GCLK2P M8 4 IO_L96N_4/GCLK1S N8 4 IO_L96P_4/GCLK0P K7 5 IO_L96N_5/GCLK7S N7 5 IO_L96P_5/GCLK6P M7 5 IO_L95N_5/GCLK5S N6 5 IO_L95P_5/GCLK4P M6 5 IO_L94N_5 L6 5 IO_L94P_5/VREF_5 K6 5 IO_L03N_5/D4/ALT_VRP_5 L5 5 IO_L03P_5/D5/ALT_VRN_5 K5 5 IO_L02N_5/D6 N4 5 IO_L02P_5/D7 M4 5 IO_L01N_5/RDWR_B L4 5 IO_L01P_5/CS_B K4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 6 R Virtex-II Platform FPGAs: Pinout Information Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description Pin Number No Connect in the XC2V40 6 IO_L01P_6 L3 6 IO_L01N_6 L2 6 IO_L02P_6/VRN_6 L1 6 IO_L02N_6/VRP_6 K3 6 IO_L03P_6 K2 6 IO_L03N_6/VREF_6 K1 6 IO_L94P_6 J2 6 IO_L94N_6 H4 6 IO_L96P_6 H3 6 IO_L96N_6 H1 7 IO_L96P_7 G4 7 IO_L96N_7 G3 7 IO_L94P_7 G1 7 IO_L94N_7 F1 7 IO_L93P_7/VREF_7 F2 NC 7 IO_L93N_7 F4 NC 7 IO_L03P_7/VREF_7 E2 7 IO_L03N_7 E3 7 IO_L02P_7/VRN_7 E4 7 IO_L02N_7/VRP_7 D1 7 IO_L01P_7 D2 7 IO_L01N_7 D3 0 VCCO_0 B5 0 VCCO_0 C3 1 VCCO_1 A11 1 VCCO_1 A9 2 VCCO_2 F10 2 VCCO_2 C12 3 VCCO_3 L12 3 VCCO_3 J12 4 VCCO_4 M9 4 VCCO_4 L11 5 VCCO_5 N3 5 VCCO_5 N5 6 VCCO_6 J3 6 VCCO_6 M1 7 VCCO_7 D4 7 VCCO_7 F3 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 7 R Virtex-II Platform FPGAs: Pinout Information Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description Pin Number No Connect in the XC2V40 NA CCLK M13 NA PROG_B B1 NA DONE N12 NA M0 N2 NA M1 M2 NA M2 M3 NA TCK B12 NA TDI C1 NA TDO C11 NA TMS A13 NA PWRDWN_B M12 NA HSWAP_EN A1 NA RSVD A2 NA RSVD B2 NA VBATT A12 NA RSVD B11 NA VCCAUX C2 NA VCCAUX N1 NA VCCAUX N13 NA VCCAUX B13 NA VCCINT H2 NA VCCINT L7 NA VCCINT H13 NA VCCINT C7 NA GND E1 NA GND G2 NA GND J1 NA GND J4 NA GND M5 NA GND L9 NA GND J11 NA GND H10 NA GND F13 NA GND E12 NA GND B9 NA GND C5 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 8 R Virtex-II Platform FPGAs: Pinout Information CS144/CSG144 Chip-Scale BGA Package Specifications (0.80mm pitch) Figure 1: CS144/CSG144 Chip-Scale BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 9 R Virtex-II Platform FPGAs: Pinout Information FG256/FGG256 Fine-Pitch BGA Package As shown in Table 6, XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG256/FGG256 fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No Connect columns show pin differences for the XC2V40 and XC2V80 devices. Following this table are the FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 0 IO_L01N_0 C4 0 IO_L01P_0 B4 0 IO_L02N_0 D5 0 IO_L02P_0 C5 0 IO_L03N_0/VRP_0 B5 0 IO_L03P_0/VRN_0 A5 0 IO_L04N_0/VREF_0 D6 NC NC 0 IO_L04P_0 C6 NC NC 0 IO_L05N_0 B6 NC NC 0 IO_L05P_0 A6 NC NC 0 IO_L92N_0 E6 NC NC 0 IO_L92P_0 E7 NC NC 0 IO_L93N_0 D7 NC NC 0 IO_L93P_0 C7 NC NC 0 IO_L94N_0/VREF_0 B7 0 IO_L94P_0 A7 0 IO_L95N_0/GCLK7P D8 0 IO_L95P_0/GCLK6S C8 0 IO_L96N_0/GCLK5P B8 0 IO_L96P_0/GCLK4S A8 1 IO_L96N_1/GCLK3P A9 1 IO_L96P_1/GCLK2S B9 1 IO_L95N_1/GCLK1P C9 1 IO_L95P_1/GCLK0S D9 1 IO_L94N_1 A10 1 IO_L94P_1/VREF_1 B10 1 IO_L93N_1 C10 NC NC 1 IO_L93P_1 D10 NC NC 1 IO_L92N_1 E10 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 10 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 1 IO_L92P_1 E11 NC NC 1 IO_L05N_1 A11 NC NC 1 IO_L05P_1 B11 NC NC 1 IO_L04N_1 C11 NC NC 1 IO_L04P_1/VREF_1 D11 NC NC 1 IO_L03N_1/VRP_1 A12 1 IO_L03P_1/VRN_1 B12 1 IO_L02N_1 C12 1 IO_L02P_1 D12 1 IO_L01N_1 B13 1 IO_L01P_1 C13 2 IO_L01N_2 C16 2 IO_L01P_2 D16 2 IO_L02N_2/VRP_2 D14 2 IO_L02P_2/VRN_2 D15 2 IO_L03N_2 E13 2 IO_L03P_2/VREF_2 E14 2 IO_L04N_2 E15 NC 2 IO_L04P_2 E16 NC 2 IO_L06N_2 F13 NC 2 IO_L06P_2 F14 NC 2 IO_L43N_2 F15 NC NC 2 IO_L43P_2 F16 NC NC 2 IO_L45N_2 F12 NC NC 2 IO_L45P_2/VREF_2 G12 NC NC 2 IO_L91N_2 G13 NC 2 IO_L91P_2 G14 NC 2 IO_L93N_2 G15 NC 2 IO_L93P_2/VREF_2 G16 NC 2 IO_L94N_2 H13 2 IO_L94P_2 H14 2 IO_L96N_2 H15 2 IO_L96P_2 H16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 11 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 3 IO_L96N_3 J16 3 IO_L96P_3 J15 3 IO_L94N_3 J14 3 IO_L94P_3 J13 3 IO_L93N_3/VREF_3 K16 NC 3 IO_L93P_3 K15 NC 3 IO_L91N_3 K14 NC 3 IO_L91P_3 K13 NC 3 IO_L45N_3/VREF_3 K12 NC NC 3 IO_L45P_3 L12 NC NC 3 IO_L43N_3 L16 NC NC 3 IO_L43P_3 L15 NC NC 3 IO_L06N_3 L14 NC 3 IO_L06P_3 L13 NC 3 IO_L04N_3 M16 NC 3 IO_L04P_3 M15 NC 3 IO_L03N_3/VREF_3 M14 3 IO_L03P_3 M13 3 IO_L02N_3/VRP_3 N15 3 IO_L02P_3/VRN_3 N14 3 IO_L01N_3 N16 3 IO_L01P_3 P16 (1) 4 IO_L01N_4/BUSY/DOUT T14 4 IO_L01P_4/INIT_B T13 (1) 4 IO_L02N_4/D0/DIN P13 4 IO_L02P_4/D1 R13 4 IO_L03N_4/D2/ALT_VRP_4 N12 4 IO_L03P_4/D3/ALT_VRN_4 P12 4 IO_L04N_4/VREF_4 R12 NC NC 4 IO_L04P_4 T12 NC NC 4 IO_L05N_4/VRP_4 N11 NC NC 4 IO_L05P_4/VRN_4 P11 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 12 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 4 IO_L91N_4/VREF_4 R11 NC NC 4 IO_L91P_4 T11 NC NC 4 IO_L92N_4 M11 NC NC 4 IO_L92P_4 M10 NC NC 4 IO_L93N_4 N10 NC NC 4 IO_L93P_4 P10 NC NC 4 IO_L94N_4/VREF_4 R10 4 IO_L94P_4 T10 4 IO_L95N_4/GCLK3S N9 4 IO_L95P_4/GCLK2P P9 4 IO_L96N_4/GCLK1S R9 4 IO_L96P_4/GCLK0P T9 5 IO_L96N_5/GCLK7S T8 5 IO_L96P_5/GCLK6P R8 5 IO_L95N_5/GCLK5S P8 5 IO_L95P_5/GCLK4P N8 5 IO_L94N_5 T7 5 IO_L94P_5/VREF_5 R7 5 IO_L93N_5 P7 NC NC 5 IO_L93P_5 N7 NC NC 5 IO_L92N_5 M7 NC NC 5 IO_L92P_5 M6 NC NC 5 IO_L91N_5 T6 NC NC 5 IO_L91P_5/VREF_5 R6 NC NC 5 IO_L05N_5/VRP_5 P6 NC NC 5 IO_L05P_5/VRN_5 N6 NC NC 5 IO_L04N_5 T5 NC NC 5 IO_L04P_5/VREF_5 R5 NC NC 5 IO_L03N_5/D4/ALT_VRP_5 P5 5 IO_L03P_5/D5/ALT_VRN_5 N5 5 IO_L02N_5/D6 R4 5 IO_L02P_5/D7 P4 5 IO_L01N_5/RDWR_B T4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 13 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 5 IO_L01P_5/CS_B T3 6 IO_L01P_6 P1 6 IO_L01N_6 N1 6 IO_L02P_6/VRN_6 N3 6 IO_L02N_6/VRP_6 N2 6 IO_L03P_6 M4 6 IO_L03N_6/VREF_6 M3 6 IO_L04P_6 M2 NC 6 IO_L04N_6 M1 NC 6 IO_L06P_6 L4 NC 6 IO_L06N_6 L3 NC 6 IO_L43P_6 L2 NC NC 6 IO_L43N_6 L1 NC NC 6 IO_L45P_6 L5 NC NC 6 IO_L45N_6/VREF_6 K5 NC NC 6 IO_L91P_6 K4 NC 6 IO_L91N_6 K3 NC 6 IO_L93P_6 K2 NC 6 IO_L93N_6/VREF_6 K1 NC 6 IO_L94P_6 J4 6 IO_L94N_6 J3 6 IO_L96P_6 J2 6 IO_L96N_6 J1 7 IO_L96P_7 H1 7 IO_L96N_7 H2 7 IO_L94P_7 H3 7 IO_L94N_7 H4 7 IO_L93P_7/VREF_7 G1 NC 7 IO_L93N_7 G2 NC 7 IO_L91P_7 G3 NC 7 IO_L91N_7 G4 NC 7 IO_L45P_7/VREF_7 G5 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 14 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 7 IO_L45N_7 F5 NC NC 7 IO_L43P_7 F1 NC NC 7 IO_L43N_7 F2 NC NC 7 IO_L06P_7 F3 NC 7 IO_L06N_7 F4 NC 7 IO_L04P_7 E1 NC 7 IO_L04N_7 E2 NC 7 IO_L03P_7/VREF_7 E3 7 IO_L03N_7 E4 7 IO_L02P_7/VRN_7 D2 7 IO_L02N_7/VRP_7 D3 7 IO_L01P_7 D1 7 IO_L01N_7 C1 0 VCCO_0 F8 0 VCCO_0 F7 0 VCCO_0 E8 1 VCCO_1 F10 1 VCCO_1 F9 1 VCCO_1 E9 2 VCCO_2 H12 2 VCCO_2 H11 2 VCCO_2 G11 3 VCCO_3 K11 3 VCCO_3 J12 3 VCCO_3 J11 4 VCCO_4 M9 4 VCCO_4 L10 4 VCCO_4 L9 5 VCCO_5 M8 5 VCCO_5 L8 5 VCCO_5 L7 6 VCCO_6 K6 6 VCCO_6 J6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 15 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 6 VCCO_6 J5 7 VCCO_7 H6 7 VCCO_7 H5 7 VCCO_7 G6 NA CCLK P15 NA PROG_B A2 NA DONE R14 NA M0 T2 NA M1 P2 NA M2 R3 NA HSWAP_EN B3 NA TCK A15 NA TDI C2 NA TDO C15 NA TMS B14 NA PWRDWN_B T15 NA RSVD A4 NA RSVD A3 NA VBATT A14 NA RSVD A13 NA VCCAUX R16 NA VCCAUX R1 NA VCCAUX B16 NA VCCAUX B1 NA VCCINT N13 NA VCCINT N4 NA VCCINT M12 NA VCCINT M5 NA VCCINT E12 NA VCCINT E5 NA VCCINT D13 NA VCCINT D4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 16 R Virtex-II Platform FPGAs: Pinout Information Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80 NA GND T16 NA GND T1 NA GND R15 NA GND R2 NA GND P14 NA GND P3 NA GND L11 NA GND L6 NA GND K10 NA GND K9 NA GND K8 NA GND K7 NA GND J10 NA GND J9 NA GND J8 NA GND J7 NA GND H10 NA GND H9 NA GND H8 NA GND H7 NA GND G10 NA GND G9 NA GND G8 NA GND G7 NA GND F11 NA GND F6 NA GND C14 NA GND C3 NA GND B15 NA GND B2 NA GND A16 NA GND A1 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 17 R Virtex-II Platform FPGAs: Pinout Information FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 2: FG256/FGG256 Fine-Pitch BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 18 R Virtex-II Platform FPGAs: Pinout Information FG456/FGG456 Fine-Pitch BGA Package As shown in Table 7, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG456/FGG456 fine-pitch BGA package. Pins in the XC2V250, XC2V500, and XC2V1000 devices are the same, except for the pin differences in the XC2V250 and XC2V500 devices shown in the No Connect columns. Following this table are the FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 0 IO_L01N_0 B4 0 IO_L01P_0 A4 0 IO_L02N_0 C4 0 IO_L02P_0 C5 0 IO_L03N_0/VRP_0 B5 0 IO_L03P_0/VRN_0 A5 0 IO_L04N_0/VREF_0 D6 0 IO_L04P_0 C6 0 IO_L05N_0 B6 0 IO_L05P_0 A6 0 IO_L06N_0 E7 0 IO_L06P_0 E8 0 IO_L21N_0 D7 NC NC 0 IO_L21P_0/VREF_0 C7 NC NC 0 IO_L22N_0 B7 NC NC 0 IO_L22P_0 A7 NC NC 0 IO_L24N_0 D8 NC NC 0 IO_L24P_0 C8 NC NC 0 IO_L49N_0 B8 NC 0 IO_L49P_0 A8 NC 0 IO_L51N_0 E9 NC 0 IO_L51P_0/VREF_0 F9 NC 0 IO_L52N_0 D9 NC 0 IO_L52P_0 C9 NC 0 IO_L54N_0 B9 NC 0 IO_L54P_0 A9 NC 0 IO_L91N_0/VREF_0 E10 0 IO_L91P_0 F10 0 IO_L92N_0 D10 0 IO_L92P_0 C10 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 19 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 0 IO_L93N_0 B10 0 IO_L93P_0 A10 0 IO_L94N_0/VREF_0 E11 0 IO_L94P_0 F11 0 IO_L95N_0/GCLK7P D11 0 IO_L95P_0/GCLK6S C11 0 IO_L96N_0/GCLK5P B11 0 IO_L96P_0/GCLK4S A11 1 IO_L96N_1/GCLK3P F12 1 IO_L96P_1/GCLK2S F13 1 IO_L95N_1/GCLK1P E12 1 IO_L95P_1/GCLK0S D12 1 IO_L94N_1 C12 1 IO_L94P_1/VREF_1 B12 1 IO_L93N_1 A13 1 IO_L93P_1 B13 1 IO_L92N_1 C13 1 IO_L92P_1 D13 1 IO_L91N_1 E13 1 IO_L91P_1/VREF_1 E14 1 IO_L54N_1 A14 NC 1 IO_L54P_1 B14 NC 1 IO_L52N_1 C14 NC 1 IO_L52P_1 D14 NC 1 IO_L51N_1/VREF_1 A15 NC 1 IO_L51P_1 B15 NC 1 IO_L49N_1 C15 NC 1 IO_L49P_1 D15 NC 1 IO_L24N_1 F14 NC NC 1 IO_L24P_1 E15 NC NC 1 IO_L22N_1 A16 NC NC 1 IO_L22P_1 B16 NC NC 1 IO_L21N_1/VREF_1 C16 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 20 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 1 IO_L21P_1 D16 NC NC 1 IO_L06N_1 E16 1 IO_L06P_1 E17 1 IO_L05N_1 A17 1 IO_L05P_1 B17 1 IO_L04N_1 C17 1 IO_L04P_1/VREF_1 D17 1 IO_L03N_1/VRP_1 A18 1 IO_L03P_1/VRN_1 B18 1 IO_L02N_1 C18 1 IO_L02P_1 D18 1 IO_L01N_1 A19 1 IO_L01P_1 B19 2 IO_L01N_2 C21 2 IO_L01P_2 C22 2 IO_L02N_2/VRP_2 E18 2 IO_L02P_2/VRN_2 F18 2 IO_L03N_2 D21 2 IO_L03P_2/VREF_2 D22 2 IO_L04N_2 E19 2 IO_L04P_2 E20 2 IO_L06N_2 E21 2 IO_L06P_2 E22 2 IO_L19N_2 F19 NC NC 2 IO_L19P_2 F20 NC NC 2 IO_L21N_2 F21 NC NC 2 IO_L21P_2/VREF_2 F22 NC NC 2 IO_L22N_2 G18 NC NC 2 IO_L22P_2 H18 NC NC 2 IO_L24N_2 G19 NC NC 2 IO_L24P_2 G20 NC NC 2 IO_L43N_2 G21 2 IO_L43P_2 G22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 21 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 2 IO_L45N_2 H19 2 IO_L45P_2/VREF_2 H20 2 IO_L46N_2 H21 2 IO_L46P_2 H22 2 IO_L48N_2 J17 2 IO_L48P_2 J18 2 IO_L49N_2 J19 NC 2 IO_L49P_2 J20 NC 2 IO_L51N_2 J21 NC 2 IO_L51P_2/VREF_2 J22 NC 2 IO_L52N_2 K17 NC 2 IO_L52P_2 K18 NC 2 IO_L54N_2 K19 NC 2 IO_L54P_2 K20 NC 2 IO_L91N_2 K21 2 IO_L91P_2 K22 2 IO_L93N_2 L17 2 IO_L93P_2/VREF_2 L18 2 IO_L94N_2 L19 2 IO_L94P_2 L20 2 IO_L96N_2 L21 2 IO_L96P_2 L22 3 IO_L96N_3 M21 3 IO_L96P_3 M20 3 IO_L94N_3 M19 3 IO_L94P_3 M18 3 IO_L93N_3/VREF_3 M17 3 IO_L93P_3 N17 3 IO_L91N_3 N22 3 IO_L91P_3 N21 3 IO_L54N_3 N20 NC 3 IO_L54P_3 N19 NC 3 IO_L52N_3 N18 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 22 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 3 IO_L52P_3 P18 NC 3 IO_L51N_3/VREF_3 P22 NC 3 IO_L51P_3 P21 NC 3 IO_L49N_3 P20 NC 3 IO_L49P_3 P19 NC 3 IO_L48N_3 R22 3 IO_L48P_3 R21 3 IO_L46N_3 R20 3 IO_L46P_3 R19 3 IO_L45N_3/VREF_3 R18 3 IO_L45P_3 P17 3 IO_L43N_3 T22 3 IO_L43P_3 T21 3 IO_L24N_3 T20 NC NC 3 IO_L24P_3 T19 NC NC 3 IO_L22N_3 U22 NC NC 3 IO_L22P_3 U21 NC NC 3 IO_L21N_3/VREF_3 U20 NC NC 3 IO_L21P_3 U19 NC NC 3 IO_L19N_3 T18 NC NC 3 IO_L19P_3 U18 NC NC 3 IO_L06N_3 V22 3 IO_L06P_3 V21 3 IO_L04N_3 V20 3 IO_L04P_3 V19 3 IO_L03N_3/VREF_3 W22 3 IO_L03P_3 W21 3 IO_L02N_3/VRP_3 Y22 3 IO_L02P_3/VRN_3 Y21 3 IO_L01N_3 W20 3 IO_L01P_3 AA20 (1) 4 IO_L01N_4/BUSY/DOUT AB19 4 IO_L01P_4/INIT_B AA19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 23 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 (1) 4 IO_L02N_4/D0/DIN V18 4 IO_L02P_4/D1 V17 4 IO_L03N_4/D2/ALT_VRP_4 W18 4 IO_L03P_4/D3/ALT_VRN_4 Y18 4 IO_L04N_4/VREF_4 AA18 4 IO_L04P_4 AB18 4 IO_L05N_4/VRP_4 W17 4 IO_L05P_4/VRN_4 Y17 4 IO_L06N_4 AA17 4 IO_L06P_4 AB17 4 IO_L19N_4 V16 NC NC 4 IO_L19P_4 V15 NC NC 4 IO_L21N_4 W16 NC NC 4 IO_L21P_4/VREF_4 Y16 NC NC 4 IO_L22N_4 AA16 NC NC 4 IO_L22P_4 AB16 NC NC 4 IO_L24N_4 W15 NC NC 4 IO_L24P_4 Y15 NC NC 4 IO_L49N_4 AA15 NC 4 IO_L49P_4 AB15 NC 4 IO_L51N_4 U14 NC 4 IO_L51P_4/VREF_4 V14 NC 4 IO_L52N_4 W14 NC 4 IO_L52P_4 Y14 NC 4 IO_L54N_4 AA14 NC 4 IO_L54P_4 AB14 NC 4 IO_L91N_4/VREF_4 U13 4 IO_L91P_4 V13 4 IO_L92N_4 W13 4 IO_L92P_4 Y13 4 IO_L93N_4 AA13 4 IO_L93P_4 AB13 4 IO_L94N_4/VREF_4 U12 4 IO_L94P_4 V12 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 24 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 4 IO_L95N_4/GCLK3S W12 4 IO_L95P_4/GCLK2P Y12 4 IO_L96N_4/GCLK1S AA12 4 IO_L96P_4/GCLK0P AB12 5 IO_L96N_5/GCLK7S AA11 5 IO_L96P_5/GCLK6P Y11 5 IO_L95N_5/GCLK5S W11 5 IO_L95P_5/GCLK4P V11 5 IO_L94N_5 U11 5 IO_L94P_5/VREF_5 U10 5 IO_L93N_5 AB10 5 IO_L93P_5 AA10 5 IO_L92N_5 Y10 5 IO_L92P_5 W10 5 IO_L91N_5 V10 5 IO_L91P_5/VREF_5 V9 5 IO_L54N_5 AB9 NC 5 IO_L54P_5 AA9 NC 5 IO_L52N_5 Y9 NC 5 IO_L52P_5 W9 NC 5 IO_L51N_5/VREF_5 AB8 NC 5 IO_L51P_5 AA8 NC 5 IO_L49N_5 Y8 NC 5 IO_L49P_5 W8 NC 5 IO_L24N_5 U9 NC NC 5 IO_L24P_5 V8 NC NC 5 IO_L22N_5 AB7 NC NC 5 IO_L22P_5 AA7 NC NC 5 IO_L21N_5/VREF_5 Y7 NC NC 5 IO_L21P_5 W7 NC NC 5 IO_L19N_5 AB6 NC NC 5 IO_L19P_5 AA6 NC NC 5 IO_L06N_5 Y6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 25 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 5 IO_L06P_5 W6 5 IO_L05N_5/VRP_5 V7 5 IO_L05P_5/VRN_5 V6 5 IO_L04N_5 AB5 5 IO_L04P_5/VREF_5 AA5 5 IO_L03N_5/D4/ALT_VRP_5 Y5 5 IO_L03P_5/D5/ALT_VRN_5 W5 5 IO_L02N_5/D6 AB4 5 IO_L02P_5/D7 AA4 5 IO_L01N_5/RDWR_B Y4 5 IO_L01P_5/CS_B AA3 6 IO_L01P_6 V5 6 IO_L01N_6 U5 6 IO_L02P_6/VRN_6 Y2 6 IO_L02N_6/VRP_6 Y1 6 IO_L03P_6 V4 6 IO_L03N_6/VREF_6 V3 6 IO_L04P_6 W2 6 IO_L04N_6 W1 6 IO_L06P_6 U4 6 IO_L06N_6 U3 6 IO_L19P_6 V2 NC NC 6 IO_L19N_6 V1 NC NC 6 IO_L21P_6 U2 NC NC 6 IO_L21N_6/VREF_6 U1 NC NC 6 IO_L22P_6 T5 NC NC 6 IO_L22N_6 R5 NC NC 6 IO_L24P_6 T4 NC NC 6 IO_L24N_6 T3 NC NC 6 IO_L43P_6 T2 6 IO_L43N_6 T1 6 IO_L45P_6 R4 6 IO_L45N_6/VREF_6 R3 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 26 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 6 IO_L46P_6 R2 6 IO_L46N_6 R1 6 IO_L48P_6 P6 6 IO_L48N_6 P5 6 IO_L49P_6 P4 NC 6 IO_L49N_6 P3 NC 6 IO_L51P_6 P2 NC 6 IO_L51N_6/VREF_6 P1 NC 6 IO_L52P_6 N6 NC 6 IO_L52N_6 N5 NC 6 IO_L54P_6 N4 NC 6 IO_L54N_6 N3 NC 6 IO_L91P_6 N2 6 IO_L91N_6 N1 6 IO_L93P_6 M6 6 IO_L93N_6/VREF_6 M5 6 IO_L94P_6 M4 6 IO_L94N_6 M3 6 IO_L96P_6 M2 6 IO_L96N_6 M1 7 IO_L96P_7 L2 7 IO_L96N_7 L3 7 IO_L94P_7 L4 7 IO_L94N_7 L5 7 IO_L93P_7/VREF_7 K1 7 IO_L93N_7 K2 7 IO_L91P_7 K3 7 IO_L91N_7 K4 7 IO_L54P_7 L6 NC 7 IO_L54N_7 K6 NC 7 IO_L52P_7 K5 NC 7 IO_L52N_7 J5 NC 7 IO_L51P_7/VREF_7 J1 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 27 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 7 IO_L51N_7 J2 NC 7 IO_L49P_7 J3 NC 7 IO_L49N_7 J4 NC 7 IO_L48P_7 H1 7 IO_L48N_7 H2 7 IO_L46P_7 H3 7 IO_L46N_7 H4 7 IO_L45P_7/VREF_7 J6 7 IO_L45N_7 H5 7 IO_L43P_7 G1 7 IO_L43N_7 G2 7 IO_L24P_7 G3 NC NC 7 IO_L24N_7 G4 NC NC 7 IO_L22P_7 F1 NC NC 7 IO_L22N_7 F2 NC NC 7 IO_L21P_7/VREF_7 F3 NC NC 7 IO_L21N_7 F4 NC NC 7 IO_L19P_7 G5 NC NC 7 IO_L19N_7 F5 NC NC 7 IO_L06P_7 E1 7 IO_L06N_7 E2 7 IO_L04P_7 E3 7 IO_L04N_7 E4 7 IO_L03P_7/VREF_7 D1 7 IO_L03N_7 D2 7 IO_L02P_7/VRN_7 C1 7 IO_L02N_7/VRP_7 C2 7 IO_L01P_7 E5 7 IO_L01N_7 E6 0 VCCO_0 G11 0 VCCO_0 G10 0 VCCO_0 G9 0 VCCO_0 F8 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 28 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 0 VCCO_0 F7 1 VCCO_1 G14 1 VCCO_1 G13 1 VCCO_1 G12 1 VCCO_1 F16 1 VCCO_1 F15 2 VCCO_2 L16 2 VCCO_2 K16 2 VCCO_2 J16 2 VCCO_2 H17 2 VCCO_2 G17 3 VCCO_3 T17 3 VCCO_3 R17 3 VCCO_3 P16 3 VCCO_3 N16 3 VCCO_3 M16 4 VCCO_4 U16 4 VCCO_4 U15 4 VCCO_4 T14 4 VCCO_4 T13 4 VCCO_4 T12 5 VCCO_5 U8 5 VCCO_5 U7 5 VCCO_5 T11 5 VCCO_5 T10 5 VCCO_5 T9 6 VCCO_6 T6 6 VCCO_6 R6 6 VCCO_6 P7 6 VCCO_6 N7 6 VCCO_6 M7 7 VCCO_7 L7 7 VCCO_7 K7 7 VCCO_7 J7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 29 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 7 VCCO_7 H6 7 VCCO_7 G6 NA CCLK Y19 NA PROG_B A2 NA DONE AB20 NA M0 AB2 NA M1 W3 NA M2 AB3 NA HSWAP_EN B3 NA TCK C19 NA TDI D3 NA TDO D20 NA TMS B20 NA PWRDWN_B AB21 NA DXN D5 NA DXP A3 NA VBATT A21 NA RSVD A20 NA VCCAUX AB11 NA VCCAUX AA22 NA VCCAUX AA1 NA VCCAUX M22 NA VCCAUX L1 NA VCCAUX B22 NA VCCAUX B1 NA VCCAUX A12 NA VCCINT U17 NA VCCINT U6 NA VCCINT T16 NA VCCINT T15 NA VCCINT T8 NA VCCINT T7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 30 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 NA VCCINT R16 NA VCCINT R7 NA VCCINT H16 NA VCCINT H7 NA VCCINT G16 NA VCCINT G15 NA VCCINT G8 NA VCCINT G7 NA VCCINT F17 NA VCCINT F6 NA GND AB22 NA GND AB1 NA GND AA21 NA GND AA2 NA GND Y20 NA GND Y3 NA GND W19 NA GND W4 NA GND P14 NA GND P13 NA GND P12 NA GND P11 NA GND P10 NA GND P9 NA GND N14 NA GND N13 NA GND N12 NA GND N11 NA GND N10 NA GND N9 NA GND M14 NA GND M13 NA GND M12 NA GND M11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 31 R Virtex-II Platform FPGAs: Pinout Information Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500 NA GND M10 NA GND M9 NA GND L14 NA GND L13 NA GND L12 NA GND L11 NA GND L10 NA GND L9 NA GND K14 NA GND K13 NA GND K12 NA GND K11 NA GND K10 NA GND K9 NA GND J14 NA GND J13 NA GND J12 NA GND J11 NA GND J10 NA GND J9 NA GND D19 NA GND D4 NA GND C20 NA GND C3 NA GND B21 NA GND B2 NA GND A22 NA GND A1 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 32 R Virtex-II Platform FPGAs: Pinout Information FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 3: FG456/FGG456 Fine-Pitch BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 33 R Virtex-II Platform FPGAs: Pinout Information FG676/FGG676 Fine-Pitch BGA Package As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676/FGG676 fine-pitch BGA package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 0 IO_L01N_0 D6 0 IO_L01P_0 C6 0 IO_L02N_0 B1 0 IO_L02P_0 A2 0 IO_L03N_0/VRP_0 D7 0 IO_L03P_0/VRN_0 C7 0 IO_L04N_0/VREF_0 B3 0 IO_L04P_0 A3 0 IO_L05N_0 G6 0 IO_L05P_0 G7 0 IO_L06N_0 E6 0 IO_L06P_0 E7 0 IO_L19N_0 B4 0 IO_L19P_0 A4 0 IO_L21N_0 B5 0 IO_L21P_0/VREF_0 A5 0 IO_L22N_0 B6 0 IO_L22P_0 A6 0 IO_L24N_0 A7 0 IO_L24P_0 A8 0 IO_L25N_0 E8 NC NC 0 IO_L25P_0 D8 NC NC 0 IO_L27N_0 G8 NC NC 0 IO_L27P_0/VREF_0 F8 NC NC 0 IO_L49N_0 C8 0 IO_L49P_0 B8 0 IO_L51N_0 D9 0 IO_L51P_0/VREF_0 E9 0 IO_L52N_0 F9 0 IO_L52P_0 G9 0 IO_L54N_0 B9 0 IO_L54P_0 A9 0 IO_L67N_0 C9 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 34 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 0 IO_L67P_0 C10 0 IO_L69N_0 F10 0 IO_L69P_0/VREF_0 G10 0 IO_L70N_0 E10 0 IO_L70P_0 D10 0 IO_L72N_0 A10 0 IO_L72P_0 A11 0 IO_L73N_0 F11 NC 0 IO_L73P_0 E11 NC 0 IO_L75N_0 G11 NC 0 IO_L75P_0/VREF_0 H11 NC 0 IO_L76N_0 D11 NC 0 IO_L76P_0 C11 NC 0 IO_L78N_0 B11 NC 0 IO_L78P_0 B12 NC 0 IO_L91N_0/VREF_0 G12 0 IO_L91P_0 H12 0 IO_L92N_0 F12 0 IO_L92P_0 E12 0 IO_L93N_0 D12 0 IO_L93P_0 C12 0 IO_L94N_0/VREF_0 G13 0 IO_L94P_0 H13 0 IO_L95N_0/GCLK7P F13 0 IO_L95P_0/GCLK6S E13 0 IO_L96N_0/GCLK5P D13 0 IO_L96P_0/GCLK4S C13 1 IO_L96N_1/GCLK3P H14 1 IO_L96P_1/GCLK2S H15 1 IO_L95N_1/GCLK1P G14 1 IO_L95P_1/GCLK0S F14 1 IO_L94N_1 E14 1 IO_L94P_1/VREF_1 D14 1 IO_L93N_1 A12 1 IO_L93P_1 A13 1 IO_L92N_1 A14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 35 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 1 IO_L92P_1 A15 1 IO_L91N_1 B15 1 IO_L91P_1/VREF_1 C15 1 IO_L78N_1 D15 NC 1 IO_L78P_1 E15 NC 1 IO_L76N_1 F15 NC 1 IO_L76P_1 G15 NC 1 IO_L75N_1/VREF_1 G16 NC 1 IO_L75P_1 F16 NC 1 IO_L73N_1 A16 NC 1 IO_L73P_1 A17 NC 1 IO_L72N_1 B16 1 IO_L72P_1 C16 1 IO_L70N_1 D16 1 IO_L70P_1 E16 1 IO_L69N_1/VREF_1 C17 1 IO_L69P_1 D17 1 IO_L67N_1 H16 1 IO_L67P_1 G17 1 IO_L54N_1 E17 1 IO_L54P_1 F17 1 IO_L52N_1 A18 1 IO_L52P_1 A19 1 IO_L51N_1/VREF_1 E18 1 IO_L51P_1 D18 1 IO_L49N_1 B18 1 IO_L49P_1 C18 1 IO_L27N_1/VREF_1 F19 NC NC 1 IO_L27P_1 F18 NC NC 1 IO_L25N_1 G18 NC NC 1 IO_L25P_1 G19 NC NC 1 IO_L24N_1 B19 1 IO_L24P_1 C19 1 IO_L22N_1 D19 1 IO_L22P_1 E19 1 IO_L21N_1/VREF_1 A20 1 IO_L21P_1 A21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 36 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 1 IO_L19N_1 E20 1 IO_L19P_1 F20 1 IO_L06N_1 B21 1 IO_L06P_1 B22 1 IO_L05N_1 A22 1 IO_L05P_1 A23 1 IO_L04N_1 C21 1 IO_L04P_1/VREF_1 D21 1 IO_L03N_1/VRP_1 C20 1 IO_L03P_1/VRN_1 D20 1 IO_L02N_1 A24 1 IO_L02P_1 A25 1 IO_L01N_1 B23 1 IO_L01P_1 B24 2 IO_L01N_2 B26 2 IO_L01P_2 C26 2 IO_L02N_2/VRP_2 G20 2 IO_L02P_2/VRN_2 H20 2 IO_L03N_2 C25 2 IO_L03P_2/VREF_2 D25 2 IO_L04N_2 E23 2 IO_L04P_2 E24 2 IO_L06N_2 G21 2 IO_L06P_2 G22 2 IO_L19N_2 D26 2 IO_L19P_2 E26 2 IO_L21N_2 F23 2 IO_L21P_2/VREF_2 F24 2 IO_L22N_2 E25 2 IO_L22P_2 F25 2 IO_L24N_2 H22 2 IO_L24P_2 H21 2 IO_L25N_2 G23 NC NC 2 IO_L25P_2 G24 NC NC 2 IO_L43N_2 F26 2 IO_L43P_2 G26 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 37 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 2 IO_L45N_2 H23 2 IO_L45P_2/VREF_2 H24 2 IO_L46N_2 J21 2 IO_L46P_2 J20 2 IO_L48N_2 H25 2 IO_L48P_2 H26 2 IO_L49N_2 J22 2 IO_L49P_2 J23 2 IO_L51N_2 K21 2 IO_L51P_2/VREF_2 K22 2 IO_L52N_2 K20 2 IO_L52P_2 L20 2 IO_L54N_2 J24 2 IO_L54P_2 J25 2 IO_L67N_2 K23 2 IO_L67P_2 K24 2 IO_L69N_2 J26 2 IO_L69P_2/VREF_2 K26 2 IO_L70N_2 L22 2 IO_L70P_2 L21 2 IO_L72N_2 L25 2 IO_L72P_2 L26 2 IO_L73N_2 L19 NC 2 IO_L73P_2 M19 NC 2 IO_L75N_2 L23 NC 2 IO_L75P_2/VREF_2 L24 NC 2 IO_L76N_2 M22 NC 2 IO_L76P_2 M21 NC 2 IO_L78N_2 M23 NC 2 IO_L78P_2 M24 NC 2 IO_L91N_2 M25 2 IO_L91P_2 M26 2 IO_L93N_2 M20 2 IO_L93P_2/VREF_2 N20 2 IO_L94N_2 N22 2 IO_L94P_2 N21 2 IO_L96N_2 N24 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 38 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 2 IO_L96P_2 N23 3 IO_L96N_3 N26 3 IO_L96P_3 P26 3 IO_L94N_3 P23 3 IO_L94P_3 P22 3 IO_L93N_3/VREF_3 P19 3 IO_L93P_3 N19 3 IO_L91N_3 P21 3 IO_L91P_3 P20 3 IO_L78N_3 R26 NC 3 IO_L78P_3 R25 NC 3 IO_L76N_3 R20 NC 3 IO_L76P_3 R19 NC 3 IO_L75N_3/VREF_3 R24 NC 3 IO_L75P_3 R23 NC 3 IO_L73N_3 R22 NC 3 IO_L73P_3 R21 NC 3 IO_L72N_3 T26 3 IO_L72P_3 T25 3 IO_L70N_3 T20 3 IO_L70P_3 T19 3 IO_L69N_3/VREF_3 T24 3 IO_L69P_3 T23 3 IO_L67N_3 T22 3 IO_L67P_3 T21 3 IO_L54N_3 U26 3 IO_L54P_3 V26 3 IO_L52N_3 U24 3 IO_L52P_3 U23 3 IO_L51N_3/VREF_3 U22 3 IO_L51P_3 U21 3 IO_L49N_3 V25 3 IO_L49P_3 V24 3 IO_L48N_3 V23 3 IO_L48P_3 V22 3 IO_L46N_3 W26 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 39 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 3 IO_L46P_3 Y26 3 IO_L45N_3/VREF_3 U20 3 IO_L45P_3 V20 3 IO_L43N_3 W25 3 IO_L43P_3 W24 3 IO_L25N_3 V21 NC NC 3 IO_L25P_3 W21 NC NC 3 IO_L24N_3 AA26 3 IO_L24P_3 AA25 3 IO_L22N_3 Y24 3 IO_L22P_3 Y23 3 IO_L21N_3/VREF_3 W22 3 IO_L21P_3 W23 3 IO_L19N_3 AB26 3 IO_L19P_3 AB25 3 IO_L06N_3 AC26 3 IO_L06P_3 AC25 3 IO_L04N_3 AD26 3 IO_L04P_3 AD25 3 IO_L03N_3/VREF_3 AA24 3 IO_L03P_3 AA23 3 IO_L02N_3/VRP_3 AB24 3 IO_L02P_3/VRN_3 AB23 3 IO_L01N_3 Y22 3 IO_L01P_3 AA22 (1) 4 IO_L01N_4/BUSY/DOUT AD21 4 IO_L01P_4/INIT_B AC21 (1) 4 IO_L02N_4/D0/DIN Y20 4 IO_L02P_4/D1 Y19 4 IO_L03N_4/D2/ALT_VRP_4 AA20 4 IO_L03P_4/D3/ALT_VRN_4 AB20 4 IO_L04N_4/VREF_4 AC22 4 IO_L04P_4 AE21 4 IO_L05N_4/VRP_4 AE26 4 IO_L05P_4/VRN_4 AF25 4 IO_L06N_4 W20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 40 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 4 IO_L06P_4 Y21 4 IO_L19N_4 AE24 4 IO_L19P_4 AF24 4 IO_L21N_4 AE23 4 IO_L21P_4/VREF_4 AF23 4 IO_L22N_4 AE22 4 IO_L22P_4 AF22 4 IO_L24N_4 AF21 4 IO_L24P_4 AF20 4 IO_L25N_4 AA19 NC NC 4 IO_L25P_4 AB19 NC NC 4 IO_L27N_4 AD20 NC NC 4 IO_L27P_4/VREF_4 AC20 NC NC 4 IO_L28N_4 AC19 NC NC 4 IO_L28P_4 AD19 NC NC 4 IO_L49N_4 AE19 4 IO_L49P_4 AF19 4 IO_L51N_4 AA18 4 IO_L51P_4/VREF_4 AB18 4 IO_L52N_4 Y18 4 IO_L52P_4 Y17 4 IO_L54N_4 AC18 4 IO_L54P_4 AD18 4 IO_L67N_4 AE18 4 IO_L67P_4 AF18 4 IO_L69N_4 AA17 4 IO_L69P_4/VREF_4 AB17 4 IO_L70N_4 AC17 4 IO_L70P_4 AD17 4 IO_L72N_4 AF17 4 IO_L72P_4 AF16 4 IO_L73N_4 AB16 NC 4 IO_L73P_4 AC16 NC 4 IO_L75N_4 AA16 NC 4 IO_L75P_4/VREF_4 Y16 NC 4 IO_L76N_4 AD16 NC 4 IO_L76P_4 AE16 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 41 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 4 IO_L78N_4 Y15 NC 4 IO_L78P_4 AA15 NC 4 IO_L91N_4/VREF_4 W15 4 IO_L91P_4 W16 4 IO_L92N_4 AB15 4 IO_L92P_4 AC15 4 IO_L93N_4 AD15 4 IO_L93P_4 AE15 4 IO_L94N_4/VREF_4 W14 4 IO_L94P_4 Y14 4 IO_L95N_4/GCLK3S AA14 4 IO_L95P_4/GCLK2P AB14 4 IO_L96N_4/GCLK1S AC14 4 IO_L96P_4/GCLK0P AD14 5 IO_L96N_5/GCLK7S AC13 5 IO_L96P_5/GCLK6P AB13 5 IO_L95N_5/GCLK5S AA13 5 IO_L95P_5/GCLK4P Y13 5 IO_L94N_5 W13 5 IO_L94P_5/VREF_5 W12 5 IO_L93N_5 AF15 5 IO_L93P_5 AF14 5 IO_L92N_5 AF13 5 IO_L92P_5 AF12 5 IO_L91N_5 AE12 5 IO_L91P_5/VREF_5 AD12 5 IO_L78N_5 AC12 NC 5 IO_L78P_5 AB12 NC 5 IO_L76N_5 AA12 NC 5 IO_L76P_5 Y12 NC 5 IO_L75N_5/VREF_5 AF11 NC 5 IO_L75P_5 AF10 NC 5 IO_L73N_5 AE11 NC 5 IO_L73P_5 AD11 NC 5 IO_L72N_5 AC11 5 IO_L72P_5 AB11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 42 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 5 IO_L70N_5 W11 5 IO_L70P_5 Y10 5 IO_L69N_5/VREF_5 Y11 5 IO_L69P_5 AA11 5 IO_L67N_5 AF9 5 IO_L67P_5 AF8 5 IO_L54N_5 AE9 5 IO_L54P_5 AD9 5 IO_L52N_5 AB10 5 IO_L52P_5 AA10 5 IO_L51N_5/VREF_5 AD10 5 IO_L51P_5 AC10 5 IO_L49N_5 AE8 5 IO_L49P_5 AF7 5 IO_L28N_5 AD8 NC NC 5 IO_L28P_5 AC8 NC NC 5 IO_L27N_5/VREF_5 AB9 NC NC 5 IO_L27P_5 AC9 NC NC 5 IO_L25N_5 AA9 NC NC 5 IO_L25P_5 Y9 NC NC 5 IO_L24N_5 AF6 5 IO_L24P_5 AE6 5 IO_L22N_5 AB8 5 IO_L22P_5 AA8 5 IO_L21N_5/VREF_5 AC7 5 IO_L21P_5 AD7 5 IO_L19N_5 AF5 5 IO_L19P_5 AE5 5 IO_L06N_5 AF4 5 IO_L06P_5 AE4 5 IO_L05N_5/VRP_5 AF3 5 IO_L05P_5/VRN_5 AE3 5 IO_L04N_5 Y8 5 IO_L04P_5/VREF_5 Y7 5 IO_L03N_5/D4/ALT_VRP_5 AB7 5 IO_L03P_5/D5/ALT_VRN_5 AA7 5 IO_L02N_5/D6 AD6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 43 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 5 IO_L02P_5/D7 AC6 5 IO_L01N_5/RDWR_B AB6 5 IO_L01P_5/CS_B AC5 6 IO_L01P_6 AF2 6 IO_L01N_6 AE1 6 IO_L02P_6/VRN_6 AB4 6 IO_L02N_6/VRP_6 AB3 6 IO_L03P_6 AD2 6 IO_L03N_6/VREF_6 AD1 6 IO_L04P_6 AC2 6 IO_L04N_6 AC1 6 IO_L06P_6 AB2 6 IO_L06N_6 AB1 6 IO_L19P_6 AA4 6 IO_L19N_6 AA3 6 IO_L21P_6 Y6 6 IO_L21N_6/VREF_6 Y5 6 IO_L22P_6 W6 6 IO_L22N_6 W7 6 IO_L24P_6 AA2 6 IO_L24N_6 AA1 6 IO_L25P_6 Y4 NC NC 6 IO_L25N_6 Y3 NC NC 6 IO_L43P_6 W5 6 IO_L43N_6 W4 6 IO_L45P_6 W2 6 IO_L45N_6/VREF_6 W3 6 IO_L46P_6 Y1 6 IO_L46N_6 W1 6 IO_L48P_6 V6 6 IO_L48N_6 V7 6 IO_L49P_6 V5 6 IO_L49N_6 V4 6 IO_L51P_6 V3 6 IO_L51N_6/VREF_6 V2 6 IO_L52P_6 V1 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 44 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 6 IO_L52N_6 U1 6 IO_L54P_6 U7 6 IO_L54N_6 T7 6 IO_L67P_6 U4 6 IO_L67N_6 U3 6 IO_L69P_6 U6 6 IO_L69N_6/VREF_6 U5 6 IO_L70P_6 T5 6 IO_L70N_6 T6 6 IO_L72P_6 T8 6 IO_L72N_6 R8 6 IO_L73P_6 T2 NC 6 IO_L73N_6 T1 NC 6 IO_L75P_6 T4 NC 6 IO_L75N_6/VREF_6 T3 NC 6 IO_L76P_6 R6 NC 6 IO_L76N_6 R5 NC 6 IO_L78P_6 R4 NC 6 IO_L78N_6 R3 NC 6 IO_L91P_6 R2 6 IO_L91N_6 R1 6 IO_L93P_6 R7 6 IO_L93N_6/VREF_6 P7 6 IO_L94P_6 P6 6 IO_L94N_6 P5 6 IO_L96P_6 P4 6 IO_L96N_6 P3 7 IO_L96P_7 P1 7 IO_L96N_7 N1 7 IO_L94P_7 N4 7 IO_L94N_7 N5 7 IO_L93P_7/VREF_7 N6 7 IO_L93N_7 N7 7 IO_L91P_7 P8 7 IO_L91N_7 N8 7 IO_L78P_7 M1 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 45 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 7 IO_L78N_7 M2 NC 7 IO_L76P_7 M5 NC 7 IO_L76N_7 M6 NC 7 IO_L75P_7/VREF_7 M3 NC 7 IO_L75N_7 M4 NC 7 IO_L73P_7 M7 NC 7 IO_L73N_7 M8 NC 7 IO_L72P_7 L1 7 IO_L72N_7 L2 7 IO_L70P_7 L5 7 IO_L70N_7 L6 7 IO_L69P_7/VREF_7 L3 7 IO_L69N_7 L4 7 IO_L67P_7 K1 7 IO_L67N_7 J1 7 IO_L54P_7 K3 7 IO_L54N_7 K4 7 IO_L52P_7 K5 7 IO_L52N_7 K6 7 IO_L51P_7/VREF_7 L8 7 IO_L51N_7 L7 7 IO_L49P_7 J2 7 IO_L49N_7 H1 7 IO_L48P_7 J3 7 IO_L48N_7 J4 7 IO_L46P_7 J5 7 IO_L46N_7 J6 7 IO_L45P_7/VREF_7 H5 7 IO_L45N_7 H4 7 IO_L43P_7 K7 7 IO_L43N_7 J7 7 IO_L25P_7 H2 NC NC 7 IO_L25N_7 H3 NC NC 7 IO_L24P_7 G1 7 IO_L24N_7 F1 7 IO_L22P_7 G3 7 IO_L22N_7 G4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 46 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 7 IO_L21P_7/VREF_7 F3 7 IO_L21N_7 F2 7 IO_L19P_7 H6 7 IO_L19N_7 H7 7 IO_L06P_7 E1 7 IO_L06N_7 E2 7 IO_L04P_7 D1 7 IO_L04N_7 D2 7 IO_L03P_7/VREF_7 C1 7 IO_L03N_7 C2 7 IO_L02P_7/VRN_7 E3 7 IO_L02N_7/VRP_7 E4 7 IO_L01P_7 G5 7 IO_L01N_7 F4 0 VCCO_0 J13 0 VCCO_0 J12 0 VCCO_0 J11 0 VCCO_0 H10 0 VCCO_0 H9 0 VCCO_0 B10 0 VCCO_0 B7 1 VCCO_1 B17 1 VCCO_1 J16 1 VCCO_1 J15 1 VCCO_1 J14 1 VCCO_1 H18 1 VCCO_1 H17 1 VCCO_1 B20 2 VCCO_2 N18 2 VCCO_2 M18 2 VCCO_2 L18 2 VCCO_2 K25 2 VCCO_2 K19 2 VCCO_2 J19 2 VCCO_2 G25 3 VCCO_3 Y25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 47 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 3 VCCO_3 V19 3 VCCO_3 U25 3 VCCO_3 U19 3 VCCO_3 T18 3 VCCO_3 R18 3 VCCO_3 P18 4 VCCO_4 AE20 4 VCCO_4 AE17 4 VCCO_4 W18 4 VCCO_4 W17 4 VCCO_4 V16 4 VCCO_4 V15 4 VCCO_4 V14 5 VCCO_5 AE10 5 VCCO_5 AE7 5 VCCO_5 W10 5 VCCO_5 W9 5 VCCO_5 V13 5 VCCO_5 V12 5 VCCO_5 V11 6 VCCO_6 Y2 6 VCCO_6 V8 6 VCCO_6 U8 6 VCCO_6 U2 6 VCCO_6 T9 6 VCCO_6 R9 6 VCCO_6 P9 7 VCCO_7 N9 7 VCCO_7 M9 7 VCCO_7 L9 7 VCCO_7 K8 7 VCCO_7 K2 7 VCCO_7 J8 7 VCCO_7 G2 NA CCLK AB21 NA PROG_B C4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 48 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 NA DONE AD22 NA M0 AD4 NA M1 AA5 NA M2 AD5 NA HSWAP_EN D5 NA TCK E21 NA TDI F5 NA TDO F22 NA TMS D22 NA PWRDWN_B AD23 NA DXN F7 NA DXP C5 NA VBATT C23 NA RSVD C22 NA VCCAUX AD13 NA VCCAUX AC24 NA VCCAUX AC3 NA VCCAUX P24 NA VCCAUX N3 NA VCCAUX D24 NA VCCAUX D3 NA VCCAUX C14 NA VCCINT W19 NA VCCINT W8 NA VCCINT V18 NA VCCINT V17 NA VCCINT V10 NA VCCINT V9 NA VCCINT U18 NA VCCINT U9 NA VCCINT K18 NA VCCINT K9 NA VCCINT J18 NA VCCINT J17 NA VCCINT J10 NA VCCINT J9 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 49 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 NA VCCINT H19 NA VCCINT H8 NA GND AF26 NA GND AF1 NA GND AE25 NA GND AE14 NA GND AE13 NA GND AE2 NA GND AD24 NA GND AD3 NA GND AC23 NA GND AC4 NA GND AB22 NA GND AB5 NA GND AA21 NA GND AA6 NA GND U17 NA GND U16 NA GND U15 NA GND U14 NA GND U13 NA GND U12 NA GND U11 NA GND U10 NA GND T17 NA GND T16 NA GND T15 NA GND T14 NA GND T13 NA GND T12 NA GND T11 NA GND T10 NA GND R17 NA GND R16 NA GND R15 NA GND R14 NA GND R13 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 50 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 NA GND R12 NA GND R11 NA GND R10 NA GND P25 NA GND P17 NA GND P16 NA GND P15 NA GND P14 NA GND P13 NA GND P12 NA GND P11 NA GND P10 NA GND P2 NA GND N25 NA GND N17 NA GND N16 NA GND N15 NA GND N14 NA GND N13 NA GND N12 NA GND N11 NA GND N10 NA GND N2 NA GND M17 NA GND M16 NA GND M15 NA GND M14 NA GND M13 NA GND M12 NA GND M11 NA GND M10 NA GND L17 NA GND L16 NA GND L15 NA GND L14 NA GND L13 NA GND L12 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 51 R Virtex-II Platform FPGAs: Pinout Information Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000 NA GND L11 NA GND L10 NA GND K17 NA GND K16 NA GND K15 NA GND K14 NA GND K13 NA GND K12 NA GND K11 NA GND K10 NA GND F21 NA GND F6 NA GND E22 NA GND E5 NA GND D23 NA GND D4 NA GND C24 NA GND C3 NA GND B25 NA GND B14 NA GND B13 NA GND B2 NA GND A26 NA GND A1 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 52 R Virtex-II Platform FPGAs: Pinout Information FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 4: FG676/FGG676 Fine-Pitch BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 53 R Virtex-II Platform FPGAs: Pinout Information BG575/BGG575 Standard BGA Package As shown in Table 9, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575/BGG575 BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the BG575/BGG575 Standard BGA Package Specifications (1.27mm pitch). Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 0 IO_L01N_0 A3 0 IO_L01P_0 A4 0 IO_L02N_0 D5 0 IO_L02P_0 C5 0 IO_L03N_0/VRP_0 E6 0 IO_L03P_0/VRN_0 D6 0 IO_L04N_0/VREF_0 F7 0 IO_L04P_0 E7 0 IO_L05N_0 G8 0 IO_L05P_0 H9 0 IO_L06N_0 A5 0 IO_L06P_0 A6 0 IO_L19N_0 B5 0 IO_L19P_0 B6 0 IO_L21N_0 D7 0 IO_L21P_0/VREF_0 C7 0 IO_L22N_0 F8 0 IO_L22P_0 E8 0 IO_L24N_0 G9 0 IO_L24P_0 F9 0 IO_L49N_0 G10 0 IO_L49P_0 H10 0 IO_L51N_0 B7 0 IO_L51P_0/VREF_0 B8 0 IO_L52N_0 D8 0 IO_L52P_0 C8 0 IO_L54N_0 E9 0 IO_L54P_0 D9 0 IO_L67N_0 A8 NC 0 IO_L67P_0 A9 NC 0 IO_L69N_0 C9 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 54 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 0 IO_L69P_0/VREF_0 B9 NC 0 IO_L70N_0 F10 NC 0 IO_L70P_0 E10 NC 0 IO_L72N_0 A10 NC 0 IO_L72P_0 A11 NC 0 IO_L73N_0 C10 NC NC 0 IO_L73P_0 B10 NC NC 0 IO_L91N_0/VREF_0 D11 0 IO_L91P_0 C11 0 IO_L92N_0 G11 0 IO_L92P_0 E11 0 IO_L93N_0 C12 0 IO_L93P_0 B12 0 IO_L94N_0/VREF_0 E12 0 IO_L94P_0 D12 0 IO_L95N_0/GCLK7P G12 0 IO_L95P_0/GCLK6S F12 0 IO_L96N_0/GCLK5P H11 0 IO_L96P_0/GCLK4S H12 1 IO_L96N_1/GCLK3P A13 1 IO_L96P_1/GCLK2S A14 1 IO_L95N_1/GCLK1P B13 1 IO_L95P_1/GCLK0S C13 1 IO_L94N_1 D13 1 IO_L94P_1/VREF_1 E13 1 IO_L93N_1 F13 1 IO_L93P_1 G13 1 IO_L92N_1 H13 1 IO_L92P_1 H14 1 IO_L91N_1 C14 1 IO_L91P_1/VREF_1 D14 1 IO_L73N_1 E14 NC NC 1 IO_L73P_1 G14 NC NC 1 IO_L72N_1 A15 NC 1 IO_L72P_1 A16 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 55 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 1 IO_L70N_1 B15 NC 1 IO_L70P_1 C15 NC 1 IO_L69N_1/VREF_1 E15 NC 1 IO_L69P_1 F15 NC 1 IO_L67N_1 G15 NC 1 IO_L67P_1 H15 NC 1 IO_L54N_1 B16 1 IO_L54P_1 C16 1 IO_L52N_1 D16 1 IO_L52P_1 E16 1 IO_L51N_1/VREF_1 F16 1 IO_L51P_1 G16 1 IO_L49N_1 A17 1 IO_L49P_1 A19 1 IO_L24N_1 B17 1 IO_L24P_1 B18 1 IO_L22N_1 C17 1 IO_L22P_1 D17 1 IO_L21N_1/VREF_1 F17 1 IO_L21P_1 E17 1 IO_L19N_1 A20 1 IO_L19P_1 A21 1 IO_L06N_1 B19 1 IO_L06P_1 B20 1 IO_L05N_1 C18 1 IO_L05P_1 D18 1 IO_L04N_1 C20 1 IO_L04P_1/VREF_1 D20 1 IO_L03N_1/VRP_1 D19 1 IO_L03P_1/VRN_1 E19 1 IO_L02N_1 E18 1 IO_L02P_1 F18 1 IO_L01N_1 H16 1 IO_L01P_1 G17 2 IO_L01N_2 D22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 56 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 2 IO_L01P_2 D23 2 IO_L02N_2/VRP_2 E21 2 IO_L02P_2/VRN_2 E22 2 IO_L03N_2 F21 2 IO_L03P_2/VREF_2 F20 2 IO_L04N_2 G20 2 IO_L04P_2 G19 2 IO_L06N_2 H18 2 IO_L06P_2 J17 2 IO_L19N_2 D24 2 IO_L19P_2 E23 2 IO_L21N_2 E24 2 IO_L21P_2/VREF_2 F24 2 IO_L22N_2 F23 2 IO_L22P_2 G23 2 IO_L24N_2 G21 2 IO_L24P_2 G22 2 IO_L43N_2 H19 2 IO_L43P_2 H20 2 IO_L45N_2 J18 2 IO_L45P_2/VREF_2 J19 2 IO_L46N_2 K17 2 IO_L46P_2 K18 2 IO_L48N_2 H23 2 IO_L48P_2 H24 2 IO_L49N_2 H21 2 IO_L49P_2 H22 2 IO_L51N_2 J24 2 IO_L51P_2/VREF_2 K24 2 IO_L52N_2 J22 2 IO_L52P_2 J23 2 IO_L54N_2 J20 2 IO_L54P_2 J21 2 IO_L67N_2 K19 NC 2 IO_L67P_2 K20 NC 2 IO_L69N_2 L17 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 57 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 2 IO_L69P_2/VREF_2 L18 NC 2 IO_L70N_2 K23 NC 2 IO_L70P_2 L24 NC 2 IO_L72N_2 K22 NC 2 IO_L72P_2 L22 NC 2 IO_L73N_2 L21 NC NC 2 IO_L73P_2 L20 NC NC 2 IO_L91N_2 M23 2 IO_L91P_2 N24 2 IO_L93N_2 M21 2 IO_L93P_2/VREF_2 M22 2 IO_L94N_2 M19 2 IO_L94P_2 M20 2 IO_L96N_2 M17 2 IO_L96P_2 M18 3 IO_L96N_3 N23 3 IO_L96P_3 N22 3 IO_L94N_3 N20 3 IO_L94P_3 N21 3 IO_L93N_3/VREF_3 N19 3 IO_L93P_3 N18 3 IO_L91N_3 N17 3 IO_L91P_3 P17 3 IO_L73N_3 P24 NC NC 3 IO_L73P_3 R24 NC NC 3 IO_L72N_3 R23 NC 3 IO_L72P_3 R22 NC 3 IO_L70N_3 P22 NC 3 IO_L70P_3 P21 NC 3 IO_L69N_3/VREF_3 P20 NC 3 IO_L69P_3 P18 NC 3 IO_L67N_3 T24 NC 3 IO_L67P_3 U24 NC 3 IO_L54N_3 T23 3 IO_L54P_3 T22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 58 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 3 IO_L52N_3 T21 3 IO_L52P_3 T20 3 IO_L51N_3/VREF_3 R20 3 IO_L51P_3 R19 3 IO_L49N_3 W24 3 IO_L49P_3 W23 3 IO_L48N_3 U23 3 IO_L48P_3 V23 3 IO_L46N_3 U22 3 IO_L46P_3 U21 3 IO_L45N_3/VREF_3 V22 3 IO_L45P_3 V21 3 IO_L43N_3 U19 3 IO_L43P_3 U20 3 IO_L24N_3 T19 3 IO_L24P_3 T18 3 IO_L22N_3 R18 3 IO_L22P_3 R17 3 IO_L21N_3/VREF_3 Y24 3 IO_L21P_3 Y23 3 IO_L19N_3 AA24 3 IO_L19P_3 AB24 3 IO_L06N_3 AA23 3 IO_L06P_3 AA22 3 IO_L04N_3 Y22 3 IO_L04P_3 Y21 3 IO_L03N_3/VREF_3 W21 3 IO_L03P_3 W20 3 IO_L02N_3/VRP_3 V20 3 IO_L02P_3/VRN_3 V19 3 IO_L01N_3 U18 3 IO_L01P_3 T17 (1) 4 IO_L01N_4/BUSY/DOUT AD22 4 IO_L01P_4/INIT_B AD21 (1) 4 IO_L02N_4/D0/DIN AA20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 59 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 4 IO_L02P_4/D1 AB20 4 IO_L03N_4/D2/ALT_VRP_4 Y19 4 IO_L03P_4/D3/ALT_VRN_4 AA19 4 IO_L04N_4/VREF_4 W18 4 IO_L04P_4 Y18 4 IO_L05N_4/VRP_4 U16 4 IO_L05P_4/VRN_4 V17 4 IO_L06N_4 AD20 4 IO_L06P_4 AD19 4 IO_L19N_4 AC20 4 IO_L19P_4 AC19 4 IO_L21N_4 AA18 4 IO_L21P_4/VREF_4 AB18 4 IO_L22N_4 AC18 4 IO_L22P_4 AC17 4 IO_L24N_4 AA17 4 IO_L24P_4 AB17 4 IO_L49N_4 Y17 4 IO_L49P_4 W17 4 IO_L51N_4 V16 4 IO_L51P_4/VREF_4 W16 4 IO_L52N_4 AD17 4 IO_L52P_4 AD16 4 IO_L54N_4 AB16 4 IO_L54P_4 AC16 4 IO_L67N_4 Y16 NC 4 IO_L67P_4 AA16 NC 4 IO_L69N_4 W15 NC 4 IO_L69P_4/VREF_4 Y15 NC 4 IO_L70N_4 U15 NC 4 IO_L70P_4 V15 NC 4 IO_L72N_4 AD15 NC 4 IO_L72P_4 AD14 NC 4 IO_L73N_4 AB15 NC NC 4 IO_L73P_4 AC15 NC NC 4 IO_L91N_4/VREF_4 AA14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 60 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 4 IO_L91P_4 AB14 4 IO_L92N_4 V14 4 IO_L92P_4 Y14 4 IO_L93N_4 AB13 4 IO_L93P_4 AC13 4 IO_L94N_4/VREF_4 Y13 4 IO_L94P_4 AA13 4 IO_L95N_4/GCLK3S V13 4 IO_L95P_4/GCLK2P W13 4 IO_L96N_4/GCLK1S U14 4 IO_L96P_4/GCLK0P U13 5 IO_L96N_5/GCLK7S AD12 5 IO_L96P_5/GCLK6P AD11 5 IO_L95N_5/GCLK5S AC12 5 IO_L95P_5/GCLK4P AB12 5 IO_L94N_5 AA12 5 IO_L94P_5/VREF_5 Y12 5 IO_L93N_5 W12 5 IO_L93P_5 V12 5 IO_L92N_5 U12 5 IO_L92P_5 U11 5 IO_L91N_5 AB11 5 IO_L91P_5/VREF_5 AA11 5 IO_L73N_5 Y11 NC NC 5 IO_L73P_5 V11 NC NC 5 IO_L72N_5 AD10 NC 5 IO_L72P_5 AD9 NC 5 IO_L70N_5 AC10 NC 5 IO_L70P_5 AB10 NC 5 IO_L69N_5/VREF_5 Y10 NC 5 IO_L69P_5 W10 NC 5 IO_L67N_5 V10 NC 5 IO_L67P_5 U10 NC 5 IO_L54N_5 AC9 5 IO_L54P_5 AB9 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 61 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 5 IO_L52N_5 AA9 5 IO_L52P_5 Y9 5 IO_L51N_5/VREF_5 W9 5 IO_L51P_5 V9 5 IO_L49N_5 AD8 5 IO_L49P_5 AD6 5 IO_L24N_5 AC8 5 IO_L24P_5 AC7 5 IO_L22N_5 AB8 5 IO_L22P_5 AA8 5 IO_L21N_5/VREF_5 W8 5 IO_L21P_5 Y8 5 IO_L19N_5 AD5 5 IO_L19P_5 AD4 5 IO_L06N_5 AC6 5 IO_L06P_5 AC5 5 IO_L05N_5/VRP_5 AB7 5 IO_L05P_5/VRN_5 AA7 5 IO_L04N_5 AB5 5 IO_L04P_5/VREF_5 AA5 5 IO_L03N_5/D4/ALT_VRP_5 AA6 5 IO_L03P_5/D5/ALT_VRN_5 Y6 5 IO_L02N_5/D6 Y7 5 IO_L02P_5/D7 W7 5 IO_L01N_5/RDWR_B V8 5 IO_L01P_5/CS_B U9 6 IO_L01P_6 AB2 6 IO_L01N_6 AB1 6 IO_L02P_6/VRN_6 AA3 6 IO_L02N_6/VRP_6 AA2 6 IO_L03P_6 Y4 6 IO_L03N_6/VREF_6 Y3 6 IO_L04P_6 W4 6 IO_L04N_6 W5 6 IO_L06P_6 V5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 62 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 6 IO_L06N_6 V6 6 IO_L19P_6 U7 6 IO_L19N_6 T8 6 IO_L21P_6 AA1 6 IO_L21N_6/VREF_6 Y2 6 IO_L22P_6 Y1 6 IO_L22N_6 W1 6 IO_L24P_6 W2 6 IO_L24N_6 V2 6 IO_L43P_6 V4 6 IO_L43N_6 V3 6 IO_L45P_6 U6 6 IO_L45N_6/VREF_6 U5 6 IO_L46P_6 T7 6 IO_L46N_6 T6 6 IO_L48P_6 R8 6 IO_L48N_6 R7 6 IO_L49P_6 U2 6 IO_L49N_6 U1 6 IO_L51P_6 U4 6 IO_L51N_6/VREF_6 U3 6 IO_L52P_6 T1 6 IO_L52N_6 R1 6 IO_L54P_6 T3 6 IO_L54N_6 T2 6 IO_L67P_6 T5 NC 6 IO_L67N_6 T4 NC 6 IO_L69P_6 R6 NC 6 IO_L69N_6/VREF_6 R5 NC 6 IO_L70P_6 P8 NC 6 IO_L70N_6 P7 NC 6 IO_L72P_6 R2 NC 6 IO_L72N_6 P1 NC 6 IO_L73P_6 R3 NC NC 6 IO_L73N_6 P3 NC NC 6 IO_L91P_6 P5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 63 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 6 IO_L91N_6 P4 6 IO_L93P_6 N4 6 IO_L93N_6/VREF_6 N3 6 IO_L94P_6 N6 6 IO_L94N_6 N5 6 IO_L96P_6 N8 6 IO_L96N_6 N7 7 IO_L96P_7 N2 7 IO_L96N_7 M1 7 IO_L94P_7 M2 7 IO_L94N_7 M3 7 IO_L93P_7/VREF_7 M4 7 IO_L93N_7 M5 7 IO_L91P_7 M6 7 IO_L91N_7 M7 7 IO_L73P_7 M8 NC NC 7 IO_L73N_7 L8 NC NC 7 IO_L72P_7 L1 NC 7 IO_L72N_7 K1 NC 7 IO_L70P_7 K2 NC 7 IO_L70N_7 K3 NC 7 IO_L69P_7/VREF_7 L3 NC 7 IO_L69N_7 L4 NC 7 IO_L67P_7 L5 NC 7 IO_L67N_7 L7 NC 7 IO_L54P_7 J1 7 IO_L54N_7 H1 7 IO_L52P_7 J2 7 IO_L52N_7 J3 7 IO_L51P_7/VREF_7 J4 7 IO_L51N_7 J5 7 IO_L49P_7 K5 7 IO_L49N_7 K6 7 IO_L48P_7 F1 7 IO_L48N_7 F2 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 64 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 7 IO_L46P_7 H2 7 IO_L46N_7 G2 7 IO_L45P_7/VREF_7 H3 7 IO_L45N_7 H4 7 IO_L43P_7 G3 7 IO_L43N_7 G4 7 IO_L24P_7 H5 7 IO_L24N_7 H6 7 IO_L22P_7 J6 7 IO_L22N_7 J7 7 IO_L21P_7/VREF_7 K7 7 IO_L21N_7 K8 7 IO_L19P_7 E1 7 IO_L19N_7 E2 7 IO_L06P_7 D2 7 IO_L06N_7 D3 7 IO_L04P_7 E3 7 IO_L04N_7 E4 7 IO_L03P_7/VREF_7 F4 7 IO_L03N_7 F5 7 IO_L02P_7/VRN_7 G5 7 IO_L02N_7/VRP_7 G6 7 IO_L01P_7 H7 7 IO_L01N_7 J8 0 VCCO_0 J12 0 VCCO_0 J11 0 VCCO_0 J10 0 VCCO_0 F11 0 VCCO_0 C6 0 VCCO_0 B11 1 VCCO_1 J15 1 VCCO_1 J14 1 VCCO_1 J13 1 VCCO_1 F14 1 VCCO_1 C19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 65 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 1 VCCO_1 B14 2 VCCO_2 M16 2 VCCO_2 L23 2 VCCO_2 L19 2 VCCO_2 L16 2 VCCO_2 K16 2 VCCO_2 F22 3 VCCO_3 W22 3 VCCO_3 R16 3 VCCO_3 P23 3 VCCO_3 P19 3 VCCO_3 P16 3 VCCO_3 N16 4 VCCO_4 AC14 4 VCCO_4 AB19 4 VCCO_4 W14 4 VCCO_4 T15 4 VCCO_4 T14 4 VCCO_4 T13 5 VCCO_5 AC11 5 VCCO_5 AB6 5 VCCO_5 W11 5 VCCO_5 T12 5 VCCO_5 T11 5 VCCO_5 T10 6 VCCO_6 W3 6 VCCO_6 R9 6 VCCO_6 P9 6 VCCO_6 P6 6 VCCO_6 P2 6 VCCO_6 N9 7 VCCO_7 M9 7 VCCO_7 L9 7 VCCO_7 L6 7 VCCO_7 L2 7 VCCO_7 K9 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 66 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 7 VCCO_7 F3 NA CCLK AB23 NA PROG_B C1 NA DONE AB21 NA M0 AC4 NA M1 AB4 NA M2 AD3 NA HSWAP_EN C2 NA TCK C23 NA TDI D1 NA TDO C24 NA TMS C21 NA PWRDWN_B AC21 NA DXN B4 NA DXP C4 NA VBATT B21 NA RSVD A22 NA VCCAUX AD13 NA VCCAUX AC22 NA VCCAUX AC3 NA VCCAUX N1 NA VCCAUX M24 NA VCCAUX B22 NA VCCAUX B3 NA VCCAUX A12 NA VCCINT U17 NA VCCINT U8 NA VCCINT T16 NA VCCINT T9 NA VCCINT R15 NA VCCINT R14 NA VCCINT R13 NA VCCINT R12 NA VCCINT R11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 67 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 NA VCCINT R10 NA VCCINT P15 NA VCCINT P10 NA VCCINT N15 NA VCCINT N10 NA VCCINT M15 NA VCCINT M10 NA VCCINT L15 NA VCCINT L10 NA VCCINT K15 NA VCCINT K14 NA VCCINT K13 NA VCCINT K12 NA VCCINT K11 NA VCCINT K10 NA VCCINT J16 NA VCCINT J9 NA VCCINT H17 NA VCCINT H8 NA GND AD24 NA GND AD23 NA GND AD18 NA GND AD7 NA GND AD2 NA GND AD1 NA GND AC24 NA GND AC23 NA GND AC2 NA GND AC1 NA GND AB22 NA GND AB3 NA GND AA21 NA GND AA15 NA GND AA10 NA GND AA4 NA GND Y20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 68 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 NA GND Y5 NA GND W19 NA GND W6 NA GND V24 NA GND V18 NA GND V7 NA GND V1 NA GND R21 NA GND R4 NA GND P14 NA GND P13 NA GND P12 NA GND P11 NA GND N14 NA GND N13 NA GND N12 NA GND N11 NA GND M14 NA GND M13 NA GND M12 NA GND M11 NA GND L14 NA GND L13 NA GND L12 NA GND L11 NA GND K21 NA GND K4 NA GND G24 NA GND G18 NA GND G7 NA GND G1 NA GND F19 NA GND F6 NA GND E20 NA GND E5 NA GND D21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 69 R Virtex-II Platform FPGAs: Pinout Information Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500 NA GND D15 NA GND D10 NA GND D4 NA GND C22 NA GND C3 NA GND B24 NA GND B23 NA GND B2 NA GND B1 NA GND A24 NA GND A23 NA GND A18 NA GND A7 NA GND A2 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 70 R Virtex-II Platform FPGAs: Pinout Information BG575/BGG575 Standard BGA Package Specifications (1.27mm pitch) Figure 5: BG575/BGG575 Standard BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 71 R Virtex-II Platform FPGAs: Pinout Information BG728/BGG728 Standard BGA Package As shown in Table 10, XC2V3000 Virtex-II devices are available in the BG728/BGG728 BGA package. Following this table are the BG728/BGG728 Standard BGA Package Specifications (1.27mm pitch). Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 0 IO_L01N_0 B3 0 IO_L01P_0 A3 0 IO_L02N_0 B4 0 IO_L02P_0 A4 0 IO_L03N_0/VRP_0 C5 0 IO_L03P_0/VRN_0 C6 0 IO_L04N_0/VREF_0 B5 0 IO_L04P_0 A5 0 IO_L05N_0 E6 0 IO_L05P_0 D6 0 IO_L06N_0 B6 0 IO_L06P_0 A6 0 IO_L19N_0 E7 0 IO_L19P_0 D8 0 IO_L21N_0 F8 0 IO_L21P_0/VREF_0 E8 0 IO_L22N_0 C7 0 IO_L22P_0 C8 0 IO_L24N_0 B7 0 IO_L24P_0 A7 0 IO_L25N_0 H9 0 IO_L25P_0 J9 0 IO_L27N_0 F9 0 IO_L27P_0/VREF_0 G9 0 IO_L28N_0 E9 0 IO_L28P_0 D9 0 IO_L30N_0 C9 0 IO_L30P_0 B9 0 IO_L49N_0 A8 0 IO_L49P_0 A9 0 IO_L51N_0 G10 0 IO_L51P_0/VREF_0 H10 0 IO_L52N_0 F10 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 72 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 0 IO_L52P_0 E10 0 IO_L54N_0 D10 0 IO_L54P_0 C10 0 IO_L67N_0 B10 0 IO_L67P_0 A10 0 IO_L69N_0 G11 0 IO_L69P_0/VREF_0 H11 0 IO_L70N_0 F11 0 IO_L70P_0 F12 0 IO_L72N_0 D11 0 IO_L72P_0 C11 0 IO_L73N_0 B11 0 IO_L73P_0 A11 0 IO_L75N_0 H12 0 IO_L75P_0/VREF_0 J12 0 IO_L76N_0 E12 0 IO_L76P_0 D12 0 IO_L78N_0 B12 0 IO_L78P_0 A12 0 IO_L91N_0/VREF_0 J13 0 IO_L91P_0 H13 0 IO_L92N_0 G13 0 IO_L92P_0 F13 0 IO_L93N_0 E13 0 IO_L93P_0 D13 0 IO_L94N_0/VREF_0 B13 0 IO_L94P_0 A13 0 IO_L95N_0/GCLK7P C13 0 IO_L95P_0/GCLK6S C14 0 IO_L96N_0/GCLK5P F14 0 IO_L96P_0/GCLK4S E14 1 IO_L96N_1/GCLK3P G14 1 IO_L96P_1/GCLK2S H14 1 IO_L95N_1/GCLK1P A15 1 IO_L95P_1/GCLK0S B15 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 73 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 1 IO_L94N_1 C15 1 IO_L94P_1/VREF_1 D15 1 IO_L93N_1 E15 1 IO_L93P_1 F15 1 IO_L92N_1 G15 1 IO_L92P_1 H15 1 IO_L91N_1 J15 1 IO_L91P_1/VREF_1 J16 1 IO_L78N_1 A16 1 IO_L78P_1 B16 1 IO_L76N_1 D16 1 IO_L76P_1 E16 1 IO_L75N_1/VREF_1 F16 1 IO_L75P_1 F17 1 IO_L73N_1 H16 1 IO_L73P_1 H17 1 IO_L72N_1 A17 1 IO_L72P_1 B17 1 IO_L70N_1 C17 1 IO_L70P_1 D17 1 IO_L69N_1/VREF_1 G18 1 IO_L69P_1 G17 1 IO_L67N_1 A18 1 IO_L67P_1 B18 1 IO_L54N_1 C18 1 IO_L54P_1 D18 1 IO_L52N_1 E18 1 IO_L52P_1 F18 1 IO_L51N_1/VREF_1 H19 1 IO_L51P_1 H18 1 IO_L49N_1 A19 1 IO_L49P_1 A20 1 IO_L30N_1 B19 1 IO_L30P_1 C19 1 IO_L28N_1 D19 1 IO_L28P_1 E19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 74 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 1 IO_L27N_1/VREF_1 F19 1 IO_L27P_1 G19 1 IO_L25N_1 J19 1 IO_L25P_1 J20 1 IO_L24N_1 C20 1 IO_L24P_1 C21 1 IO_L22N_1 D20 1 IO_L22P_1 E21 1 IO_L21N_1/VREF_1 E20 1 IO_L21P_1 F20 1 IO_L19N_1 A21 1 IO_L19P_1 B21 1 IO_L06N_1 A22 1 IO_L06P_1 B22 1 IO_L05N_1 C22 1 IO_L05P_1 C23 1 IO_L04N_1 D22 1 IO_L04P_1/VREF_1 E22 1 IO_L03N_1/VRP_1 A23 1 IO_L03P_1/VRN_1 B23 1 IO_L02N_1 A24 1 IO_L02P_1 B24 1 IO_L01N_1 A25 1 IO_L01P_1 B25 2 IO_L01N_2 C27 2 IO_L01P_2 D27 2 IO_L02N_2/VRP_2 D25 2 IO_L02P_2/VRN_2 D26 2 IO_L03N_2 E24 2 IO_L03P_2/VREF_2 E25 2 IO_L04N_2 E26 2 IO_L04P_2 E27 2 IO_L06N_2 F23 2 IO_L06P_2 F24 2 IO_L19N_2 F25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 75 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 2 IO_L19P_2 F26 2 IO_L21N_2 F27 2 IO_L21P_2/VREF_2 G27 2 IO_L22N_2 G23 2 IO_L22P_2 H23 2 IO_L24N_2 G25 2 IO_L24P_2 G26 2 IO_L25N_2 H21 2 IO_L25P_2 J21 2 IO_L27N_2 H22 2 IO_L27P_2/VREF_2 J22 2 IO_L28N_2 H24 2 IO_L28P_2 H25 2 IO_L30N_2 H27 2 IO_L30P_2 J27 2 IO_L43N_2 J23 2 IO_L43P_2 J24 2 IO_L45N_2 J25 2 IO_L45P_2/VREF_2 J26 2 IO_L46N_2 K20 2 IO_L46P_2 K21 2 IO_L48N_2 K22 2 IO_L48P_2 K23 2 IO_L49N_2 K24 2 IO_L49P_2 K25 2 IO_L51N_2 K26 2 IO_L51P_2/VREF_2 K27 2 IO_L52N_2 L20 2 IO_L52P_2 M20 2 IO_L54N_2 L21 2 IO_L54P_2 L22 2 IO_L67N_2 L24 2 IO_L67P_2 L25 2 IO_L69N_2 L26 2 IO_L69P_2/VREF_2 L27 2 IO_L70N_2 M19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 76 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 2 IO_L70P_2 N19 2 IO_L72N_2 M22 2 IO_L72P_2 M23 2 IO_L73N_2 M24 2 IO_L73P_2 N24 2 IO_L75N_2 M26 2 IO_L75P_2/VREF_2 M27 2 IO_L76N_2 N20 2 IO_L76P_2 N21 2 IO_L78N_2 N22 2 IO_L78P_2 N23 2 IO_L91N_2 N25 2 IO_L91P_2 P25 2 IO_L93N_2 N26 2 IO_L93P_2/VREF_2 N27 2 IO_L94N_2 P20 2 IO_L94P_2 P21 2 IO_L96N_2 P22 2 IO_L96P_2 P23 3 IO_L96N_3 R27 3 IO_L96P_3 R26 3 IO_L94N_3 R25 3 IO_L94P_3 R24 3 IO_L93N_3/VREF_3 R23 3 IO_L93P_3 T23 3 IO_L91N_3 R22 3 IO_L91P_3 R21 3 IO_L78N_3 R20 3 IO_L78P_3 R19 3 IO_L76N_3 T27 3 IO_L76P_3 T26 3 IO_L75N_3/VREF_3 T24 3 IO_L75P_3 U24 3 IO_L73N_3 T22 3 IO_L73P_3 U22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 77 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 3 IO_L72N_3 T20 3 IO_L72P_3 T19 3 IO_L70N_3 U27 3 IO_L70P_3 U26 3 IO_L69N_3/VREF_3 U25 3 IO_L69P_3 V25 3 IO_L67N_3 U21 3 IO_L67P_3 U20 3 IO_L54N_3 V27 3 IO_L54P_3 V26 3 IO_L52N_3 V24 3 IO_L52P_3 V23 3 IO_L51N_3/VREF_3 V22 3 IO_L51P_3 W22 3 IO_L49N_3 V21 3 IO_L49P_3 V20 3 IO_L48N_3 W27 3 IO_L48P_3 Y27 3 IO_L46N_3 W26 3 IO_L46P_3 W25 3 IO_L45N_3/VREF_3 W24 3 IO_L45P_3 W23 3 IO_L43N_3 W21 3 IO_L43P_3 W20 3 IO_L28N_3 W19 3 IO_L28P_3 Y19 3 IO_L27N_3/VREF_3 Y25 3 IO_L27P_3 Y24 3 IO_L25N_3 Y23 3 IO_L25P_3 AA23 3 IO_L24N_3 Y22 3 IO_L24P_3 Y21 3 IO_L22N_3 AA27 3 IO_L22P_3 AB27 3 IO_L21N_3/VREF_3 AA26 3 IO_L21P_3 AA25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 78 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 3 IO_L19N_3 AB26 3 IO_L19P_3 AB25 3 IO_L06N_3 AB24 3 IO_L06P_3 AB23 3 IO_L04N_3 AC27 3 IO_L04P_3 AC26 3 IO_L03N_3/VREF_3 AC25 3 IO_L03P_3 AC24 3 IO_L02N_3/VRP_3 AD27 3 IO_L02P_3/VRN_3 AE27 3 IO_L01N_3 AD26 3 IO_L01P_3 AD25 (1) 4 IO_L01N_4/BUSY/DOUT AF25 4 IO_L01P_4/INIT_B AG25 (1) 4 IO_L02N_4/D0/DIN AF24 4 IO_L02P_4/D1 AG24 4 IO_L03N_4/D2/ALT_VRP_4 AD23 4 IO_L03P_4/D3/ALT_VRN_4 AE23 4 IO_L04N_4/VREF_4 AF23 4 IO_L04P_4 AG23 4 IO_L05N_4/VRP_4 AD22 4 IO_L05P_4/VRN_4 AE22 4 IO_L06N_4 AF22 4 IO_L06P_4 AG22 4 IO_L19N_4 AC21 4 IO_L19P_4 AB21 4 IO_L21N_4 AE21 4 IO_L21P_4/VREF_4 AE20 4 IO_L22N_4 AF21 4 IO_L22P_4 AG21 4 IO_L24N_4 AB20 4 IO_L24P_4 AA20 4 IO_L25N_4 AC20 4 IO_L25P_4 AD20 4 IO_L27N_4 AG20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 79 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 4 IO_L27P_4/VREF_4 AG19 4 IO_L28N_4 AB19 4 IO_L28P_4 AA19 4 IO_L30N_4 AC19 4 IO_L30P_4 AD19 4 IO_L49N_4 AE19 4 IO_L49P_4 AF19 4 IO_L51N_4 AA18 4 IO_L51P_4/VREF_4 Y18 4 IO_L52N_4 AB18 4 IO_L52P_4 AC18 4 IO_L54N_4 AD18 4 IO_L54P_4 AE18 4 IO_L67N_4 AF18 4 IO_L67P_4 AG18 4 IO_L69N_4 AA17 4 IO_L69P_4/VREF_4 Y17 4 IO_L70N_4 AB17 4 IO_L70P_4 AB16 4 IO_L72N_4 AD17 4 IO_L72P_4 AE17 4 IO_L73N_4 AF17 4 IO_L73P_4 AG17 4 IO_L75N_4 Y16 4 IO_L75P_4/VREF_4 W16 4 IO_L76N_4 AC16 4 IO_L76P_4 AD16 4 IO_L78N_4 AF16 4 IO_L78P_4 AG16 4 IO_L91N_4/VREF_4 W15 4 IO_L91P_4 Y15 4 IO_L92N_4 AB15 4 IO_L92P_4 AA15 4 IO_L93N_4 AC15 4 IO_L93P_4 AD15 4 IO_L94N_4/VREF_4 AE15 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 80 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 4 IO_L94P_4 AE14 4 IO_L95N_4/GCLK3S AF15 4 IO_L95P_4/GCLK2P AG15 4 IO_L96N_4/GCLK1S Y14 4 IO_L96P_4/GCLK0P AA14 5 IO_L96N_5/GCLK7S AC14 5 IO_L96P_5/GCLK6P AB14 5 IO_L95N_5/GCLK5S AG13 5 IO_L95P_5/GCLK4P AF13 5 IO_L94N_5 AE13 5 IO_L94P_5/VREF_5 AD13 5 IO_L93N_5 AC13 5 IO_L93P_5 AB13 5 IO_L92N_5 AA13 5 IO_L92P_5 Y13 5 IO_L91N_5 W13 5 IO_L91P_5/VREF_5 W12 5 IO_L78N_5 AG12 5 IO_L78P_5 AF12 5 IO_L76N_5 AD12 5 IO_L76P_5 AC12 5 IO_L75N_5/VREF_5 AB12 5 IO_L75P_5 AB11 5 IO_L73N_5 Y12 5 IO_L73P_5 Y11 5 IO_L72N_5 AG11 5 IO_L72P_5 AF11 5 IO_L70N_5 AE11 5 IO_L70P_5 AD11 5 IO_L69N_5/VREF_5 AA10 5 IO_L69P_5 AA11 5 IO_L67N_5 AG10 5 IO_L67P_5 AF10 5 IO_L54N_5 AE10 5 IO_L54P_5 AD10 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 81 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 5 IO_L52N_5 AC10 5 IO_L52P_5 AB10 5 IO_L51N_5/VREF_5 Y9 5 IO_L51P_5 Y10 5 IO_L49N_5 AG9 5 IO_L49P_5 AG8 5 IO_L30N_5 AF9 5 IO_L30P_5 AE9 5 IO_L28N_5 AD9 5 IO_L28P_5 AC9 5 IO_L27N_5/VREF_5 AB9 5 IO_L27P_5 AA9 5 IO_L25N_5 AE8 5 IO_L25P_5 AE7 5 IO_L24N_5 AD8 5 IO_L24P_5 AC8 5 IO_L22N_5 AB8 5 IO_L22P_5 AA8 5 IO_L21N_5/VREF_5 AG7 5 IO_L21P_5 AF7 5 IO_L19N_5 AC7 5 IO_L19P_5 AB7 5 IO_L06N_5 AG6 5 IO_L06P_5 AF6 5 IO_L05N_5/VRP_5 AE6 5 IO_L05P_5/VRN_5 AD6 5 IO_L04N_5 AG5 5 IO_L04P_5/VREF_5 AF5 5 IO_L03N_5/D4/ALT_VRP_5 AE5 5 IO_L03P_5/D5/ALT_VRN_5 AD5 5 IO_L02N_5/D6 AG4 5 IO_L02P_5/D7 AF4 5 IO_L01N_5/RDWR_B AG3 5 IO_L01P_5/CS_B AF3 6 IO_L01P_6 AE1 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 82 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 6 IO_L01N_6 AD1 6 IO_L02P_6/VRN_6 AD3 6 IO_L02N_6/VRP_6 AD2 6 IO_L03P_6 AC4 6 IO_L03N_6/VREF_6 AC3 6 IO_L04P_6 AC2 6 IO_L04N_6 AC1 6 IO_L06P_6 AB5 6 IO_L06N_6 AB4 6 IO_L19P_6 AB3 6 IO_L19N_6 AB2 6 IO_L21P_6 AB1 6 IO_L21N_6/VREF_6 AA1 6 IO_L22P_6 AA5 6 IO_L22N_6 AA6 6 IO_L24P_6 AA3 6 IO_L24N_6 AA2 6 IO_L25P_6 Y5 6 IO_L25N_6 Y6 6 IO_L27P_6 Y4 6 IO_L27N_6/VREF_6 Y3 6 IO_L28P_6 Y1 6 IO_L28N_6 W1 6 IO_L43P_6 W8 6 IO_L43N_6 W9 6 IO_L45P_6 W6 6 IO_L45N_6/VREF_6 W7 6 IO_L46P_6 W5 6 IO_L46N_6 W4 6 IO_L48P_6 W3 6 IO_L48N_6 W2 6 IO_L49P_6 V7 6 IO_L49N_6 V8 6 IO_L51P_6 V5 6 IO_L51N_6/VREF_6 V6 6 IO_L52P_6 V4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 83 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 6 IO_L52N_6 V3 6 IO_L54P_6 V2 6 IO_L54N_6 V1 6 IO_L67P_6 U8 6 IO_L67N_6 T8 6 IO_L69P_6 U6 6 IO_L69N_6/VREF_6 U7 6 IO_L70P_6 U4 6 IO_L70N_6 U3 6 IO_L72P_6 U2 6 IO_L72N_6 U1 6 IO_L73P_6 T9 6 IO_L73N_6 R9 6 IO_L75P_6 T5 6 IO_L75N_6/VREF_6 T6 6 IO_L76P_6 T4 6 IO_L76N_6 R4 6 IO_L78P_6 T2 6 IO_L78N_6 T1 6 IO_L91P_6 R7 6 IO_L91N_6 R8 6 IO_L93P_6 R5 6 IO_L93N_6/VREF_6 R6 6 IO_L94P_6 R3 6 IO_L94N_6 P3 6 IO_L96P_6 R2 6 IO_L96N_6 R1 7 IO_L96P_7 P5 7 IO_L96N_7 P6 7 IO_L94P_7 P7 7 IO_L94N_7 P8 7 IO_L93P_7/VREF_7 N1 7 IO_L93N_7 N2 7 IO_L91P_7 N3 7 IO_L91N_7 N4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 84 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 7 IO_L78P_7 N6 7 IO_L78N_7 N7 7 IO_L76P_7 N9 7 IO_L76N_7 N8 7 IO_L75P_7/VREF_7 N5 7 IO_L75N_7 M6 7 IO_L73P_7 M1 7 IO_L73N_7 M2 7 IO_L72P_7 M4 7 IO_L72N_7 M5 7 IO_L70P_7 M8 7 IO_L70N_7 M9 7 IO_L69P_7/VREF_7 L1 7 IO_L69N_7 L2 7 IO_L67P_7 L3 7 IO_L67N_7 L4 7 IO_L54P_7 K1 7 IO_L54N_7 K2 7 IO_L52P_7 K4 7 IO_L52N_7 K5 7 IO_L51P_7/VREF_7 L6 7 IO_L51N_7 L7 7 IO_L49P_7 K6 7 IO_L49N_7 K7 7 IO_L48P_7 L8 7 IO_L48N_7 K8 7 IO_L46P_7 J1 7 IO_L46N_7 H1 7 IO_L45P_7/VREF_7 J2 7 IO_L45N_7 J3 7 IO_L43P_7 K3 7 IO_L43N_7 J4 7 IO_L30P_7 H3 7 IO_L30N_7 H4 7 IO_L28P_7 J5 7 IO_L28N_7 J6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 85 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 7 IO_L27P_7/VREF_7 H5 7 IO_L27N_7 H6 7 IO_L25P_7 J7 7 IO_L25N_7 J8 7 IO_L24P_7 G1 7 IO_L24N_7 F1 7 IO_L22P_7 G2 7 IO_L22N_7 G3 7 IO_L21P_7/VREF_7 F2 7 IO_L21N_7 F3 7 IO_L19P_7 G5 7 IO_L19N_7 G6 7 IO_L06P_7 F4 7 IO_L06N_7 F5 7 IO_L04P_7 E1 7 IO_L04N_7 E2 7 IO_L03P_7/VREF_7 D1 7 IO_L03N_7 C1 7 IO_L02P_7/VRN_7 E3 7 IO_L02N_7/VRP_7 E4 7 IO_L01P_7 D2 7 IO_L01N_7 D3 0 VCCO_0 K13 0 VCCO_0 K12 0 VCCO_0 K11 0 VCCO_0 J11 0 VCCO_0 J10 0 VCCO_0 G12 0 VCCO_0 D7 0 VCCO_0 C12 1 VCCO_1 K17 1 VCCO_1 K16 1 VCCO_1 K15 1 VCCO_1 J18 1 VCCO_1 J17 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 86 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 1 VCCO_1 G16 1 VCCO_1 D21 1 VCCO_1 C16 2 VCCO_2 N18 2 VCCO_2 M25 2 VCCO_2 M21 2 VCCO_2 M18 2 VCCO_2 L19 2 VCCO_2 L18 2 VCCO_2 K19 2 VCCO_2 G24 3 VCCO_3 AA24 3 VCCO_3 V19 3 VCCO_3 U19 3 VCCO_3 U18 3 VCCO_3 T25 3 VCCO_3 T21 3 VCCO_3 T18 3 VCCO_3 R18 4 VCCO_4 AE16 4 VCCO_4 AD21 4 VCCO_4 AA16 4 VCCO_4 W18 4 VCCO_4 W17 4 VCCO_4 V17 4 VCCO_4 V16 4 VCCO_4 V15 5 VCCO_5 AE12 5 VCCO_5 AD7 5 VCCO_5 AA12 5 VCCO_5 W11 5 VCCO_5 W10 5 VCCO_5 V13 5 VCCO_5 V12 5 VCCO_5 V11 6 VCCO_6 AA4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 87 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number 6 VCCO_6 V9 6 VCCO_6 U10 6 VCCO_6 U9 6 VCCO_6 T10 6 VCCO_6 T7 6 VCCO_6 T3 6 VCCO_6 R10 7 VCCO_7 M10 7 VCCO_7 M7 7 VCCO_7 M3 7 VCCO_7 L10 7 VCCO_7 L9 7 VCCO_7 K9 7 VCCO_7 G4 7 VCCO_7 N10 NA CCLK AA22 NA PROG_B C4 NA DONE AC22 NA M0 AC6 NA M1 Y7 NA M2 AE4 NA HSWAP_EN D5 NA TCK G20 NA TDI H7 NA TDO G22 NA TMS F21 NA PWRDWN_B AE24 NA DXN G8 NA DXP F7 NA VBATT D23 NA RSVD C24 NA VCCAUX AF14 NA VCCAUX AE26 NA VCCAUX AE2 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 88 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number NA VCCAUX P26 NA VCCAUX P2 NA VCCAUX C26 NA VCCAUX C2 NA VCCAUX B14 NA VCCINT V18 NA VCCINT V14 NA VCCINT V10 NA VCCINT U17 NA VCCINT U16 NA VCCINT U15 NA VCCINT U14 NA VCCINT U13 NA VCCINT U12 NA VCCINT U11 NA VCCINT T17 NA VCCINT T11 NA VCCINT R17 NA VCCINT R11 NA VCCINT P18 NA VCCINT P17 NA VCCINT P11 NA VCCINT P10 NA VCCINT N17 NA VCCINT N11 NA VCCINT M17 NA VCCINT M11 NA VCCINT L17 NA VCCINT L16 NA VCCINT L15 NA VCCINT L14 NA VCCINT L13 NA VCCINT L12 NA VCCINT L11 NA VCCINT K18 NA VCCINT K14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 89 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number NA VCCINT K10 NA GND AG27 NA GND AG26 NA GND AG14 NA GND AG2 NA GND AG1 NA GND AF27 NA GND AF26 NA GND AF20 NA GND AF8 NA GND AF2 NA GND AF1 NA GND AE25 NA GND AE3 NA GND AD24 NA GND AD14 NA GND AD4 NA GND AC23 NA GND AC17 NA GND AC11 NA GND AC5 NA GND AB22 NA GND AB6 NA GND AA21 NA GND AA7 NA GND Y26 NA GND Y20 NA GND Y8 NA GND Y2 NA GND W14 NA GND U23 NA GND U5 NA GND T16 NA GND T15 NA GND T14 NA GND T13 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 90 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number NA GND T12 NA GND R16 NA GND R15 NA GND R14 NA GND R13 NA GND R12 NA GND P27 NA GND P24 NA GND P19 NA GND P16 NA GND P15 NA GND P14 NA GND P13 NA GND P12 NA GND P9 NA GND P4 NA GND P1 NA GND N16 NA GND N15 NA GND N14 NA GND N13 NA GND N12 NA GND M16 NA GND M15 NA GND M14 NA GND M13 NA GND M12 NA GND L23 NA GND L5 NA GND J14 NA GND H26 NA GND H20 NA GND H8 NA GND H2 NA GND G21 NA GND G7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 91 R Virtex-II Platform FPGAs: Pinout Information Table 10: BG728 BGA — XC2V3000 Bank Pin Description Pin Number NA GND F22 NA GND F6 NA GND E23 NA GND E17 NA GND E11 NA GND E5 NA GND D24 NA GND D14 NA GND D4 NA GND C25 NA GND C3 NA GND B27 NA GND B26 NA GND B20 NA GND B8 NA GND B2 NA GND B1 NA GND A27 NA GND A26 NA GND A14 NA GND A2 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 92 R Virtex-II Platform FPGAs: Pinout Information BG728/BGG728 Standard BGA Package Specifications (1.27mm pitch) Figure 6: BG728/BGG728 Standard BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 93 R Virtex-II Platform FPGAs: Pinout Information FF896 Flip-Chip Fine-Pitch BGA Package As shown in Table 11, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the FF896 flip-chip fine-pitch BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 0 IO_L01N_0 B27 0 IO_L01P_0 A27 0 IO_L02N_0 F24 0 IO_L02P_0 E24 0 IO_L03N_0/VRP_0 C26 0 IO_L03P_0/VRN_0 C25 0 IO_L04N_0/VREF_0 A26 0 IO_L04P_0 A25 0 IO_L05N_0 F23 0 IO_L05P_0 F22 0 IO_L06N_0 C24 0 IO_L06P_0 D25 0 IO_L19N_0 A24 0 IO_L19P_0 B25 0 IO_L20N_0 G22 0 IO_L20P_0 G21 0 IO_L21N_0 D24 0 IO_L21P_0/VREF_0 D23 0 IO_L22N_0 B23 0 IO_L22P_0 B24 0 IO_L23N_0 H21 0 IO_L23P_0 H20 0 IO_L24N_0 E22 0 IO_L24P_0 E23 0 IO_L49N_0 A22 0 IO_L49P_0 B22 0 IO_L50N_0 F21 0 IO_L50P_0 F20 0 IO_L51N_0 C23 0 IO_L51P_0/VREF_0 C22 0 IO_L52N_0 B20 0 IO_L52P_0 B21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 94 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 0 IO_L53N_0 G20 0 IO_L53P_0 G19 0 IO_L54N_0 D21 0 IO_L54P_0 D22 0 IO_L67N_0 E20 NC 0 IO_L67P_0 E21 NC 0 IO_L68N_0 H19 NC 0 IO_L68P_0 H18 NC 0 IO_L69N_0 D20 NC 0 IO_L69P_0/VREF_0 D19 NC 0 IO_L70N_0 A20 NC 0 IO_L70P_0 A21 NC 0 IO_L71N_0 F19 NC 0 IO_L71P_0 F18 NC 0 IO_L72N_0 C19 NC 0 IO_L72P_0 C20 NC 0 IO_L73N_0 B18 NC NC 0 IO_L73P_0 B19 NC NC 0 IO_L74N_0 G18 NC NC 0 IO_L74P_0 H17 NC NC 0 IO_L75N_0 E18 NC NC 0 IO_L75P_0/VREF_0 D18 NC NC 0 IO_L76N_0 A18 NC NC 0 IO_L76P_0 A19 NC NC 0 IO_L77N_0 J17 NC NC 0 IO_L77P_0 J16 NC NC 0 IO_L78N_0 E16 NC NC 0 IO_L78P_0 E17 NC NC 0 IO_L91N_0/VREF_0 B17 0 IO_L91P_0 B16 0 IO_L92N_0 F17 0 IO_L92P_0 F16 0 IO_L93N_0 D16 0 IO_L93P_0 D17 0 IO_L94N_0/VREF_0 A17 0 IO_L94P_0 A16 0 IO_L95N_0/GCLK7P H16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 95 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 0 IO_L95P_0/GCLK6S G16 0 IO_L96N_0/GCLK5P C17 0 IO_L96P_0/GCLK4S C16 1 IO_L96N_1/GCLK3P C15 1 IO_L96P_1/GCLK2S C14 1 IO_L95N_1/GCLK1P F15 1 IO_L95P_1/GCLK0S F14 1 IO_L94N_1 B15 1 IO_L94P_1/VREF_1 B14 1 IO_L93N_1 D14 1 IO_L93P_1 D15 1 IO_L92N_1 G15 1 IO_L92P_1 H15 1 IO_L91N_1 A14 1 IO_L91P_1/VREF_1 A13 1 IO_L78N_1 E14 NC NC 1 IO_L78P_1 E15 NC NC 1 IO_L77N_1 J15 NC NC 1 IO_L77P_1 J14 NC NC 1 IO_L76N_1 B12 NC NC 1 IO_L76P_1 B13 NC NC 1 IO_L75N_1/VREF_1 D13 NC NC 1 IO_L75P_1 E13 NC NC 1 IO_L74N_1 H14 NC NC 1 IO_L74P_1 H13 NC NC 1 IO_L73N_1 A11 NC NC 1 IO_L73P_1 A12 NC NC 1 IO_L72N_1 C11 NC 1 IO_L72P_1 C12 NC 1 IO_L71N_1 F13 NC 1 IO_L71P_1 F12 NC 1 IO_L70N_1 B10 NC 1 IO_L70P_1 B11 NC 1 IO_L69N_1/VREF_1 D12 NC 1 IO_L69P_1 D11 NC 1 IO_L68N_1 G13 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 96 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 1 IO_L68P_1 G12 NC 1 IO_L67N_1 A9 NC 1 IO_L67P_1 A10 NC 1 IO_L54N_1 E10 1 IO_L54P_1 E11 1 IO_L53N_1 H12 1 IO_L53P_1 H11 1 IO_L52N_1 D9 1 IO_L52P_1 D10 1 IO_L51N_1/VREF_1 C9 1 IO_L51P_1 C8 1 IO_L50N_1 F11 1 IO_L50P_1 F10 1 IO_L49N_1 B8 1 IO_L49P_1 B9 1 IO_L24N_1 E8 1 IO_L24P_1 E9 1 IO_L23N_1 G11 1 IO_L23P_1 H10 1 IO_L22N_1 B7 1 IO_L22P_1 A7 1 IO_L21N_1/VREF_1 D8 1 IO_L21P_1 E7 1 IO_L20N_1 G10 1 IO_L20P_1 G9 1 IO_L19N_1 A5 1 IO_L19P_1 A6 1 IO_L06N_1 C6 1 IO_L06P_1 C7 1 IO_L05N_1 F9 1 IO_L05P_1 G8 1 IO_L04N_1 B6 1 IO_L04P_1/VREF_1 C5 1 IO_L03N_1/VRP_1 D7 1 IO_L03P_1/VRN_1 D6 1 IO_L02N_1 F8 1 IO_L02P_1 F7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 97 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 1 IO_L01N_1 B4 1 IO_L01P_1 A4 2 IO_L01N_2 C1 2 IO_L01P_2 B1 2 IO_L02N_2/VRP_2 H9 2 IO_L02P_2/VRN_2 H8 2 IO_L03N_2 D3 2 IO_L03P_2/VREF_2 E3 2 IO_L04N_2 D2 2 IO_L04P_2 C2 2 IO_L05N_2 G7 2 IO_L05P_2 H7 2 IO_L06N_2 F4 2 IO_L06P_2 E4 2 IO_L19N_2 E1 2 IO_L19P_2 D1 2 IO_L20N_2 G6 2 IO_L20P_2 H6 2 IO_L21N_2 F5 2 IO_L21P_2/VREF_2 G5 2 IO_L22N_2 G2 2 IO_L22P_2 F2 2 IO_L23N_2 J8 2 IO_L23P_2 J7 2 IO_L24N_2 G3 2 IO_L24P_2 F3 2 IO_L43N_2 G1 2 IO_L43P_2 F1 2 IO_L44N_2 K8 2 IO_L44P_2 L8 2 IO_L45N_2 G4 2 IO_L45P_2/VREF_2 H4 2 IO_L46N_2 J2 2 IO_L46P_2 H2 2 IO_L47N_2 J6 2 IO_L47P_2 K6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 98 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 2 IO_L48N_2 J5 2 IO_L48P_2 H5 2 IO_L49N_2 J3 2 IO_L49P_2 H3 2 IO_L50N_2 K7 2 IO_L50P_2 L7 2 IO_L51N_2 J4 2 IO_L51P_2/VREF_2 K4 2 IO_L52N_2 K1 2 IO_L52P_2 J1 2 IO_L53N_2 L6 2 IO_L53P_2 M6 2 IO_L54N_2 L5 2 IO_L54P_2 K5 2 IO_L67N_2 L2 NC 2 IO_L67P_2 K2 NC 2 IO_L68N_2 M8 NC 2 IO_L68P_2 N8 NC 2 IO_L69N_2 L4 NC 2 IO_L69P_2/VREF_2 M4 NC 2 IO_L70N_2 M1 NC 2 IO_L70P_2 L1 NC 2 IO_L71N_2 M7 NC 2 IO_L71P_2 N7 NC 2 IO_L72N_2 M3 NC 2 IO_L72P_2 L3 NC 2 IO_L73N_2 N2 NC NC 2 IO_L73P_2 M2 NC NC 2 IO_L74N_2 N6 NC NC 2 IO_L74P_2 P6 NC NC 2 IO_L75N_2 N5 NC NC 2 IO_L75P_2/VREF_2 N4 NC NC 2 IO_L76N_2 P1 NC NC 2 IO_L76P_2 N1 NC NC 2 IO_L77N_2 P9 NC NC 2 IO_L77P_2 R9 NC NC 2 IO_L78N_2 R5 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 99 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 2 IO_L78P_2 P5 NC NC 2 IO_L91N_2 R2 2 IO_L91P_2 P2 2 IO_L92N_2 P8 2 IO_L92P_2 R8 2 IO_L93N_2 P4 2 IO_L93P_2/VREF_2 R4 2 IO_L94N_2 R1 2 IO_L94P_2 T2 2 IO_L95N_2 R7 2 IO_L95P_2 R6 2 IO_L96N_2 R3 2 IO_L96P_2 P3 3 IO_L96N_3 T7 3 IO_L96P_3 T6 3 IO_L95N_3 U1 3 IO_L95P_3 V1 3 IO_L94N_3 T3 3 IO_L94P_3 U3 3 IO_L93N_3/VREF_3 T8 3 IO_L93P_3 U8 3 IO_L92N_3 U2 3 IO_L92P_3 V2 3 IO_L91N_3 T4 3 IO_L91P_3 U4 3 IO_L78N_3 U9 NC NC 3 IO_L78P_3 T9 NC NC 3 IO_L77N_3 W1 NC NC 3 IO_L77P_3 Y1 NC NC 3 IO_L76N_3 T5 NC NC 3 IO_L76P_3 U5 NC NC 3 IO_L75N_3/VREF_3 U6 NC NC 3 IO_L75P_3 V6 NC NC 3 IO_L74N_3 W2 NC NC 3 IO_L74P_3 Y2 NC NC 3 IO_L73N_3 V4 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 100 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 3 IO_L73P_3 W4 NC NC 3 IO_L72N_3 W7 NC 3 IO_L72P_3 V7 NC 3 IO_L71N_3 V5 NC 3 IO_L71P_3 W6 NC 3 IO_L70N_3 W3 NC 3 IO_L70P_3 Y3 NC 3 IO_L69N_3/VREF_3 V8 NC 3 IO_L69P_3 W8 NC 3 IO_L68N_3 AA1 NC 3 IO_L68P_3 AB1 NC 3 IO_L67N_3 Y4 NC 3 IO_L67P_3 AA4 NC 3 IO_L54N_3 AA6 3 IO_L54P_3 Y6 3 IO_L53N_3 AA2 3 IO_L53P_3 AB2 3 IO_L52N_3 Y5 3 IO_L52P_3 AA5 3 IO_L51N_3/VREF_3 Y8 3 IO_L51P_3 AA8 3 IO_L50N_3 AC2 3 IO_L50P_3 AD2 3 IO_L49N_3 Y7 3 IO_L49P_3 AA7 3 IO_L48N_3 AC6 3 IO_L48P_3 AB6 3 IO_L47N_3 AD1 3 IO_L47P_3 AE1 3 IO_L46N_3 AB3 3 IO_L46P_3 AC3 3 IO_L45N_3/VREF_3 AB7 3 IO_L45P_3 AC7 3 IO_L44N_3 AB4 3 IO_L44P_3 AC4 3 IO_L43N_3 AB5 3 IO_L43P_3 AC5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 101 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 3 IO_L24N_3 AC8 3 IO_L24P_3 AB8 3 IO_L23N_3 AE2 3 IO_L23P_3 AF3 3 IO_L22N_3 AD3 3 IO_L22P_3 AE3 3 IO_L21N_3/VREF_3 AD6 3 IO_L21P_3 AD7 3 IO_L20N_3 AF1 3 IO_L20P_3 AG1 3 IO_L19N_3 AD4 3 IO_L19P_3 AE4 3 IO_L06N_3 AD8 3 IO_L06P_3 AE7 3 IO_L05N_3 AG2 3 IO_L05P_3 AH2 3 IO_L04N_3 AD5 3 IO_L04P_3 AE5 3 IO_L03N_3/VREF_3 AC9 3 IO_L03P_3 AD9 3 IO_L02N_3/VRP_3 AH1 3 IO_L02P_3/VRN_3 AJ1 3 IO_L01N_3 AF4 3 IO_L01P_3 AG3 (1) 4 IO_L01N_4/BUSY/DOUT AK2 4 IO_L01P_4/INIT_B AJ3 (1) 4 IO_L02N_4/D0/DIN AE8 4 IO_L02P_4/D1 AF9 4 IO_L03N_4/D2/ALT_VRP_4 AH5 4 IO_L03P_4/D3/ALT_VRN_4 AH6 4 IO_L04N_4/VREF_4 AJ4 4 IO_L04P_4 AK4 4 IO_L05N_4/VRP_4 AC10 4 IO_L05P_4/VRN_4 AC11 4 IO_L06N_4 AH7 4 IO_L06P_4 AG6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 102 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 4 IO_L19N_4 AK6 4 IO_L19P_4 AK5 4 IO_L20N_4 AE9 4 IO_L20P_4 AE10 4 IO_L21N_4 AF7 4 IO_L21P_4/VREF_4 AF8 4 IO_L22N_4 AK7 4 IO_L22P_4 AJ6 4 IO_L23N_4 AD10 4 IO_L23P_4 AD11 4 IO_L24N_4 AG8 4 IO_L24P_4 AG7 4 IO_L49N_4 AJ8 4 IO_L49P_4 AJ7 4 IO_L50N_4 AE11 4 IO_L50P_4 AE12 4 IO_L51N_4 AG9 4 IO_L51P_4/VREF_4 AG10 4 IO_L52N_4 AK9 4 IO_L52P_4 AJ9 4 IO_L53N_4 AH8 4 IO_L53P_4 AH9 4 IO_L54N_4 AF11 4 IO_L54P_4 AF10 4 IO_L67N_4 AJ11 NC 4 IO_L67P_4 AJ10 NC 4 IO_L68N_4 AC12 NC 4 IO_L68P_4 AC13 NC 4 IO_L69N_4 AG11 NC 4 IO_L69P_4/VREF_4 AG12 NC 4 IO_L70N_4 AK11 NC 4 IO_L70P_4 AK10 NC 4 IO_L71N_4 AD12 NC 4 IO_L71P_4 AD13 NC 4 IO_L72N_4 AH12 NC 4 IO_L72P_4 AH11 NC 4 IO_L73N_4 AJ13 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 103 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 4 IO_L73P_4 AJ12 NC NC 4 IO_L74N_4 AE13 NC NC 4 IO_L74P_4 AE14 NC NC 4 IO_L75N_4 AF13 NC NC 4 IO_L75P_4/VREF_4 AG13 NC NC 4 IO_L76N_4 AK13 NC NC 4 IO_L76P_4 AK12 NC NC 4 IO_L77N_4 AB14 NC NC 4 IO_L77P_4 AB15 NC NC 4 IO_L78N_4 AF15 NC NC 4 IO_L78P_4 AF14 NC NC 4 IO_L91N_4/VREF_4 AJ14 4 IO_L91P_4 AJ15 4 IO_L92N_4 AC14 4 IO_L92P_4 AC15 4 IO_L93N_4 AG15 4 IO_L93P_4 AG14 4 IO_L94N_4/VREF_4 AK14 4 IO_L94P_4 AK15 4 IO_L95N_4/GCLK3S AD15 4 IO_L95P_4/GCLK2P AE15 4 IO_L96N_4/GCLK1S AH14 4 IO_L96P_4/GCLK0P AH15 5 IO_L96N_5/GCLK7S AH16 5 IO_L96P_5/GCLK6P AH17 5 IO_L95N_5/GCLK5S AE16 5 IO_L95P_5/GCLK4P AD16 5 IO_L94N_5 AJ16 5 IO_L94P_5/VREF_5 AJ17 5 IO_L93N_5 AG17 5 IO_L93P_5 AG16 5 IO_L92N_5 AC16 5 IO_L92P_5 AC17 5 IO_L91N_5 AK17 5 IO_L91P_5/VREF_5 AK18 5 IO_L78N_5 AF17 NC NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 104 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 5 IO_L78P_5 AF16 NC NC 5 IO_L77N_5 AB16 NC NC 5 IO_L77P_5 AB17 NC NC 5 IO_L76N_5 AJ19 NC NC 5 IO_L76P_5 AJ18 NC NC 5 IO_L75N_5/VREF_5 AG18 NC NC 5 IO_L75P_5 AF18 NC NC 5 IO_L74N_5 AE17 NC NC 5 IO_L74P_5 AE18 NC NC 5 IO_L73N_5 AK20 NC NC 5 IO_L73P_5 AK19 NC NC 5 IO_L72N_5 AH20 NC 5 IO_L72P_5 AH19 NC 5 IO_L71N_5 AD18 NC 5 IO_L71P_5 AD19 NC 5 IO_L70N_5 AJ21 NC 5 IO_L70P_5 AJ20 NC 5 IO_L69N_5/VREF_5 AG19 NC 5 IO_L69P_5 AG20 NC 5 IO_L68N_5 AC18 NC 5 IO_L68P_5 AC19 NC 5 IO_L67N_5 AK22 NC 5 IO_L67P_5 AK21 NC 5 IO_L54N_5 AF21 5 IO_L54P_5 AF20 5 IO_L53N_5 AH22 5 IO_L53P_5 AH23 5 IO_L52N_5 AG22 5 IO_L52P_5 AG21 5 IO_L51N_5/VREF_5 AF22 5 IO_L51P_5 AF23 5 IO_L50N_5 AE19 5 IO_L50P_5 AE20 5 IO_L49N_5 AJ23 5 IO_L49P_5 AJ22 5 IO_L24N_5 AF24 5 IO_L24P_5 AG23 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 105 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 5 IO_L23N_5 AD20 5 IO_L23P_5 AD21 5 IO_L22N_5 AK25 5 IO_L22P_5 AK24 5 IO_L21N_5/VREF_5 AH24 5 IO_L21P_5 AH25 5 IO_L20N_5 AE21 5 IO_L20P_5 AD22 5 IO_L19N_5 AJ25 5 IO_L19P_5 AJ24 5 IO_L06N_5 AG25 5 IO_L06P_5 AG24 5 IO_L05N_5/VRP_5 AC20 5 IO_L05P_5/VRN_5 AC21 5 IO_L04N_5 AK26 5 IO_L04P_5/VREF_5 AK27 5 IO_L03N_5/D4/ALT_VRP_5 AH26 5 IO_L03P_5/D5/ALT_VRN_5 AJ27 5 IO_L02N_5/D6 AE22 5 IO_L02P_5/D7 AE23 5 IO_L01N_5/RDWR_B AJ28 5 IO_L01P_5/CS_B AK29 6 IO_L01P_6 AC22 6 IO_L01N_6 AB23 6 IO_L02P_6/VRN_6 AG28 6 IO_L02N_6/VRP_6 AF28 6 IO_L03P_6 AJ30 6 IO_L03N_6/VREF_6 AH30 6 IO_L04P_6 AD23 6 IO_L04N_6 AC23 6 IO_L05P_6 AF27 6 IO_L05N_6 AE27 6 IO_L06P_6 AG29 6 IO_L06N_6 AH29 6 IO_L19P_6 AE24 6 IO_L19N_6 AD24 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 106 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 6 IO_L20P_6 AE26 6 IO_L20N_6 AD26 6 IO_L21P_6 AG30 6 IO_L21N_6/VREF_6 AF30 6 IO_L22P_6 AD25 6 IO_L22N_6 AC25 6 IO_L23P_6 AE28 6 IO_L23N_6 AD28 6 IO_L24P_6 AD29 6 IO_L24N_6 AE29 6 IO_L43P_6 AC24 6 IO_L43N_6 AB24 6 IO_L44P_6 AD27 6 IO_L44N_6 AC27 6 IO_L45P_6 AC26 6 IO_L45N_6/VREF_6 AB26 6 IO_L46P_6 AA23 6 IO_L46N_6 Y23 6 IO_L47P_6 AC28 6 IO_L47N_6 AB28 6 IO_L48P_6 AD30 6 IO_L48N_6 AE30 6 IO_L49P_6 AB25 6 IO_L49N_6 AA25 6 IO_L50P_6 AA24 6 IO_L50N_6 Y24 6 IO_L51P_6 AC29 6 IO_L51N_6/VREF_6 AB30 6 IO_L52P_6 Y25 6 IO_L52N_6 W25 6 IO_L53P_6 AB27 6 IO_L53N_6 AA27 6 IO_L54P_6 AA29 6 IO_L54N_6 AB29 6 IO_L67P_6 W23 NC 6 IO_L67N_6 V23 NC 6 IO_L68P_6 AA26 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 107 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 6 IO_L68N_6 Y26 NC 6 IO_L69P_6 AA30 NC 6 IO_L69N_6/VREF_6 Y30 NC 6 IO_L70P_6 W24 NC 6 IO_L70N_6 V24 NC 6 IO_L71P_6 Y27 NC 6 IO_L71N_6 W27 NC 6 IO_L72P_6 W28 NC 6 IO_L72N_6 Y28 NC 6 IO_L73P_6 V25 NC NC 6 IO_L73N_6 U25 NC NC 6 IO_L74P_6 V26 NC NC 6 IO_L74N_6 V27 NC NC 6 IO_L75P_6 Y29 NC NC 6 IO_L75N_6/VREF_6 W29 NC NC 6 IO_L76P_6 U22 NC NC 6 IO_L76N_6 T22 NC NC 6 IO_L77P_6 U26 NC NC 6 IO_L77N_6 T26 NC NC 6 IO_L78P_6 V30 NC NC 6 IO_L78N_6 W30 NC NC 6 IO_L91P_6 U23 6 IO_L91N_6 T23 6 IO_L92P_6 U27 6 IO_L92N_6 T27 6 IO_L93P_6 V29 6 IO_L93N_6/VREF_6 U29 6 IO_L94P_6 T24 6 IO_L94N_6 T25 6 IO_L95P_6 U28 6 IO_L95N_6 T28 6 IO_L96P_6 T30 6 IO_L96N_6 U30 7 IO_L96P_7 P28 7 IO_L96N_7 R28 7 IO_L95P_7 R25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 108 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 7 IO_L95N_7 R24 7 IO_L94P_7 R29 7 IO_L94N_7 T29 7 IO_L93P_7/VREF_7 R27 7 IO_L93N_7 P27 7 IO_L92P_7 R23 7 IO_L92N_7 P23 7 IO_L91P_7 N30 7 IO_L91N_7 P30 7 IO_L78P_7 P26 NC NC 7 IO_L78N_7 R26 NC NC 7 IO_L77P_7 R22 NC NC 7 IO_L77N_7 P22 NC NC 7 IO_L76P_7 N29 NC NC 7 IO_L76N_7 P29 NC NC 7 IO_L75P_7/VREF_7 N27 NC NC 7 IO_L75N_7 N26 NC NC 7 IO_L74P_7 P25 NC NC 7 IO_L74N_7 N25 NC NC 7 IO_L73P_7 L30 NC NC 7 IO_L73N_7 M30 NC NC 7 IO_L72P_7 L28 NC 7 IO_L72N_7 M28 NC 7 IO_L71P_7 N24 NC 7 IO_L71N_7 M24 NC 7 IO_L70P_7 L29 NC 7 IO_L70N_7 M29 NC 7 IO_L69P_7/VREF_7 M27 NC 7 IO_L69N_7 L27 NC 7 IO_L68P_7 N23 NC 7 IO_L68N_7 M23 NC 7 IO_L67P_7 J30 NC 7 IO_L67N_7 K30 NC 7 IO_L54P_7 K26 7 IO_L54N_7 L26 7 IO_L53P_7 M25 7 IO_L53N_7 L25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 109 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 7 IO_L52P_7 J29 7 IO_L52N_7 K29 7 IO_L51P_7/VREF_7 K27 7 IO_L51N_7 J27 7 IO_L50P_7 L24 7 IO_L50N_7 K24 7 IO_L49P_7 H27 7 IO_L49N_7 J28 7 IO_L48P_7 H26 7 IO_L48N_7 J26 7 IO_L47P_7 K25 7 IO_L47N_7 J25 7 IO_L46P_7 H28 7 IO_L46N_7 H29 7 IO_L45P_7/VREF_7 G28 7 IO_L45N_7 F28 7 IO_L44P_7 L23 7 IO_L44N_7 K23 7 IO_L43P_7 F30 7 IO_L43N_7 G30 7 IO_L24P_7 F26 7 IO_L24N_7 G27 7 IO_L23P_7 J24 7 IO_L23N_7 H24 7 IO_L22P_7 F29 7 IO_L22N_7 G29 7 IO_L21P_7/VREF_7 G26 7 IO_L21N_7 G25 7 IO_L20P_7 H25 7 IO_L20N_7 G24 7 IO_L19P_7 D30 7 IO_L19N_7 E30 7 IO_L06P_7 E27 7 IO_L06N_7 F27 7 IO_L05P_7 J23 7 IO_L05N_7 H22 7 IO_L04P_7 C29 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 110 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 7 IO_L04N_7 D29 7 IO_L03P_7/VREF_7 E28 7 IO_L03N_7 D28 7 IO_L02P_7/VRN_7 H23 7 IO_L02N_7/VRP_7 G23 7 IO_L01P_7 B30 7 IO_L01N_7 C30 0 VCCO_0 K20 0 VCCO_0 K19 0 VCCO_0 K18 0 VCCO_0 K17 0 VCCO_0 K16 0 VCCO_0 J21 0 VCCO_0 J20 0 VCCO_0 J19 0 VCCO_0 J18 0 VCCO_0 C18 0 VCCO_0 B26 1 VCCO_1 K15 1 VCCO_1 K14 1 VCCO_1 K13 1 VCCO_1 K12 1 VCCO_1 K11 1 VCCO_1 J13 1 VCCO_1 J12 1 VCCO_1 J11 1 VCCO_1 J10 1 VCCO_1 C13 1 VCCO_1 B5 2 VCCO_2 R10 2 VCCO_2 P10 2 VCCO_2 N10 2 VCCO_2 N9 2 VCCO_2 N3 2 VCCO_2 M10 2 VCCO_2 M9 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 111 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 2 VCCO_2 L10 2 VCCO_2 L9 2 VCCO_2 K9 2 VCCO_2 E2 3 VCCO_3 AF2 3 VCCO_3 AA9 3 VCCO_3 Y10 3 VCCO_3 Y9 3 VCCO_3 W10 3 VCCO_3 W9 3 VCCO_3 V10 3 VCCO_3 V9 3 VCCO_3 V3 3 VCCO_3 U10 3 VCCO_3 T10 4 VCCO_4 AJ5 4 VCCO_4 AH13 4 VCCO_4 AB13 4 VCCO_4 AB12 4 VCCO_4 AB11 4 VCCO_4 AB10 4 VCCO_4 AA15 4 VCCO_4 AA14 4 VCCO_4 AA13 4 VCCO_4 AA12 4 VCCO_4 AA11 5 VCCO_5 AJ26 5 VCCO_5 AH18 5 VCCO_5 AB21 5 VCCO_5 AB20 5 VCCO_5 AB19 5 VCCO_5 AB18 5 VCCO_5 AA20 5 VCCO_5 AA19 5 VCCO_5 AA18 5 VCCO_5 AA17 5 VCCO_5 AA16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 112 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 6 VCCO_6 AF29 6 VCCO_6 AA22 6 VCCO_6 Y22 6 VCCO_6 Y21 6 VCCO_6 W22 6 VCCO_6 W21 6 VCCO_6 V28 6 VCCO_6 V22 6 VCCO_6 V21 6 VCCO_6 U21 6 VCCO_6 T21 7 VCCO_7 R21 7 VCCO_7 P21 7 VCCO_7 N28 7 VCCO_7 N22 7 VCCO_7 N21 7 VCCO_7 M22 7 VCCO_7 M21 7 VCCO_7 L22 7 VCCO_7 L21 7 VCCO_7 K22 7 VCCO_7 E29 NA CCLK AF6 NA PROG_B B28 NA DONE AG5 NA M0 AF25 NA M1 AG26 NA M2 AH27 NA HSWAP_EN C27 NA TCK D5 NA TDI A29 NA TDO B3 NA TMS C4 NA PWRDWN_B AH4 NA DXN D26 NA DXP E25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 113 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 NA VBATT A2 NA RSVD E6 NA VCCAUX AK28 NA VCCAUX AK16 NA VCCAUX AK3 NA VCCAUX T1 NA VCCAUX R30 NA VCCAUX A28 NA VCCAUX A15 NA VCCAUX A3 NA VCCINT AB22 NA VCCINT AB9 NA VCCINT AA21 NA VCCINT AA10 NA VCCINT Y20 NA VCCINT Y19 NA VCCINT Y18 NA VCCINT Y17 NA VCCINT Y16 NA VCCINT Y15 NA VCCINT Y14 NA VCCINT Y13 NA VCCINT Y12 NA VCCINT Y11 NA VCCINT W20 NA VCCINT W11 NA VCCINT V20 NA VCCINT V11 NA VCCINT U20 NA VCCINT U11 NA VCCINT T20 NA VCCINT T11 NA VCCINT R20 NA VCCINT R11 NA VCCINT P20 NA VCCINT P11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 114 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 NA VCCINT N20 NA VCCINT N11 NA VCCINT M20 NA VCCINT M11 NA VCCINT L20 NA VCCINT L19 NA VCCINT L18 NA VCCINT L17 NA VCCINT L16 NA VCCINT L15 NA VCCINT L14 NA VCCINT L13 NA VCCINT L12 NA VCCINT L11 NA VCCINT K21 NA VCCINT K10 NA VCCINT J22 NA VCCINT J9 NA GND AK23 NA GND AK8 NA GND AJ29 NA GND AJ2 NA GND AH28 NA GND AH21 NA GND AH10 NA GND AH3 NA GND AG27 NA GND AG4 NA GND AF26 NA GND AF19 NA GND AF12 NA GND AF5 NA GND AE25 NA GND AE6 NA GND AD17 NA GND AD14 NA GND AC30 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 115 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 NA GND AC1 NA GND AA28 NA GND AA3 NA GND W26 NA GND W19 NA GND W18 NA GND W17 NA GND W16 NA GND W15 NA GND W14 NA GND W13 NA GND W12 NA GND W5 NA GND V19 NA GND V18 NA GND V17 NA GND V16 NA GND V15 NA GND V14 NA GND V13 NA GND V12 NA GND U24 NA GND U19 NA GND U18 NA GND U17 NA GND U16 NA GND U15 NA GND U14 NA GND U13 NA GND U12 NA GND U7 NA GND T19 NA GND T18 NA GND T17 NA GND T16 NA GND T15 NA GND T14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 116 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 NA GND T13 NA GND T12 NA GND R19 NA GND R18 NA GND R17 NA GND R16 NA GND R15 NA GND R14 NA GND R13 NA GND R12 NA GND P24 NA GND P19 NA GND P18 NA GND P17 NA GND P16 NA GND P15 NA GND P14 NA GND P13 NA GND P12 NA GND P7 NA GND N19 NA GND N18 NA GND N17 NA GND N16 NA GND N15 NA GND N14 NA GND N13 NA GND N12 NA GND M26 NA GND M19 NA GND M18 NA GND M17 NA GND M16 NA GND M15 NA GND M14 NA GND M13 NA GND M12 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 117 R Virtex-II Platform FPGAs: Pinout Information Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500 NA GND M5 NA GND K28 NA GND K3 NA GND H30 NA GND H1 NA GND G17 NA GND G14 NA GND F25 NA GND F6 NA GND E26 NA GND E19 NA GND E12 NA GND E5 NA GND D27 NA GND D4 NA GND C28 NA GND C21 NA GND C10 NA GND C3 NA GND B29 NA GND B2 NA GND A23 NA GND A8 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 118 R Virtex-II Platform FPGAs: Pinout Information FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 7: FF896 Flip-Chip Fine-Pitch BGA Package Specifications FF1152 Flip-Chip Fine-Pitch BGA Package As shown in Table 12, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1152 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V3000 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 119 R Virtex-II Platform FPGAs: Pinout Information device shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 0 IO_L01N_0 D29 0 IO_L01P_0 C29 0 IO_L02N_0 H26 0 IO_L02P_0 G26 0 IO_L03N_0/VRP_0 E28 0 IO_L03P_0/VRN_0 E27 0 IO_L04N_0/VREF_0 F25 0 IO_L04P_0 F26 0 IO_L05N_0 H25 0 IO_L05P_0 H24 0 IO_L06N_0 E26 0 IO_L06P_0 F27 0 IO_L19N_0 B32 0 IO_L19P_0 C33 0 IO_L20N_0 J24 0 IO_L20P_0 J23 0 IO_L21N_0 C27 0 IO_L21P_0/VREF_0 C28 0 IO_L22N_0 B30 0 IO_L22P_0 B31 0 IO_L23N_0 K23 0 IO_L23P_0 K22 0 IO_L24N_0 C26 0 IO_L24P_0 D27 0 IO_L25N_0 A30 0 IO_L25P_0 A31 0 IO_L26N_0 G24 0 IO_L26P_0 G25 0 IO_L27N_0 E25 0 IO_L27P_0/VREF_0 E24 0 IO_L28N_0 D25 0 IO_L28P_0 D26 0 IO_L29N_0 H23 0 IO_L29P_0 H22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 120 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 0 IO_L30N_0 F23 0 IO_L30P_0 F24 0 IO_L49N_0 B28 0 IO_L49P_0 B29 0 IO_L50N_0 J22 0 IO_L50P_0 J21 0 IO_L51N_0 A28 0 IO_L51P_0/VREF_0 A29 0 IO_L52N_0 A26 0 IO_L52P_0 B27 0 IO_L53N_0 C24 0 IO_L53P_0 D24 0 IO_L54N_0 D22 0 IO_L54P_0 D23 0 IO_L60N_0 B25 NC 0 IO_L60P_0 B26 NC 0 IO_L67N_0 B23 0 IO_L67P_0 B24 0 IO_L68N_0 G22 0 IO_L68P_0 G23 0 IO_L69N_0 F22 0 IO_L69P_0/VREF_0 F21 0 IO_L70N_0 A23 0 IO_L70P_0 A24 0 IO_L71N_0 K21 0 IO_L71P_0 K20 0 IO_L72N_0 C22 0 IO_L72P_0 C23 0 IO_L73N_0 E21 0 IO_L73P_0 E22 0 IO_L74N_0 H21 0 IO_L74P_0 H20 0 IO_L75N_0 G20 0 IO_L75P_0/VREF_0 F20 0 IO_L76N_0 B21 0 IO_L76P_0 B22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 121 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 0 IO_L77N_0 J20 0 IO_L77P_0 K19 0 IO_L78N_0 D20 0 IO_L78P_0 D21 0 IO_L79N_0 A21 NC 0 IO_L79P_0 A22 NC 0 IO_L80N_0 L19 NC 0 IO_L80P_0 L18 NC 0 IO_L81N_0 B19 NC 0 IO_L81P_0/VREF_0 A20 NC 0 IO_L82N_0 A18 NC 0 IO_L82P_0 B18 NC 0 IO_L83N_0 H19 NC 0 IO_L83P_0 H18 NC 0 IO_L84N_0 C20 NC 0 IO_L84P_0 C21 NC 0 IO_L91N_0/VREF_0 D19 0 IO_L91P_0 D18 0 IO_L92N_0 G18 0 IO_L92P_0 G19 0 IO_L93N_0 F18 0 IO_L93P_0 F19 0 IO_L94N_0/VREF_0 C19 0 IO_L94P_0 C18 0 IO_L95N_0/GCLK7P K18 0 IO_L95P_0/GCLK6S J18 0 IO_L96N_0/GCLK5P E19 0 IO_L96P_0/GCLK4S E18 1 IO_L96N_1/GCLK3P E17 1 IO_L96P_1/GCLK2S E16 1 IO_L95N_1/GCLK1P H17 1 IO_L95P_1/GCLK0S H16 1 IO_L94N_1 D17 1 IO_L94P_1/VREF_1 D16 1 IO_L93N_1 F16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 122 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 1 IO_L93P_1 F17 1 IO_L92N_1 G16 1 IO_L92P_1 G17 1 IO_L91N_1 C16 1 IO_L91P_1/VREF_1 C15 1 IO_L84N_1 D14 NC 1 IO_L84P_1 D15 NC 1 IO_L83N_1 J17 NC 1 IO_L83P_1 K17 NC 1 IO_L82N_1 B17 NC 1 IO_L82P_1 A17 NC 1 IO_L81N_1/VREF_1 A15 NC 1 IO_L81P_1 B16 NC 1 IO_L80N_1 L17 NC 1 IO_L80P_1 L16 NC 1 IO_L79N_1 A13 NC 1 IO_L79P_1 A14 NC 1 IO_L78N_1 C13 1 IO_L78P_1 C14 1 IO_L77N_1 K16 1 IO_L77P_1 K15 1 IO_L76N_1 B13 1 IO_L76P_1 B14 1 IO_L75N_1/VREF_1 F15 1 IO_L75P_1 G15 1 IO_L74N_1 H15 1 IO_L74P_1 H14 1 IO_L73N_1 A11 1 IO_L73P_1 A12 1 IO_L72N_1 E13 1 IO_L72P_1 E14 1 IO_L71N_1 J15 1 IO_L71P_1 J14 1 IO_L70N_1 D12 1 IO_L70P_1 D13 1 IO_L69N_1/VREF_1 F14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 123 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 1 IO_L69P_1 F13 1 IO_L68N_1 C11 1 IO_L68P_1 C12 1 IO_L67N_1 B11 1 IO_L67P_1 B12 1 IO_L60N_1 F11 NC 1 IO_L60P_1 F12 NC 1 IO_L54N_1 D10 1 IO_L54P_1 D11 1 IO_L53N_1 G12 1 IO_L53P_1 G13 1 IO_L52N_1 B9 1 IO_L52P_1 B10 1 IO_L51N_1/VREF_1 B8 1 IO_L51P_1 A9 1 IO_L50N_1 K14 1 IO_L50P_1 K13 1 IO_L49N_1 A6 1 IO_L49P_1 A7 1 IO_L30N_1 D9 1 IO_L30P_1 C9 1 IO_L29N_1 H13 1 IO_L29P_1 H12 1 IO_L28N_1 C7 1 IO_L28P_1 C8 1 IO_L27N_1/VREF_1 E11 1 IO_L27P_1 E10 1 IO_L26N_1 J13 1 IO_L26P_1 K12 1 IO_L25N_1 B6 1 IO_L25P_1 B7 1 IO_L24N_1 E8 1 IO_L24P_1 E9 1 IO_L23N_1 G10 1 IO_L23P_1 G11 1 IO_L22N_1 A4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 124 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 1 IO_L22P_1 A5 1 IO_L21N_1/VREF_1 F10 1 IO_L21P_1 G9 1 IO_L20N_1 J12 1 IO_L20P_1 J11 1 IO_L19N_1 B4 1 IO_L19P_1 B5 1 IO_L06N_1 D6 1 IO_L06P_1 C6 1 IO_L05N_1 H11 1 IO_L05P_1 J10 1 IO_L04N_1 D8 1 IO_L04P_1/VREF_1 E7 1 IO_L03N_1/VRP_1 F9 1 IO_L03P_1/VRN_1 F8 1 IO_L02N_1 H10 1 IO_L02P_1 H9 1 IO_L01N_1 C2 1 IO_L01P_1 B3 2 IO_L01N_2 E2 2 IO_L01P_2 D2 2 IO_L02N_2/VRP_2 K11 2 IO_L02P_2/VRN_2 K10 2 IO_L03N_2 F5 2 IO_L03P_2/VREF_2 G5 2 IO_L04N_2 E3 2 IO_L04P_2 D3 2 IO_L05N_2 J9 2 IO_L05P_2 K9 2 IO_L06N_2 F4 2 IO_L06P_2 E4 2 IO_L19N_2 E1 2 IO_L19P_2 D1 2 IO_L20N_2 J8 2 IO_L20P_2 K8 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 125 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 2 IO_L21N_2 H7 2 IO_L21P_2/VREF_2 J7 2 IO_L22N_2 H6 2 IO_L22P_2 G6 2 IO_L23N_2 L10 2 IO_L23P_2 L9 2 IO_L24N_2 G3 2 IO_L24P_2 F3 2 IO_L25N_2 G2 2 IO_L25P_2 F2 2 IO_L26N_2 M10 2 IO_L26P_2 N10 2 IO_L27N_2 J6 2 IO_L27P_2/VREF_2 K6 2 IO_L28N_2 J5 2 IO_L28P_2 H5 2 IO_L29N_2 L7 2 IO_L29P_2 K7 2 IO_L30N_2 J4 2 IO_L30P_2 H4 2 IO_L43N_2 G1 2 IO_L43P_2 F1 2 IO_L44N_2 L8 2 IO_L44P_2 M8 2 IO_L45N_2 J1 2 IO_L45P_2/VREF_2 H2 2 IO_L46N_2 J3 2 IO_L46P_2 H3 2 IO_L47N_2 M9 2 IO_L47P_2 N9 2 IO_L48N_2 L5 2 IO_L48P_2 K5 2 IO_L49N_2 K2 2 IO_L49P_2 J2 2 IO_L50N_2 N7 2 IO_L50P_2 M7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 126 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 2 IO_L51N_2 L6 2 IO_L51P_2/VREF_2 M6 2 IO_L52N_2 M3 2 IO_L52P_2 L3 2 IO_L53N_2 L4 2 IO_L53P_2 K4 2 IO_L54N_2 N4 2 IO_L54P_2 M4 2 IO_L67N_2 M2 2 IO_L67P_2 L2 2 IO_L68N_2 N8 2 IO_L68P_2 P8 2 IO_L69N_2 N6 2 IO_L69P_2/VREF_2 P6 2 IO_L70N_2 P5 2 IO_L70P_2 N5 2 IO_L71N_2 P10 2 IO_L71P_2 R10 2 IO_L72N_2 P3 2 IO_L72P_2 N3 2 IO_L73N_2 M1 2 IO_L73P_2 L1 2 IO_L74N_2 P9 2 IO_L74P_2 R9 2 IO_L75N_2 P2 2 IO_L75P_2/VREF_2 N2 2 IO_L76N_2 R4 2 IO_L76P_2 P4 2 IO_L77N_2 R8 2 IO_L77P_2 T8 2 IO_L78N_2 T3 2 IO_L78P_2 R3 2 IO_L79N_2 P1 NC 2 IO_L79P_2 N1 NC 2 IO_L80N_2 T11 NC 2 IO_L80P_2 U11 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 127 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 2 IO_L81N_2 R7 NC 2 IO_L81P_2/VREF_2 R6 NC 2 IO_L82N_2 U5 NC 2 IO_L82P_2 T5 NC 2 IO_L83N_2 T10 NC 2 IO_L83P_2 U10 NC 2 IO_L84N_2 U4 NC 2 IO_L84P_2 T4 NC 2 IO_L91N_2 T2 2 IO_L91P_2 R1 2 IO_L92N_2 U7 2 IO_L92P_2 T7 2 IO_L93N_2 T6 2 IO_L93P_2/VREF_2 U6 2 IO_L94N_2 U1 2 IO_L94P_2 U2 2 IO_L95N_2 U9 2 IO_L95P_2 U8 2 IO_L96N_2 U3 2 IO_L96P_2 V4 3 IO_L96N_3 V6 3 IO_L96P_3 W6 3 IO_L95N_3 V5 3 IO_L95P_3 W5 3 IO_L94N_3 V7 3 IO_L94P_3 W7 3 IO_L93N_3/VREF_3 V10 3 IO_L93P_3 W10 3 IO_L92N_3 V1 3 IO_L92P_3 V2 3 IO_L91N_3 W3 3 IO_L91P_3 Y3 3 IO_L84N_3 V9 NC 3 IO_L84P_3 V8 NC 3 IO_L83N_3 W4 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 128 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 3 IO_L83P_3 Y4 NC 3 IO_L82N_3 W11 NC 3 IO_L82P_3 V11 NC 3 IO_L81N_3/VREF_3 W8 NC 3 IO_L81P_3 Y8 NC 3 IO_L80N_3 W2 NC 3 IO_L80P_3 Y1 NC 3 IO_L79N_3 AA3 NC 3 IO_L79P_3 AB3 NC 3 IO_L78N_3 Y6 3 IO_L78P_3 AA6 3 IO_L77N_3 AA4 3 IO_L77P_3 AB4 3 IO_L76N_3 Y7 3 IO_L76P_3 AA8 3 IO_L75N_3/VREF_3 Y10 3 IO_L75P_3 AA10 3 IO_L74N_3 AA1 3 IO_L74P_3 AB1 3 IO_L73N_3 AA5 3 IO_L73P_3 AB5 3 IO_L72N_3 AA9 3 IO_L72P_3 Y9 3 IO_L71N_3 AA2 3 IO_L71P_3 AB2 3 IO_L70N_3 AB6 3 IO_L70P_3 AC6 3 IO_L69N_3/VREF_3 AD1 3 IO_L69P_3 AC1 3 IO_L68N_3 AC3 3 IO_L68P_3 AD3 3 IO_L67N_3 AC4 3 IO_L67P_3 AD4 3 IO_L54N_3 AB7 3 IO_L54P_3 AC7 3 IO_L53N_3 AC2 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 129 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 3 IO_L53P_3 AD2 3 IO_L52N_3 AC8 3 IO_L52P_3 AB8 3 IO_L51N_3/VREF_3 AB10 3 IO_L51P_3 AC10 3 IO_L50N_3 AD5 3 IO_L50P_3 AE5 3 IO_L49N_3 AE4 3 IO_L49P_3 AF4 3 IO_L48N_3 AB9 3 IO_L48P_3 AC9 3 IO_L47N_3 AE2 3 IO_L47P_3 AF1 3 IO_L46N_3 AD6 3 IO_L46P_3 AE6 3 IO_L45N_3/VREF_3 AD9 3 IO_L45P_3 AE9 3 IO_L44N_3 AF2 3 IO_L44P_3 AG2 3 IO_L43N_3 AF3 3 IO_L43P_3 AG3 3 IO_L30N_3 AD7 3 IO_L30P_3 AE7 3 IO_L29N_3 AF5 3 IO_L29P_3 AG5 3 IO_L28N_3 AE8 3 IO_L28P_3 AD8 3 IO_L27N_3/VREF_3 AF8 3 IO_L27P_3 AF9 3 IO_L26N_3 AH1 3 IO_L26P_3 AJ1 3 IO_L25N_3 AG4 3 IO_L25P_3 AH5 3 IO_L24N_3 AF6 3 IO_L24P_3 AG6 3 IO_L23N_3 AH3 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 130 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 3 IO_L23P_3 AJ3 3 IO_L22N_3 AF7 3 IO_L22P_3 AG7 3 IO_L21N_3/VREF_3 AL1 3 IO_L21P_3 AK1 3 IO_L20N_3 AH2 3 IO_L20P_3 AJ2 3 IO_L19N_3 AJ4 3 IO_L19P_3 AK4 3 IO_L06N_3 AE10 3 IO_L06P_3 AD10 3 IO_L05N_3 AK2 3 IO_L05P_3 AL2 3 IO_L04N_3 AH6 3 IO_L04P_3 AJ5 3 IO_L03N_3/VREF_3 AE11 3 IO_L03P_3 AF11 3 IO_L02N_3/VRP_3 AK3 3 IO_L02P_3/VRN_3 AL3 3 IO_L01N_3 AF10 3 IO_L01P_3 AG9 (1) 4 IO_L01N_4/BUSY/DOUT AM4 4 IO_L01P_4/INIT_B AL5 (1) 4 IO_L02N_4/D0/DIN AG10 4 IO_L02P_4/D1 AH11 4 IO_L03N_4/D2/ALT_VRP_4 AK7 4 IO_L03P_4/D3/ALT_VRN_4 AK8 4 IO_L04N_4/VREF_4 AL6 4 IO_L04P_4 AM6 4 IO_L05N_4/VRP_4 AK9 4 IO_L05P_4/VRN_4 AJ8 4 IO_L06N_4 AM8 4 IO_L06P_4 AM7 4 IO_L19N_4 AN3 4 IO_L19P_4 AM2 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 131 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 4 IO_L20N_4 AJ10 4 IO_L20P_4 AJ9 4 IO_L21N_4 AH9 4 IO_L21P_4/VREF_4 AH10 4 IO_L22N_4 AN5 4 IO_L22P_4 AN4 4 IO_L23N_4 AE12 4 IO_L23P_4 AE13 4 IO_L24N_4 AM9 4 IO_L24P_4 AL8 4 IO_L25N_4 AP5 4 IO_L25P_4 AP4 4 IO_L26N_4 AG11 4 IO_L26P_4 AG12 4 IO_L27N_4 AN7 4 IO_L27P_4/VREF_4 AN6 4 IO_L28N_4 AL10 4 IO_L28P_4 AL9 4 IO_L29N_4 AF12 4 IO_L29P_4 AF13 4 IO_L30N_4 AK10 4 IO_L30P_4 AK11 4 IO_L49N_4 AP7 4 IO_L49P_4 AP6 4 IO_L50N_4 AH13 4 IO_L50P_4 AH12 4 IO_L51N_4 AJ11 4 IO_L51P_4/VREF_4 AJ12 4 IO_L52N_4 AP9 4 IO_L52P_4 AN8 4 IO_L53N_4 AG13 4 IO_L53P_4 AG14 4 IO_L54N_4 AM11 4 IO_L54P_4 AL11 4 IO_L60N_4 AN10 NC 4 IO_L60P_4 AN9 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 132 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 4 IO_L67N_4 AN12 4 IO_L67P_4 AN11 4 IO_L68N_4 AE14 4 IO_L68P_4 AE15 4 IO_L69N_4 AJ13 4 IO_L69P_4/VREF_4 AJ14 4 IO_L70N_4 AL13 4 IO_L70P_4 AL12 4 IO_L71N_4 AF14 4 IO_L71P_4 AF15 4 IO_L72N_4 AM13 4 IO_L72P_4 AM12 4 IO_L73N_4 AP12 4 IO_L73P_4 AP11 4 IO_L74N_4 AG15 4 IO_L74P_4 AG16 4 IO_L75N_4 AN14 4 IO_L75P_4/VREF_4 AN13 4 IO_L76N_4 AP14 4 IO_L76P_4 AP13 4 IO_L77N_4 AD16 4 IO_L77P_4 AD17 4 IO_L78N_4 AK14 4 IO_L78P_4 AK13 4 IO_L79N_4 AN16 NC 4 IO_L79P_4 AP15 NC 4 IO_L80N_4 AE16 NC 4 IO_L80P_4 AE17 NC 4 IO_L81N_4 AH15 NC 4 IO_L81P_4/VREF_4 AJ15 NC 4 IO_L82N_4 AP17 NC 4 IO_L82P_4 AN17 NC 4 IO_L83N_4 AH17 NC 4 IO_L83P_4 AH16 NC 4 IO_L84N_4 AL15 NC 4 IO_L84P_4 AL14 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 133 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 4 IO_L91N_4/VREF_4 AL16 4 IO_L91P_4 AL17 4 IO_L92N_4 AJ17 4 IO_L92P_4 AJ16 4 IO_L93N_4 AM15 4 IO_L93P_4 AM14 4 IO_L94N_4/VREF_4 AM16 4 IO_L94P_4 AM17 4 IO_L95N_4/GCLK3S AF17 4 IO_L95P_4/GCLK2P AG17 4 IO_L96N_4/GCLK1S AK16 4 IO_L96P_4/GCLK0P AK17 5 IO_L96N_5/GCLK7S AK18 5 IO_L96P_5/GCLK6P AK19 5 IO_L95N_5/GCLK5S AG18 5 IO_L95P_5/GCLK4P AF18 5 IO_L94N_5 AL18 5 IO_L94P_5/VREF_5 AL19 5 IO_L93N_5 AJ19 5 IO_L93P_5 AJ18 5 IO_L92N_5 AH19 5 IO_L92P_5 AH18 5 IO_L91N_5 AM19 5 IO_L91P_5/VREF_5 AM20 5 IO_L84N_5 AL21 NC 5 IO_L84P_5 AL20 NC 5 IO_L83N_5 AM22 NC 5 IO_L83P_5 AM21 NC 5 IO_L82N_5 AN18 NC 5 IO_L82P_5 AP18 NC 5 IO_L81N_5/VREF_5 AP20 NC 5 IO_L81P_5 AN19 NC 5 IO_L80N_5 AE18 NC 5 IO_L80P_5 AE19 NC 5 IO_L79N_5 AP22 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 134 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 5 IO_L79P_5 AP21 NC 5 IO_L78N_5 AK22 5 IO_L78P_5 AK21 5 IO_L77N_5 AD18 5 IO_L77P_5 AD19 5 IO_L76N_5 AN22 5 IO_L76P_5 AN21 5 IO_L75N_5/VREF_5 AJ20 5 IO_L75P_5 AH20 5 IO_L74N_5 AG19 5 IO_L74P_5 AG20 5 IO_L73N_5 AP24 5 IO_L73P_5 AP23 5 IO_L72N_5 AL23 5 IO_L72P_5 AL22 5 IO_L71N_5 AF20 5 IO_L71P_5 AF21 5 IO_L70N_5 AM24 5 IO_L70P_5 AM23 5 IO_L69N_5/VREF_5 AJ21 5 IO_L69P_5 AJ22 5 IO_L68N_5 AJ24 5 IO_L68P_5 AJ23 5 IO_L67N_5 AN24 5 IO_L67P_5 AN23 5 IO_L60N_5 AN26 NC 5 IO_L60P_5 AN25 NC 5 IO_L54N_5 AL25 5 IO_L54P_5 AL24 5 IO_L53N_5 AE20 5 IO_L53P_5 AE21 5 IO_L52N_5 AN27 5 IO_L52P_5 AP26 5 IO_L51N_5/VREF_5 AP29 5 IO_L51P_5 AP28 5 IO_L50N_5 AG21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 135 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 5 IO_L50P_5 AG22 5 IO_L49N_5 AN29 5 IO_L49P_5 AN28 5 IO_L30N_5 AK24 5 IO_L30P_5 AK25 5 IO_L29N_5 AH23 5 IO_L29P_5 AH22 5 IO_L28N_5 AP31 5 IO_L28P_5 AP30 5 IO_L27N_5/VREF_5 AH24 5 IO_L27P_5 AH25 5 IO_L26N_5 AF22 5 IO_L26P_5 AF23 5 IO_L25N_5 AM27 5 IO_L25P_5 AM26 5 IO_L24N_5 AL27 5 IO_L24P_5 AL26 5 IO_L23N_5 AH26 5 IO_L23P_5 AJ25 5 IO_L22N_5 AN31 5 IO_L22P_5 AN30 5 IO_L21N_5/VREF_5 AK26 5 IO_L21P_5 AK27 5 IO_L20N_5 AG23 5 IO_L20P_5 AF24 5 IO_L19N_5 AM33 5 IO_L19P_5 AN32 5 IO_L06N_5 AJ27 5 IO_L06P_5 AJ26 5 IO_L05N_5/VRP_5 AE22 5 IO_L05P_5/VRN_5 AE23 5 IO_L04N_5 AM28 5 IO_L04P_5/VREF_5 AM29 5 IO_L03N_5/D4/ALT_VRP_5 AK28 5 IO_L03P_5/D5/ALT_VRN_5 AL29 5 IO_L02N_5/D6 AG24 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 136 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 5 IO_L02P_5/D7 AG25 5 IO_L01N_5/RDWR_B AL30 5 IO_L01P_5/CS_B AM31 6 IO_L01P_6 AE24 6 IO_L01N_6 AD25 6 IO_L02P_6/VRN_6 AJ30 6 IO_L02N_6/VRP_6 AH30 6 IO_L03P_6 AL32 6 IO_L03N_6/VREF_6 AK32 6 IO_L04P_6 AF25 6 IO_L04N_6 AE25 6 IO_L05P_6 AJ31 6 IO_L05N_6 AK31 6 IO_L06P_6 AH29 6 IO_L06N_6 AG29 6 IO_L19P_6 AG26 6 IO_L19N_6 AF26 6 IO_L20P_6 AL33 6 IO_L20N_6 AK33 6 IO_L21P_6 AJ32 6 IO_L21N_6/VREF_6 AH32 6 IO_L22P_6 AG28 6 IO_L22N_6 AF28 6 IO_L23P_6 AG30 6 IO_L23N_6 AF30 6 IO_L24P_6 AF29 6 IO_L24N_6 AE29 6 IO_L25P_6 AF27 6 IO_L25N_6 AE27 6 IO_L26P_6 AL34 6 IO_L26N_6 AK34 6 IO_L27P_6 AE28 6 IO_L27N_6/VREF_6 AD28 6 IO_L28P_6 AE26 6 IO_L28N_6 AD26 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 137 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 6 IO_L29P_6 AF31 6 IO_L29N_6 AG31 6 IO_L30P_6 AF32 6 IO_L30N_6 AG32 6 IO_L43P_6 AC25 6 IO_L43N_6 AB25 6 IO_L44P_6 AJ33 6 IO_L44N_6 AH33 6 IO_L45P_6 AE31 6 IO_L45N_6/VREF_6 AD32 6 IO_L46P_6 AD27 6 IO_L46N_6 AC27 6 IO_L47P_6 AJ34 6 IO_L47N_6 AH34 6 IO_L48P_6 AE30 6 IO_L48N_6 AD30 6 IO_L49P_6 AC26 6 IO_L49N_6 AB26 6 IO_L50P_6 AD29 6 IO_L50N_6 AC29 6 IO_L51P_6 AF33 6 IO_L51N_6/VREF_6 AG33 6 IO_L52P_6 AC28 6 IO_L52N_6 AB28 6 IO_L53P_6 AF34 6 IO_L53N_6 AE33 6 IO_L54P_6 AB27 6 IO_L54N_6 AA27 6 IO_L67P_6 AA25 6 IO_L67N_6 Y25 6 IO_L68P_6 AD33 6 IO_L68N_6 AC33 6 IO_L69P_6 AC32 6 IO_L69N_6/VREF_6 AB32 6 IO_L70P_6 AA26 6 IO_L70N_6 Y26 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 138 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 6 IO_L71P_6 AD34 6 IO_L71N_6 AC34 6 IO_L72P_6 AC31 6 IO_L72N_6 AD31 6 IO_L73P_6 Y27 6 IO_L73N_6 W27 6 IO_L74P_6 AB29 6 IO_L74N_6 AA29 6 IO_L75P_6 AB31 6 IO_L75N_6/VREF_6 AA31 6 IO_L76P_6 Y28 6 IO_L76N_6 Y29 6 IO_L77P_6 AB33 6 IO_L77N_6 AA33 6 IO_L78P_6 AA30 6 IO_L78N_6 AB30 6 IO_L79P_6 W24 NC 6 IO_L79N_6 V24 NC 6 IO_L80P_6 AB34 NC 6 IO_L80N_6 AA34 NC 6 IO_L81P_6 W33 NC 6 IO_L81N_6/VREF_6 Y34 NC 6 IO_L82P_6 W25 NC 6 IO_L82N_6 V25 NC 6 IO_L83P_6 Y32 NC 6 IO_L83N_6 AA32 NC 6 IO_L84P_6 W29 NC 6 IO_L84N_6 V29 NC 6 IO_L91P_6 W28 6 IO_L91N_6 V28 6 IO_L92P_6 V33 6 IO_L92N_6 V34 6 IO_L93P_6 Y31 6 IO_L93N_6/VREF_6 W31 6 IO_L94P_6 V26 6 IO_L94N_6 V27 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 139 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 6 IO_L95P_6 W30 6 IO_L95N_6 V30 6 IO_L96P_6 V32 6 IO_L96N_6 W32 7 IO_L96P_7 U31 7 IO_L96N_7 V31 7 IO_L95P_7 T28 7 IO_L95N_7 U28 7 IO_L94P_7 U33 7 IO_L94N_7 U34 7 IO_L93P_7/VREF_7 U29 7 IO_L93N_7 T29 7 IO_L92P_7 U27 7 IO_L92N_7 U26 7 IO_L91P_7 T30 7 IO_L91N_7 U30 7 IO_L84P_7 R32 NC 7 IO_L84N_7 T32 NC 7 IO_L83P_7 U25 NC 7 IO_L83N_7 T25 NC 7 IO_L82P_7 R34 NC 7 IO_L82N_7 T33 NC 7 IO_L81P_7/VREF_7 N34 NC 7 IO_L81N_7 P34 NC 7 IO_L80P_7 U24 NC 7 IO_L80N_7 T24 NC 7 IO_L79P_7 R31 NC 7 IO_L79N_7 T31 NC 7 IO_L78P_7 N32 7 IO_L78N_7 P32 7 IO_L77P_7 T27 7 IO_L77N_7 R27 7 IO_L76P_7 N33 7 IO_L76N_7 P33 7 IO_L75P_7/VREF_7 R29 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 140 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 7 IO_L75N_7 R28 7 IO_L74P_7 R26 7 IO_L74N_7 P26 7 IO_L73P_7 N31 7 IO_L73N_7 P31 7 IO_L72P_7 N30 7 IO_L72N_7 P30 7 IO_L71P_7 R25 7 IO_L71N_7 P25 7 IO_L70P_7 L34 7 IO_L70N_7 M34 7 IO_L69P_7/VREF_7 P29 7 IO_L69N_7 N29 7 IO_L68P_7 P27 7 IO_L68N_7 N27 7 IO_L67P_7 L32 7 IO_L67N_7 M32 7 IO_L54P_7 L31 7 IO_L54N_7 M31 7 IO_L53P_7 K29 7 IO_L53N_7 L30 7 IO_L52P_7 L33 7 IO_L52N_7 M33 7 IO_L51P_7/VREF_7 M29 7 IO_L51N_7 L29 7 IO_L50P_7 M28 7 IO_L50N_7 N28 7 IO_L49P_7 K30 7 IO_L49N_7 K31 7 IO_L48P_7 H32 7 IO_L48N_7 J32 7 IO_L47P_7 N26 7 IO_L47N_7 M26 7 IO_L46P_7 J33 7 IO_L46N_7 K33 7 IO_L45P_7/VREF_7 H33 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 141 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 7 IO_L45N_7 J34 7 IO_L44P_7 M27 7 IO_L44N_7 L27 7 IO_L43P_7 H31 7 IO_L43N_7 J31 7 IO_L30P_7 F32 7 IO_L30N_7 G32 7 IO_L29P_7 N25 7 IO_L29N_7 M25 7 IO_L28P_7 F34 7 IO_L28N_7 G34 7 IO_L27P_7/VREF_7 J30 7 IO_L27N_7 H30 7 IO_L26P_7 K28 7 IO_L26N_7 L28 7 IO_L25P_7 H28 7 IO_L25N_7 J29 7 IO_L24P_7 G29 7 IO_L24N_7 H29 7 IO_L23P_7 L26 7 IO_L23N_7 K26 7 IO_L22P_7 F33 7 IO_L22N_7 G33 7 IO_L21P_7/VREF_7 J28 7 IO_L21N_7 J27 7 IO_L20P_7 K27 7 IO_L20N_7 J26 7 IO_L19P_7 E31 7 IO_L19N_7 F31 7 IO_L06P_7 D32 7 IO_L06N_7 E32 7 IO_L05P_7 L25 7 IO_L05N_7 K24 7 IO_L04P_7 D34 7 IO_L04N_7 E34 7 IO_L03P_7/VREF_7 G30 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 142 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 7 IO_L03N_7 F30 7 IO_L02P_7/VRN_7 K25 7 IO_L02N_7/VRP_7 J25 7 IO_L01P_7 D33 7 IO_L01N_7 E33 0 VCCO_0 M22 0 VCCO_0 M21 0 VCCO_0 M20 0 VCCO_0 M19 0 VCCO_0 M18 0 VCCO_0 L23 0 VCCO_0 L22 0 VCCO_0 L21 0 VCCO_0 L20 0 VCCO_0 E20 0 VCCO_0 D28 0 VCCO_0 A25 0 VCCO_0 A19 1 VCCO_1 M17 1 VCCO_1 M16 1 VCCO_1 M15 1 VCCO_1 M14 1 VCCO_1 M13 1 VCCO_1 L15 1 VCCO_1 L14 1 VCCO_1 L13 1 VCCO_1 L12 1 VCCO_1 E15 1 VCCO_1 D7 1 VCCO_1 A16 1 VCCO_1 A10 2 VCCO_2 U12 2 VCCO_2 T12 2 VCCO_2 T1 2 VCCO_2 R12 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 143 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 2 VCCO_2 R11 2 VCCO_2 R5 2 VCCO_2 P12 2 VCCO_2 P11 2 VCCO_2 N12 2 VCCO_2 N11 2 VCCO_2 M11 2 VCCO_2 K1 2 VCCO_2 G4 3 VCCO_3 AH4 3 VCCO_3 AE1 3 VCCO_3 AC11 3 VCCO_3 AB12 3 VCCO_3 AB11 3 VCCO_3 AA12 3 VCCO_3 AA11 3 VCCO_3 Y12 3 VCCO_3 Y11 3 VCCO_3 Y5 3 VCCO_3 W12 3 VCCO_3 W1 3 VCCO_3 V12 4 VCCO_4 AP16 4 VCCO_4 AP10 4 VCCO_4 AL7 4 VCCO_4 AK15 4 VCCO_4 AD15 4 VCCO_4 AD14 4 VCCO_4 AD13 4 VCCO_4 AD12 4 VCCO_4 AC17 4 VCCO_4 AC16 4 VCCO_4 AC15 4 VCCO_4 AC14 4 VCCO_4 AC13 5 VCCO_5 AP25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 144 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 5 VCCO_5 AP19 5 VCCO_5 AL28 5 VCCO_5 AK20 5 VCCO_5 AD23 5 VCCO_5 AD22 5 VCCO_5 AD21 5 VCCO_5 AD20 5 VCCO_5 AC22 5 VCCO_5 AC21 5 VCCO_5 AC20 5 VCCO_5 AC19 5 VCCO_5 AC18 6 VCCO_6 AH31 6 VCCO_6 AE34 6 VCCO_6 AC24 6 VCCO_6 AB24 6 VCCO_6 AB23 6 VCCO_6 AA24 6 VCCO_6 AA23 6 VCCO_6 Y30 6 VCCO_6 Y24 6 VCCO_6 Y23 6 VCCO_6 W34 6 VCCO_6 W23 6 VCCO_6 V23 7 VCCO_7 U23 7 VCCO_7 T34 7 VCCO_7 T23 7 VCCO_7 R30 7 VCCO_7 R24 7 VCCO_7 R23 7 VCCO_7 P24 7 VCCO_7 P23 7 VCCO_7 N24 7 VCCO_7 N23 7 VCCO_7 M24 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 145 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 7 VCCO_7 K34 7 VCCO_7 G31 NA CCLK AH8 NA PROG_B D30 NA DONE AJ7 NA M0 AH27 NA M1 AJ28 NA M2 AK29 NA HSWAP_EN E29 NA TCK F7 NA TDI C31 NA TDO D5 NA TMS E6 NA PWRDWN_B AK6 NA DXN F28 NA DXP G27 NA VBATT C4 NA RSVD G8 NA VCCAUX AM30 NA VCCAUX AM18 NA VCCAUX AM5 NA VCCAUX V3 NA VCCAUX U32 NA VCCAUX C30 NA VCCAUX C17 NA VCCAUX C5 NA VCCINT AD24 NA VCCINT AD11 NA VCCINT AC23 NA VCCINT AC12 NA VCCINT AB22 NA VCCINT AB21 NA VCCINT AB20 NA VCCINT AB19 NA VCCINT AB18 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 146 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA VCCINT AB17 NA VCCINT AB16 NA VCCINT AB15 NA VCCINT AB14 NA VCCINT AB13 NA VCCINT AA22 NA VCCINT AA13 NA VCCINT Y22 NA VCCINT Y13 NA VCCINT W22 NA VCCINT W13 NA VCCINT V22 NA VCCINT V13 NA VCCINT U22 NA VCCINT U13 NA VCCINT T22 NA VCCINT T13 NA VCCINT R22 NA VCCINT R13 NA VCCINT P22 NA VCCINT P13 NA VCCINT N22 NA VCCINT N21 NA VCCINT N20 NA VCCINT N19 NA VCCINT N18 NA VCCINT N17 NA VCCINT N16 NA VCCINT N15 NA VCCINT N14 NA VCCINT N13 NA VCCINT M23 NA VCCINT M12 NA VCCINT L24 NA VCCINT L11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 147 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA GND AP33 NA GND AP32 NA GND AP27 NA GND AP8 NA GND AP3 NA GND AP2 NA GND AN34 NA GND AN33 NA GND AN20 NA GND AN15 NA GND AN2 NA GND AN1 NA GND AM34 NA GND AM32 NA GND AM25 NA GND AM10 NA GND AM3 NA GND AM1 NA GND AL31 NA GND AL4 NA GND AK30 NA GND AK23 NA GND AK12 NA GND AK5 NA GND AJ29 NA GND AJ6 NA GND AH28 NA GND AH21 NA GND AH14 NA GND AH7 NA GND AG34 NA GND AG27 NA GND AG8 NA GND AG1 NA GND AF19 NA GND AF16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 148 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA GND AE32 NA GND AE3 NA GND AC30 NA GND AC5 NA GND AA28 NA GND AA21 NA GND AA20 NA GND AA19 NA GND AA18 NA GND AA17 NA GND AA16 NA GND AA15 NA GND AA14 NA GND AA7 NA GND Y33 NA GND Y21 NA GND Y20 NA GND Y19 NA GND Y18 NA GND Y17 NA GND Y16 NA GND Y15 NA GND Y14 NA GND Y2 NA GND W26 NA GND W21 NA GND W20 NA GND W19 NA GND W18 NA GND W17 NA GND W16 NA GND W15 NA GND W14 NA GND W9 NA GND V21 NA GND V20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 149 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA GND V19 NA GND V18 NA GND V17 NA GND V16 NA GND V15 NA GND V14 NA GND U21 NA GND U20 NA GND U19 NA GND U18 NA GND U17 NA GND U16 NA GND U15 NA GND U14 NA GND T26 NA GND T21 NA GND T20 NA GND T19 NA GND T18 NA GND T17 NA GND T16 NA GND T15 NA GND T14 NA GND T9 NA GND R33 NA GND R21 NA GND R20 NA GND R19 NA GND R18 NA GND R17 NA GND R16 NA GND R15 NA GND R14 NA GND R2 NA GND P28 NA GND P21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 150 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA GND P20 NA GND P19 NA GND P18 NA GND P17 NA GND P16 NA GND P15 NA GND P14 NA GND P7 NA GND M30 NA GND M5 NA GND K32 NA GND K3 NA GND J19 NA GND J16 NA GND H34 NA GND H27 NA GND H8 NA GND H1 NA GND G28 NA GND G21 NA GND G14 NA GND G7 NA GND F29 NA GND F6 NA GND E30 NA GND E23 NA GND E12 NA GND E5 NA GND D31 NA GND D4 NA GND C34 NA GND C32 NA GND C25 NA GND C10 NA GND C3 NA GND C1 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 151 R Virtex-II Platform FPGAs: Pinout Information Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V3000 NA GND B34 NA GND B33 NA GND B20 NA GND B15 NA GND B2 NA GND B1 NA GND A33 NA GND A32 NA GND A27 NA GND A8 NA GND A3 NA GND A2 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 152 R Virtex-II Platform FPGAs: Pinout Information FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 8: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 153 R Virtex-II Platform FPGAs: Pinout Information FF1517 Flip-Chip Fine-Pitch BGA Package As shown in Table 13, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1517 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V4000 and XC2V6000 devices shown in the No Connect columns. Following this table are the FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 0 IO_L01N_0 B36 0 IO_L01P_0 C36 0 IO_L02N_0 J30 0 IO_L02P_0 J29 0 IO_L03N_0/VRP_0 D33 0 IO_L03P_0/VRN_0 D34 0 IO_L04N_0/VREF_0 C34 0 IO_L04P_0 C35 0 IO_L05N_0 H30 0 IO_L05P_0 G30 0 IO_L06N_0 D32 0 IO_L06P_0 E33 0 IO_L07N_0 A35 NC 0 IO_L07P_0 A36 NC 0 IO_L08N_0 K28 NC 0 IO_L08P_0 J28 NC 0 IO_L09N_0 E32 NC 0 IO_L09P_0/VREF_0 F32 NC 0 IO_L10N_0 B34 NC 0 IO_L10P_0 B35 NC 0 IO_L11N_0 H29 NC 0 IO_L11P_0 H28 NC 0 IO_L12N_0 F31 NC 0 IO_L12P_0 G31 NC 0 IO_L19N_0 C32 0 IO_L19P_0 C33 0 IO_L20N_0 M26 0 IO_L20P_0 M25 0 IO_L21N_0 E30 0 IO_L21P_0/VREF_0 E31 0 IO_L22N_0 A33 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 154 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 0 IO_L22P_0 A34 0 IO_L23N_0 K27 0 IO_L23P_0 K26 0 IO_L24N_0 F29 0 IO_L24P_0 F30 0 IO_L25N_0 B32 0 IO_L25P_0 B33 0 IO_L26N_0 L26 0 IO_L26P_0 L25 0 IO_L27N_0 G28 0 IO_L27P_0/VREF_0 G29 0 IO_L28N_0 C30 0 IO_L28P_0 C31 0 IO_L29N_0 J27 0 IO_L29P_0 J26 0 IO_L30N_0 D30 0 IO_L30P_0 D31 0 IO_L31N_0 A31 NC 0 IO_L31P_0 A32 NC 0 IO_L32N_0 H27 NC 0 IO_L32P_0 H26 NC 0 IO_L33N_0 F27 NC 0 IO_L33P_0/VREF_0 F28 NC 0 IO_L34N_0 B30 NC 0 IO_L34P_0 B31 NC 0 IO_L35N_0 M24 NC 0 IO_L35P_0 M23 NC 0 IO_L36N_0 D28 NC 0 IO_L36P_0 D29 NC 0 IO_L49N_0 C28 0 IO_L49P_0 C29 0 IO_L50N_0 K25 0 IO_L50P_0 L24 0 IO_L51N_0 E27 0 IO_L51P_0/VREF_0 E28 0 IO_L52N_0 A29 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 155 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 0 IO_L52P_0 A30 0 IO_L53N_0 G26 0 IO_L53P_0 G25 0 IO_L54N_0 D26 0 IO_L54P_0 D27 0 IO_L55N_0 B27 0 IO_L55P_0 B28 0 IO_L56N_0 H25 0 IO_L56P_0 H24 0 IO_L57N_0 F25 0 IO_L57P_0/VREF_0 F26 0 IO_L58N_0 A27 0 IO_L58P_0 A28 0 IO_L59N_0 K24 0 IO_L59P_0 K23 0 IO_L60N_0 E24 0 IO_L60P_0 E25 0 IO_L67N_0 C26 0 IO_L67P_0 C27 0 IO_L68N_0 J24 0 IO_L68P_0 J23 0 IO_L69N_0 D24 0 IO_L69P_0/VREF_0 D25 0 IO_L70N_0 A25 0 IO_L70P_0 A26 0 IO_L71N_0 M22 0 IO_L71P_0 M21 0 IO_L72N_0 G23 0 IO_L72P_0 G24 0 IO_L73N_0 B25 0 IO_L73P_0 C25 0 IO_L74N_0 L22 0 IO_L74P_0 L21 0 IO_L75N_0 F23 0 IO_L75P_0/VREF_0 F24 0 IO_L76N_0 C23 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 156 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 0 IO_L76P_0 C24 0 IO_L77N_0 K22 0 IO_L77P_0 K21 0 IO_L78N_0 E22 0 IO_L78P_0 E23 0 IO_L79N_0 B23 0 IO_L79P_0 B24 0 IO_L80N_0 J22 0 IO_L80P_0 J21 0 IO_L81N_0 G21 0 IO_L81P_0/VREF_0 G22 0 IO_L82N_0 A23 0 IO_L82P_0 A24 0 IO_L83N_0 H22 0 IO_L83P_0 H21 0 IO_L84N_0 F21 0 IO_L84P_0 F22 0 IO_L91N_0/VREF_0 B21 0 IO_L91P_0 B22 0 IO_L92N_0 L20 0 IO_L92P_0 M20 0 IO_L93N_0 E21 0 IO_L93P_0 D22 0 IO_L94N_0/VREF_0 A21 0 IO_L94P_0 A22 0 IO_L95N_0/GCLK7P H20 0 IO_L95P_0/GCLK6S J20 0 IO_L96N_0/GCLK5P C21 0 IO_L96P_0/GCLK4S D21 1 IO_L96N_1/GCLK3P F19 1 IO_L96P_1/GCLK2S F20 1 IO_L95N_1/GCLK1P H19 1 IO_L95P_1/GCLK0S H18 1 IO_L94N_1 C19 1 IO_L94P_1/VREF_1 C20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 157 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 1 IO_L93N_1 E19 1 IO_L93P_1 E20 1 IO_L92N_1 J19 1 IO_L92P_1 J18 1 IO_L91N_1 A18 1 IO_L91P_1/VREF_1 A19 1 IO_L84N_1 D18 1 IO_L84P_1 D19 1 IO_L83N_1 K19 1 IO_L83P_1 K18 1 IO_L82N_1 B18 1 IO_L82P_1 B19 1 IO_L81N_1/VREF_1 G18 1 IO_L81P_1 G19 1 IO_L80N_1 E18 1 IO_L80P_1 E17 1 IO_L79N_1 A16 1 IO_L79P_1 A17 1 IO_L78N_1 F17 1 IO_L78P_1 F18 1 IO_L77N_1 L19 1 IO_L77P_1 L18 1 IO_L76N_1 B16 1 IO_L76P_1 B17 1 IO_L75N_1/VREF_1 G16 1 IO_L75P_1 G17 1 IO_L74N_1 M19 1 IO_L74P_1 M18 1 IO_L73N_1 C16 1 IO_L73P_1 C17 1 IO_L72N_1 D15 1 IO_L72P_1 D16 1 IO_L71N_1 J17 1 IO_L71P_1 J16 1 IO_L70N_1 A14 1 IO_L70P_1 A15 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 158 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 1 IO_L69N_1/VREF_1 E15 1 IO_L69P_1 E16 1 IO_L68N_1 K17 1 IO_L68P_1 K16 1 IO_L67N_1 C15 1 IO_L67P_1 B15 1 IO_L60N_1 F15 1 IO_L60P_1 F16 1 IO_L59N_1 H16 1 IO_L59P_1 H15 1 IO_L58N_1 C13 1 IO_L58P_1 C14 1 IO_L57N_1/VREF_1 D13 1 IO_L57P_1 D14 1 IO_L56N_1 M17 1 IO_L56P_1 M16 1 IO_L55N_1 A12 1 IO_L55P_1 A13 1 IO_L54N_1 B12 1 IO_L54P_1 B13 1 IO_L53N_1 G15 1 IO_L53P_1 G14 1 IO_L52N_1 C11 1 IO_L52P_1 C12 1 IO_L51N_1/VREF_1 F13 1 IO_L51P_1 F14 1 IO_L50N_1 L16 1 IO_L50P_1 L15 1 IO_L49N_1 A10 1 IO_L49P_1 A11 1 IO_L36N_1 E12 NC 1 IO_L36P_1 E13 NC 1 IO_L35N_1 K15 NC 1 IO_L35P_1 J14 NC 1 IO_L34N_1 B9 NC 1 IO_L34P_1 B10 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 159 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 1 IO_L33N_1/VREF_1 D11 NC 1 IO_L33P_1 D12 NC 1 IO_L32N_1 H14 NC 1 IO_L32P_1 H13 NC 1 IO_L31N_1 A8 NC 1 IO_L31P_1 A9 NC 1 IO_L30N_1 F11 1 IO_L30P_1 F12 1 IO_L29N_1 K14 1 IO_L29P_1 L14 1 IO_L28N_1 C9 1 IO_L28P_1 C10 1 IO_L27N_1/VREF_1 G11 1 IO_L27P_1 G12 1 IO_L26N_1 M15 1 IO_L26P_1 M14 1 IO_L25N_1 B7 1 IO_L25P_1 B8 1 IO_L24N_1 D9 1 IO_L24P_1 D10 1 IO_L23N_1 J13 1 IO_L23P_1 J12 1 IO_L22N_1 A6 1 IO_L22P_1 A7 1 IO_L21N_1/VREF_1 E9 1 IO_L21P_1 E10 1 IO_L20N_1 D8 1 IO_L20P_1 E7 1 IO_L19N_1 C7 1 IO_L19P_1 C8 1 IO_L12N_1 F9 NC 1 IO_L12P_1 F10 NC 1 IO_L11N_1 H12 NC 1 IO_L11P_1 H11 NC 1 IO_L10N_1 B5 NC 1 IO_L10P_1 B6 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 160 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 1 IO_L09N_1/VREF_1 G9 NC 1 IO_L09P_1 G10 NC 1 IO_L08N_1 K13 NC 1 IO_L08P_1 K12 NC 1 IO_L07N_1 A4 NC 1 IO_L07P_1 A5 NC 1 IO_L06N_1 F8 1 IO_L06P_1 E8 1 IO_L05N_1 J11 1 IO_L05P_1 K11 1 IO_L04N_1 C5 1 IO_L04P_1/VREF_1 C6 1 IO_L03N_1/VRP_1 D6 1 IO_L03P_1/VRN_1 D7 1 IO_L02N_1 H10 1 IO_L02P_1 J10 1 IO_L01N_1 C4 1 IO_L01P_1 B4 2 IO_L01N_2 E3 2 IO_L01P_2 D2 2 IO_L02N_2/VRP_2 L13 2 IO_L02P_2/VRN_2 M13 2 IO_L03N_2 F4 2 IO_L03P_2/VREF_2 E4 2 IO_L04N_2 E1 2 IO_L04P_2 D1 2 IO_L05N_2 L12 2 IO_L05P_2 M11 2 IO_L06N_2 G6 2 IO_L06P_2 F5 2 IO_L07N_2 F2 NC 2 IO_L07P_2 E2 NC 2 IO_L08N_2 M12 NC 2 IO_L08P_2 N12 NC 2 IO_L09N_2 H6 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 161 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 2 IO_L09P_2/VREF_2 H7 NC 2 IO_L10N_2 G3 NC 2 IO_L10P_2 F3 NC 2 IO_L11N_2 J8 NC 2 IO_L11P_2 K8 NC 2 IO_L12N_2 H5 NC 2 IO_L12P_2 G5 NC 2 IO_L19N_2 G1 2 IO_L19P_2 F1 2 IO_L20N_2 K9 2 IO_L20P_2 L10 2 IO_L21N_2 K7 2 IO_L21P_2/VREF_2 J7 2 IO_L22N_2 H2 2 IO_L22P_2 G2 2 IO_L23N_2 L9 2 IO_L23P_2 M9 2 IO_L24N_2 H4 2 IO_L24P_2 G4 2 IO_L25N_2 J3 2 IO_L25P_2 H3 2 IO_L26N_2 M10 2 IO_L26P_2 N10 2 IO_L27N_2 K6 2 IO_L27P_2/VREF_2 J6 2 IO_L28N_2 K5 2 IO_L28P_2 J5 2 IO_L29N_2 N11 2 IO_L29P_2 P11 2 IO_L30N_2 M7 2 IO_L30P_2 L7 2 IO_L31N_2 J1 NC 2 IO_L31P_2 H1 NC 2 IO_L32N_2 L8 NC 2 IO_L32P_2 M8 NC 2 IO_L33N_2 K4 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 162 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 2 IO_L33P_2/VREF_2 J4 NC 2 IO_L34N_2 K2 NC 2 IO_L34P_2 J2 NC 2 IO_L35N_2 P12 NC 2 IO_L35P_2 R12 NC 2 IO_L36N_2 M6 NC 2 IO_L36P_2 L6 NC 2 IO_L43N_2 L3 2 IO_L43P_2 K3 2 IO_L44N_2 N9 2 IO_L44P_2 P9 2 IO_L45N_2 M4 2 IO_L45P_2/VREF_2 L4 2 IO_L46N_2 L1 2 IO_L46P_2 K1 2 IO_L47N_2 P10 2 IO_L47P_2 R10 2 IO_L48N_2 N5 2 IO_L48P_2 M5 2 IO_L49N_2 N3 2 IO_L49P_2 M3 2 IO_L50N_2 N8 2 IO_L50P_2 P8 2 IO_L51N_2 T11 2 IO_L51P_2/VREF_2 R11 2 IO_L52N_2 N2 2 IO_L52P_2 M2 2 IO_L53N_2 T12 2 IO_L53P_2 U12 2 IO_L54N_2 P6 2 IO_L54P_2 N6 2 IO_L55N_2 N1 2 IO_L55P_2 M1 2 IO_L56N_2 R8 2 IO_L56P_2 T8 2 IO_L57N_2 R7 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 163 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 2 IO_L57P_2/VREF_2 P7 2 IO_L58N_2 R3 2 IO_L58P_2 P3 2 IO_L59N_2 T10 2 IO_L59P_2 U10 2 IO_L60N_2 P4 2 IO_L60P_2 N4 2 IO_L67N_2 T6 2 IO_L67P_2 R6 2 IO_L68N_2 T9 2 IO_L68P_2 U9 2 IO_L69N_2 T5 2 IO_L69P_2/VREF_2 R5 2 IO_L70N_2 R1 2 IO_L70P_2 P1 2 IO_L71N_2 V12 2 IO_L71P_2 W12 2 IO_L72N_2 T4 2 IO_L72P_2 R4 2 IO_L73N_2 T2 2 IO_L73P_2 R2 2 IO_L74N_2 V11 2 IO_L74P_2 W11 2 IO_L75N_2 U7 2 IO_L75P_2/VREF_2 T7 2 IO_L76N_2 U3 2 IO_L76P_2 T3 2 IO_L77N_2 V10 2 IO_L77P_2 W10 2 IO_L78N_2 V6 2 IO_L78P_2 U6 2 IO_L79N_2 U1 2 IO_L79P_2 T1 2 IO_L80N_2 V9 2 IO_L80P_2 W9 2 IO_L81N_2 V5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 164 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 2 IO_L81P_2/VREF_2 U5 2 IO_L82N_2 V2 2 IO_L82P_2 U2 2 IO_L83N_2 V8 2 IO_L83P_2 W8 2 IO_L84N_2 W7 2 IO_L84P_2 V7 2 IO_L91N_2 W1 2 IO_L91P_2 V1 2 IO_L92N_2 Y11 2 IO_L92P_2 Y12 2 IO_L93N_2 W4 2 IO_L93P_2/VREF_2 V4 2 IO_L94N_2 W2 2 IO_L94P_2 W3 2 IO_L95N_2 Y8 2 IO_L95P_2 Y9 2 IO_L96N_2 W5 2 IO_L96P_2 W6 3 IO_L96N_3 AB8 3 IO_L96P_3 AA8 3 IO_L95N_3 Y3 3 IO_L95P_3 AA3 3 IO_L94N_3 Y6 3 IO_L94P_3 AA6 3 IO_L93N_3/VREF_3 AB9 3 IO_L93P_3 AA9 3 IO_L92N_3 AA1 3 IO_L92P_3 AB1 3 IO_L91N_3 Y5 3 IO_L91P_3 AA5 3 IO_L84N_3 AB10 3 IO_L84P_3 AA10 3 IO_L83N_3 AA2 3 IO_L83P_3 AB2 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 165 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 3 IO_L82N_3 AA4 3 IO_L82P_3 AB4 3 IO_L81N_3/VREF_3 AB11 3 IO_L81P_3 AA11 3 IO_L80N_3 AC1 3 IO_L80P_3 AD1 3 IO_L79N_3 AA7 3 IO_L79P_3 AB7 3 IO_L78N_3 AB12 3 IO_L78P_3 AA12 3 IO_L77N_3 AC2 3 IO_L77P_3 AC3 3 IO_L76N_3 AB5 3 IO_L76P_3 AC5 3 IO_L75N_3/VREF_3 AD9 3 IO_L75P_3 AC9 3 IO_L74N_3 AD2 3 IO_L74P_3 AE2 3 IO_L73N_3 AB6 3 IO_L73P_3 AC6 3 IO_L72N_3 AD10 3 IO_L72P_3 AC10 3 IO_L71N_3 AD3 3 IO_L71P_3 AE3 3 IO_L70N_3 AC7 3 IO_L70P_3 AD7 3 IO_L69N_3/VREF_3 AE8 3 IO_L69P_3 AD8 3 IO_L68N_3 AE1 3 IO_L68P_3 AF1 3 IO_L67N_3 AD4 3 IO_L67P_3 AE4 3 IO_L60N_3 AD12 3 IO_L60P_3 AC12 3 IO_L59N_3 AF3 3 IO_L59P_3 AG3 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 166 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 3 IO_L58N_3 AD5 3 IO_L58P_3 AE5 3 IO_L57N_3/VREF_3 AE11 3 IO_L57P_3 AD11 3 IO_L56N_3 AG1 3 IO_L56P_3 AH1 3 IO_L55N_3 AD6 3 IO_L55P_3 AE6 3 IO_L54N_3 AF10 3 IO_L54P_3 AE10 3 IO_L53N_3 AG2 3 IO_L53P_3 AH2 3 IO_L52N_3 AF4 3 IO_L52P_3 AG4 3 IO_L51N_3/VREF_3 AG8 3 IO_L51P_3 AF8 3 IO_L50N_3 AH3 3 IO_L50P_3 AJ3 3 IO_L49N_3 AE7 3 IO_L49P_3 AF7 3 IO_L48N_3 AG9 3 IO_L48P_3 AF9 3 IO_L47N_3 AF6 3 IO_L47P_3 AG6 3 IO_L46N_3 AG5 3 IO_L46P_3 AH5 3 IO_L45N_3/VREF_3 AF12 3 IO_L45P_3 AE12 3 IO_L44N_3 AJ1 3 IO_L44P_3 AK1 3 IO_L43N_3 AH4 3 IO_L43P_3 AJ4 3 IO_L36N_3 AG11 NC 3 IO_L36P_3 AF11 NC 3 IO_L35N_3 AK2 NC 3 IO_L35P_3 AL2 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 167 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 3 IO_L34N_3 AH6 NC 3 IO_L34P_3 AJ6 NC 3 IO_L33N_3/VREF_3 AJ8 NC 3 IO_L33P_3 AH8 NC 3 IO_L32N_3 AL1 NC 3 IO_L32P_3 AM1 NC 3 IO_L31N_3 AH7 NC 3 IO_L31P_3 AJ7 NC 3 IO_L30N_3 AH10 3 IO_L30P_3 AG10 3 IO_L29N_3 AK3 3 IO_L29P_3 AL3 3 IO_L28N_3 AK4 3 IO_L28P_3 AL4 3 IO_L27N_3/VREF_3 AJ9 3 IO_L27P_3 AH9 3 IO_L26N_3 AM2 3 IO_L26P_3 AN2 3 IO_L25N_3 AK5 3 IO_L25P_3 AL5 3 IO_L24N_3 AK9 3 IO_L24P_3 AK8 3 IO_L23N_3 AN1 3 IO_L23P_3 AP1 3 IO_L22N_3 AK6 3 IO_L22P_3 AL6 3 IO_L21N_3/VREF_3 AH12 3 IO_L21P_3 AG12 3 IO_L20N_3 AM3 3 IO_L20P_3 AN3 3 IO_L19N_3 AM4 3 IO_L19P_3 AN4 3 IO_L12N_3 AJ12 NC 3 IO_L12P_3 AH11 NC 3 IO_L11N_3 AP2 NC 3 IO_L11P_3 AR2 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 168 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 3 IO_L10N_3 AK7 NC 3 IO_L10P_3 AL7 NC 3 IO_L09N_3/VREF_3 AK11 NC 3 IO_L09P_3 AJ10 NC 3 IO_L08N_3 AR1 NC 3 IO_L08P_3 AT1 NC 3 IO_L07N_3 AM5 NC 3 IO_L07P_3 AN5 NC 3 IO_L06N_3 AM7 3 IO_L06P_3 AL8 3 IO_L05N_3 AP3 3 IO_L05P_3 AP4 3 IO_L04N_3 AM6 3 IO_L04P_3 AN6 3 IO_L03N_3/VREF_3 AJ13 3 IO_L03P_3 AH13 3 IO_L02N_3/VRP_3 AR3 3 IO_L02P_3/VRN_3 AT2 3 IO_L01N_3 AP5 3 IO_L01P_3 AR4 (1) 4 IO_L01N_4/BUSY/DOUT AV4 4 IO_L01P_4/INIT_B AU4 (1) 4 IO_L02N_4/D0/DIN AM9 4 IO_L02P_4/D1 AM10 4 IO_L03N_4/D2/ALT_VRP_4 AT6 4 IO_L03P_4/D3/ALT_VRN_4 AR6 4 IO_L04N_4/VREF_4 AU6 4 IO_L04P_4 AU5 4 IO_L05N_4/VRP_4 AL10 4 IO_L05P_4/VRN_4 AL11 4 IO_L06N_4 AR8 4 IO_L06P_4 AR7 4 IO_L07N_4 AW5 NC 4 IO_L07P_4 AW4 NC 4 IO_L08N_4 AK12 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 169 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 4 IO_L08P_4 AL12 NC 4 IO_L09N_4 AP9 NC 4 IO_L09P_4/VREF_4 AP8 NC 4 IO_L10N_4 AV6 NC 4 IO_L10P_4 AV5 NC 4 IO_L11N_4 AM11 NC 4 IO_L11P_4 AM12 NC 4 IO_L12N_4 AN10 NC 4 IO_L12P_4 AN9 NC 4 IO_L19N_4 AU8 4 IO_L19P_4 AU7 4 IO_L20N_4 AH14 4 IO_L20P_4 AH15 4 IO_L21N_4 AT8 4 IO_L21P_4/VREF_4 AT7 4 IO_L22N_4 AW7 4 IO_L22P_4 AW6 4 IO_L23N_4 AK13 4 IO_L23P_4 AK14 4 IO_L24N_4 AR10 4 IO_L24P_4 AR9 4 IO_L25N_4 AV8 4 IO_L25P_4 AV7 4 IO_L26N_4 AJ14 4 IO_L26P_4 AJ15 4 IO_L27N_4 AP11 4 IO_L27P_4/VREF_4 AP10 4 IO_L28N_4 AU10 4 IO_L28P_4 AU9 4 IO_L29N_4 AL13 4 IO_L29P_4 AL14 4 IO_L30N_4 AN12 4 IO_L30P_4 AN11 4 IO_L31N_4 AW9 NC 4 IO_L31P_4 AW8 NC 4 IO_L32N_4 AM13 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 170 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 4 IO_L32P_4 AM14 NC 4 IO_L33N_4 AT10 NC 4 IO_L33P_4/VREF_4 AT9 NC 4 IO_L34N_4 AV10 NC 4 IO_L34P_4 AV9 NC 4 IO_L35N_4 AH16 NC 4 IO_L35P_4 AH17 NC 4 IO_L36N_4 AP13 NC 4 IO_L36P_4 AP12 NC 4 IO_L49N_4 AU12 4 IO_L49P_4 AU11 4 IO_L50N_4 AK15 4 IO_L50P_4 AJ16 4 IO_L51N_4 AT12 4 IO_L51P_4/VREF_4 AT11 4 IO_L52N_4 AN15 4 IO_L52P_4 AN14 4 IO_L53N_4 AR12 4 IO_L53P_4 AR13 4 IO_L54N_4 AT14 4 IO_L54P_4 AT13 4 IO_L55N_4 AW11 4 IO_L55P_4 AW10 4 IO_L56N_4 AM15 4 IO_L56P_4 AM16 4 IO_L57N_4 AP15 4 IO_L57P_4/VREF_4 AP14 4 IO_L58N_4 AV13 4 IO_L58P_4 AV12 4 IO_L59N_4 AK16 4 IO_L59P_4 AK17 4 IO_L60N_4 AR16 4 IO_L60P_4 AR15 4 IO_L67N_4 AW13 4 IO_L67P_4 AW12 4 IO_L68N_4 AL16 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 171 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 4 IO_L68P_4 AL17 4 IO_L69N_4 AT16 4 IO_L69P_4/VREF_4 AT15 4 IO_L70N_4 AU14 4 IO_L70P_4 AU13 4 IO_L71N_4 AH18 4 IO_L71P_4 AH19 4 IO_L72N_4 AN17 4 IO_L72P_4 AN16 4 IO_L73N_4 AW15 4 IO_L73P_4 AW14 4 IO_L74N_4 AJ18 4 IO_L74P_4 AJ19 4 IO_L75N_4 AP17 4 IO_L75P_4/VREF_4 AP16 4 IO_L76N_4 AV15 4 IO_L76P_4 AU15 4 IO_L77N_4 AK18 4 IO_L77P_4 AK19 4 IO_L78N_4 AR18 4 IO_L78P_4 AR17 4 IO_L79N_4 AU17 4 IO_L79P_4 AU16 4 IO_L80N_4 AL18 4 IO_L80P_4 AL19 4 IO_L81N_4 AN19 4 IO_L81P_4/VREF_4 AN18 4 IO_L82N_4 AV17 4 IO_L82P_4 AV16 4 IO_L83N_4 AM18 4 IO_L83P_4 AM19 4 IO_L84N_4 AP19 4 IO_L84P_4 AP18 4 IO_L85N_4 AW17 NC NC 4 IO_L85P_4 AW16 NC NC 4 IO_L91N_4/VREF_4 AV19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 172 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 4 IO_L91P_4 AV18 4 IO_L92N_4 AH20 4 IO_L92P_4 AJ20 4 IO_L93N_4 AR19 4 IO_L93P_4 AT18 4 IO_L94N_4/VREF_4 AW19 4 IO_L94P_4 AW18 4 IO_L95N_4/GCLK3S AL20 4 IO_L95P_4/GCLK2P AM20 4 IO_L96N_4/GCLK1S AU19 4 IO_L96P_4/GCLK0P AT19 5 IO_L96N_5/GCLK7S AP21 5 IO_L96P_5/GCLK6P AP20 5 IO_L95N_5/GCLK5S AN21 5 IO_L95P_5/GCLK4P AN22 5 IO_L94N_5 AU21 5 IO_L94P_5/VREF_5 AU20 5 IO_L93N_5 AR21 5 IO_L93P_5 AR20 5 IO_L92N_5 AM21 5 IO_L92P_5 AM22 5 IO_L91N_5 AW22 5 IO_L91P_5/VREF_5 AW21 5 IO_L85N_5 AV22 NC NC 5 IO_L85P_5 AV21 NC NC 5 IO_L84N_5 AT22 5 IO_L84P_5 AT21 5 IO_L83N_5 AL21 5 IO_L83P_5 AL22 5 IO_L82N_5 AW24 5 IO_L82P_5 AW23 5 IO_L81N_5/VREF_5 AR23 5 IO_L81P_5 AR22 5 IO_L80N_5 AK21 5 IO_L80P_5 AK22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 173 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 5 IO_L79N_5 AV24 5 IO_L79P_5 AV23 5 IO_L78N_5 AP23 5 IO_L78P_5 AP22 5 IO_L77N_5 AJ21 5 IO_L77P_5 AJ22 5 IO_L76N_5 AU24 5 IO_L76P_5 AU23 5 IO_L75N_5/VREF_5 AT25 5 IO_L75P_5 AT24 5 IO_L74N_5 AH21 5 IO_L74P_5 AH22 5 IO_L73N_5 AW26 5 IO_L73P_5 AW25 5 IO_L72N_5 AR25 5 IO_L72P_5 AR24 5 IO_L71N_5 AN23 5 IO_L71P_5 AN24 5 IO_L70N_5 AU25 5 IO_L70P_5 AV25 5 IO_L69N_5/VREF_5 AL24 5 IO_L69P_5 AL23 5 IO_L68N_5 AK23 5 IO_L68P_5 AK24 5 IO_L67N_5 AU27 5 IO_L67P_5 AU26 5 IO_L60N_5 AP25 5 IO_L60P_5 AP24 5 IO_L59N_5 AM24 5 IO_L59P_5 AM25 5 IO_L58N_5 AW28 5 IO_L58P_5 AW27 5 IO_L57N_5/VREF_5 AT27 5 IO_L57P_5 AT26 5 IO_L56N_5 AH23 5 IO_L56P_5 AH24 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 174 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 5 IO_L55N_5 AV28 5 IO_L55P_5 AV27 5 IO_L54N_5 AP27 5 IO_L54P_5 AP26 5 IO_L53N_5 AN25 5 IO_L53P_5 AN26 5 IO_L52N_5 AU29 5 IO_L52P_5 AU28 5 IO_L51N_5/VREF_5 AR28 5 IO_L51P_5 AR27 5 IO_L50N_5 AJ24 5 IO_L50P_5 AJ25 5 IO_L49N_5 AW30 5 IO_L49P_5 AW29 5 IO_L36N_5 AT29 NC 5 IO_L36P_5 AT28 NC 5 IO_L35N_5 AK25 NC 5 IO_L35P_5 AL26 NC 5 IO_L34N_5 AV31 NC 5 IO_L34P_5 AV30 NC 5 IO_L33N_5/VREF_5 AP29 NC 5 IO_L33P_5 AP28 NC 5 IO_L32N_5 AK26 NC 5 IO_L32P_5 AJ26 NC 5 IO_L31N_5 AW32 NC 5 IO_L31P_5 AW31 NC 5 IO_L30N_5 AM27 5 IO_L30P_5 AM26 5 IO_L29N_5 AN28 5 IO_L29P_5 AN29 5 IO_L28N_5 AU31 5 IO_L28P_5 AU30 5 IO_L27N_5/VREF_5 AT31 5 IO_L27P_5 AT30 5 IO_L26N_5 AH25 5 IO_L26P_5 AH26 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 175 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 5 IO_L25N_5 AV33 5 IO_L25P_5 AV32 5 IO_L24N_5 AR31 5 IO_L24P_5 AR30 5 IO_L23N_5 AL27 5 IO_L23P_5 AL28 5 IO_L22N_5 AW34 5 IO_L22P_5 AW33 5 IO_L21N_5/VREF_5 AN30 5 IO_L21P_5 AP30 5 IO_L20N_5 AM28 5 IO_L20P_5 AM29 5 IO_L19N_5 AU33 5 IO_L19P_5 AU32 5 IO_L12N_5 AT33 NC 5 IO_L12P_5 AT32 NC 5 IO_L11N_5 AK27 NC 5 IO_L11P_5 AK28 NC 5 IO_L10N_5 AV35 NC 5 IO_L10P_5 AV34 NC 5 IO_L09N_5/VREF_5 AP32 NC 5 IO_L09P_5 AP31 NC 5 IO_L08N_5 AL29 NC 5 IO_L08P_5 AK29 NC 5 IO_L07N_5 AW36 NC 5 IO_L07P_5 AW35 NC 5 IO_L06N_5 AR33 5 IO_L06P_5 AR32 5 IO_L05N_5/VRP_5 AM30 5 IO_L05P_5/VRN_5 AL30 5 IO_L04N_5 AU35 5 IO_L04P_5/VREF_5 AU34 5 IO_L03N_5/D4/ALT_VRP_5 AR34 5 IO_L03P_5/D5/ALT_VRN_5 AT34 5 IO_L02N_5/D6 AN31 5 IO_L02P_5/D7 AM31 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 176 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 5 IO_L01N_5/RDWR_B AU36 5 IO_L01P_5/CS_B AV36 6 IO_L01P_6 AJ27 6 IO_L01N_6 AH27 6 IO_L02P_6/VRN_6 AT38 6 IO_L02N_6/VRP_6 AR37 6 IO_L03P_6 AP36 6 IO_L03N_6/VREF_6 AR36 6 IO_L04P_6 AJ28 6 IO_L04N_6 AH29 6 IO_L05P_6 AT39 6 IO_L05N_6 AR39 6 IO_L06P_6 AN34 6 IO_L06N_6 AP35 6 IO_L07P_6 AH28 NC 6 IO_L07N_6 AG28 NC 6 IO_L08P_6 AR38 NC 6 IO_L08N_6 AP38 NC 6 IO_L09P_6 AM34 NC 6 IO_L09N_6/VREF_6 AM33 NC 6 IO_L10P_6 AL32 NC 6 IO_L10N_6 AK32 NC 6 IO_L11P_6 AP37 NC 6 IO_L11N_6 AN37 NC 6 IO_L12P_6 AM35 NC 6 IO_L12N_6 AN35 NC 6 IO_L19P_6 AK31 6 IO_L19N_6 AJ30 6 IO_L20P_6 AP39 6 IO_L20N_6 AN39 6 IO_L21P_6 AK33 6 IO_L21N_6/VREF_6 AL33 6 IO_L22P_6 AJ31 6 IO_L22N_6 AH31 6 IO_L23P_6 AN38 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 177 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 6 IO_L23N_6 AM38 6 IO_L24P_6 AM36 6 IO_L24N_6 AN36 6 IO_L25P_6 AH30 6 IO_L25N_6 AG30 6 IO_L26P_6 AM37 6 IO_L26N_6 AL37 6 IO_L27P_6 AK34 6 IO_L27N_6/VREF_6 AL34 6 IO_L28P_6 AG29 6 IO_L28N_6 AF29 6 IO_L29P_6 AL35 6 IO_L29N_6 AK35 6 IO_L30P_6 AH33 6 IO_L30N_6 AJ33 6 IO_L31P_6 AJ32 NC 6 IO_L31N_6 AH32 NC 6 IO_L32P_6 AM39 NC 6 IO_L32N_6 AL39 NC 6 IO_L33P_6 AK36 NC 6 IO_L33N_6/VREF_6 AL36 NC 6 IO_L34P_6 AF28 NC 6 IO_L34N_6 AE28 NC 6 IO_L35P_6 AL38 NC 6 IO_L35N_6 AK38 NC 6 IO_L36P_6 AH34 NC 6 IO_L36N_6 AJ34 NC 6 IO_L43P_6 AG31 6 IO_L43N_6 AF31 6 IO_L44P_6 AK37 6 IO_L44N_6 AJ37 6 IO_L45P_6 AH36 6 IO_L45N_6/VREF_6 AJ36 6 IO_L46P_6 AF30 6 IO_L46N_6 AE30 6 IO_L47P_6 AK39 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 178 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 6 IO_L47N_6 AJ39 6 IO_L48P_6 AG35 6 IO_L48N_6 AH35 6 IO_L49P_6 AG32 6 IO_L49N_6 AF32 6 IO_L50P_6 AH37 6 IO_L50N_6 AG37 6 IO_L51P_6 AD29 6 IO_L51N_6/VREF_6 AE29 6 IO_L52P_6 AD28 6 IO_L52N_6 AC28 6 IO_L53P_6 AH38 6 IO_L53N_6 AG38 6 IO_L54P_6 AF34 6 IO_L54N_6 AG34 6 IO_L55P_6 AE32 6 IO_L55N_6 AD32 6 IO_L56P_6 AH39 6 IO_L56N_6 AG39 6 IO_L57P_6 AE33 6 IO_L57N_6/VREF_6 AF33 6 IO_L58P_6 AD30 6 IO_L58N_6 AC30 6 IO_L59P_6 AF37 6 IO_L59N_6 AE37 6 IO_L60P_6 AF36 6 IO_L60N_6 AG36 6 IO_L67P_6 AD31 6 IO_L67N_6 AC31 6 IO_L68P_6 AE34 6 IO_L68N_6 AD34 6 IO_L69P_6 AD35 6 IO_L69N_6/VREF_6 AE35 6 IO_L70P_6 AB28 6 IO_L70N_6 AA28 6 IO_L71P_6 AF39 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 179 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 6 IO_L71N_6 AE39 6 IO_L72P_6 AD36 6 IO_L72N_6 AE36 6 IO_L73P_6 AB29 6 IO_L73N_6 AA29 6 IO_L74P_6 AE38 6 IO_L74N_6 AD38 6 IO_L75P_6 AC33 6 IO_L75N_6/VREF_6 AD33 6 IO_L76P_6 AB30 6 IO_L76N_6 AA30 6 IO_L77P_6 AD37 6 IO_L77N_6 AC37 6 IO_L78P_6 AB34 6 IO_L78N_6 AC34 6 IO_L79P_6 AB31 6 IO_L79N_6 AA31 6 IO_L80P_6 AD39 6 IO_L80N_6 AC39 6 IO_L81P_6 AB35 6 IO_L81N_6/VREF_6 AC35 6 IO_L82P_6 AB32 6 IO_L82N_6 AA32 6 IO_L83P_6 AC38 6 IO_L83N_6 AB38 6 IO_L84P_6 AA33 6 IO_L84N_6 AB33 6 IO_L91P_6 Y28 6 IO_L91N_6 Y29 6 IO_L92P_6 AB39 6 IO_L92N_6 AA39 6 IO_L93P_6 AA36 6 IO_L93N_6/VREF_6 AB36 6 IO_L94P_6 Y31 6 IO_L94N_6 Y32 6 IO_L95P_6 AA37 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 180 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 6 IO_L95N_6 AA38 6 IO_L96P_6 AA35 6 IO_L96N_6 AA34 7 IO_L96P_7 W34 7 IO_L96N_7 Y34 7 IO_L95P_7 W32 7 IO_L95N_7 V32 7 IO_L94P_7 W37 7 IO_L94N_7 Y37 7 IO_L93P_7/VREF_7 W35 7 IO_L93N_7 Y35 7 IO_L92P_7 W31 7 IO_L92N_7 V31 7 IO_L91P_7 V39 7 IO_L91N_7 W39 7 IO_L84P_7 V36 7 IO_L84N_7 W36 7 IO_L83P_7 W30 7 IO_L83N_7 V30 7 IO_L82P_7 V38 7 IO_L82N_7 W38 7 IO_L81P_7/VREF_7 V33 7 IO_L81N_7 W33 7 IO_L80P_7 W29 7 IO_L80N_7 V29 7 IO_L79P_7 T39 7 IO_L79N_7 U39 7 IO_L78P_7 U35 7 IO_L78N_7 V35 7 IO_L77P_7 W28 7 IO_L77N_7 V28 7 IO_L76P_7 U37 7 IO_L76N_7 U38 7 IO_L75P_7/VREF_7 U34 7 IO_L75N_7 V34 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 181 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 7 IO_L74P_7 U31 7 IO_L74N_7 T31 7 IO_L73P_7 R38 7 IO_L73N_7 T38 7 IO_L72P_7 T33 7 IO_L72N_7 U33 7 IO_L71P_7 U30 7 IO_L71N_7 T30 7 IO_L70P_7 R37 7 IO_L70N_7 T37 7 IO_L69P_7/VREF_7 R36 7 IO_L69N_7 T36 7 IO_L68P_7 T32 7 IO_L68N_7 R32 7 IO_L67P_7 P39 7 IO_L67N_7 R39 7 IO_L60P_7 R35 7 IO_L60N_7 T35 7 IO_L59P_7 U28 7 IO_L59N_7 T28 7 IO_L58P_7 N37 7 IO_L58N_7 P37 7 IO_L57P_7/VREF_7 R34 7 IO_L57N_7 T34 7 IO_L56P_7 T29 7 IO_L56N_7 R29 7 IO_L55P_7 M39 7 IO_L55N_7 N39 7 IO_L54P_7 N36 7 IO_L54N_7 P36 7 IO_L53P_7 R30 7 IO_L53N_7 P30 7 IO_L52P_7 M38 7 IO_L52N_7 N38 7 IO_L51P_7/VREF_7 P33 7 IO_L51N_7 R33 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 182 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 7 IO_L50P_7 P32 7 IO_L50N_7 N32 7 IO_L49P_7 L37 7 IO_L49N_7 M37 7 IO_L48P_7 N34 7 IO_L48N_7 P34 7 IO_L47P_7 P31 7 IO_L47N_7 N31 7 IO_L46P_7 M35 7 IO_L46N_7 N35 7 IO_L45P_7/VREF_7 L36 7 IO_L45N_7 M36 7 IO_L44P_7 R28 7 IO_L44N_7 P28 7 IO_L43P_7 K39 7 IO_L43N_7 L39 7 IO_L36P_7 L34 NC 7 IO_L36N_7 M34 NC 7 IO_L35P_7 P29 NC 7 IO_L35N_7 N29 NC 7 IO_L34P_7 J38 NC 7 IO_L34N_7 K38 NC 7 IO_L33P_7/VREF_7 L33 NC 7 IO_L33N_7 M33 NC 7 IO_L32P_7 M32 NC 7 IO_L32N_7 L32 NC 7 IO_L31P_7 H39 NC 7 IO_L31N_7 J39 NC 7 IO_L30P_7 J36 7 IO_L30N_7 K36 7 IO_L29P_7 N30 7 IO_L29N_7 M30 7 IO_L28P_7 J37 7 IO_L28N_7 K37 7 IO_L27P_7/VREF_7 J35 7 IO_L27N_7 K35 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 183 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 7 IO_L26P_7 M31 7 IO_L26N_7 L31 7 IO_L25P_7 G38 7 IO_L25N_7 H38 7 IO_L24P_7 J34 7 IO_L24N_7 K34 7 IO_L23P_7 K32 7 IO_L23N_7 K31 7 IO_L22P_7 F39 7 IO_L22N_7 G39 7 IO_L21P_7/VREF_7 G36 7 IO_L21N_7 H36 7 IO_L20P_7 N28 7 IO_L20N_7 M28 7 IO_L19P_7 G37 7 IO_L19N_7 H37 7 IO_L12P_7 J33 NC 7 IO_L12N_7 K33 NC 7 IO_L11P_7 M29 NC 7 IO_L11N_7 L28 NC 7 IO_L10P_7 E38 NC 7 IO_L10N_7 F38 NC 7 IO_L09P_7/VREF_7 G35 NC 7 IO_L09N_7 H35 NC 7 IO_L08P_7 L30 NC 7 IO_L08N_7 K29 NC 7 IO_L07P_7 D39 NC 7 IO_L07N_7 E39 NC 7 IO_L06P_7 G34 7 IO_L06N_7 H34 7 IO_L05P_7 J32 7 IO_L05N_7 H33 7 IO_L04P_7 F36 7 IO_L04N_7 F37 7 IO_L03P_7/VREF_7 E36 7 IO_L03N_7 F35 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 184 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 7 IO_L02P_7/VRN_7 M27 7 IO_L02N_7/VRP_7 L27 7 IO_L01P_7 D38 7 IO_L01N_7 E37 0 VCCO_0 P25 0 VCCO_0 P24 0 VCCO_0 P23 0 VCCO_0 P22 0 VCCO_0 P21 0 VCCO_0 N26 0 VCCO_0 N25 0 VCCO_0 N24 0 VCCO_0 N23 0 VCCO_0 N22 0 VCCO_0 N21 0 VCCO_0 L23 0 VCCO_0 J25 0 VCCO_0 G27 0 VCCO_0 E29 0 VCCO_0 C22 0 VCCO_0 B26 1 VCCO_1 P19 1 VCCO_1 P18 1 VCCO_1 P17 1 VCCO_1 P16 1 VCCO_1 P15 1 VCCO_1 N19 1 VCCO_1 N18 1 VCCO_1 N17 1 VCCO_1 N16 1 VCCO_1 N15 1 VCCO_1 N14 1 VCCO_1 L17 1 VCCO_1 J15 1 VCCO_1 G13 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 185 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 1 VCCO_1 E11 1 VCCO_1 C18 1 VCCO_1 B14 2 VCCO_2 W14 2 VCCO_2 W13 2 VCCO_2 V14 2 VCCO_2 V13 2 VCCO_2 V3 2 VCCO_2 U14 2 VCCO_2 U13 2 VCCO_2 U11 2 VCCO_2 T14 2 VCCO_2 T13 2 VCCO_2 R14 2 VCCO_2 R13 2 VCCO_2 R9 2 VCCO_2 P13 2 VCCO_2 P2 2 VCCO_2 N7 2 VCCO_2 L5 3 VCCO_3 AJ5 3 VCCO_3 AG7 3 VCCO_3 AF13 3 VCCO_3 AF2 3 VCCO_3 AE14 3 VCCO_3 AE13 3 VCCO_3 AE9 3 VCCO_3 AD14 3 VCCO_3 AD13 3 VCCO_3 AC14 3 VCCO_3 AC13 3 VCCO_3 AC11 3 VCCO_3 AB14 3 VCCO_3 AB13 3 VCCO_3 AB3 3 VCCO_3 AA14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 186 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 3 VCCO_3 AA13 4 VCCO_4 AV14 4 VCCO_4 AU18 4 VCCO_4 AR11 4 VCCO_4 AN13 4 VCCO_4 AL15 4 VCCO_4 AJ17 4 VCCO_4 AG19 4 VCCO_4 AG18 4 VCCO_4 AG17 4 VCCO_4 AG16 4 VCCO_4 AG15 4 VCCO_4 AG14 4 VCCO_4 AF19 4 VCCO_4 AF18 4 VCCO_4 AF17 4 VCCO_4 AF16 4 VCCO_4 AF15 5 VCCO_5 AV26 5 VCCO_5 AU22 5 VCCO_5 AR29 5 VCCO_5 AN27 5 VCCO_5 AL25 5 VCCO_5 AJ23 5 VCCO_5 AG26 5 VCCO_5 AG25 5 VCCO_5 AG24 5 VCCO_5 AG23 5 VCCO_5 AG22 5 VCCO_5 AG21 5 VCCO_5 AF25 5 VCCO_5 AF24 5 VCCO_5 AF23 5 VCCO_5 AF22 5 VCCO_5 AF21 6 VCCO_6 AJ35 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 187 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 6 VCCO_6 AG33 6 VCCO_6 AF38 6 VCCO_6 AF27 6 VCCO_6 AE31 6 VCCO_6 AE27 6 VCCO_6 AE26 6 VCCO_6 AD27 6 VCCO_6 AD26 6 VCCO_6 AC29 6 VCCO_6 AC27 6 VCCO_6 AC26 6 VCCO_6 AB37 6 VCCO_6 AB27 6 VCCO_6 AB26 6 VCCO_6 AA27 6 VCCO_6 AA26 7 VCCO_7 W27 7 VCCO_7 W26 7 VCCO_7 V37 7 VCCO_7 V27 7 VCCO_7 V26 7 VCCO_7 U29 7 VCCO_7 U27 7 VCCO_7 U26 7 VCCO_7 T27 7 VCCO_7 T26 7 VCCO_7 R31 7 VCCO_7 R27 7 VCCO_7 R26 7 VCCO_7 P38 7 VCCO_7 P27 7 VCCO_7 N33 7 VCCO_7 L35 NA CCLK AT5 NA PROG_B H31 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 188 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA DONE AP7 NA M0 AN32 NA M1 AP33 NA M2 AT35 NA HSWAP_EN E34 NA TCK G8 NA TDI D35 NA TDO E6 NA TMS F7 NA PWRDWN_B AN8 NA DXN G32 NA DXP F33 NA VBATT D5 NA RSVD H9 NA VCCAUX AV20 NA VCCAUX AT37 NA VCCAUX AT3 NA VCCAUX Y38 NA VCCAUX Y2 NA VCCAUX D37 NA VCCAUX D3 NA VCCAUX B20 NA VCCINT AG27 NA VCCINT AG20 NA VCCINT AG13 NA VCCINT AF26 NA VCCINT AF20 NA VCCINT AF14 NA VCCINT AE25 NA VCCINT AE24 NA VCCINT AE23 NA VCCINT AE22 NA VCCINT AE21 NA VCCINT AE20 NA VCCINT AE19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 189 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA VCCINT AE18 NA VCCINT AE17 NA VCCINT AE16 NA VCCINT AE15 NA VCCINT AD25 NA VCCINT AD24 NA VCCINT AD16 NA VCCINT AD15 NA VCCINT AC25 NA VCCINT AC15 NA VCCINT AB25 NA VCCINT AB15 NA VCCINT AA25 NA VCCINT AA15 NA VCCINT Y27 NA VCCINT Y26 NA VCCINT Y25 NA VCCINT Y15 NA VCCINT Y14 NA VCCINT Y13 NA VCCINT W25 NA VCCINT W15 NA VCCINT V25 NA VCCINT V15 NA VCCINT U25 NA VCCINT U15 NA VCCINT T25 NA VCCINT T24 NA VCCINT T16 NA VCCINT T15 NA VCCINT R25 NA VCCINT R24 NA VCCINT R23 NA VCCINT R22 NA VCCINT R21 NA VCCINT R20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 190 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA VCCINT R19 NA VCCINT R18 NA VCCINT R17 NA VCCINT R16 NA VCCINT R15 NA VCCINT P26 NA VCCINT P20 NA VCCINT P14 NA VCCINT N27 NA VCCINT N20 NA VCCINT N13 NA GND AW38 NA GND AW37 NA GND AW20 NA GND AW3 NA GND AW2 NA GND AV39 NA GND AV38 NA GND AV37 NA GND AV29 NA GND AV11 NA GND AV3 NA GND AV2 NA GND AV1 NA GND AU39 NA GND AU38 NA GND AU37 NA GND AU3 NA GND AU2 NA GND AU1 NA GND AT36 NA GND AT23 NA GND AT20 NA GND AT17 NA GND AT4 NA GND AR35 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 191 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA GND AR26 NA GND AR14 NA GND AR5 NA GND AP34 NA GND AP6 NA GND AN33 NA GND AN20 NA GND AN7 NA GND AM32 NA GND AM23 NA GND AM17 NA GND AM8 NA GND AL31 NA GND AL9 NA GND AK30 NA GND AK20 NA GND AK10 NA GND AJ38 NA GND AJ29 NA GND AJ11 NA GND AJ2 NA GND AF35 NA GND AF5 NA GND AD23 NA GND AD22 NA GND AD21 NA GND AD20 NA GND AD19 NA GND AD18 NA GND AD17 NA GND AC36 NA GND AC32 NA GND AC24 NA GND AC23 NA GND AC22 NA GND AC21 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 192 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA GND AC20 NA GND AC19 NA GND AC18 NA GND AC17 NA GND AC16 NA GND AC8 NA GND AC4 NA GND AB24 NA GND AB23 NA GND AB22 NA GND AB21 NA GND AB20 NA GND AB19 NA GND AB18 NA GND AB17 NA GND AB16 NA GND AA24 NA GND AA23 NA GND AA22 NA GND AA21 NA GND AA20 NA GND AA19 NA GND AA18 NA GND AA17 NA GND AA16 NA GND Y39 NA GND Y36 NA GND Y33 NA GND Y30 NA GND Y24 NA GND Y23 NA GND Y22 NA GND Y21 NA GND Y20 NA GND Y19 NA GND Y18 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 193 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA GND Y17 NA GND Y16 NA GND Y10 NA GND Y7 NA GND Y4 NA GND Y1 NA GND W24 NA GND W23 NA GND W22 NA GND W21 NA GND W20 NA GND W19 NA GND W18 NA GND W17 NA GND W16 NA GND V24 NA GND V23 NA GND V22 NA GND V21 NA GND V20 NA GND V19 NA GND V18 NA GND V17 NA GND V16 NA GND U36 NA GND U32 NA GND U24 NA GND U23 NA GND U22 NA GND U21 NA GND U20 NA GND U19 NA GND U18 NA GND U17 NA GND U16 NA GND U8 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 194 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA GND U4 NA GND T23 NA GND T22 NA GND T21 NA GND T20 NA GND T19 NA GND T18 NA GND T17 NA GND P35 NA GND P5 NA GND L38 NA GND L29 NA GND L11 NA GND L2 NA GND K30 NA GND K20 NA GND K10 NA GND J31 NA GND J9 NA GND H32 NA GND H23 NA GND H17 NA GND H8 NA GND G33 NA GND G20 NA GND G7 NA GND F34 NA GND F6 NA GND E35 NA GND E26 NA GND E14 NA GND E5 NA GND D36 NA GND D23 NA GND D20 NA GND D17 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 195 R Virtex-II Platform FPGAs: Pinout Information Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000 Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000 NA GND D4 NA GND C39 NA GND C38 NA GND C37 NA GND C3 NA GND C2 NA GND C1 NA GND B39 NA GND B38 NA GND B37 NA GND B29 NA GND B11 NA GND B3 NA GND B2 NA GND B1 NA GND A38 NA GND A37 NA GND A20 NA GND A3 NA GND A2 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 196 R Virtex-II Platform FPGAs: Pinout Information FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 9: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 197 R Virtex-II Platform FPGAs: Pinout Information BF957 Flip-Chip BGA Package As shown in Table 14, XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Virtex-II devices are available in the BF957 package. Pins in each of these devices are the same, except for the pin differences in the XC2V2000 device shown in the No Connect column. Following this table are the BF957 Flip-Chip BGA Package Specifications (1.27mm pitch). Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 0 IO_L01N_0 H23 0 IO_L01P_0 H22 0 IO_L02N_0 G24 0 IO_L02P_0 E25 0 IO_L03N_0/VRP_0 B29 0 IO_L03P_0/VRN_0 C27 0 IO_L04N_0/VREF_0 F24 0 IO_L04P_0 F23 0 IO_L05N_0 D26 0 IO_L05P_0 D25 0 IO_L06N_0 A28 0 IO_L06P_0 A27 0 IO_L19N_0 J22 0 IO_L19P_0 J21 0 IO_L20N_0 G23 0 IO_L20P_0 G22 0 IO_L21N_0 B27 0 IO_L21P_0/VREF_0 B26 0 IO_L22N_0 K20 0 IO_L22P_0 K19 0 IO_L23N_0 C26 0 IO_L23P_0 C24 0 IO_L24N_0 D24 0 IO_L24P_0 D23 0 IO_L25N_0 E24 NC 0 IO_L25P_0 E23 NC 0 IO_L26N_0 G21 NC 0 IO_L26P_0 G20 NC 0 IO_L27N_0 A26 NC 0 IO_L27P_0/VREF_0 A25 NC 0 IO_L29N_0 H21 NC 0 IO_L29P_0 H20 NC 0 IO_L30N_0 B25 NC 0 IO_L30P_0 B23 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 198 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 0 IO_L49N_0 C23 0 IO_L49P_0 C22 0 IO_L50N_0 E22 0 IO_L50P_0 E21 0 IO_L51N_0 F21 0 IO_L51P_0/VREF_0 F20 0 IO_L52N_0 A24 0 IO_L52P_0 A23 0 IO_L53N_0 E20 0 IO_L53P_0 E19 0 IO_L54N_0 B22 0 IO_L54P_0 B21 0 IO_L67N_0 D21 0 IO_L67P_0 D20 0 IO_L68N_0 J20 0 IO_L68P_0 J19 0 IO_L69N_0 F19 0 IO_L69P_0/VREF_0 F18 0 IO_L70N_0 A22 0 IO_L70P_0 A21 0 IO_L71N_0 H19 0 IO_L71P_0 H17 0 IO_L72N_0 C21 0 IO_L72P_0 C20 0 IO_L73N_0 B20 0 IO_L73P_0 B19 0 IO_L74N_0 G18 0 IO_L74P_0 G17 0 IO_L75N_0 E18 0 IO_L75P_0/VREF_0 D17 0 IO_L76N_0 A20 0 IO_L76P_0 A19 0 IO_L77N_0 D19 0 IO_L77P_0 D18 0 IO_L78N_0 C19 0 IO_L78P_0 C17 0 IO_L91N_0/VREF_0 K18 0 IO_L91P_0 J18 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 199 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 0 IO_L92N_0 F17 0 IO_L92P_0 F16 0 IO_L93N_0 B18 0 IO_L93P_0 B17 0 IO_L94N_0/VREF_0 J17 0 IO_L94P_0 J16 0 IO_L95N_0/GCLK7P E17 0 IO_L95P_0/GCLK6S E16 0 IO_L96N_0/GCLK5P A18 0 IO_L96P_0/GCLK4S A17 1 IO_L96N_1/GCLK3P C16 1 IO_L96P_1/GCLK2S C15 1 IO_L95N_1/GCLK1P H16 1 IO_L95P_1/GCLK0S H15 1 IO_L94N_1 A15 1 IO_L94P_1/VREF_1 A14 1 IO_L93N_1 F15 1 IO_L93P_1 F14 1 IO_L92N_1 G15 1 IO_L92P_1 G14 1 IO_L91N_1 B15 1 IO_L91P_1/VREF_1 B14 1 IO_L78N_1 D15 1 IO_L78P_1 E15 1 IO_L77N_1 J15 1 IO_L77P_1 K14 1 IO_L76N_1 D14 1 IO_L76P_1 D13 1 IO_L75N_1/VREF_1 E14 1 IO_L75P_1 E13 1 IO_L74N_1 A13 1 IO_L74P_1 A12 1 IO_L73N_1 F13 1 IO_L73P_1 F12 1 IO_L72N_1 J14 1 IO_L72P_1 J13 1 IO_L71N_1 B13 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 200 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 1 IO_L71P_1 B12 1 IO_L70N_1 C13 1 IO_L70P_1 C12 1 IO_L69N_1/VREF_1 H13 1 IO_L69P_1 H12 1 IO_L68N_1 D12 1 IO_L68P_1 D11 1 IO_L67N_1 B11 1 IO_L67P_1 B10 1 IO_L54N_1 E12 1 IO_L54P_1 E11 1 IO_L53N_1 A11 1 IO_L53P_1 A10 1 IO_L52N_1 G12 1 IO_L52P_1 G11 1 IO_L51N_1/VREF_1 K13 1 IO_L51P_1 K12 1 IO_L50N_1 C11 1 IO_L50P_1 C10 1 IO_L49N_1 B9 1 IO_L49P_1 B7 1 IO_L30N_1 F11 NC 1 IO_L30P_1 F9 NC 1 IO_L29N_1 A9 NC 1 IO_L29P_1 A8 NC 1 IO_L27N_1/VREF_1 D9 NC 1 IO_L27P_1 D8 NC 1 IO_L26N_1 J12 NC 1 IO_L26P_1 J11 NC 1 IO_L25N_1 C9 NC 1 IO_L25P_1 C8 NC 1 IO_L24N_1 E10 1 IO_L24P_1 E9 1 IO_L23N_1 H11 1 IO_L23P_1 H10 1 IO_L22N_1 A7 1 IO_L22P_1 A6 1 IO_L21N_1/VREF_1 A5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 201 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 1 IO_L21P_1 A4 1 IO_L20N_1 G10 1 IO_L20P_1 G9 1 IO_L19N_1 B6 1 IO_L19P_1 C5 1 IO_L06N_1 C6 1 IO_L06P_1 D6 1 IO_L05N_1 H9 1 IO_L05P_1 G8 1 IO_L04N_1 D7 1 IO_L04P_1/VREF_1 E6 1 IO_L03N_1/VRP_1 E8 1 IO_L03P_1/VRN_1 E7 1 IO_L02N_1 F8 1 IO_L02P_1 F7 1 IO_L01N_1 B5 1 IO_L01P_1 B3 2 IO_L01N_2 F5 2 IO_L01P_2 G4 2 IO_L02N_2/VRP_2 G6 2 IO_L02P_2/VRN_2 H6 2 IO_L03N_2 D3 2 IO_L03P_2/VREF_2 E4 2 IO_L04N_2 K10 2 IO_L04P_2 K9 2 IO_L05N_2 D2 2 IO_L05P_2 E3 2 IO_L06N_2 F4 2 IO_L06P_2 F3 2 IO_L19N_2 L10 2 IO_L19P_2 M10 2 IO_L20N_2 H7 2 IO_L20P_2 J8 2 IO_L21N_2 D1 2 IO_L21P_2/VREF_2 E1 2 IO_L22N_2 G5 2 IO_L22P_2 H5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 202 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 2 IO_L23N_2 E2 2 IO_L23P_2 F2 2 IO_L24N_2 H4 2 IO_L24P_2 J4 2 IO_L25N_2 K8 NC 2 IO_L25P_2 L8 NC 2 IO_L27N_2 J7 NC 2 IO_L27P_2/VREF_2 K7 NC 2 IO_L43N_2 F1 2 IO_L43P_2 G1 2 IO_L44N_2 L9 2 IO_L44P_2 M9 2 IO_L45N_2 G2 2 IO_L45P_2/VREF_2 J2 2 IO_L46N_2 H3 2 IO_L46P_2 J3 2 IO_L47N_2 J6 2 IO_L47P_2 L6 2 IO_L48N_2 J5 2 IO_L48P_2 K5 2 IO_L49N_2 H1 2 IO_L49P_2 J1 2 IO_L50N_2 N10 2 IO_L50P_2 P10 2 IO_L51N_2 L7 2 IO_L51P_2/VREF_2 M7 2 IO_L52N_2 K3 2 IO_L52P_2 L3 2 IO_L53N_2 M8 2 IO_L53P_2 N8 2 IO_L54N_2 L5 2 IO_L54P_2 M5 2 IO_L67N_2 K2 2 IO_L67P_2 L2 2 IO_L68N_2 M6 2 IO_L68P_2 N6 2 IO_L69N_2 L4 2 IO_L69P_2/VREF_2 M4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 203 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 2 IO_L70N_2 K1 2 IO_L70P_2 L1 2 IO_L71N_2 N9 2 IO_L71P_2 P9 2 IO_L72N_2 N5 2 IO_L72P_2 P5 2 IO_L73N_2 M3 2 IO_L73P_2 N3 2 IO_L74N_2 R8 2 IO_L74P_2 R9 2 IO_L75N_2 M2 2 IO_L75P_2/VREF_2 N2 2 IO_L76N_2 M1 2 IO_L76P_2 N1 2 IO_L77N_2 P7 2 IO_L77P_2 R7 2 IO_L78N_2 N4 2 IO_L78P_2 P4 2 IO_L91N_2 T8 2 IO_L91P_2 T9 2 IO_L92N_2 P6 2 IO_L92P_2 R6 2 IO_L93N_2 P2 2 IO_L93P_2/VREF_2 R2 2 IO_L94N_2 R5 2 IO_L94P_2 T5 2 IO_L95N_2 P1 2 IO_L95P_2 R1 2 IO_L96N_2 R4 2 IO_L96P_2 R3 3 IO_L96N_3 T6 3 IO_L96P_3 U5 3 IO_L95N_3 U6 3 IO_L95P_3 V6 3 IO_L94N_3 T3 3 IO_L94P_3 U3 3 IO_L93N_3/VREF_3 U1 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 204 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 3 IO_L93P_3 V1 3 IO_L92N_3 U8 3 IO_L92P_3 W8 3 IO_L91N_3 U2 3 IO_L91P_3 V2 3 IO_L78N_3 U7 3 IO_L78P_3 V7 3 IO_L77N_3 U4 3 IO_L77P_3 V4 3 IO_L76N_3 W1 3 IO_L76P_3 Y1 3 IO_L75N_3/VREF_3 V5 3 IO_L75P_3 W5 3 IO_L74N_3 W2 3 IO_L74P_3 Y2 3 IO_L73N_3 W6 3 IO_L73P_3 Y6 3 IO_L72N_3 Y5 3 IO_L72P_3 AA5 3 IO_L71N_3 W3 3 IO_L71P_3 Y3 3 IO_L70N_3 W4 3 IO_L70P_3 Y4 3 IO_L69N_3/VREF_3 U9 3 IO_L69P_3 V9 3 IO_L68N_3 AA1 3 IO_L68P_3 AB1 3 IO_L67N_3 Y7 3 IO_L67P_3 AA7 3 IO_L54N_3 AA6 3 IO_L54P_3 AC6 3 IO_L53N_3 AA2 3 IO_L53P_3 AB2 3 IO_L52N_3 AA4 3 IO_L52P_3 AC4 3 IO_L51N_3/VREF_3 V10 3 IO_L51P_3 W10 3 IO_L50N_3 AA3 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 205 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 3 IO_L50P_3 AB3 3 IO_L49N_3 AB5 3 IO_L49P_3 AC5 3 IO_L48N_3 W9 3 IO_L48P_3 Y9 3 IO_L47N_3 AC1 3 IO_L47P_3 AD1 3 IO_L46N_3 AC3 3 IO_L46P_3 AD3 3 IO_L45N_3/VREF_3 Y8 3 IO_L45P_3 AA8 3 IO_L44N_3 AC2 3 IO_L44P_3 AE2 3 IO_L43N_3 AB7 3 IO_L43P_3 AC7 3 IO_L27N_3/VREF_3 Y10 NC 3 IO_L27P_3 AA10 NC 3 IO_L25N_3 AE1 NC 3 IO_L25P_3 AF1 NC 3 IO_L24N_3 AF2 3 IO_L24P_3 AG2 3 IO_L23N_3 AA9 3 IO_L23P_3 AB9 3 IO_L22N_3 AD4 3 IO_L22P_3 AE4 3 IO_L21N_3/VREF_3 AD5 3 IO_L21P_3 AE5 3 IO_L20N_3 AB8 3 IO_L20P_3 AC8 3 IO_L19N_3 AG1 3 IO_L19P_3 AH1 3 IO_L06N_3 AF4 3 IO_L06P_3 AG4 3 IO_L05N_3 AB10 3 IO_L05P_3 AB11 3 IO_L04N_3 AF3 3 IO_L04P_3 AG3 3 IO_L03N_3/VREF_3 AD6 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 206 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 3 IO_L03P_3 AD7 3 IO_L02N_3/VRP_3 AE6 3 IO_L02P_3/VRN_3 AF5 3 IO_L01N_3 AH2 3 IO_L01P_3 AH3 (1) 4 IO_L01N_4/BUSY/DOUT AD9 4 IO_L01P_4/INIT_B AD10 (1) 4 IO_L02N_4/D0/DIN AF7 4 IO_L02P_4/D1 AG7 4 IO_L03N_4/D2/ALT_VRP_4 AK3 4 IO_L03P_4/D3/ALT_VRN_4 AJ5 4 IO_L04N_4/VREF_4 AE8 4 IO_L04P_4 AF8 4 IO_L05N_4/VRP_4 AK4 4 IO_L05P_4/VRN_4 AK5 4 IO_L06N_4 AH6 4 IO_L06P_4 AH7 4 IO_L19N_4 AC10 4 IO_L19P_4 AC11 4 IO_L20N_4 AE9 4 IO_L20P_4 AE10 4 IO_L21N_4 AL4 4 IO_L21P_4/VREF_4 AL5 4 IO_L22N_4 AB12 4 IO_L22P_4 AB13 4 IO_L23N_4 AJ6 4 IO_L23P_4 AJ8 4 IO_L24N_4 AK6 4 IO_L24P_4 AK7 4 IO_L25N_4 AG8 NC 4 IO_L25P_4 AG9 NC 4 IO_L26N_4 AF9 NC 4 IO_L26P_4 AF11 NC 4 IO_L27N_4 AH8 NC 4 IO_L27P_4/VREF_4 AH9 NC 4 IO_L28N_4 AD11 NC 4 IO_L28P_4 AD12 NC DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 207 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 4 IO_L29N_4 AL6 NC 4 IO_L29P_4 AL7 NC 4 IO_L30N_4 AJ9 NC 4 IO_L30P_4 AJ10 NC 4 IO_L49N_4 AE11 4 IO_L49P_4 AE12 4 IO_L50N_4 AG10 4 IO_L50P_4 AG11 4 IO_L51N_4 AL8 4 IO_L51P_4/VREF_4 AL9 4 IO_L52N_4 AF12 4 IO_L52P_4 AF13 4 IO_L53N_4 AK9 4 IO_L53P_4 AK10 4 IO_L54N_4 AH11 4 IO_L54P_4 AH12 4 IO_L67N_4 AC12 4 IO_L67P_4 AC13 4 IO_L68N_4 AG12 4 IO_L68P_4 AG13 4 IO_L69N_4 AL10 4 IO_L69P_4/VREF_4 AL11 4 IO_L70N_4 AD13 4 IO_L70P_4 AD15 4 IO_L71N_4 AJ11 4 IO_L71P_4 AJ12 4 IO_L72N_4 AK11 4 IO_L72P_4 AK12 4 IO_L73N_4 AE14 4 IO_L73P_4 AE15 4 IO_L74N_4 AF14 4 IO_L74P_4 AF15 4 IO_L75N_4 AL12 4 IO_L75P_4/VREF_4 AL13 4 IO_L76N_4 AB14 4 IO_L76P_4 AC14 4 IO_L77N_4 AH13 4 IO_L77P_4 AH14 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 208 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 4 IO_L78N_4 AJ13 4 IO_L78P_4 AK13 4 IO_L91N_4/VREF_4 AC15 4 IO_L91P_4 AC16 4 IO_L92N_4 AG14 4 IO_L92P_4 AG15 4 IO_L93N_4 AK14 4 IO_L93P_4 AK15 4 IO_L94N_4/VREF_4 AF16 4 IO_L94P_4 AG16 4 IO_L95N_4/GCLK3S AL14 4 IO_L95P_4/GCLK2P AL15 4 IO_L96N_4/GCLK1S AH15 4 IO_L96P_4/GCLK0P AJ15 5 IO_L96N_5/GCLK7S AJ16 5 IO_L96P_5/GCLK6P AH17 5 IO_L95N_5/GCLK5S AD16 5 IO_L95P_5/GCLK4P AD17 5 IO_L94N_5 AL17 5 IO_L94P_5/VREF_5 AL18 5 IO_L93N_5 AG17 5 IO_L93P_5 AF17 5 IO_L92N_5 AE17 5 IO_L92P_5 AE18 5 IO_L91N_5 AK17 5 IO_L91P_5/VREF_5 AJ17 5 IO_L78N_5 AK18 5 IO_L78P_5 AK19 5 IO_L77N_5 AC17 5 IO_L77P_5 AB18 5 IO_L76N_5 AH18 5 IO_L76P_5 AH19 5 IO_L75N_5/VREF_5 AL19 5 IO_L75P_5 AL20 5 IO_L74N_5 AC18 5 IO_L74P_5 AC19 5 IO_L73N_5 AJ19 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 209 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 5 IO_L73P_5 AJ20 5 IO_L72N_5 AG18 5 IO_L72P_5 AG19 5 IO_L71N_5 AF18 5 IO_L71P_5 AF19 5 IO_L70N_5 AK20 5 IO_L70P_5 AK21 5 IO_L69N_5/VREF_5 AH20 5 IO_L69P_5 AH21 5 IO_L68N_5 AD19 5 IO_L68P_5 AD20 5 IO_L67N_5 AL21 5 IO_L67P_5 AL22 5 IO_L54N_5 AG20 5 IO_L54P_5 AG21 5 IO_L53N_5 AB19 5 IO_L53P_5 AB20 5 IO_L52N_5 AJ21 5 IO_L52P_5 AJ22 5 IO_L51N_5/VREF_5 AF20 5 IO_L51P_5 AF21 5 IO_L50N_5 AE20 5 IO_L50P_5 AE21 5 IO_L49N_5 AK22 5 IO_L49P_5 AK23 5 IO_L30N_5 AJ23 NC 5 IO_L30P_5 AJ24 NC 5 IO_L29N_5 AC20 NC 5 IO_L29P_5 AC21 NC 5 IO_L28N_5 AL23 NC 5 IO_L28P_5 AL24 NC 5 IO_L27N_5/VREF_5 AL25 NC 5 IO_L27P_5 AL26 NC 5 IO_L26N_5 AD21 NC 5 IO_L26P_5 AD22 NC 5 IO_L25N_5 AH23 NC 5 IO_L25P_5 AH24 NC 5 IO_L24N_5 AG22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 210 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 5 IO_L24P_5 AG23 5 IO_L23N_5 AE22 5 IO_L23P_5 AE23 5 IO_L22N_5 AK25 5 IO_L22P_5 AK26 5 IO_L21N_5/VREF_5 AH25 5 IO_L21P_5 AG25 5 IO_L20N_5 AB21 5 IO_L20P_5 AC22 5 IO_L19N_5 AL27 5 IO_L19P_5 AL28 5 IO_L06N_5 AK27 5 IO_L06P_5 AJ27 5 IO_L05N_5/VRP_5 AD23 5 IO_L05P_5/VRN_5 AE24 5 IO_L04N_5 AJ26 5 IO_L04P_5/VREF_5 AH26 5 IO_L03N_5/D4/ALT_VRP_5 AF23 5 IO_L03P_5/D5/ALT_VRN_5 AF24 5 IO_L02N_5/D6 AG24 5 IO_L02P_5/D7 AF25 5 IO_L01N_5/RDWR_B AK28 5 IO_L01P_5/CS_B AK29 6 IO_L01P_6 AF27 6 IO_L01N_6 AF28 6 IO_L02P_6/VRN_6 AE26 6 IO_L02N_6/VRP_6 AE27 6 IO_L03P_6 AH29 6 IO_L03N_6/VREF_6 AH30 6 IO_L04P_6 AB22 6 IO_L04N_6 AB23 6 IO_L05P_6 AG28 6 IO_L05N_6 AG29 6 IO_L06P_6 AH31 6 IO_L06N_6 AG31 6 IO_L19P_6 AA22 6 IO_L19N_6 Y22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 211 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 6 IO_L20P_6 AD25 6 IO_L20N_6 AC24 6 IO_L21P_6 AG30 6 IO_L21N_6/VREF_6 AF30 6 IO_L22P_6 AD26 6 IO_L22N_6 AC26 6 IO_L23P_6 AF29 6 IO_L23N_6 AD29 6 IO_L24P_6 AE28 6 IO_L24N_6 AD28 6 IO_L25P_6 AB24 NC 6 IO_L25N_6 AA24 NC 6 IO_L27P_6 AC25 NC 6 IO_L27N_6/VREF_6 AB25 NC 6 IO_L43P_6 AF31 6 IO_L43N_6 AE31 6 IO_L44P_6 AA23 6 IO_L44N_6 Y23 6 IO_L45P_6 AE30 6 IO_L45N_6/VREF_6 AC30 6 IO_L46P_6 AC28 6 IO_L46N_6 AA28 6 IO_L47P_6 AD27 6 IO_L47N_6 AC27 6 IO_L48P_6 AA25 6 IO_L48N_6 Y25 6 IO_L49P_6 AC29 6 IO_L49N_6 AB29 6 IO_L50P_6 AB27 6 IO_L50N_6 AA27 6 IO_L51P_6 AA26 6 IO_L51N_6/VREF_6 Y26 6 IO_L52P_6 AD31 6 IO_L52N_6 AC31 6 IO_L53P_6 W22 6 IO_L53N_6 V22 6 IO_L54P_6 Y27 6 IO_L54N_6 W27 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 212 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 6 IO_L67P_6 AB30 6 IO_L67N_6 AA30 6 IO_L68P_6 W26 6 IO_L68N_6 V26 6 IO_L69P_6 AB31 6 IO_L69N_6/VREF_6 AA31 6 IO_L70P_6 AA29 6 IO_L70N_6 Y29 6 IO_L71P_6 Y24 6 IO_L71N_6 W24 6 IO_L72P_6 V25 6 IO_L72N_6 U25 6 IO_L73P_6 Y28 6 IO_L73N_6 W28 6 IO_L74P_6 W23 6 IO_L74N_6 V23 6 IO_L75P_6 Y30 6 IO_L75N_6/VREF_6 W30 6 IO_L76P_6 Y31 6 IO_L76N_6 W31 6 IO_L77P_6 V27 6 IO_L77N_6 U27 6 IO_L78P_6 W29 6 IO_L78N_6 U29 6 IO_L91P_6 U23 6 IO_L91N_6 T23 6 IO_L92P_6 U26 6 IO_L92N_6 T26 6 IO_L93P_6 V28 6 IO_L93N_6/VREF_6 U28 6 IO_L94P_6 U24 6 IO_L94N_6 T24 6 IO_L95P_6 V30 6 IO_L95N_6 U30 6 IO_L96P_6 V31 6 IO_L96N_6 U31 7 IO_L96P_7 T27 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 213 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 7 IO_L96N_7 R27 7 IO_L95P_7 R24 7 IO_L95N_7 N24 7 IO_L94P_7 T29 7 IO_L94N_7 R29 7 IO_L93P_7/VREF_7 R31 7 IO_L93N_7 P31 7 IO_L92P_7 R26 7 IO_L92N_7 P26 7 IO_L91P_7 R30 7 IO_L91N_7 P30 7 IO_L78P_7 R25 7 IO_L78N_7 P25 7 IO_L77P_7 R28 7 IO_L77N_7 P28 7 IO_L76P_7 N31 7 IO_L76N_7 M31 7 IO_L75P_7/VREF_7 R23 7 IO_L75N_7 P23 7 IO_L74P_7 N30 7 IO_L74N_7 M30 7 IO_L73P_7 P27 7 IO_L73N_7 N27 7 IO_L72P_7 P22 7 IO_L72N_7 N22 7 IO_L71P_7 N29 7 IO_L71N_7 M29 7 IO_L70P_7 N28 7 IO_L70N_7 M28 7 IO_L69P_7/VREF_7 N26 7 IO_L69N_7 M26 7 IO_L68P_7 L31 7 IO_L68N_7 K31 7 IO_L67P_7 M27 7 IO_L67N_7 L27 7 IO_L54P_7 N23 7 IO_L54N_7 M23 7 IO_L53P_7 L30 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 214 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 7 IO_L53N_7 K30 7 IO_L52P_7 L28 7 IO_L52N_7 J28 7 IO_L51P_7/VREF_7 M24 7 IO_L51N_7 L24 7 IO_L50P_7 L29 7 IO_L50N_7 K29 7 IO_L49P_7 M25 7 IO_L49N_7 L25 7 IO_L48P_7 L26 7 IO_L48N_7 J26 7 IO_L47P_7 J31 7 IO_L47N_7 H31 7 IO_L46P_7 J29 7 IO_L46N_7 H29 7 IO_L45P_7/VREF_7 M22 7 IO_L45N_7 L22 7 IO_L44P_7 J30 7 IO_L44N_7 G30 7 IO_L43P_7 K27 7 IO_L43N_7 J27 7 IO_L27P_7/VREF_7 L23 NC 7 IO_L27N_7 K23 NC 7 IO_L25P_7 G31 NC 7 IO_L25N_7 F31 NC 7 IO_L24P_7 F30 7 IO_L24N_7 E30 7 IO_L23P_7 K25 7 IO_L23N_7 J25 7 IO_L22P_7 H28 7 IO_L22N_7 G28 7 IO_L21P_7/VREF_7 H27 7 IO_L21N_7 G27 7 IO_L20P_7 K24 7 IO_L20N_7 J24 7 IO_L19P_7 E31 7 IO_L19N_7 D31 7 IO_L06P_7 F28 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 215 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 7 IO_L06N_7 E28 7 IO_L05P_7 K22 7 IO_L05N_7 K21 7 IO_L04P_7 F29 7 IO_L04N_7 E29 7 IO_L03P_7/VREF_7 H26 7 IO_L03N_7 H25 7 IO_L02P_7/VRN_7 G26 7 IO_L02N_7/VRP_7 F27 7 IO_L01P_7 D30 7 IO_L01N_7 D29 0 VCCO_0 C18 0 VCCO_0 C25 0 VCCO_0 F22 0 VCCO_0 H18 0 VCCO_0 L17 0 VCCO_0 L18 0 VCCO_0 L19 0 VCCO_0 L20 0 VCCO_0 M17 0 VCCO_0 M18 0 VCCO_0 M19 1 VCCO_1 C7 1 VCCO_1 C14 1 VCCO_1 F10 1 VCCO_1 H14 1 VCCO_1 L12 1 VCCO_1 L13 1 VCCO_1 L14 1 VCCO_1 L15 1 VCCO_1 M13 1 VCCO_1 M14 1 VCCO_1 M15 2 VCCO_2 G3 2 VCCO_2 K6 2 VCCO_2 M11 2 VCCO_2 N11 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 216 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 2 VCCO_2 N12 2 VCCO_2 P3 2 VCCO_2 P8 2 VCCO_2 P11 2 VCCO_2 P12 2 VCCO_2 R11 2 VCCO_2 R12 3 VCCO_3 U11 3 VCCO_3 U12 3 VCCO_3 V3 3 VCCO_3 V8 3 VCCO_3 V11 3 VCCO_3 V12 3 VCCO_3 W11 3 VCCO_3 W12 3 VCCO_3 Y11 3 VCCO_3 AB6 3 VCCO_3 AE3 4 VCCO_4 Y13 4 VCCO_4 Y14 4 VCCO_4 Y15 4 VCCO_4 AA12 4 VCCO_4 AA13 4 VCCO_4 AA14 4 VCCO_4 AA15 4 VCCO_4 AD14 4 VCCO_4 AF10 4 VCCO_4 AJ7 4 VCCO_4 AJ14 5 VCCO_5 Y17 5 VCCO_5 Y18 5 VCCO_5 Y19 5 VCCO_5 AA17 5 VCCO_5 AA18 5 VCCO_5 AA19 5 VCCO_5 AA20 5 VCCO_5 AD18 5 VCCO_5 AF22 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 217 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 5 VCCO_5 AJ18 5 VCCO_5 AJ25 6 VCCO_6 U20 6 VCCO_6 U21 6 VCCO_6 V20 6 VCCO_6 V21 6 VCCO_6 V24 6 VCCO_6 V29 6 VCCO_6 W20 6 VCCO_6 W21 6 VCCO_6 Y21 6 VCCO_6 AB26 6 VCCO_6 AE29 7 VCCO_7 G29 7 VCCO_7 K26 7 VCCO_7 M21 7 VCCO_7 N20 7 VCCO_7 N21 7 VCCO_7 P20 7 VCCO_7 P21 7 VCCO_7 P24 7 VCCO_7 P29 7 VCCO_7 R20 7 VCCO_7 R21 NA CCLK AJ4 NA PROG_B D27 NA DONE AG6 NA M0 AH27 NA M1 AJ28 NA M2 AG26 NA HSWAP_EN E26 NA TCK K11 NA TDI C28 NA TDO C4 NA TMS J10 NA PWRDWN_B AH5 NA DXN F25 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 218 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 NA DXP B28 NA VBATT D5 NA RSVD B4 NA VCCAUX B16 NA VCCAUX C2 NA VCCAUX C30 NA VCCAUX T2 NA VCCAUX T30 NA VCCAUX AJ2 NA VCCAUX AJ30 NA VCCAUX AK16 NA VCCINT K15 NA VCCINT K17 NA VCCINT L11 NA VCCINT L16 NA VCCINT L21 NA VCCINT M12 NA VCCINT M16 NA VCCINT M20 NA VCCINT N13 NA VCCINT N14 NA VCCINT N15 NA VCCINT N16 NA VCCINT N17 NA VCCINT N18 NA VCCINT N19 NA VCCINT P13 NA VCCINT P19 NA VCCINT R10 NA VCCINT R13 NA VCCINT R19 NA VCCINT R22 NA VCCINT T11 NA VCCINT T12 NA VCCINT T13 NA VCCINT T19 NA VCCINT T20 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 219 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 NA VCCINT T21 NA VCCINT U10 NA VCCINT U13 NA VCCINT U19 NA VCCINT U22 NA VCCINT V13 NA VCCINT V19 NA VCCINT W13 NA VCCINT W14 NA VCCINT W15 NA VCCINT W16 NA VCCINT W17 NA VCCINT W18 NA VCCINT W19 NA VCCINT Y12 NA VCCINT Y16 NA VCCINT Y20 NA VCCINT AA11 NA VCCINT AA16 NA VCCINT AA21 NA VCCINT AB15 NA VCCINT AB17 NA GND A2 NA GND A3 NA GND A16 NA GND A29 NA GND A30 NA GND B1 NA GND B2 NA GND B8 NA GND B24 NA GND B30 NA GND B31 NA GND C1 NA GND C3 NA GND C29 NA GND C31 NA GND D4 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 220 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 NA GND D10 NA GND D16 NA GND D22 NA GND D28 NA GND E5 NA GND E27 NA GND F6 NA GND F26 NA GND G7 NA GND G13 NA GND G16 NA GND G19 NA GND G25 NA GND H2 NA GND H8 NA GND H24 NA GND H30 NA GND J9 NA GND J23 NA GND K4 NA GND K16 NA GND K28 NA GND N7 NA GND N25 NA GND P14 NA GND P15 NA GND P16 NA GND P17 NA GND P18 NA GND R14 NA GND R15 NA GND R16 NA GND R17 NA GND R18 NA GND T1 NA GND T4 NA GND T7 NA GND T10 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 221 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 NA GND T14 NA GND T15 NA GND T16 NA GND T17 NA GND T18 NA GND T22 NA GND T25 NA GND T28 NA GND T31 NA GND U14 NA GND U15 NA GND U16 NA GND U17 NA GND U18 NA GND V14 NA GND V15 NA GND V16 NA GND V17 NA GND V18 NA GND W7 NA GND W25 NA GND AB4 NA GND AB16 NA GND AB28 NA GND AC9 NA GND AC23 NA GND AD2 NA GND AD8 NA GND AD24 NA GND AD30 NA GND AE7 NA GND AE13 NA GND AE16 NA GND AE19 NA GND AE25 NA GND AF6 NA GND AF26 NA GND AG5 DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 222 R Virtex-II Platform FPGAs: Pinout Information Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Bank Pin Description Pin Number No Connect in XC2V2000 NA GND AG27 NA GND AH4 NA GND AH10 NA GND AH16 NA GND AH22 NA GND AH28 NA GND AJ1 NA GND AJ3 NA GND AJ29 NA GND AJ31 NA GND AK1 NA GND AK2 NA GND AK8 NA GND AK24 NA GND AK30 NA GND AK31 NA GND AL2 NA GND AL3 NA GND AL16 NA GND AL29 NA GND AL30 Notes: 1. See Table 4 for an explanation of the signals available on this pin. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 223 R Virtex-II Platform FPGAs: Pinout Information BF957 Flip-Chip BGA Package Specifications (1.27mm pitch) Figure 10: BF957 Flip-Chip BGA Package Specifications DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 224 R Virtex-II Platform FPGAs: Pinout Information Revision History This section records the change history for this module of the data sheet. Date Version Revision 11/07/00 1.0 Early access draft. 11/22/00 1.1 Initial Xilinx release. Made the following corrections: CS144 package - Table 5, page 5: Added missing pin D10 in Bank 1. Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP). FG256 package - Table 6, page 10: Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP). FG896 package - Table 11, page 94: Corrected pin AG1 in Bank 4 to be AG12. FF1152 package - Table 12, page 120: Corrected pin Y3 in Bank 6 to be Y32. 12/19/00 1.2 Reverse designations were fixed for pins in every package. 01/25/01 1.3 Data sheet divided into four modules (per current style standard). DXN and DXP pin information added for CS144 package (Table 5) and FG256 package (Table 6). 02/07/01 1.4 DXN and DXP pin information was changed back to RSVD for the CS144 package (Table 5) and the FG256 package (Table 6). 04/02/01 1.5ALT_VRN and ALT_VRP pin information was added for each package. Table 8, page 34 – added No Connect designations for the XC2V1500 device in the FG676 package. Reverted to traditional double-column format. 11/07/01 1.6Updated list of devices supported in the FF1152, FF1517, and BF957 packages. 09/26/02 1.7Updated Table 3 to reflect devices supported in the BG728 and BF957 packages. Added mention of LVPECL to pin definition in Table 4. 10/07/02 1.8Corrected Table 10 heading to reflect supported devices in the BG728 package. 12/06/02 1.8.1Enhanced the description of the PWRDWN_B pin in Table 4. 05/07/03 1.8.2Added clarification to Table 4 and all device pinout tables regarding the dual-use nature of pins D0/DIN and BUSY/DOUT during configuration. 06/19/03 1.8.3The final GND pin in each of five pinout tables was inadvertently deleted in v1.8.2. This revision restores the deleted GND pins as follows: - Pin C5, Table 5, page 5 (CS144) - Pin A1, Table 6, page 10 (FG256) - Pin A2, Table 10, page 72 (BG728) - Pin A2, Table 12, page 120 (FF1152) - Pin AL30, Table 14, page 198 (BF957) 08/01/03 2.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3. 03/29/04 2.0.1 Recompiled for backward compatibility with Acrobat 4 and above. 06/24/04 3.3 Added references to, and new package drawings for, Pb-free wire-bond packages CSG, FGG, and BGG. (Revision number advanced to level of complete data sheet.) 03/01/05 3.4 Table 4: Changed Direction for User I/O pins (IO_LXXY_#) from “Input/Output” to “Input/Output/Bidirectional”. Added requirement to V to connect pin to V or GND BATT CCAUX if battery is not used. DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 225 R Virtex-II Platform FPGAs: Pinout Information Virtex-II Data Sheet The Virtex-II Data Sheet contains the following modules: Virtex-II Platform FPGAs: Introduction and Overview Virtex-II Platform FPGAs: DC and Switching (Module 1) Characteristics (Module 3) Virtex-II Platform FPGAs: Functional Description Virtex-II Platform FPGAs: Pinout Information (Module 2) (Module 4) DS031-4 (v3.4) March 1, 2005 www.xilinx.com Module 4 of 4 Product Specification 226