ST16C554/554D ST68C554 QUAD UART WITH 16-BYTE FIFO’S DESCRIPTION The ST16C554D is a universal asynchronous receiver PLCC Package and transmitter (UART) with a dual foot print interface. The 554D is an enhanced UART with 16 byte FIFOs, receive trigger levels and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet -DSRA 10 60 -DSRD -CTSA 11 59 -CTSD user requirements. An internal loopback capability -DTRA 12 58 -DTRD allows onboard diagnostics. The 554D is available in VCC 13 57 GND 64 pin TQFP, and 68 pin PLCC packages. The 68 pin -RTSA 14 56 -RTSD PLCC package offer an additional 68 mode which INTA 15 55 INTD allows easy integration with Motorola, and other popu- -CSA 16 54 -CSD TXA 17 53 TXD lar microprocessors. The ST16C554CQ64 (64 pin) ST16C554DCJ68 -IOW 18 52 -IOR offers three state interrupt control while the 16 MODE TXB 19 51 TXC ST16C554DCQ64 provides constant active interrupt -CSB 20 50 -CSC outputs. The 64 pin devices do not offer TXRDY/ INTB 21 49 INTC RXRDY outputs. The 554D combines the package -RTSB 22 48 -RTSC interface modes of the 16C554 and 68C554 series on GND 23 47 VCC -DTRB 24 46 -DTRC a single integrated chip. -CTSB 25 45 -CTSC -DSRB 26 44 -DSRC FEATURES • Compatibility with the Industry Standard ST16C454, ST68C454, ST68C554, TL16C554 • 1.5 Mbps transmit/receive operation (24MHz) • 16 byte transmit FIFO • 16 byte receive FIFO with error flags • Independent transmit and receive control • Software selectable Baud Rate Generator •Four selectable Receive FIFO interrupt trigger levels • Standard modem interface ORDERING INFORMATION Part number Pins Package Operating temperature ST16C554DCJ68 68 PLCC 0° C to + 70° C ST16C554DCQ64 64 TQFP 0° C to + 70° C ST16C554CQ64 64 TQFP 0° C to + 70° C ST16C554DIJ68 68 PLCC -40° C to + 85° C ST16C554DIQ64 64 TQFP -40° C to + 85° C Rev. 3.10 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 -CDA -CDB 27 9 -RIB 28 8 -RIA RXA RXB 29 7 VCC 30 6 GND 16/-68 31 5 D7 A2 32 4 D6 A1 33 3 D5 A0 34 2 D4 XTAL1 35 1 D3 XTAL2 36 68 D2 RESET 37 67 D1 -RXRDY 38 66 D0 -TXRDY 39 65 INTSEL GND 40 64 VCC RXC 41 RXD 63 -RID -RIC 42 62 -CDD -CDC 43 61 ST16C554/554D/68C554 Figure 1, Package Descriptions 64 Pin TQFP Package 68 Pin PLCC Package -DSRA 10 60 -DSRD -DSRA 1 48 -DSRD -CTSA 11 59 -CTSD -CTSA 2 47 -CTSD -DTRA 12 58 -DTRD 3 46 -DTRD -DTRA VCC 13 57 GND VCC 4 45 GND -RTSA 14 56 -RTSD -RTSA 5 44 -RTSD -IRQ 15 55 N.C. INTA 6 43 INTD -CS 16 54 N.C. -CSA 7 42 -CSD TXA 17 53 TXD TXA 8 41 TXD ST16C554CQ64 ST16C554DCJ68 R/-W 18 52 N.C. -IOW 9 40 -IOR 68 MODE TXB 19 51 TXC ST16C554DCQ64 TXC -TXB 10 39 A3 20 50 A4 -CSB 11 38 -CSC N.C. 21 49 N.C. INTB 12 37 INTC -RTSB 22 48 -RTSC -RTSC -RTSB 13 36 GND 23 47 VCC GND 14 35 VCC -DTRB 24 46 -DTRC -DTRB 15 34 -DTRC -CTSB 25 45 -CTSC -CTSC -CTSB 16 33 -DSRB 26 44 -DSRC Rev. 3.10 2 -DSRB 17 64 -CDA -CDB 18 63 -RIA -RIB 19 62 RXA RXB 20 61 GND VCC 21 60 D7 A2 22 59 D6 A1 23 58 D5 A0 24 57 D4 XTAL1 25 56 D3 XTAL2 26 55 D2 RESET 27 54 D1 GND 28 53 D0 RXC 29 52 VCC -RIC 30 51 RXD -RID -CDC 31 50 -DSRC 32 49 -CDD -CDA -CDB 27 9 -RIB 28 8 -RIA RXA RXB 29 7 VCC 30 6 GND 16/-68 31 5 D7 A2 32 4 D6 A1 33 3 D5 A0 34 2 D4 XTAL1 35 1 D3 XTAL2 36 68 D2 -RESET 37 67 D1 -RXRDY 38 66 D0 -TXRDY 39 65 N.C. GND 40 64 VCC RXC 41 RXD 63 -RID -RIC 42 62 -CDD -CDC 43 61 ST16C554/554D/68C554 Figure 2, Block Diagram 16 Mode Transmit Transmit TX A-D FIFO Shift D0-D7 Registers Register -IOR -IOW RESET Receive Receive A0-A2 RX A-D FIFO Shift -CS A-D Registers Register INT A-D -RXRDY -TXRDY INTSEL -DTR A-D -RTS A-D Modem -CTS A-D XTAL1 Control -RI A-D Logic -CD A-D -DSR A-D XTAL2 Rev. 3.10 3 Clock Interrupt Register Data bus & Control Select & Baud Rate Logic Logic Control Logic Generator Inter Connect Bus Lines & Control signals ST16C554/554D/68C554 Figure 3, Block Diagram 68 Mode Transmit Transmit TX A-D FIFO Shift Registers Register D0-D7 R/-W -RESET Receive Receive A0-A4 RX A-D FIFO Shift -CS Registers Register -IRQ -RXRDY -TXRDY -DTR A-D -RTS A-D Modem -CTS A-D Control XTAL1 -RI A-D Logic -CD A-D XTAL2 -DSR A-D Rev. 3.10 4 Clock Interrupt Register Data bus & & Control Select Baud Rate Logic Logic Control Logic Generator Inter Connect Bus Lines & Control signals ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type 16/-68 31 - I 16/68 Interface Type Select (input with internal pull-up). - This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of -IOR, -IOW, INT A- D, and -CS A-D are re-assigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface 16C554D is selected. When this pin is a logic 0, the 68 mode interface (68C554) is selected. When this pin is a logic 0, - IOW is re-assigned to -R/W, RESET is re-assigned to - RESET, -IOR is not used, and INT A-D(s) are connected in a WIRE-OR” configuration. The WIRE-OR outputs are connected internally to the open source IRQ signal output. This pin is not available on 64 pin packages which operate in the 16 mode only. A0 34 24 I Address-0 Select Bit. Internal registers address selection in 16 and 68 modes. A1 33 23 I Address-1 Select Bit. Internal registers address selection in 16 and 68 modes. A2 32 22 I Address-2 Select Bit. - Internal registers address selection in 16 and 68 modes. A3-A4 20,50 - I Address 3-4 Select Bits. - When the 68 mode is selected, these pins are used to address or select individual UART’s (providing -CS is a logic 0). In the 16 mode, these pins are reassigned as chip selects, see -CSB and -CSC. These pins are not available on 64 pin packages which operate in the 16 mode only. -CS 16 - I Chip Select. (active low) - In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four UARTs (A-D) are enabled when the -CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3-A4. When the 16 mode is selected (68 pin device), this pin functions as -CSA, see definition under -CS A-B. This pin is not available on 64 pin packages which operate in the 16 mode only. Rev. 3.10 5 ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type -CS A-B 16,20 7,11 -CS C-D 50,54 38,42 I Chip Select A, B, C, D (active low) - This function is associated with the 16 mode only, and for individual chan- nels, “A” through “D.” When in 16 Mode, these pins enable data transfers between the user CPU and the ST16C554D for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective -CS A-D pin. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin head- ings. D0-D2 66-68 53-55 I/O D3-D7 1-5 56-60 Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. GND 6,23 14,28 GND 40,57 45,61 Pwr Signal and power ground. INT A-B 15,21 6,12 INT C-D 49,55 37,43 O Interrupt A, B, C, D (active high) - This function is associated with the 16 mode only. These pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt con- dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. INTSEL 65 - I Interrupt Select. (active high, with internal pull-down) - This function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR bit-3 to enable or disable the three state interrupts, INT A-D or override MCR bit-3 and force continuous interrupts. Interrupt outputs are enabled continuously by making this Rev. 3.10 6 ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to control the three state interrupt output. In this mode, MCR bit-3 is set to a logic “1” to enable the three state outputs. This pin is disabled in the 68 mode. Due to pin limitations on 64 pin packages, this pin is not available. To cover this limitation, two 64 pin QFP package versions are offered. The ST16C554DCQ64 operates in the continuos interrupt enable mode by bonded this pin to VCC internally. The ST16C554CQ64 operates with MCR bit-3 control by bond- ing this pin to GND. -IOR 52 40 I Read strobe. (active low Strobe) - This function is associ- ated with the 16 mode only. A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the ST16C554D data bus (D0-D7) for access by an external CPU. This pin is disabled in the 68 mode. -IOW 18 9 I Write strobe. (active low strobe) - This function is associ- ated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0/A2. When the 16 mode is selected, this pin functions as -R/W, see definition under R/W. -IRQ 15 - O Interrupt Request or Interrupt “A” - This function is associ- ated with the 68 mode only. In the 68 mode, interrupts from UART channels A-D are WIRE-OR’ed” internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using -CS and A3- A4. In the 68 mode an external pull-up resistor must be connected between this pin and VCC. The function of this pin changes to INTA when operating in the 16 mode, see definition under INTA. Rev. 3.10 7 ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type -RESET RESET 37 27 I Reset. - In the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C554D External Reset Conditions for ini- tialization details.) When 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -RESET. -R/W 18 - I Read/Write Strobe (active low) - This function is associated with the 68 mode only. This pin provides the combined functions for Read or Write strobes. A logic 1 to 0 transition transfers the contents of the CPU data bus (D0-D7) to the register selected by -CS and A0-A4. Similarly a logic 0 to 1 transition places the contents of a 554D register selected by -CS and A0-A4 on the data bus, D0-D7, for transfer to an external CPU. -RXRDY 38 - O Receive Ready (active low) - This function is associated with 68 pin packages only. -RXRDY contains the wire “OR- ed” status of all four receive channel FIFOs, RXRDY A-D. A logic 0 indicates receive data ready status, i.e. the RHR is full or the FIFO has one or more RX characters available for unloading. This pin goes to a logic 1 when the FIFO/RHR is full or when there are no more characters available in either the FIFO or RHR. For 64/68 pin packages, individual channel RX status is read by examining individual internal registers via -CS and A0-A4 pin functions. -TXRDY 39 - O Transmit Ready (active low) - This function is associated with 68 pin package only. -TXRDY contains the wire “OR- ed” status of all four transmit channel FIFOs, TXRDY A-D. A logic 0 indicates a buffer ready status, i.e., at least one location is empty and available in one of the TX channels (A- D). This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR. VCC 13 4,21 VCC 47,64 35,52 I Power supply inputs. Rev. 3.10 8 ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type XTAL1 35 25 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see figure 8). Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming). XTAL2 36 26 O Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. -CD A-B 9,27 64,18 -CD C-D 43,61 31,49 I Carrier Detect (active low) - These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -CTS A-B 11,25 2,16 -CTS C-D 45,59 33,47 I Clear to Send (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on the - CTS pin indicates the modem or data set is ready to accept transmit data from the 554D. Status can be tested by reading MSR bit-4. -DSR A-B 10,26 1,17 -DSR C-D 44,60 32,48 I Data Set Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation. This pin has no effect on the UART’s transmit or receive operation. -DTR A-B 12,24 3,15 -DTR C-D 46,58 34,46 O Data Terminal Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the 554D is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0. This pin has no effect on the UART’s transmit or receive operation. Rev. 3.10 9 ST16C554/554D/68C554 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 64 type -RI A-B 8,28 63,19 -RI C-D 42,62 30,50 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS A-B 14,22 5,13 -RTS C-D 48,56 36,44 O Request to Send (active low) - These outputs are associated with individual UART channels, A through D. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive operation. RX A-B 7,29 62,20 RX C-D 41,63 29,51 I Receive Data Input RX A-D. - These inputs are associated with individual serial channel data to the ST16C554D. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally. TX A-B 17,19 8,10 TX C-D 51,53 39,41 O Transmit Data - These outputs are associated with indi- vidual serial transmit channel data from the 554D. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX Input. Rev. 3.10 10 ST16C554/554D/68C554 921.6Kbps. GENERAL DESCRIPTION The rich feature set of the 554D is available through The 554D provides serial asynchronous receive data internal registers. Selectable receive FIFO trigger synchronization, parallel-to-serial and serial-to-paral- levels, selectable TX and RX baud rates, modem lel data conversions for both the transmitter and interface controls. In the 16 mode INTSEL and MCR receiver sections. These functions are necessary for bit-3 can be configured to provide a software con- converting the serial data stream into parallel data that trolled or continuous interrupt capability. Due of pin is required with digital data systems. Synchronization limitations for the 64 pin 554D this feature is offered by for the serial data stream is accomplished by adding two different QFP packages. The ST16C554DCQ64 start and stops bits to the transmit data to form a data operates in the continuos interrupt enable mode by character (character orientated protocol). Data integ- bonded INTSEL to VCC internally. The rity is insured by attaching a parity bit to the data ST16C554CQ64 operates in conjunction with MCR character. The parity bit is checked by the receiver for bit-3 by bonding INTSEL to GND internally. any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially FUNCTIONAL DESCRIPTIONS when manufactured on a single integrated silicon chip. The ST16C554D represents such an integration Interface Options with greatly enhanced features. The 554D is fabri- cated with an advanced CMOS process to achieve low Two user interface modes are selectable for the 554D drain power and high speed requirements. package. These interface modes are designated as the “16 mode” and the “68 mode.” This nomenclature The 554D is an upward solution that provides 16 bytes corresponds to the early 16C554D and 68C554 pack- of transmit and receive FIFO memory, instead of 1 age interfaces respectively. bytes provided in the 16/68C454. The 554D is de- signed to work with high speed modems and shared The 16 Mode Interface network environments, that require fast data process- The 16 mode configures the package interface pins for ing time. Increased performance is realized in the connection as a standard 16 series (Intel) device and 554D by the larger transmit and receive FIFOs. This operates similar to the standard CPU interface avail- allows the external processor to handle more network- able on the 16C554D. In the 16 mode (pin 16/-68 logic ing tasks within a given time. This increases the 1) each UART is selected with individual chip select service interval giving the external CPU additional (CSx) pins as shown in Table 2 below. time for other applications and reducing the overall UART interrupt servicing time. Table 2, SERIAL PORT CHANNEL SELECTION GUIDE, 16 MODE INTERFACE The 554D combines the package interface modes of the 16C554D and 68C554 series on a single inte- -CSA -CSB -CSC -CSD UART grated chip. The 16 mode interface is designed to CHANNEL operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and 1111 None other popular microprocessors. Following a reset, the 0111 A 554D is down-ward compatible with the ST16C454/ 1011 B ST68C454 dependent on the state of the interface 1101 C mode selection pin, 16/-68. 1110 D The 554D is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz, the user can select data rates up to Rev. 3.10 11 ST16C554/554D/68C554 The 68 Mode Interface Internal Registers The 68 mode configures the package interface pins for connection with Motorola, and other popular micro- The 554D provides 13 internal registers for monitoring processor bus types. The interface operates similar to and control. These resisters are shown in Table 4 the 68C454/554. In this mode the 554D decodes two below. Twelve registers are similar to those already additional addresses, A3-A4 to select one of the four available in the standard 16C454. These registers UART ports. The A3-A4 address decode function is function as data holding registers (THR/RHR), inter- used only when in the 68 mode (16/-68 logic 0), and is rupt status and control registers (IER/ISR), line status shown in Table 3 below. and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data Table 3, SERIAL PORT CHANNEL SELECTION rate (clock) control registers (DLL/DLM), and a user GUIDE, 68 MODE INTERFACE assessable scratchpad register (SPR). Register func- tions are more fully described in the following para- -CS A4 A3 UART graphs. CHANNEL 1 N/A N/A None 00 0 A 00 1 B 01 0 C 01 1 D Table 4, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register 1 1 0 Modem Status Register 1 1 1 Scratchpad Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1. Rev. 3.10 12 ST16C554/554D/68C554 FIFO Operation characters, or as shown in the fully worked out ex- ample: T = [(programmed word length = 7) + (stop bit The 16 byte transmit and receive data FIFO’s are = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = enabled by the FIFO Control Register (FCR) bit-0. 4.4 characters. With 16C554 devices, the user can only set the receive trigger level. The receiver FIFO section in- Example -B: If the user programs the word length = 7, cludes a time-out function to ensure data is delivered with parity and one stop bit, the time out will be: to the external CPU. An interrupt is generated when- T = 4 X 7(programmed word length) + 12 = 40 bit times. ever the Receive Holding Register (RHR) has not Character time = 40 / 10 [ (programmed word length been read following the loading of a character or the = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 receive trigger level has not been reached. characters. Timeout Interrupts In the 16 mode for 68 pin packages, the system/board designer can optionally provide software controlled The interrupts are enabled by IER bits 0-3. Care must three state interrupt operation. This is accomplished be taken when handling these interrupts. Following a by INTSEL and MCR bit-3. When INTSEL interface reset the transmitter interrupt is enabled, the 554D will pin is left open or made a logic 0, MCR bit-3 controls issue an interrupt to indicate that transmit holding the three state interrupt outputs, INT A-D. When register is empty. This interrupt must be serviced prior INTSEL is a logic 1, MCR bit-3 has no effect on the INT to continuing operations. The LSR register provides A-D outputs and the package operates with interrupt the current singular highest priority interrupt only. outputs enabled continuously. Servicing the interrupt without investigating further interrupt conditions can result in data errors. Programmable Baud Rate Generator When two interrupt conditions have the same priority, The 554D supports high speed modem technologies it is important to service these interrupts correctly. that have increased input data rates by employing Receive Data Ready and Receive Time Out have the data compression schemes. For example a 33.6Kbps same interrupt priority (when enabled by IER bit-0). modem that employs data compression may require a The receiver issues an interrupt after the number of 115.2Kbps input data rate. A 128.0Kbps ISDN modem characters have reached the programmed trigger that supports data compression may need an input level. In this case the 554D FIFO may hold more data rate of 460.8Kbps. The 554D can support a characters than the programmed trigger level. Follow- standard data rate of 921.6Kbps. ing the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Single baud rate generator is provided for the Out will not occur if the receive FIFO is empty. The transmitter and receiver, allowing independent TX/ time out counter is reset at the center of each stop bit RX channel control. The programmable Baud Rate received or each time the receive holding register Generator is capable of accepting an input clock up (RHR) is read. The actual time out value is T (Time out to 24 MHz, as required for supporting a 1.5Mbps length in bits) = 4 X P (Programmed word length) + 12. data rate. The 554D can be configured for internal To convert the time out value to a character value, the or external clock operation. For internal clock user has to consider the complete word length, includ- oscillator operation, an industry standard micropro- ing data information length, start bit, parity bit, and the cessor crystal (parallel resonant/ 22-33 pF load) is size of stop bit, i.e., 1X, 1.5X, or 2X bit times. connected externally between the XTAL1 and XTAL2 pins (see figure 8). Alternatively, an external Example -A: If the user programs a word length of 7, clock can be connected to the XTAL1 pin to clock with no parity and one stop bit, the time out will be: the internal baud rate generator for standard or T = 4 X 7( programmed word length) +12 = 40 bit times. custom rates. (see Baud Rate Generator Program- The character time will be equal to 40 / 9 = 4.4 ming). Rev. 3.10 13 ST16C554/554D/68C554 The generator divides the input 16X clock by any Figure 8, Crystal oscillator connection 16 divisor from 1 to 2 -1. The 554D divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers X1 DLM (MSB) and DLL (LSB) provides a user capability 1.8432 MHz for selecting the desired final baud rate. The example C1 C2 in Table 5 below, shows the two selectable baud rate 22pF 33pF tables available when using a 7.3728 MHz crystal. Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE: Output Output User User DLM DLL Baud Rate Baud Rate 16 x Clock 16 x Clock Program Program (1.8432 MHz (7.3728 MHz Divisor Divisor Value Value Clock) Clock) (Decimal) (HEX) (HEX) (HEX) 50 200 2304 900 09 00 300 1200 384 180 01 80 600 2400 192 C0 00 C0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2K 24 18 00 18 9600 38.4k 12 0C 00 0C 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01 Rev. 3.10 14 XTAL1 XTAL2 ST16C554/554D/68C554 DMA Operation In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts The 554D FIFO trigger level provides additional are also operational. However, the interrupts can only flexibility to the user for block mode operation. LSR be read using lower four bits of the Modem Control bits 5-6 provide an indication when the transmitter is Register (MCR bits 0-3) instead of the four Modem empty or has an empty location(s). The user can Status Register bits 4-7. The interrupts are still con- optionally operate the transmit and receive FIFOs in trolled by the IER. the DMA mode (FCR bit-3). When the transmit and receive FIFOs are enabled and the DMA mode is deactivated (DMA Mode “0”), the 554D activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode “1”), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the 554D sets the interrupt output pin when characters in the transmit FIFOs are below the trans- mit trigger level, or the characters in the receive FIFOs are above the receive trigger level. Loopback Mode The internal loopback capability allows onboard diag- nostics. In the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally. MCR register bits 0-3 are used for controlling loopback diagnostic testing. In the loopback mode OP1 and OP2 in the MCR register (bits 3/2) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their asso- ciated interface pins, and instead are connected to- gether internally (See Figure 12). The -CTS, -DSR, - CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loopback test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connec- tion. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. Rev. 3.10 15 ST16C554/554D/68C554 Figure 12, INTERNAL LOOPBACK MODE DIAGRAM Transmit Transmit TX A-D FIFO Shift Registers Register D0-D7 -IOR,-IOW RESET Receive Receive FIFO Shift Registers Register RX A-D A0-A2 -CS A-D -RTS A-D -CD A-D -DTR A-D INT A-D -RXRDY -TXRDY -RI A-D (-OP1 A-D) XTAL1 -DSR A-D XTAL2 (-OP2 A-D) -CTS A-D Rev. 3.10 16 Clock Interrupt Register Data bus & Control Select & Baud Rate Logic Logic Control Logic Generator Inter C onnect B us Lin es & C ontrol signals Modem Control Logic MCR Bit-4=1 ST16C554/554D/68C554 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 554D internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 6, ST16C554D INTERNAL REGISTERS A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 [Note *5] General Register Set 0 0 0 RHR[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER[00] 0000 modem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 FCR RCVR RCVR 0 0 DMA XMIT RCVR FIFO trigger trigger mode FIFO FIFO enable (MSB) (LSB) select reset reset 0 1 0 ISR[01] FIFO’s FIFO’s 0 0 INT INT INT INT enabled enabled priority priority priority status bit-2 bit-1 bit-0 0 1 1 LCR[00] divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 MCR[00] 0 0 0 loop -OP2/ -OP1 -RTS -DTR back INTx enable 1 0 1 LSR[60] FIFO trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 MSR[X0] CD RI DSR CTS delta delta delta delta -CD -RI -DSR -CTS 1 1 1 SPR[FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Special Register set: Note *2 0 0 0 DLL[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM[XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 2 Note * : The Special register set is accessible only when LCR bit-7 is set to “1”. Rev. 3.10 17 ST16C554/554D/68C554 5 Note * : The value between the square brackets represents the register’s initialized HEX value. A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the Transmit (THR) and Receive (RHR) Holding Reg- programmed trigger level. It will be cleared when the isters FIFO drops below the programmed trigger level. The serial transmitter section consists of an 8-bit B) FIFO status will also be reflected in the user Transmit Hold Register (THR) and Transmit Shift accessible ISR register when the FIFO trigger level is Register (TSR). The status of the THR is provided in reached. Both the ISR register status bit and the the Line Status Register (LSR). Writing to the THR interrupt will be cleared when the FIFO drops below transfers the contents of the data bus (D7-D0) to the the trigger level. THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic C) The data ready bit (LSR BIT-0) is set as soon as a 1 when the transmitter is empty or when data is character is transferred from the shift register to the transferred to the TSR. Note that a write operation can receive FIFO. It is reset when the FIFO is empty. be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least IER Vs Receive/Transmit FIFO Polled Mode Op- one FIFO location available). eration The serial receive section also contains an 8-bit When FCR BIT-0 equals a logic 1; resetting IER bits Receive Holding Register, RHR. Receive data is 0-3 enables the 554D in the FIFO polled mode of removed from the 554D and receive FIFO by reading operation. Since the receiver and transmitter have the RHR register. The receive section provides a separate bits in the LSR either or both can be used in mechanism to prevent false starts. On the falling edge the polled mode by selecting respective transmit or of a start or false start bit, an internal receiver counter receive control bit(s). starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center A) LSR BIT-0 will be a logic 1 as long as there is one of the start bit. At this time the start bit is sampled and byte in the receive FIFO. if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assem- B) LSR BIT 1-4 will provide the type of errors encoun- bling a false character. Receiver status codes will be tered, if any. posted in the LSR. C) LSR BIT-5 will indicate when the transmit FIFO is Interrupt Enable Register (IER) empty. The Interrupt Enable Register (IER) masks the inter- D) LSR BIT-6 will indicate when both the transmit rupts from receiver ready, transmitter empty, line FIFO and transmit shift register are empty. status and modem status registers. These interrupts would normally be seen on the INT A-D output pins in E) LSR BIT-7 will indicate any FIFO data errors. the 16 mode, or on WIRE-OR IRQ output pin, in the 68 mode. IER BIT-0: IER Vs Receive FIFO Interrupt Mode Operation This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared When the receive FIFO (FCR BIT-0 = a logic 1) and when the FIFO drops below the trigger level in the receive interrupts (IER BIT-0 = logic 1) are enabled, FIFO mode of operation. the receive interrupts and register status will reflect Logic 0 = Disable the receiver ready interrupt. (normal the following: Rev. 3.10 18 ST16C554/554D/68C554 default condition) remains a logic 0 as long as the FIFO fill level is above Logic 1 = Enable the receiver ready interrupt. the programmed trigger level. IER BIT-1: FCR BIT-0: This interrupt will be issued whenever the THR is Logic 0 = Disable the transmit and receive FIFO. empty and is associated with bit-1 in the LSR register. (normal default condition) Logic 0 = Disable the transmitter empty interrupt. Logic 1 = Enable the transmit and receive FIFO. This (normal default condition) bit must be a “1” when other FCR bits are written to or Logic 1 = Enable the transmitter empty interrupt. they will not be programmed. IER BIT-2: This interrupt will be issued whenever a fully as- FCR BIT-1: sembled receive character is transferred from the Logic 0 = No FIFO receive reset. (normal default RSR to the RHR/FIFO, i.e., data ready, LSR bit-0. condition) Logic 0 = Disable the receiver line status interrupt. Logic 1 = Clears the contents of the receive FIFO and (normal default condition) resets the FIFO counter logic (the receive shift regis- Logic 1 = Enable the receiver line status interrupt. ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. IER BIT-3: Logic 0 = Disable the modem status register interrupt. FCR BIT-2: (normal default condition) Logic 0 = No FIFO transmit reset. (normal default Logic 1 = Enable the modem status register interrupt. condition) Logic 1 = Clears the contents of the transmit FIFO and IER BIT 4-7: resets the FIFO counter logic (the transmit shift regis- Not used - Initialized to a logic 0. ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FIFO Control Register (FCR) FCR BIT-3: This register is used to enable the FIFOs, clear the Logic 0 = Set DMA mode “0”. (normal default condi- FIFOs, set the transmit/receive FIFO trigger levels, tion) and select the DMA mode. The DMA, and FIFO Logic 1 = Set DMA mode “1.” modes are defined as follows: Transmit operation in mode “0”: DMA MODE When the 554D is in the ST16C450 mode (FIFOs Mode 0 Set and enable the interrupt for each disabled, FCR bit-0 = logic 0) or in the FIFO mode single transmit or receive operation, and is similar to (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic the ST16C454 mode. Transmit Ready (-TXRDY) will 0) and when there are no characters in the transmit go to a logic 0 when ever an empty transmit space is FIFO or transmit holding register, the -TXRDY pin will available in the Transmit Holding Register (THR). be a logic 0. Once active the -TXRDY pin will go to a Receive Ready (-RXRDY) will go to a logic 0 when- logic 1 after the first character is loaded into the ever the Receive Holding Register (RHR) is loaded transmit holding register. with a character. Mode 1 Set and enable the interrupt in a block Receive operation in mode “0”: mode operation. The transmit interrupt is set when the When the 554D is in mode “0” (FCR bit-0 = logic 0) or transmit FIFO is below the programmed trigger level. in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = -TXRDY remains a logic 0 as long as one empty FIFO logic 0) and there is at least one character in the location is available. The receive interrupt is set when receive FIFO, the -RXRDY pin will be a logic 0. Once the receive FIFO fills to the programmed trigger level. active the -RXRDY pin will go to a logic 1 when there However the FIFO continues to fill regardless of the are no more characters in the receiver. programmed level until the FIFO is full. -RXRDY Rev. 3.10 19 ST16C554/554D/68C554 Transmit operation in mode “1”: When the 554D is in FIFO mode ( FCR bit-0 = logic 1, BIT-7 BIT-6 RX FIFO trigger level FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a 00 1 logic 0 if one or more FIFO locations are empty. 01 4 10 8 Receive operation in mode “1”: 11 14 When the 554D is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the - Interrupt Status Register (ISR) RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the The 554D provides four levels of prioritized interrupts FIFO. to minimize external software interaction. The Inter- rupt Status Register (ISR) provides the user with six FCR BIT 4-5: interrupt status bits. Performing a read cycle on the Not used - Initialized to a logic 0. ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are FCR BIT 6-7: (logic 0 or cleared is the default condi- acknowledged until the pending interrupt is serviced. tion, Rx trigger level = 1) Whenever the interrupt status register is read, the These bits are used to set the trigger level for the interrupt status is cleared. However it should be noted receive FIFO interrupt. that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after reread- An interrupt is generated when the number of charac- ing the interrupt status bits. The Interrupt Source ters in the FIFO equals the programmed trigger level. Table 7 (below) shows the data values (bit 0-5) for the However the FIFO will continue to be loaded until it is four prioritized interrupt levels and the interrupt full. sources associated with each of these interrupt levels: Table 7, INTERRUPT SOURCE TABLE Priority [ ISR BITS ] Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt 1 000110 LSR (Receiver Line Status Register) 2 000100 RXRDY (Received Data Ready) 2 001100 RXRDY (Receive Data time out) 3 000010 TXRDY ( Transmitter Holding Register Empty) 4 000000 MSR (Modem Status Register) Rev. 3.10 20 ST16C554/554D/68C554 ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents BIT-2 Word length Stop bit may be used as a pointer to the appropriate interrupt length service routine. (Bit time(s)) Logic 1 = No interrupt pending. (normal default condi- tion) 0 5,6,7,8 1 1 5 1-1/2 ISR BIT 1-3: (logic 0 or cleared is the default condition) 1 6,7,8 2 These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). LCR BIT-3: Parity or no parity can be selected via this bit. ISR BIT 4-5: Logic 0 = No parity. (normal default condition) Not used - Initialized to a logic 0. Logic 1 = A parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- ISR BIT 6-7: (logic 0 or cleared is the default condition) sion errors. These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs LCR BIT-4: are enabled. If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Line Control Register (LCR) Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted data. The The Line Control Register is used to specify the receiver must be programmed to check the same asynchronous data communication format. The word format. (normal default condition) length, the number of stop bits, and the parity are Logic 1 = EVEN Parity is generated by forcing an even selected by writing the appropriate bits in this register. the number of logic 1’s in the transmitted. The receiver must be programmed to check the same format. LCR BIT 0-1: (logic 0 or cleared is the default condi- tion) LCR BIT-5: These two bits specify the word length to be transmit- If the parity bit is enabled, LCR BIT-5 selects the ted or received. forced parity format. LCR BIT-5 = logic 0, parity is not forced. (normal default condition) BIT-1 BIT-0 Word length LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive 00 5 data. 01 6 LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit 10 7 is forced to a logical 0 for the transmit and receive 11 8 data. LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. Rev. 3.10 21 ST16C554/554D/68C554 Logic 0 = Forces INT (A-D) outputs to the three state LCR LCR LCR Parity selection mode during the 16 mode. (normal default condition) Bit-5 Bit-4 Bit-3 In the Loopback mode, sets -OP2 (-CD) internally to a logic 1. X X 0 No parity Logic 1 = Forces the INT (A-D) outputs to the active 0 0 1 Odd parity mode during the 16 mode. In the Loopback mode, sets 0 1 1 Even parity -OP2 (-CD) internally to a logic 0. 1 0 1 Force parity “1” 1 1 1 Forced parity “0” MCR BIT-4: Logic 0 = Disable loopback mode. (normal default condition) Logic 1 = Enable local loopback mode (diagnostics). LCR BIT-6: When enabled the Break control bit causes a break MCR BIT 5-7: condition to be transmitted (the TX output is forced to Not used - Initialized to a logic 0. a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Line Status Register (LSR) Logic 0 = No TX break condition. (normal default condition) This register provides the status of data transfers Logic 1 = Forces the transmitter output (TX) to a logic between. the 554D and the CPU. 0 for alerting the remote receiver to a line break condition. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO. LCR BIT-7: (normal default condition) Not used - Initialized to a logic 0. Logic 1 = Data has been received and is saved in the receive holding register or FIFO. Modem Control Register (MCR) LSR BIT-1: This register controls the interface with the modem or Logic 0 = No overrun error. (normal default condition) a peripheral device. Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when addi- MCR BIT-0: tional data arrives while the FIFO is full. In this case Logic 0 = Force -DTR output to a logic 1. (normal the previous data in the shift register is overwritten. default condition) Note that under this condition the data byte in the Logic 1 = Force -DTR output to a logic 0. receive shift register is not transfered into the FIFO, therefore the data in the FIFO is not corrupted by the MCR BIT-1: error. Logic 0 = Force -RTS output to a logic 1. (normal default condition) LSR BIT-2: Logic 1 = Force -RTS output to a logic 0. Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not MCR BIT-2: have correct parity information and is suspect. In the This bit is used in the Loopback mode only. In the FIFO mode, this error is associated with the character loopback mode this bit is use to write the state of the at the top of the FIFO. modem -RI interface signal via -OP1. LSR BIT-3: MCR BIT-3: (Used to control the modem -CD signal Logic 0 = No framing error. (normal default condition) in the loopback mode.) Logic 1 = Framing error. The receive character did not Rev. 3.10 22 ST16C554/554D/68C554 have a valid stop bit(s). In the FIFO mode this error is from the modem changes state. These bits are set to associated with the character at the top of the FIFO. a logic 0 whenever the CPU reads this register. LSR BIT-4: MSR BIT-0: Logic 0 = No break condition. (normal default condi- Logic 0 = No -CTS Change (normal default condition) tion) Logic 1 = The -CTS input to the 554D has changed Logic 1 = The receiver received a break signal (RX state since the last time it was read. A modem Status was a logic 0 for one character frame time). In the Interrupt will be generated. FIFO mode, only one break character is loaded into the FIFO. MSR BIT-1: LSR BIT-5: Logic 0 = No -DSR Change. (normal default condition) This bit is the Transmit Holding Register Empty indi- Logic 1 = The -DSR input to the 554D has changed cator. This bit indicates that the UART is ready to state since the last time it was read. A modem Status accept a new character for transmission. In addition, Interrupt will be generated. this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the MSR BIT-2: transmit holding register into the transmitter shift Logic 0 = No -RI Change. (normal default condition) register. The bit is reset to logic 0 concurrently with the Logic 1 = The -RI input to the 554D has changed from loading of the transmitter holding register by the CPU. a logic 0 to a logic 1. A modem Status Interrupt will be In the FIFO mode this bit is set when the transmit FIFO generated. is empty; it is cleared when at least 1 byte is written to the transmit FIFO. MSR BIT-3: LSR BIT-6: Logic 0 = No -CD Change. (normal default condition) This bit is the Transmit Empty indicator. This bit is set Logic 1 = Indicates that the -CD input to the has to a logic 1 whenever the transmit holding register and changed state since the last time it was read. A the transmit shift register are both empty. It is reset to modem Status Interrupt will be generated. logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one MSR BIT-4: whenever the transmit FIFO and transmit shift register -CTS (active high, logical 1). Normally MSR bit-4 bit are both empty. is the compliment of the -CTS input. However in the loopback mode, this bit is equivalent to the RTS bit in LSR BIT-7: the MCR register. Logic 0 = No Error. (normal default condition) Logic 1 = At least one parity error, framing error or MSR BIT-5: break indication is in the current FIFO data. This bit is DSR (active high, logical 1). Normally this bit is the cleared when LSR register is read. compliment of the -DSR input. In the loopback mode, this bit is equivalent to the DTR bit in the MCR register. Modem Status Register (MSR) MSR BIT-6: This register provides the current state of the control RI (active high, logical 1). Normally this bit is the interface signals from the modem, or other peripheral compliment of the -RI input. In the loopback mode this device that the 554D is connected to. Four bits of this bit is equivalent to the OP1 bit in the MCR register. register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input Rev. 3.10 23 ST16C554/554D/68C554 MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loopback mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The ST16C554D provides a temporary data register to store 8 bits of user information. ST16C554D EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER IER BITS 0-7=0 ISR ISR BIT-0=1, ISR BITS 1-7=0 LCR LCR BITS 0-7=0 MCR MCR BITS 0-7=0 LSR LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR MSR BITS 0-3=0, MSR BITS 4-7= input signals FCR FCR BITS 0-7=0 SIGNALS RESET STATE TX A-D High -RTS A-D High -DTR A-D High -RXRDY High -TXRDY Low Rev. 3.10 24 ST16C554/554D/68C554 AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter Limits Limits Units Conditions 3.3 5.0 Min Max Min Max T1w,T2w Clock pulse duration 17 17 ns T3w Oscillator/Clock frequency 8 24 MHz T6s Address setup time 5 0 ns T7d -IOR delay from chip select 10 10 ns T7w -IOR strobe width 35 25 ns T7h Chip select hold time from -IOR 0 0 ns T9d Read cycle delay 40 30 ns T12d Delay from -IOR to data 35 25 ns T12h Data disable time 25 35 15 ns T13d -IOW delay from chip select 10 10 ns T13w -IOW strobe width 35 25 ns T13h Chip select hold time from -IOW 0 0 ns T15d Write cycle delay 40 30 ns T16s Data setup time 20 15 ns T16h Data hold time 5 5 ns T17d Delay from -IOW to output 50 40 ns 100 pF load T18d Delay to set interrupt from MODEM 40 35 ns 100 pF load input T19d Delay to reset interrupt from -IOR 40 35 ns 100 pF load T20d Delay from stop to set interrupt 1 1 Rclk T21d Delay from -IOR to reset interrupt 45 40 ns 100 pF load T22d Delay from stop to interrupt 45 40 ns T23d Delay from initial INT reset to transmit 8 24 8 24 Rclk start T24d Delay from -IOW to reset interrupt 45 40 ns T25d Delay from stop to set -RxRdy 1 1 Rclk T26d Delay from -IOR to reset -RxRdy 45 40 ns T27d Delay from -IOW to set -TxRdy 45 40 ns T28d Delay from start to reset -TxRdy 8 8 Rclk T30s Address setup time 10 10 ns T30w Chip select strobe width 40 40 ns T30h Address hold time 15 15 ns T30d Read cycle delay 70 70 ns T31d Delay from -CS to data 15 15 ns T31h Data disable time 15 ns T32s Write strobe setup time 10 10 ns T32h Write strobe hold time 10 10 ns T32d Write cycle delay 70 70 ns Rev. 3.10 25 ST16C554/554D/68C554 AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter Limits Limits Units Conditions 3.3 5.0 Min Max Min Max T33s Data setup time 20 15 ns T33h Data hold time 10 10 ns TR Reset pulse width 40 40 ns 16 16 N Baud rate devisor 1 2 -1 1 2 -1 Rclk Rev. 3.10 26 ST16C554/554D/68C554 ABSOLUTE MAXIMUM RATINGS Supply range 7 Volts Voltage at any pin GND - 0.3 V to VCC +0.3 V Operating temperature -40° C to +85° C Storage temperature -65° C to 150° C Package dissipation 500 mW DC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter Limits Limits Units Conditions 3.3 5.0 Min Max Min Max V Clock input low level -0.3 0.6 -0.5 0.6 V ILCK V Clock input high level 2.4 VCC 3.0 VCC V IHCK V Input low level -0.3 0.8 -0.5 0.8 V IL V Input high level 2.0 2.2 VCC V IH V Output low level on all outputs 0.4 V I = 5 mA OL OL V Output low level on all outputs 0.4 V I = 4 mA OL OL V Output high level 2.4 V I = -5 mA OH OH V Output high level 2.0 V I = -1 mA OH OH I Input leakage ±10 ±10mA IL I Clock leakage ±10 ±10mA CL I Avg power supply current 3 6 mA CC C Input capacitance 5 5 pF P RIN Internal pull-up resistance 3 15 kW Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors. Rev. 3.10 27 ST16C554/554D/68C554 A0-A4 T30h T30s T30w T30d -CS T31h R/-W T31d D0-D7 8654-RD-1 General read timing in 68 mode A0-A4 T30s T30h -CS T32h T32s T32d T30w R/-W T33h T33s D0-D7 8654-WD-1 General write timing in 68 mode Rev. 3.10 28 ST16C554/554D/68C554 Valid A0-A2 Address T6s Active -CS T13h T13d T13w T15d Active -IOW T16s T16h Data D0-D7 X552-WD-1 General write timing in 16 mode Valid A0-A2 Address T6s Active -CS T7d T7w T7h T9d -IOR Active T12d T12h D0-D7 Data X552-RD-1 General read timing in 16 mode Rev. 3.10 29 ST16C554/554D/68C554 Active -IOW T17d -RTS Change of state Change of state -DTR -CD Change of state Change of state -CTS -DSR T18d T18d INT Active Active Active T19d Active Active Active -IOR T18d -RI Change of state X552-MD-1 Modem input/output timing T1w T2w EXTERNAL CLOCK X654-CK-1 T3w External clock timing Rev. 3.10 30 ST16C554/554D/68C554 STOP START BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT 5 DATA BITS BIT DATA START BIT 6 DATA BITS T20d 7 DATA BITS Active INT T21d Active -IOR 16 BAUD RATE CLOCK X552-RX-1 Receive timing Rev. 3.10 31 ST16C554/554D/68C554 STOP START BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT BIT DATA START BIT T25d Active -RXRDY Data Ready T26d -IOR Active X552-RX-2 Receive ready timing in none FIFO mode START STOP BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY First byte BIT that reaches the trigger level T25d Active Data -RXRDY Ready T26d -IOR Active X552-RX-3 Receive timing in FIFO mode Rev. 3.10 32 ST16C554/554D/68C554 STOP START BIT BIT DATA BITS (5-8) TX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT 5 DATA BITS BIT DATA START BIT 6 DATA BITS T22d 7 DATA BITS Active INT Tx Ready T24d T23d -IOW Active Active 16 BAUD RATE CLOCK X552-TX-1 Transmit timing Rev. 3.10 33 ST16C554/554D/68C554 START STOP BIT BIT DATA BITS (5-8) TX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT BIT DATA START BIT -IOW Active T28d D0-D7 BYTE #1 T27d Active -TXRDY Transmitter Transmitter ready not ready X654-TX-2 Transmit ready timing in none FIFO mode Rev. 3.10 34 ST16C554/554D/68C554 START BIT DATA BITS (5-8) STOP BIT TX D0 D1 D2 D3 D4 D5 D6 D7 5 DATA BITS PARITY BIT 6 DATA BITS 7 DATA BITS -IOW Active T28d D0-D7 BYTE #16 T27d -TXRDY FIFO Full X552-TX-3 Transmit ready timing in FIFO mode Rev. 3.10 35 ST16C554/554D/68C554 Rev. 3.10 36 Package Dimensions 100 LEAD PLASTIC QUAD FLAT PACK (14 mm x 20 mm, QFP) Rev. 2.00 D D 1 80 51 81 50 E E 1 100 31 1 30 B A 2 e C A α Seating Plane A 1 L 1.6 mm Form 1.95 mm Form INCHES MILLIMETERS INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX A 0.102 0.130 2.60 3.30 0.102 0.134 2.60 3.40 A 0.002 0.010 0.05 0.25 0.002 0.014 0.05 0.35 1 A 0.100 0.120 2.55 3.05 0.100 0.120 2.55 3.05 2 B 0.009 0.015 0.22 0.38 0.009 0.015 0.22 0.38 C 0.005 0.009 0.13 0.23 0.005 0.009 0.13 0.23 D 0.904 0.923 22.95 23.45 0.931 0.951 23.65 24.15 D 0.783 0.791 19.90 20.10 0.783 0.791 19.90 20.10 1 E 0.667 0.687 16.95 17.45 0.695 0.715 17.65 18.15 E 0.547 0.555 13.90 14.10 0.547 0.555 13.90 14.10 1 e 0.0256 BSC 0.65 BSC 0.0256 BSC 0.65 BSC L 0.029 0.040 0.73 1.03 0.026 0.037 0.65 0.95 α 0° 7° 0° 7° 0° 7° 0° 7° Note: The control dimension is the millimeter column Package Dimensions 64 LEAD THIN QUAD FLAT PACK (10 x 10 x 1.4 mm, TQFP) Rev. 2.00 D D 1 48 33 49 32 D D 1 64 17 1 16 B A 2 e C A α Seating Plane A 1 L INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A 0.002 0.006 0.05 0.15 1 A 0.053 0.057 1.35 1.45 2 B 0.005 0.009 0.13 0.23 C 0.004 0.008 0.09 0.20 D 0.465 0.480 11.80 12.20 D 0.390 0.398 9.90 10.10 1 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° Note: The control dimension is the millimeter column Package Dimensions 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D C Seating Plane D 1 45° x H1 A 2 45° x H2 2 1 68 B 1 B D D 3 2 D D 1 e R D 3 A 1 A INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.165 0.200 4.19 5.08 A 0.090 0.130 2.29 3.30 1 A 0.020 –––. 0.51 ––– 2 B 0.013 0.021 0.33 0.53 B 0.026 0.032 0.66 0.81 1 C 0.008 0.013 0.19 0.32 D 0.985 0.995 25.02 25.27 D 0.950 0.958 24.13 24.33 1 D 0.890 0.930 22.61 23.62 2 D 0.800 typ. 20.32 typ. 3 e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1994 EXAR Corporation Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Telephone: 817-274-7553 ŸŸ Fax: 817-548-1358 http://www.winsystems.com ŸŸ E-mail: info@winsystems.com WARRANTY WinSystems warrants that for a period of two (2) years from the date of shipment any Products and Software purchased or licensed hereunder which have been developed or manufactured by WinSystems shall be free of any material defects and shall perform substantially in accordance with WinSystems' specifications therefore. With respect to any Products or Software purchased or licensed hereunder which have been developed or manufactured by others, WinSystems shall transfer and assign to Customer any warranty of such manufacturer or developer held by WinSystems, provided that the warranty, if any, may be assigned. The sole obligation of WinSystems for any breach of warranty contained herein shall be, at its option, either (i) to repair or replace at its expense any materially defective Products or Software, or (ii) to take back such Products and Software and refund the Customer the purchase price and any license fees paid for the same. Customer shall pay all freight, duty, broker's fees, insurance changes and other fees and charges for the return of any Products or Software to WinSystems under this warranty. WinSystems shall pay freight and insurance charges for any repaired or replaced Products or Software thereafter delivered to Customer within the United States. All fees and costs for shipment outside of the United States shall be paid by Customer. The foregoing warranty shall not apply to any Products or Software which have been subject to abuse, misuse, vandalism, accidents, alteration, neglect, unauthorized repair or improper installations. THERE ARE NO WARRANTIES BY WINSYSTEMS EXCEPT AS STATED HEREIN. THERE ARE NO OTHER WARRANTIES EXPRESS OR IMPLIED INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, IN NO EVENT SHALL WINSYSTEMS BE LIABLE FOR CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR LOSS OF DATA, PROFITS OR GOODWILL. WINSYSTEMS' MAXIMUM LIABILITY FOR ANY BREACH OF THIS AGREEMENT OR OTHER CLAIM RELATED TO ANY PRODUCTS, SOFTWARE, OR THE SUBJECT MATTER HEREOF, SHALL NOT EXCEED THE PURCHASE PRICE OR LICENSE FEE PAID BY CUSTOMER TO WINSYSTEMS FOR THE PRODUCTS OR SOFTWARE OR PORTION THEREOF TO WHICH SUCH BREACH OR CLAIM PERTAINS. WARRANTY SERVICE All products returned to WinSystems must be assigned a Return Material Authorization (RMA) number. To obtain this number, please call or FAX WinSystems' factory in Arlington, Texas and provide the following information: 1. Description and quantity of the product(s) to be returned including its serial number. 2. Reason for the return. 3. Invoice number and date of purchase (if available), and original purchase order number. 4. Name, address, telephone and FAX number of the person making the request. 5. Do not debit WinSystems for the repair. WinSystems does not authorize debits. After the RMA number is issued, please return the products promptly. Make sure the RMA number is visible on the outside of the shipping package. The customer must send the product freight prepaid and insured. The product must be enclosed in an anti-static bag to protect it from damage caused by static electricity. Each bag must be completely sealed. Packing material must separate each unit returned and placed as a cushion between the unit(s) and the sides and top of the shipping container. WinSystems is not responsible for any damage to the product due to inadequate packaging or static electricity.