TE tmCH T224162B 256K x 16 DYNAMIC DRAM RAM EDO PAGE MODE FEATURES PIN ASSIGNMENT ( Top View ) · Industry-standard x 16 pinouts and timing functions. Vcc 1 40 Vss I/01 2 39 I/016 · ± Single 5V ( 10%) power supply. I/02 3 38 I/015 · All device pins are TTL- compatible. I/03 4 37 I/014 · 512-cycle refresh in 8ms. I/04 5 36 I/013 · RAS CAS Refresh modes: only, BEFORE Vcc 6 35 Vss I/05 7 34 I/012 RAS (CBR) and HIDDEN. I/06 8 33 I/011 · Extended data-out (EDO) PAGE MODE I/07 9 32 I/010 access cycle. I/08 10 31 I/09 · BYTE WRITE and BYTE READ access TSOP(II) cycles. NC 11 30 NC OPTION NC 12 29 CASL TIMING EDO MARKING WE 13 28 CASH 22ns 125 MHz -22 RAS 14 27 OE 25ns 100 MHz -25 NC 15 26 A8 28ns 100 MHz -28 A0 16 25 A7 35ns 83 MHz -35 A1 17 24 A6 45ns 60 MHz -45 A2 18 23 A5 50ns 50 MHz -50 A3 19 22 A4 PACKAGE MARKING Vcc 20 21 VSS SOJ J TSOP(II) S Vcc 1 40 Vss I/01 2 39 I/016 GENERAL DESCRIPTION I/02 3 38 I/015 The T224162B is a randomly accessed solid state I/03 4 37 I/014 I/04 5 36 I/013 memory containing 4,194,304 bits organized in a x16 Vcc 6 35 Vss configuration. The T224162B has both BYTE I/05 7 34 I/012 WRITE and WORD WRITE access cycles via two I/06 8 33 I/011 I/07 9 32 I/010 CAS pins. It offers Fast Page mode with Extended I/08 10 31 I/09 Data Output. SOJ NC 11 30 NC The T224162B CAS function and timing are NC 12 29 CASL WE 13 28 CASH CAS determined by the first to transition low and RAS 14 27 OE by the last to transition back high. Use only one of NC 15 26 A8 CAS the two and leave the other staying high during A0 16 25 A7 A1 17 24 A6 WRITE will result in a BYTE WRITE. CASL A2 18 23 A5 transiting low in a WRITE cycle will write data into A3 19 22 A4 CASH the lower byte (IO1~IO8), and transiting low Vcc 20 21 VSS will write data into the upper byte (IO9~16). Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B FUNCTIONAL BLOCK DIAGRAM WE CASL CONTROL CAS DATA-IN BUFFER LOGIC CASH DQ01 . 16 . NO.2 CLOCK DQ16 GENERATOR DATA-OUT BUFFER COLUMN. COLUMN OE ADDRESS 9 9 DECODER BUFFER 16 A0 512 A1 REFRESH 8 8 CONTROLLER A2 SENSE AMPLIFIERS A3 VO GATING A4 REFRESH 512 x 16 A5 COUNTER A6 A7 9 A8 ROW. 512 x 512 x 16 512 MEMORY 9 ADDRESS 9 BUFFERS(9) ARRAY Vcc NO.1 CLOCK RAS GENERATOR Vss PIN DESCRIPTIONS PIN NO. SYM. TYPE DESCRIPTION 16~19,22~26 A0-A8 Input Address Input 14 RAS Input Row Address Strobe 28 CASH Input Column Address Strobe /Upper Byte Control 29 CASL Input Column Address Strobe /Lower Byte Control 13 WE Input Write Enable 27 OE Input Output Enable 2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output 1,6,20 Vcc Supply Power, 5V 21,35,40 Vss Ground Ground 11,12,15,30 NC - No Connect Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date:AUG. 2000 to change products or specifications without notice. Revision:L ROW DECODER TE tmCH T224162B ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Voltage on Any pin Relative to VSS..... -1V to +7V Maximum Ratings" may cause permanent damage to ° ° Operating Temperature, Ta (ambient) ..0 C to +70 C the device. This is a stress rating only and functional ° ° Storage Temperature (plastic)........ -55 C to +150 C operation of the device at these or any other conditions above those indicated in the operational Power Dissipation ............................…........... sections of this specification is not implied. Exposure 1.0W to absolute maximum rating conditions for extended Short Circuit Output Current.......…............... 50mA periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS ° £ £ ° ± (0 C Ta 70 C; VCC = 5V 10 % unless otherwise noted) DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES Supply Voltage Vcc 4.5 5.5 V 1 Supply Voltage Vss 0 0 V Input High (Logic) voltage V 2.4 Vcc+1 V 1 IH Input Low (Logic) voltage V -1.0 0.8 V 1 IL Input Leakage Current 0V £ V £ 7V I -10 10 uA IN LI £ £ 0V V 7V OUT Output Leakage Current I -10 10 uA LO Output(s) disabled Output High Voltage I = -5 mA V 2.4 Vcc V OH OH Output Low Voltage I = 4.2 mA V 0 0.4 V OL OL Note: 1.All Voltages referenced to Vss MAX DESCRIPTION CONDITIONS SYM. -22 -25 -28 -35 -45 -50 UNITS NOTES t Operating Current 1,2 RAS CAS Icc1 190 180 170 150 130 110 mA , cycling , RC = min TTL interface, RAS , 4 4 4 4 4 4 mA CAS =V , D =High-Z IH OUT Standby Current I cc2 CMOS interface, RAS , CAS > 2 2 2 2 2 2 mA Vcc-0.2V 2 RAS -only refresh t RC = min I 190 180 170 150 130 110 mA cc3 Current Standby Current 1 RAS =V CAS =V I 5 5 5 5 5 5 mA cc5 IH, IL CAS Before RAS t RC = min Icc6 190 180 170 150 130 110 mA Refresh Current t EDO Page Mode Current PC = min Icc7 190 180 170 150 130 110 mA 1,3 1. Icc depends on output load condition when the device is selected. Note: Icc max is specified at the output open condition. 2. Address can be changed twice or less while = V . RAS IL 3. Address can be changed once or less while = V . CAS IH Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B CAPACITANCE ° ± (Ta =25 C, Vcc =5V 10 %) Parameter Symbol Typ Max Unit Notes Input Capacitance (address) C - 5 pF 1 I1 Input Capacitance (clocks) C - 7 pF 1 I2 Output Capacitance (data-in, data-out) C - 10 pF 1 I/O 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. Note: (note 14) AC ELECTRICAL CHARACTERISTICS ° ± (Ta =0 to 70 C, Vcc=5V 10 %, Vss=0V) Input timing reference levels: 0.8V, 2.4V (note 29) Test Conditions Output Load: 2TTL gate + C (50pF) L -22 -25 -28 -35 -45 -50 AC CHARACTERISTICS UNIT SYM Notes MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX PARAMETER t 42 45 48 65 85 100 Read or Write Cycle Time ns RC Read Write Cycle Time t 62 65 70 95 115 135 ns RWC EDO-Page-Mode Read or t 8 10 10 12 16 20 ns 22 PC Write Cycle Time EDO-Page-Mode Read- t 30 32 34 40 46 57 ns 22 PCM Write Cycle Time t 22 25 28 35 45 50 ns 4 Access Time From RAS RAC t 7 7 7 9 11 13 ns 5,20 Access Time From CAS CAC OE t 8 8 8 9 11 13 ns 13,20 Access Time From OAC Access Time From Column t 11 12 13 15 19 23 ns AA Address Access Time From CAS t 13 14 15 18 22 26 ns 20 ACP Precharge t 22 10K 25 10K 28 10K 35 10K 45 10K 50 10K ns RAS Pulse Width RAS RAS Pulse Width t 22 100K 25 100K 28 100K 35 100K 45 100K 50 100K ns RASC (EDO Page Mode) t 7 7 7 9 11 13 ns 27 RAS Hold Time RSH t 15 15 17 25 35 37 ns RAS Precharge Time RP t 4 10K 4 10K 4 10K 4 10K 6 10K 8 10K ns 26 CAS Pulse Width CAS t 19 20 22 30 40 50 ns 19 CAS Hold Time CSH CAS Precharge Time t 3 3 3 3 5 6 ns 23 CP (EDO Page Mode) t 9 15 10 17 10 19 10 26 10 34 19 37 ns 7,18 RAS to CAS Delay Time RCD CAS RAS to Precharge t 3 3 3 3 5 5 ns 19 CRP Time Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date:AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B (continued ) AC ELECTRICAL CHARACTERISTICS -22 -25 -28 -35 -45 - 50 AC CHARACTERISTICS SYM UNIT Notes MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX PARAMETER t 0 0 0 0 0 0 ns Row Address Setup Time ASR t 5 5 5 5 5 5 ns Row Address Hold Time RAH 8 RAS to Column Address t 8 11 8 12 8 13 8 20 8 26 10 29 ns RAD Delay Time Column Address Setup Time t 0 0 0 0 0 0 ns 18 ASC Column Address Hold Time t 4 4 4 4 6 7 ns 18 CAH Column Address Hold Time t 17 19 21 30 40 45 ns AR RAS (Reference to ) Column Address to RAS t 11 12 13 15 19 23 ns RAL Lead Time t 0 0 0 0 0 0 ns Read Command Setup Time 15,18 RCS Read Command Hold Time 9,15, t 0 0 0 0 0 0 ns RCH 19 CAS Reference to Read Command Hold Time 9 t 0 0 0 0 0 0 ns RRH RAS Reference to t 3 3 3 3 3 3 ns 20 CAS to Output in Low-Z CLZ Output Buffer Turn-off 10,17, t 3 3 3 3 15 3 15 3 15 ns OFF1 20 CAS RAS Delay From or Output Buffer Turn-off to 17,28 t 8 8 8 8 8 8 ns OFF2 OE 11,15, t 0 0 0 0 0 0 ns Write Command Setup Time WCS 18 t 4 4 4 4 6 7 ns Write Command Hold Time 15,27 WCH Write Command Hold Time 15 t 19 19 21 30 46 51 ns WCR RAS (Reference to ) Write Command Pulse 15 t 4 4 4 4 6 8 ns WP Width 15 Write Command to RAS t 6 6 6 7 9 10 ns RWL Lead Time 15,19 CAS Write Command to t 5 5 5 7 9 11 ns CWL Lead Time t 0 0 0 0 0 0 ns Data-in Setup Time 12,20 DS t 4 4 4 4 6 7 ns Data-in Hold Time 12,20 DH Data-in Hold Time t 19 19 21 30 40 45 ns DHR (Reference to RAS ) t 31 34 37 51 61 70 ns 11 RAS WE to Delay Time RWD (continued ) AC ELECTRICAL CHARACTERISTICS Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date:AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B -22 -25 -28 -35 -45 -50 AC CHARACTERISTICS SYM UNIT Notes MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX PARAMETER WE Column Address to t 21 21 24 31 35 43 ns 11 AWD Delay Time CAS WE t 17 17 18 25 27 33 ns 11,18 to Delay Time CWD Transition Time (rise or fall) t 1.5 50 1.5 50 1.5 50 2.5 50 2.5 50 2.5 50 ns 2,3 T t 8 8 8 8 8 Refresh Period (512 cycles) 8 ms REF RAS to CAS Precharge t 10 10 10 10 10 10 ns RPC Time CAS Setup Time (CBR t 5 5 5 10 10 10 ns 1,18 CSR REFRESH) CAS Hold Time (CBR t 7 7 7 10 10 10 ns 1,19 CHR REFRESH) OE Hold Time From WE t 4 4 4 4 6 8 ns 16 During Read-Modify-Write OEH Cycle OE CAS Low to High t 4 4 4 4 5 5 ns OES Setup Time OE High Hold Time From t 2 2 2 2 2 2 ns OEHC CAS High t 2 2 2 2 2 2 ns OE High Pulse Width OEP OE Setup Prior to CAS t 0 0 0 0 0 0 ns During Hidden Refresh ORD Cycle Last CAS Going Low to t 4 4 4 4 6 8 ns 21 CLCH CAS First Returning High CAS Data Output Hold After t 3 3 3 3 4 5 ns COH Returning Low Output Disable Delay From t 3 6 3 7 3 7 3 7 3 7 3 9 ns WHZ WE Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date:AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B Notes: 1. Enables on-chip refresh and address counters. OE goes low result in a LATE WRITE( - 2. V (2.4V) and V (0.8V) are reference IH IL controlled) cycle. levels for measuring timing of input signals. CAS 12. These parameters are referenced to Transition times are measured between V IH leading edge in EARLY WRITE cycles and and V . (2.4V) IL (0.8V) WE leading edge in LATE WRITE or READ- 3. In addition to meet the transition rate MODIFY-WRITE cycles. specification, all input signals must transit 13. During a READ cycle, if OE is low then taken between V and V in a monotonic manner. IH IL HIGH before CAS goes high, I/O goes open, 4. Assume that t < t (max). If t is RCD RCD RCD greater than the maximum recommended value if OE is tied permanently low, a LATE shown in this table, t will increase by the WRITE or READ-MODIFY-WRITE RAC amount that t exceeds the value shown. operation is not possible. RCD 5. Assume that t t (max) . 14. An initial pause of 100ms is required after RCD³ RCD RAS CAS RAS power-up followed by eight refresh 6. If is low at the falling edge of , data-out will be maintained from the previous cycles ( RAS only or CBR) before proper cycle. To initiate a new cycle and clear the RAS device operation is assured. The eight data-out buffer, CAS and RAS must be cycle wake-ups should be repeated any time pulsed high. the t refresh requirement is exceeded. REF 7. Operation within the t (max) limit ensures RCD 15. WRITE command is defined as WE going low. that tRAC(max) can be met. tRCD(max) is 16. LATE WRITE and READ-MODIFY-WRITE specified as a reference point only; if t is RCD cycles must have both t and t met OFF2 OEH greater than the specified t (max) limit, RCD ( OE high during WRITE cycle) in order to access time is controlled by t . CAC ensure that the output buffers will be open 8. Operation within the t limit ensures that RAD during the WRITE cycles. t (max) can be met. t (max) is RAC RAD 17. The I/Os open during READ cycles once specified as a reference point only; if t is RAD t or t occur. OFF1 OFF2 greater than the specified t (max) limit, RAD CAS 18. The first edge to transition low. access time is controlled by t . AA CAS 19. The last edge to transition high. 9. Either t or t must be satisfied for a RCH RRH 20. Output parameter (I/O) is referenced to READ cycle. 10. t (max) defines the time at which the corresponding CAS input, IO1~8 by CASL OFF1 output achieves the open circuit condition; it is CASH and IO9~16 by . not a reference to V or V . OH OL CAS CAS 21. Last falling edge to first rising edge. 11. t , t , t and t are WCS RWD AWD CWD 22. Last rising CAS edge to next cycle's last rising restrictive operating parameters in LATE CAS edge. WRITE and READ-MODIFY-WRITE cycles CAS CAS 23. Last rising edge to first falling edge. only. If t t (min), the cycle is an ³ WCS WCS 24. First IOs controlled by the first CAS to go low. EARLY WRITE cycle and the data output will remain an open circuit throughout the entire CAS 25. Last IOs controlled by the last to go high. cycle. If t t (min), t ³ ³ RWD RWD AWD CAS 26. Each must meet minimum pulse width. t (min) and t ³ t (min), the AWD CWD CWD 27. Last CAS to go low. cycle is READ-WRITE and the data output 28. All IOs controlled, regardless CASL and will contain data read from the selected cell. If CASH. neither of the above conditions is met, the state 29. Data outputs are measured with a load of 50pF. CAS of I/O (at access time and until and The output reference levels are V /V OH OL RAS OE or go back to V ) is indeterminate. IH =2.0V/0.8V; The input levels are V /V = IH IL OE held high and WE taken low after CAS 3.0V/0V. Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date:AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B READ CYCLE t RC t t R A S R P V IH RAS V IL t C S H t t R SH R R H t t t t C R P R C D C A S C L C H V CA SL,CA SH IH V IL t A R t t R A D R A L t t t t A S R R A H AS C C A H V IH ADDR V R O W C O L U M N R O W IL t t RC S R C H V WE IH V IL t A A t R A C N O TE 1 t t C A C OF F 1 t C L Z V OH I/O O P E N V A L ID D A T A O P E N V OL t t O A C OF F 2 V IH OE V IL EARLY WRITE CYCLE t R C t t R A S R P V IH RAS V IL t C S H t R SH t t t t C R P R C D C A S C L C H V IH CA SL,CAS H V IL t A R t t R AD R A L t t t t A S R R A H AS C C A H V IH A DDR R O W C O L U M N R O W V IL t C WL t R WL t WC R t t WC S WC H t WP V WE IH V IL t D H R t t D S D H V I/O IOH V V A L ID D A T A IOL V OE IH V IL DON'T CARE UNDEFINED Note: 1. t is referenced from the rising edge of RAS or CAS , whichever occurs last. OFF1 Taiwan Memory Technology, Inc. reserves the right P. 8 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) t R WC t t R A S R P V RAS IH V IL t C S H t R SH t t t t C R P R CD C A S C L C H V IH CA SL,CASH V IL t A R t t R A D R A L t t t t A S R R A H AS C C A H V IH A DDR V R O W C O L U M N R O W IL t t R WD C WL t t t RC S C WD R WL t t A WD WP V IH WE V IL t A A t R A C t C A C t t D S DH t CL Z V IOH I/O VA L ID D V A L ID D O P E N O P E N V OUT IN IOL t t t O A C OF F 2 OE H V IH OE V IL EDO-PAGE-MODE READ CYCLE t t R A S C R P V IH RAS V IL t t t C S H P C ( N O T E 2 ) R S H t t t t t t t t t t t C R P R C D C A S, C LC H C P C AS , C LC H C P C AS , C LC H C P N V IH CA SL,CA SH V IL t A R t t R A D R A L t t t t t t t t A S R R A H A S C C A H A S C C A H A S C C A H V ADDR IH V RO W C O L U M N C O L U MN C O L U M N R O W IL t t t R R H R C S R C H V IH WE V IL t t t A A A A A A t t t R A C A C P A C P t t t C A C C A C C A C N O T E 1 t t t C L Z C O H C L Z t O F F 1 V OH V A L ID V A L ID I/O V A L ID O P E N O P E N V D A T A D AT A t D A T A OL O E H C t t t O A C O A C O F F 2 t O FF 2 t O E S t V O E S IH OE V IL t O E P DON'T CARE UNDEF INED RAS CAS Note: 1. t is referenced from the rising edge of or , whichever occurs last. OFF1 CAS CAS 2. t can be measured from falling edge of to falling edge of , or from rising edge of PC CAS RAS to rising edge of . Both measurements must meet the t specification. PC Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B EDO-PAGE-MODE EARLY-WRITE CYCLE t t R A S C R P V IH RAS V IL t t t C S H P C R S H t t t t t t t t t t t C R P R C D CA S , C LC H C P C A S, C LC H C P C A S, C LC H C P N V IH CASL,CASH V IL t A R t t R A D R A L t t t t t t t t A S R R A H A S C C A H A S C C A H A S C C A H V IH ADDR RO W C O L U MN C O L U M N CO LU MN R O W V IL t t t C W L C W L C W L t t t t t t W C S W C H W C S W C H W C S W C H t t t W P W P W P V IH WE V IL t t W C R R W L t D H R t t t t t t D S D H D S D H D S D H V IOH I/O V A L ID D A T A V A L ID D A T A V A L ID D A T A V IOL V IH OE V IL EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) t t R A S C R P V IH RA S V IL t t t C S H P C M R S H t t t t t t t t t t t C R P R C D C A S , C L C H C P C A S , C L C H C P C A S , C LC H C P N V IH CA SL ,CASH V IL t A R t t R A D R A L t t t t t t t t A S R R A H A S C C A H A S C C A H A S C C A H V IH ADDR R O W C O L U MN C O L U MN C O L U MN RO W V IL t R W D t R W L t R C S t t t C W L C W L C W L t t t W P W P W P t t t A W D A W D A W D t t t C W D C W D C W D V IH WE V IL t t t A A A A A A t R A C t t D H D H t D H t t A C P A C P t t t D S D S D S t t C A C t C A C C A C t t t C L Z C L Z C L Z V IOH VAL I D VA LI D VAL I D VA LI D VAL I D VAL I D I/O O P E N O P E N D D D D D D V OU T I N O U T I N O U T I N IOL t t t O F F 2 O F F 2 O F F 2 t t t t O E H O A C O A C O A C V IH OE V IL DON'T CAR E UNDEF INED Note: 1. t can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of PC CAS . Both measurements must meet the tPC specification. Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE) t t R A S C R P V IH RA S V IL t C S H t t t P C P C R S H t t t t t t t t C R P R C D C A S C P C A S C P C A S C P V IH CAS V IL t t A R R A L t R AD t t t t t t t t A S R R A H A S C C A H A S C C A H A S C C A H V IH ADDR V R O W C O L U M N ( A ) C O L U M N ( B ) C O L U M N (N ) R O W IL t R C H t t t R C S WC S WC H V IH WE V IL t A A t A A t t AC P WH Z t R A C t t t D S D H C A C t C A C t C O H V IOH V A L ID VALID DATA I/O V O P E N V A L I D D A T A ( A ) IOL D A T A (B ) IN t O A C V IH OE V IL RAS ONLY REFRESH CYCLE (ADDR=A0-A8 ; =DON‘T CARE) OE , WE t R C t t R A S R P V IH RAS V IL t t C R P RP C V IH CA SL,CA SH V IL t t A S R R A H V A DDR IH V R O W R O W IL V OH I/O V O P E N OL DON'T CARE UNDEFINED Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B CBR REFRESH CYCLE (A0-A8 ; OE =DON‘T CARE) t t t t R P R A S R P R A S V IH RA S V IL t R P C t t t t t t C P N C S R C H R RP C C S R C H R V IH CA SH,CA S L V IL I/O O P E N V IH WE V IL HIDDEN REFRESH CYCLE WE =HIGH ; OE =LOW) ( ( R E A D ) (R E F R E SH ) t t t R A S R P R A S V IH RAS V IL t t t t C R P R C D R SH C H R V IH CAS L,CA SH V IL t A R t t R A D R A L t t t t A S R R A H A S C C A H V IH ADDR V R O W C O L U MN IL t A A t R A C N OT E1 t C A C t O F F 1 t C L Z V OH I/O O P EN V AL ID D A T A O P EN V OL t t O A C O F F 2 t V ORD OE IH V IL DON'T CARE UNDEFINED RAS CAS Note: 1. t is referenced from the rising edge of or , whichever occurs last. OFF1 Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM ± ± A 1.025 0.010 26.035 0.254 ± ± B 0.400 0.005 10.160 0.127 C 0.045(MAX) 1.143(MAX) ± ± D 0.050 0.006 1.27 0.152 ± ± E 0.019 0.003 0.483 0.08 F 0.026±0.003 0.661±0.080 G 0.440±0.010 11.176±0.254 ± ± H 0.011 0.003 0.280 0.080 I 0.025(MIN) 0.635(MIN) ± ± J 0.364 0.020 9.246 0.508 ± ± K 0.047 0.006 1.194 0.152 L 0.150(MAX) 3.810(MAX) y 0.004(MAX) 0.102(MAX) Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L TE tmCH T224162B PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil) "A" SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.047(max) 1.20(max) A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.014(typ.) 0.35(typ.) e 0.030(typ.) 0.80(typ.) D 0.725±0.004 18.41±0.10 E 0.463±0.008 11.76±0.20 E1 0.400±0.004 10.16±0.10 L1' 0.031 0.80 L' 0.020±0.004 0.500±0.10 y 0.004(max) 0.10(max) q 0°~5° 0°~5° Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: AUG. 2000 to change products or specifications without notice. Revision:L