The Embedded I/O Company TIP630 Reconfigurable FPGA with 48 TTL I/O Application Information Technical Information  Interface according to IndustryPack specification The TIP630 is an IndustryPack® compatible module  Single Size IndustryPack providing a user configurable FPGA with 200,000 system  Xilinx XC2S200-5 SpartanII FPGA logic configurable gates. 48 I/O lines of the FPGA are directly connected to via IP bus or optional by PROM XC17S200APD8I the IP I/O connector. Each I/O line has a series damping resistor and is protected against ESD and overvoltage. Six  All IP bus interface signals routed to the FPGA pull up resistor networks mounted in sockets are provided  FPGA clock options: for the I/O lines. Pull up voltage is selectable to be either  IP bus clock (8 or 32 MHz) +3.3V or +5V. The I/O lines are individually programmable  Local 32 MHz clock oscillator as input, output or tri-state I/O.  PLL programmable clock generator CY22150 All IP bus signals of the IP interface are routed to the FPGA (250 KHz – 166 MHz), 2 clock outputs connected allowing to implement 8 MHz or 32 MHz bus interfaces with to FPGA or without DMA.  48 digital TTL I/O lines Several clock sources are available at the FPGA: the IP  I/O lines individually programmable as input, clock (8 MHz or 32 MHz), a local 32 MHz clock and two output, tri-state I/O outputs of the programmable clock generator (250 KHz –  6 pull up resistor networks mounted in sockets 166 MHz).  jumper selectable +3.3V or +5V common for all pull up resistor networks  ESD and overvoltage protection for each I/O line  Operating temperature range -40°C to +85°C The FPGA can be configured via the IP bus or optional by a PROM which can be mounted in a socket. The configuration download for the FPGA and the programming of the clock generator is implemented by a CPLD reserving the upper two 16 bit registers of the IP I/O space. After the FPGA has been configured with the user application it can be accessed via the IP bus. The CPLD can be used for Order Information reprogramming the FPGA without turning power off. TIP630-10 Reconfigurable FPGA logic with 48 Furthermore the CPLD offers a default ID-Prom contents TTL I/O lines which can stay active after configuring the FPGA or it can be switched off and replaced by a user ID-PROM TIP630-DOC User Manual implemented in the FPGA. TIP630-ED Engineering Documentation, includes User applications can be developed using the design TIP630-DOC software ISE WebPACK which can be downloaded free of charge from www.xilinx.com . TIP630-SW-12 OS-9 Software Support For First Time Users the Engineering Documentation TIP630-SW-32 pSOS Software Support TIP630-ED is recommended. The Engineering TIP630-SW-42 VxWorks Software Support Documentation includes TIP630-DOC, schematics, data TIP630-SW-62 Windows NT 4.0 Software Support sheets / application notes of the components and well documented sample VHDL source code. TIP630-SW-65 Windows XP/2000 Software Support TIP630-SW-72 LynxOS Software Support Software support (TIP630-SW-xx) is available for different operating systems. TIP630-SW-82 LiNUX Software Support TIP630-SW-92 QNX 4 Software Support TIP630- SW-95 QNX 6 Software Support TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice 03/2004 IndustryPack is a registered trademark of SBS Technologies, Inc. TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek / Germany 1 E. Liberty Street, Sixth Floor Reno, Nevada 89504 / USA Phone: +49-(0)4101-4058-0 Fax: +49-(0)4101-4058-19 Phone: +1 (775) 686 6077 Fax: +1 (775) 686 6024 E-mail: info@tews.com www.tews.com E-mail: usasales@tews.com www.tews.com