ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET ■ HIGH PERFORMANCE 32 OR 40 MHZ CPU WITH DSP FUNCTION – 16-bit CPU With 4-stage Pipeline – 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or 32MHz) Max CPU Clock – Multiply/accumulate Unit (Mac) 16 X 16-bit Multipli- PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack) cation, 40-bit Accumulator – Repeat Unit – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operat- ing Systems – Single-cycle Context Switching Support ■ MEMORY ORGANIZATION TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack) – 128K or 256K Byte On-chip Flash Memory Single Volt- ■ TWO CAN 2.0B INTERFACES OPERATING ON age With Erase/program Controller ONE OR TWO CAN BUSSES (30 OR 2x15 – Up to 1K Erasing/programming Cycles MESSAGE OBJECTS) ■ FAIL-SAFE PROTECTION – Up to 16 MByte Linear Address Space For Code And Data (5 MBytes With CAN) – Programmable Watchdog Timer – 2K Byte On-chip Internal RAM (IRAM) – Oscillator Watchdog – 10K Byte On-chip Extension RAM (XRAM) ■ ON-CHIP BOOTSTRAP LOADER ■ FAST AND FLEXIBLE BUS ■ CLOCK GENERATION – Programmable External Bus Characteristics for Dif- – On-chip PLL ferent Address Ranges – Direct or Prescaled Clock Input – 8-bit or 16-bit External Data Bus ■ REAL TIME CLOCK – Multiplexed or Demultiplexed External Address/data ■ UP TO 111 GENERAL PURPOSE I/O LINES Buses – Individually Programmable as Input, Output or Spe- – Five Programmable Chip-select Signals cial Function – Hold-acknowledge Bus Arbitration Support – Programmable Threshold (Hysteresis) ■ INTERRUPT ■ IDLE AND POWER DOWN MODES – 8-channel Peripheral Event Controller for Single Cy- ■ SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED cle Interrupt Driven Data Transfer REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY). – 16-priority-level Interrupt System with 56 Sources, ° ■ TEMPERATURE RANGES: -40 +125 C / -40 to 85°C Sampling Rate Down to 25ns at 40MHz (31.25ns at ■ 144-PIN PQFP/TQFP PACKAGES 32MHz) 16 32 ■ TIMERS 2K Byte 128K or 256KByte 16 Internal Flash Memory CPU-Core and MAC Unit RAM – Two Multi-functional General Purpose Timer Units with 5 Timers Watchdog 16 ■ TWO 16-CHANNEL CAPTURE / COMPARE UNITS 10K Byte PEC Oscillator XRAM and PLL ■ A/D CONVERTER CAN1_RXD CAN1 XTAL1 XTAL2 – 16-channel 10-bit CAN1_TXD Interrupt Controller 16 Voltage 3.3V CAN2_RXD CAN2 Regulator – 4.85µs Conversion Time at 40MHz CPU Clock CAN2_TXD (6.06µs at 32MHz) ■ 4-CHANNEL PWM UNIT 16 ■ SERIAL CHANNELS 16 – Synchronous / Asynchronous Serial Channel 16 BRG BRG – High-speed Synchronous Channel 8 Port 6 Port 5 Port 3 Port 7 Port 8 8 16 15 8 8 September 2003 1/184 Port 4 Port 1 Port 0 External Bus Controller 10-Bit ADC GPT2 GPT1 ASC usart SSC PWM CAPCOM2 CAPCOM1 Port 2 ST10F269 TABLE OF CONTENTS PAGE ST10F269 1 - Introduction ................................................................................................................. 6 2 - Pin Data ...................................................................................................................... 7 3 - Functional Description .............................................................................................. 13 4 - Memory Organization ............................................................................................... 14 5 - Internal Flash Memory .............................................................................................. 17 5.1 - OVERVIEW ................................................................................................................... 17 5.2 - OPERATIONAL OVERVIEW ........................................................................................17 5.3 - ARCHITECTURAL DESCRIPTION .............................................................................. 19 5.3.1 - Read Mode .................................................................................................... 19 5.3.2 - Command Mode ............................................................................................ 19 5.3.3 - Ready/Busy Signal ........................................................................................19 5.3.4 - Flash Status Register .................................................................................... 19 5.3.5 - Flash Protection Register .............................................................................. 21 5.3.6 - Instructions Description .................................................................................21 5.3.7 - Reset Processing and Initial State ................................................................ 26 5.4 - FLASH MEMORY CONFIGURATION .......................................................................... 26 5.5 - APPLICATION EXAMPLES .......................................................................................... 26 5.5.1 - Handling of Flash Addresses ........................................................................ 26 5.5.2 - Basic Flash Access Control ........................................................................... 27 5.5.3 - Programming Examples ................................................................................ 28 5.6 - BOOTSTRAP LOADER .............................................................................................. 31 5.6.1 - Entering the Bootstrap Loader ...................................................................... 31 5.6.2 - Memory Configuration After Reset ................................................................ 32 5.6.3 - Loading the Startup Code ............................................................................. 33 5.6.4 - Exiting Bootstrap Loader Mode .....................................................................33 5.6.5 - Choosing the Baud Rate for the BSL ............................................................ 34 6 - Central Processing Unit (CPU) ................................................................................. 35 6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ............................................................... 36 6.1.1 - Features ........................................................................................................ 37 6.1.1.1 -Enhanced Addressing Capabilities .................................................. 37 6.1.1.2 -Multiply-Accumulate Unit.................................................................. 37 6.1.1.3 -Program Control............................................................................... 37 6.2 - INSTRUCTION SET SUMMARY .................................................................................. 38 6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ................................................... 39 7 - External Bus Controller ............................................................................................. 43 7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................... 43 7.2 - READY PROGRAMMABLE POLARITY ....................................................................... 43 8 - Interrupt System ....................................................................................................... 45 8.1 - EXTERNAL INTERRUPTS ........................................................................................... 45 8.2 - INTERRUPT REGISTERS AND VECTORS LOCATION LIST ..................................... 46 8.3 - INTERRUPT CONTROL REGISTERS ......................................................................... 47 2/184 ST10F269 TABLE OF CONTENTS PAGE 8.4 - EXCEPTION AND ERROR TRAPS LIST .....................................................................48 9 - Capture/Compare (CAPCOM) Units ......................................................................... 49 10 - General Purpose Timer Unit ..................................................................................... 52 10.1 - GPT1 ............................................................................................................................. 52 10.2 - GPT2 ............................................................................................................................. 53 11 - PWM Module ............................................................................................................ 56 12 - Parallel Ports ............................................................................................................ 57 12.1 - INTRODUCTION ...........................................................................................................57 12.2 - I/O’S SPECIAL FEATURES .......................................................................................... 59 12.2.1 - Open Drain Mode .......................................................................................... 59 12.2.2 - Input Threshold Control ............................................................................... 59 12.2.3 - Output Driver Control .................................................................................. 60 12.2.4 - Alternate Port Functions ................................................................................ 62 12.3 - PORT0 .......................................................................................................................... 63 12.3.1 - Alternate Functions of PORT0 ...................................................................... 64 12.4 - PORT1 .......................................................................................................................... 66 12.4.1 - Alternate Functions of PORT1 ...................................................................... 66 12.5 - PORT 2 .........................................................................................................................68 12.5.1 - Alternate Functions of Port 2 ......................................................................... 68 12.6 - PORT 3 .........................................................................................................................71 12.6.1 - Alternate Functions of Port 3 ......................................................................... 73 12.7 - PORT 4 .........................................................................................................................76 12.7.1 - Alternate Functions of Port 4 ......................................................................... 77 12.8 - PORT 5 .........................................................................................................................80 12.8.1 - Alternate Functions of Port 5 ......................................................................... 81 12.8.2 - Port 5 Schmitt Trigger Analog Inputs ............................................................ 82 12.9 - PORT 6 .........................................................................................................................82 12.9.1 - Alternate Functions of Port 6 ......................................................................... 83 12.10 - PORT 7 .........................................................................................................................86 12.10.1 - Alternate Functions of Port 7 ......................................................................... 87 12.11 - PORT 8 .........................................................................................................................90 12.11.1 - Alternate Functions of Port 8 ......................................................................... 91 13 - A/D Converter ........................................................................................................... 93 14 - Serial Channels ........................................................................................................ 95 14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) ....................... 95 14.1.1 - ASCO in Asynchronous Mode ....................................................................... 95 14.1.2 - ASCO in Synchronous Mode ........................................................................ 98 14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ...................................... 101 15 - CAN Modules .......................................................................................................... 103 15.1 - CAN MODULES MEMORY MAPPING .......................................................................103 15.1.1 - CAN1 ...........................................................................................................103 15.1.2 - CAN2 ...........................................................................................................103 15.2 - CAN BUS CONFIGURATIONS ................................................................................... 103 3/184 ST10F269 TABLE OF CONTENTS PAGE 16 - Real Time Clock ..................................................................................................... 105 16.1 - RTC REGISTERS .......................................................................................................106 16.1.1 - RTCCON: RTC Control Register .................................................................106 16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers ....................................... 108 16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters ...............................................108 16.1.4 - RTCH & RTCL: RTC Programmable COUNTER Registers ........................109 16.1.5 - RTCAH & RTCAL: RTC ALARM Registers ................................................. 110 16.2 - PROGRAMMING THE RTC ........................................................................................110 17 - Watchdog Timer ..................................................................................................... 112 18 - System Reset ......................................................................................................... 114 18.1 - LONG HARDWARE RESET .......................................................................................114 18.1.1 - Asynchronous Reset ...................................................................................114 18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level) .115 18.1.3 - Exit of Long Hardware Reset ......................................................................116 18.2 - SHORT HARDWARE RESET .....................................................................................116 18.3 - SOFTWARE RESET ...................................................................................................117 18.4 - WATCHDOG TIMER RESET ......................................................................................117 18.5 - RSTOUT, RSTIN, BIDIRECTIONAL RESET ..............................................................118 18.5.1 - RSTOUT Pin ...............................................................................................118 18.5.2 - Bidirectional Reset ......................................................................................118 18.5.3 - RSTIN pin ....................................................................................................118 18.6 - RESET CIRCUITRY ....................................................................................................118 19 - Power Reduction Modes ......................................................................................... 122 19.1 - IDLE MODE ................................................................................................................122 19.2 - POWER DOWN MODE ..............................................................................................122 19.2.1 - Protected Power Down Mode ......................................................................122 19.2.2 - Interruptible Power Down Mode ..................................................................122 20 - Special Function Register Overview ....................................................................... 125 20.1 - IDENTIFICATION REGISTERS ..................................................................................131 20.2 - SYSTEM CONFIGURATION REGISTERS ................................................................132 21 - Electrical Characteristics ........................................................................................ 139 21.1 - ABSOLUTE MAXIMUM RATINGS .............................................................................. 139 21.2 - PARAMETER INTERPRETATION .............................................................................139 21.3 - DC CHARACTERISTICS ............................................................................................139 21.3.1 - A/D Converter Characteristics .....................................................................144 21.3.2 - Conversion Timing Control ........................................................................145 21.4 - AC CHARACTERISTICS ............................................................................................146 21.4.1 - Test Waveforms .........................................................................................146 21.4.2 - Definition of Internal Timing .........................................................................146 21.4.3 - Clock Generation Modes .............................................................................148 21.4.4 - Prescaler Operation ....................................................................................149 21.4.5 - Direct Drive ..................................................................................................149 21.4.6 - Oscillator Watchdog (OWD) ........................................................................ 149 4/184 ST10F269 TABLE OF CONTENTS PAGE 21.4.7 - Phase Locked Loop .....................................................................................149 21.4.8 - External Clock Drive XTAL1 ........................................................................150 21.4.9 - Memory Cycle Variables .............................................................................151 21.4.10 - Multiplexed Bus ........................................................................................... 152 21.4.11 - Demultiplexed Bus ......................................................................................160 21.4.12 - CLKOUT and READY .................................................................................168 21.4.13 - External Bus Arbitration ...............................................................................171 21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ............................174 21.4.14.1Master Mode ................................................................................ 174 21.4.14.2Slave mode .................................................................................. 175 22 - Package Mechanical Data ..................................................................................... 178 23 - Ordering Information ............................................................................................... 180 ERRATA SHEET 1 - DESCRIPTION ....................................................................................................... 181 2 - FUNCTIONAL PROBLEMS .................................................................................... 181 2.1 - PWRDN.1 - EXECUTION OF PWRDN INSTRUCTION .............................................181 2.2 - MAC.9 - COCMP INSTRUCTION INVERTED OPERANDS .......................................182 2.3 - MAC.10 - E FLAG EVALUATION FOR COSHR AND COASHR INSTRUCTIONS WHEN SATURATION MODE IS ENABLED ........................................................................... 182 2.4 - ST_PORT.3 - BAD BEHAVIOR OF HYSTERESIS FUNCTION ON INPUT FALLING EDGE ..........................................................................................................................183 3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION ............................ 183 4 - ERRATA SHEET VERSION INFORMATION ......................................................... 183 5/184 1 - INTRODUCTION ST10F269 1 - INTRODUCTION The ST10F269 is a derivative of the frees up the CPU during programming or STMicroelectronics ST10 family of 16-bit erasing the Flash. single-chip CMOS microcontrollers. It combines – 128-KByte Flash Option high CPU performance (up to 20 million – Two dedicated pins (DC1 and DC2) on the instructions per second) with high peripheral 144-pin package are used for decoupling the functionality and enhanced I/O-capabilities. It also internally generated 3.3V (or 2.7V on TQFP144 provides on-chip high-speed single voltage Flash devices) core logic supply. Do not connect memory, on-chip high-speed RAM, and clock these two pins to 5.0V external supply. generation via PLL. Instead, these pins should be connected to a decoupling capacitor (ceramic type, value ≥ 330 ST10F269 is processed in 0.35μm CMOS nF). technology. The MCU core and the logic is – The A/D Converter characteristics are different supplied with a 5V to 3.3V on chip voltage from previous ST10 derivatives ones. Refer to regulator on PQFP144 devices (or 5V to 2.7V on Section 21.3.1 -. TQFP144 devices). The part is supplied with a – The AC and DC parameters are adapted to the single 5V supply and I/Os work at 5V. 40MHz maximum CPU frequency on PQFP144 The device is upward compatible with the devices (32MHz on TQFP144 devices). The ST10F168 device, with the following set of characterization is performed with C = 50pF L differences: max on output pins. Refer to Section 21.3 -. – In order to reduce EMC, the rise/fall time and the – The Multiply/Accumulate unit is available as sink/source capability of the drivers of the I/O standard. This MAC unit adds powerful DSP pads are programmable. Refer to Section 12.2 -. functions to the ST10 architecture, but maintains full compatibility for existing code. – The Real Time Clock functionality is added. – The external interrupt sources can be selected – Flash control interface is now based on with the EXISEL register. STMicroelectronics third generation of stand-alone Flash memories, with an embedded – The reset source is identified by a dedicated Erase/Program Controller. This completely status bit in the WDTCON register. Figure 1 : Logic Symbol V DC1 DC2 V DD SS XTAL1 Port 0 XTAL2 16-bit RSTIN Port 1 16-bit RSTOUT RPD Port 2 16-bit V AREF V AGND Port 3 ST10F269 15-bit NMI EA Port 4 8-bit READY Port 6 ALE 8-bit RD Port 7 WR/WRL 8-bit Port 5 16-bit Port 8 8-bit 6/184 ST10F269 2 - PIN DATA 2 - PIN DATA Figure 2 : Pin Configuration (top view) P6.0/CS0 1 108 P0H.0/AD8 2 P6.1/CS1 107 P0L.7/AD7 3 P6.2/CS2 106 P0L.6/AD6 4 P6.3/CS3 105 P0L.5/AD5 5 P6.4/CS4 104 P0L.4/AD4 6 P6.5/HOLD 103 P0L.3/AD3 7 P6.6/HLDA 102 P0L.2AD2 P6.7/BREQ 8 101 P0L.A/AD1 P8.0/CC16IO 9 100 P0L.0/AD0 P8.1/CC17IO 10 EA 99 P8.2/CC18IO 11 98 ALE P8.3/CC19IO 12 97 READY P8.4/CC20IO 13 96 WR/WRL 14 P8.5/CC21IO 95 RD 15 P8.6/CC22IO 94 V SS 16 P8.7/CC23IO 93 V DD 17 DC2 92 P4.7A23/CAN2_TxD 18 V SS 91 P4.6A22/CAN1_TxD 19 P7.0/POUT0 ST10F269 90 P4.5A21/CAN1_RxD P7.1/POUT1 20 89 P4.4A20/CAN2_RxD P7.2/POUT2 21 88 P4.3/A19 P7.3/POUT3 22 87 P4.2/A18 P7.4/CC28I0 23 86 P4.1/A17 P7.5/CC29I0 24 85 P4.0/A16 25 P7.6/CC30I0 84 RPD 26 P7.7/CC31I0 V 83 SS 27 P5.0/AN0 82 V DD 28 P5.1/AN1 81 P3.15/CLKOUT 29 P5.2/AN2 80 P3.13/SCLK 30 P5.3/AN3 79 P3.12/BHE/WRH P5.4/AN4 31 78 P3.11/RXD0 P5.5/AN5 32 77 P3.10/TXD0 P5.6/AN6 33 76 P3.9/MTSR P5.7/AN7 34 75 P3.8/MRST P5.8/AN8 35 74 P3.7/T2IN P5.9/AN9 36 73 P3.6/T3IN Table 1 : Pin Description 7/184 V AREF 37 V 144 V DD AGND 38 143 V P5.10/AN10/T6EUD 39 SS P5.11/AN11/T5EUD 40 142 NMI P5.12/AN12/T6IN RSTOUT 41 141 140 RSTIN P5.13/AN13/T5IN 42 139 V P5.14/AN14/T4EUD 43 SS 138 P5.15/AN15/T2EUD 44 XTAL1 V SS 45 137 XTAL2 V 46 V DD 136 DD P2.0/CC0IO 47 135 P1H.7/A15/CC27IO 134 P2.1/CC1IO 48 P1H.6/A14/CC26IO P2.2/CC2IO 49 133 P1H.5/A13/CC25IO 50 132 P1H.4/A12/CC24IO P2.3/CC3IO 131 P1H.3/A11 P2.4/CC4IO 51 52 130 P1H.2/A10 P2.5/CC5IO 129 P1H.1/A9 P2.6/CC6IO 53 128 P1H.0/A8 P2.7/CC7IO 54 V 127 V 55 SS SS DC1 126 V 56 DD P2.8/CC8IO/EX0IN 57 125 P1L.7/A7 124 P2.9/CC9IO/EX1IN 58 P1L.6/A6 123 P2.10/CC10IOEX2IN 59 P1L.5/A5 P2.11/CC11IOEX3IN 60 122 P1L.4/A4 P2.12/CC12IO/EX4IN 61 121 P1L.3/A3 62 120 P1L.2/A2 P2.13/CC13IO/EX5IN 63 119 P1L.1/A1 P2.14/CC14IO/EX6IN 64 118 P1L.0/A0 P2.15/CC15IO/EX7IN/T7IN 65 117 P0H.7/AD15 P3.0/T0IN 116 P0H.6/AD14 P3.1/T6OUT 66 67 115 P0H.5/AD13 P3.2/CAPIN 114 P0H.4/AD12 P3.3/T3OUT 68 P0H.3/AD11 P3.4/T3EUD 69 113 112 P0H.2/AD10 P3.5/T4IN 70 V P0H.1/AD9 71 111 SS V 72 V DD 110 SS V 109 DD 2 - PIN DATA ST10F269 Symbol Pin Type Function P6.0 - P6.7 1 - 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The following Port 6 pins have alternate functions: 1OP6.0 CS0 Chip Select 0 Output ... ... ... ... ... 5OP6.4 CS4 Chip Select 4 Output 6IP6.5 HOLD External Master Hold Request Input 7OP6.6 HLDA Hold Acknowledge Output 8 O P6.7 BREQ Bus Request Output P8.0 - P8.7 9-16 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins have alternate functions: 9 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output ... ... ... ... ... 16 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output P7.0 - P7.7 19-26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins have alternate functions: 19 O P7.0 POUT0 PWM Channel 0 Output ... ... ... ... ... 22 O P7.3 POUT3 PWM Channel 3 Output 23 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output ... ... ... ... ... 26 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output P5.0 - P5.9 27-36 I 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be P5.10 - P5.15 39-44 I the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs: 39 I P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input 40 I P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input 41 I P5.12 T6IN GPT2 Timer T6 Count Input 42 I P5.13 T5IN GPT2 Timer T5 Count Input 43 I P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input 44 I P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input 8/184 ST10F269 2 - PIN DATA Symbol Pin Type Function P2.0 - P2.7 47-54 I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction P2.8 - P2.15 57-64 bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: 47 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output ... ... ... ... ... 54 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output 57 I/O P2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output I EX0IN Fast External Interrupt 0 Input ... ... ... ... ... 64 I/O P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output I EX7IN Fast External Interrupt 7 Input I T7IN CAPCOM2 Timer T7 Count Input P3.0 - P3.5 65-70, I/O 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or P3.6 - P3.13, 73-80, I/O output via direction bit. Programming an I/O pin as input forces the corresponding P3.15 81 I/O output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins have alternate functions: 65 I P3.0 T0IN CAPCOM Timer T0 Count Input 66 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output 67 I P3.2 CAPIN GPT2 Register CAPREL Capture Input 68 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output 69 I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input 70 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture 73 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input 74 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture 75 I/O P3.8 MRST SSC Master-Receiver / Slave-Transmitter I/O 76 I/O P3.9 MTSR SSC Master-Transmitter / Slave-Receiver O/I 77 O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous / Synchronous) 78 I/O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous) 79 O P3.12 BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe 80 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input 81 O P3.15 CLKOUT System Clock Output (=CPU Clock) 9/184 2 - PIN DATA ST10F269 Symbol Pin Type Function P4.0 –P4.7 85-92 I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or special). Port 4.6 & 4.7 outputs can be configured as push-pull or open drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines: 85 O P4.0 A16 Segment Address Line 86 O P4.1 A17 Segment Address Line 87 O P4.2 A18 Segment Address Line 88 O P4.3 A19 Segment Address Line 89 O P4.4 A20 Segment Address Line I CAN2_RxD CAN2 Receive Data Input 90 O P4.5 A21 Segment Address Line I CAN1_RxD CAN1 Receive Data Input 91 O P4.6 A22 Segment Address Line O CAN1_TxD CAN1 Transmit Data Output 92 O P4.7 A23 Most Significant Segment Address Line O CAN2_TxD CAN2 Transmit Data Output RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low Byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. READY/ 97 I Ready Input. The active level is programmable. When the Ready function is READY enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level. ALE 98 O Address Latch Enable Output. In case of use of external addressing or of multi- plexed mode, this signal is the latch command of the address lines. EA 99 I External Access Enable pin. A low level applied to this pin during and after Reset forces the ST10F269 to start the program from the external memory space. A high level forces the MCU to start in the internal memory space. 10/184 ST10F269 2 - PIN DATA Symbol Pin Type Function P0L.0 - P0L.7, 100-107, I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or P0H.0 108, output via direction bit. Programming an I/O pin as input forces the corresponding P0H.1 - P0H.7 111-117 output driver to high impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7 I/O D8 - D15 Multiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7 A8 – A15 AD8 - AD15 P1L.0 - P1L.7 118-125 I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or P1H.0 - P1H.7 128-135 output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins have alternate functions: 132 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input 133 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input 134 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input 135 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1 138 I XTAL1 Oscillator amplifier and/or external clock input. XTAL2 137 O XTAL2 Oscillator amplifier circuit output. To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed. RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F269. An internal pull-up resistor permits power-on reset using only a capacitor connected to V . In bidirec- SS tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. RSTOUT 141 O Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of ini- tialization) instruction is executed. NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. V 37 - A/D converter reference voltage. AREF V 38 - A/D converter reference ground. AGND RPD 84 - Timing pin for the return from interruptible powerdown mode and synchronous / asynchronous reset selection. 11/184 2 - PIN DATA ST10F269 Symbol Pin Type Function V 46, 72, - Digital Supply Voltage: DD 82,93, = + 5V during normal operation and idle mode. 109, 126, 136, 144 V 18,45, - Digital Ground. SS 55,71, 83,94, 110, 127, 139, 143 DC1 56 - 3.3V Decoupling pin (2.7V on TQFP144 devices): a decoupling capacitor of ≥ 330 DC2 17 - nF must be connected between this pin and nearest V pin. SS 12/184 ST10F269 3 - FUNCTIONAL DESCRIPTION 3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F269 combines block diagram gives an overview of the different advantages of both RISC and CISC processors on-chip components and the high bandwidth and an advanced peripheral subsystem. The internal bus structure of the ST10F269. Figure 3 : Block Diagram 32 16 2K Byte 128K/256K Byte 16 Internal Flash Memory CPU-Core and MAC Unit RAM Watchdog 16 10K Byte PEC Oscillator XRAM and PLL P4.5 CAN1_RXD XTAL1 XTAL2 CAN1 P4.6 CAN1_TXD Interrupt Controller 16 3.3V Voltage P4.4 CAN2_RXD CAN2 Regulator P4.7 CAN2_TXD 16 16 16 BRG BRG 8 Port 7 Port 6 Port 5 Port 3 Port 8 8 8 16 15 8 13/184 Port 4 Port 1 Port 0 External Bus Controller 10-Bit ADC GPT1 GPT2 ASC usart SSC PWM CAPCOM2 CAPCOM1 Port 2 4 - MEMORY ORGANIZATION ST10F269 4 - MEMORY ORGANIZATION The memory space of the ST10F269 is configured which are used to control and to monitor the in a unified memory architecture. Code memory, function of the different on-chip units. data memory, registers and I/O ports are CAN1: Address range 00’EF00h - 00’EFFFh is organized within the same linear address space of reserved for the CAN1 Module access. The CAN1 16M Bytes. The entire memory space can be accessed Byte wise or Word wise. Particular is enabled by setting XPEN bit 2 of the SYSCON portions of the on-chip memory have additionally register and by setting CAN1EN bit 0 of the new been made directly bit addressable. XPERCON register. Accesses to the CAN Module Flash: 128K or 256K Bytes of on-chip Flash use demultiplexed addresses and a 16-bit data memory. bus (Byte accesses are possible). Two wait states give an access time of 100ns at 40MHz CPU clock IRAM: 2K Bytes of on-chip internal RAM on PQFP144 devices (or 125ns at 32MHz CPU (dual-port) is provided as a storage for data, clock on TQFP144 devices). No tri-state wait system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) states are used. and / or Bytewide (RL0, RH0, …, RL7, RH7) CAN2: Address range 00’EE00h - 00’EEFFh is general purpose registers. reserved for the CAN2 Module access. The CAN2 XRAM: 10K Bytes of on-chip extension RAM is enabled by setting XPEN bit 2 of the SYSCON (single port XRAM) is provided as a storage for register and by setting CAN2EN bit 1 of the new data, user stack and code. XPERCON register. Accesses to the CAN Module The XRAM is divided into 2 areas, the first 2K use demultiplexed addresses and a 16-bit data Bytes named XRAM1 and the second 8K Bytes bus (Byte accesses are possible). Two wait states named XRAM2, connected to the internal XBUS give an access time of 100ns at 40MHz CPU clock and are accessed like an external memory in on PQFP144 devices (or 125ns at 32MHz CPU 16-bit demultiplexed bus-mode without wait state clock on TQFP144 devices). No tri-state wait or read/write delay (50ns access at 40MHz CPU states are used. clock on PQFP144 devices and 62.5ns access at 32MHz CPU clock on TQFP144 devices). Byte In order to meet the needs of designs where more and Word accesses are allowed. memory is required than is provided on chip, up to The XRAM1 address range is 00’E000h 16M Bytes of external RAM and/or ROM can be - 00’E7FFh if XPEN (bit 2 of SYSCON register), connected to the microcontroller. and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any Note If one or the two CAN modules are used, Port access in the address range 00’E000h - 00’E7FFh 4 cannot be programmed to output all 8 will be directed to external memory interface, segment address lines. Thus, only 4 segment using the BUSCONx register corresponding to address lines can be used, reducing the address matching ADDRSELx register external memory space to 5M Bytes (1M Byte per CS line). The XRAM2 address range is 00’C000h - 00’DFFFh if XPEN (bit 2 of SYSCON register), Visibility of XBUS Peripherals and XRAM2 (bit 3 of XPERCON register are set). If bit XRAM2EN or XPEN is cleared, then any In order to keep the ST10F269 compatible with access in the address range 00’C000h the ST10C167 and with the ST10F167, the XBUS - 00’DFFFh will be directed to external memory peripherals can be selected to be visible and / or interface, using the BUSCONx register accessible on the external address / data bus. corresponding to address matching ADDRSELx CAN1EN and CAN2EN bits of XPERCON register register. must be set. If these bits are cleared before the As the XRAM appears like external memory, it global enabling with XPEN-bit in SYSCON cannot be used as system stack or as register banks. The XRAM is not provided for single bit register, the corresponding address space, port storage and therefore is not bit addressable. pins and interrupts are not occupied by the peripheral, thus the peripheral is not visible and SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of address space is reserved for the special function not available. Refer to Chapter : Special Function register areas. SFRs are Wordwide registers Register Overview on page 125. 14/184 ST10F269 4 - MEMORY ORGANIZATION Figure 4 : ST10F269 On-chip Memory Mapping RAM, SFR and X-pheripherals are mapped into the address space. 14 05’0000 00’FFFF Block6 = 64K Bytes* SFR : 512 Bytes 04’0000 10 00’FE00 00’FDFF Block5 = 64K Bytes* IRAM : 2K Bytes 0C 03’0000 00’F600 Block4 = 64K Bytes 00’F1FF 02’0000 08 ESFR : 512 Bytes 07 00’F000 Block3 = 32K Bytes Bank 1H 06 00’EFFF 01’8000 CAN1 : 256 Bytes 05 Block2** Block1** 00’EF00 Bank 1L Block0** 04 00’EEFF 01’0000 CAN2 : 256 Bytes 03 00’EE00 00’C000 00’EC14 02 Real Time Clock 00’EC00 Block2 = 8K Bytes 00’6000 01 Block1 = 8K Bytes 00’4000 00’E7FF Bank OL XRAM1 : 2K Bytes 00 Block0 = 16K Bytes 00’E000 00’0000 00’DFFF XRAM2 : 8K Bytes Data Absolute Internal Page Memory Flash 00’C000 Number Address Memory *Reserved area for 128K versions. ** Bank 0L may be remapped from segment 0 to segment 1 (Bank 1L) by setting SYSCON-ROMS1 (before EINIT) Data Page Number and Absolute Memory Address are hexadecimal values. 15/184 Segment 0 Segment 1 Segment 2 Segment 3 Segment 4 4 - MEMORY ORGANIZATION ST10F269 XPERCON (F024h / 12h) ESFR Reset Value: - - 05h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- --- - RTCEN - -- XRAM2EN XRAM1EN CAN2EN CAN1EN RW RW RW RW RW CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN is also ‘0’. ‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed. CAN2EN CAN2 Enable Bit ‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if CAN1EN is also ‘0’. ‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed. XRAM1EN XRAM1 Enable Bit ‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1 are disabled. ’1’: Accesses to the internal 2K Bytes of XRAM1. XRAM2EN XRAM2 Enable Bit ‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal XRAM2 are disabled. ’1’: Accesses to the internal 8K Bytes of XRAM2. RTCEN RTC Enable Bit ’0’: Accesses to the on-chip Real Time Clock are disabled, external access is performed. Address range 00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also ’1’: The on-chip Real Time Clock is enabled and can be accessed. Note: - When both CAN are disabled via XPER- The access to external memory and/or CON setting, then any access in the XBus is controlled by the bondout chip. address range 00’EE00h - 00’EFFFh will - When the Real Time Clock is disabled be directed to external memory interface, (RTCEN = 0), the clock oscillator is using the BUSCONx register correspond- switch-off if the ST10 enters in ing to address matching ADDRSELx regis- power-down mode. Otherwise, when the ter. P4.4 and P4.7 can be used as General Real Time Clock is enabled, the bit Purpose I/O when CAN2 is disabled, and RTCOFF of the RTCCON register allows P4.5 and P4.6 can be used as General to choose the power-down mode of the Purpose I/O when CAN1 is disabled. clock oscillator (See Chapter : Real Time - The default XPER selection after Reset is Clock on page 105). identical to XBUS configuration of ST10C167: XCAN1 is enabled, XCAN2 is disabled, XRAM1 (2K Byte compatible XRAM) is enabled, XRAM2 (new 8K Byte XRAM) is disabled. - Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after the setting of bit XPEN in the SYSCON register. - In EMUlation mode, all the XPERipherals are enabled (XPERCON bit are all set). 16/184 ST10F269 5 - INTERNAL FLASH MEMORY 5 - INTERNAL FLASH MEMORY 5.1 - Overview Access to data of internal Flash can only be per- formed with an inner protected program – 128K or 256K Byte on-chip Flash memory – Erase Suspend and Resume Modes – Two possibilities of Flash mapping into the CPU address space  Read and Program another Block during erase suspend – Flash memory can be used for code and data storage – Single Voltage operation, no need of dedicated supply pin – 32-bit, zero waitstate read access (50ns cycle time at f = 40MHz on PQFP144 devices and – Low Power Consumption: CPU 62.5ns cycle time at f = 32MHz on TQFP144 CPU  45mA max. Read current devices)  60mA max. Program or Erase current – Erase-Program Controller (EPC) similar to M29F400B STM’s stand-alone Flash memory Automatic Stand-by-mode (50 μA maximum)  Word-by-Word Programmable (16 μs typical) – 1000 Erase-Program Cycles per block, 20 years of data retention time  Data polling and Toggle Protocol for EPC o Status – Operating temperature: -40 to +125 C / -40 to o +125 C Ready/Busy signal connected on XP2INT interrupt line 5.2 - Operational Overview  Internal Power-On detection circuit Read Mode – Memory Erase in blocks In standard mode (the normal operating mode) One 16K Byte, two 8K Byte, one 32K Byte, one the Flash appears like an on-chip ROM with the to three 64K Byte blocks same timing and functionality. The Flash module  Each block can be erased separately offers a fast access time, allowing zero waitstate (1.5 second typical) access with CPU frequency up to 40MHz on PQFP144 devices and up to 32MHz on TQFP144 Chip erase (8.5 second typical) devices. Instruction fetches and data operand  Each block can be separately protected reads are performed with all addressing modes of against programming and erasing the ST10F269 instruction set.  Each protected block can be temporary unpro- In order to optimize the programming time of the tected internal Flash, blocks of 8KBytes, 16KBytes,  When enabled, the read protection prevents 32K Bytes, 64K Bytes can be used. But the size of access to data in Flash memory using a pro- the blocks does not apply to the whole memory gram running out of the Flash memory space. space, see details in Table 2. Table 2 : 128K or 256K Byte Flash Memory Block Organization Block Addresses (Segment 0) Addresses (Segment 1) Size (byte) 0 00’0000h to 00’3FFFh 01’0000h to 01’3FFFh 16K 1 00’4000h to 00’5FFFh 01’4000h to 01’5FFFh 8K 2 00’6000h to 00’7FFFh 01’6000h to 01’7FFFh 8K 3 01’8000h to 01’FFFFh 01’8000h to 01’FFFFh 32K 4 02’0000h to 02’FFFFh 02’0000h to 02’FFFFh 64K 5* 03’0000h to 03’FFFFh* 03’0000h to 03’FFFFh* 64K* 6* 04’0000h to 04’FFFFh* 04’0000h to 04’FFFFh* 64K* *Not available on 128K versions (reserved areas). 17/184 5 - INTERNAL FLASH MEMORY ST10F269 Instructions and Commands cycles can then be performed to erase more than one block in parallel. When a time-out period All operations besides normal read operations are elapses (96μs) after the last cycle, the initiated and controlled by command sequences Erase-Program Controller (EPC) automatically written to the Flash Command Interface (CI). The starts and times the erase pulse and executes the Command Interface (CI) interprets words written erase operation. There is no need to program the to the Flash memory and enables one of the block to be erased with ‘0000h’ before an erase following operations: operation. Termination of operation is indicated in – Read memory array the Flash status register. After erase operation, – Program Word the Flash memory locations are read as 'FFFFh’ – Block Erase value. – Chip Erase Erase Suspend – Erase Suspend A block erase operation is typically executed – Erase Resume within 1.5 second for a 64K Byte block. Erasure of – Block Protection a memory block may be suspended, in order to read data from another block or to program data in – Block Temporary Unprotection another block, and then resumed. – Code Protection In-System Programming Commands are composed of several write cycles at specific addresses of the Flash memory. The In-system programming is fully supported. No different write cycles of such command special programming voltage is required. Because sequences offer a fail-safe feature to protect of the automatic execution of erase and against an inadvertent write. programming algorithms, write operations are A command only starts when the Command reduced to transferring commands and data to the Interface has decoded the last write cycle of an Flash and reading the status. Any code that operation. Until that last write is performed, Flash programs or erases Flash memory locations (that memory remains in Read Mode writes data to the Flash) must be executed from memory outside the on-chip Flash memory itself Notes: 1. As it is not possible to perform write (on-chip RAM or external memory). operations in the Flash while fetching code from Flash, the Flash commands must be A boot mechanism is provided to support written by instructions executed from in-system programming. It works using serial link internal RAM or external memory. via USART interface and a PC compatible or other programming host. 2. Command write cycles do not need to Read/Write Protection be consecutively received, pauses are allowed, save for Block Erase command. The Flash module supports read and write During this operation all Erase Confirm protection in a very comfortable and advanced commands must be sent to complete any protection functionality. If Read Protection is block erase operation before time-out installed, the whole Flash memory is protected period expires (typically 96μs). Command against any "external" read access; read sequencing must be followed exactly. Any accesses are only possible with instructions invalid combination of commands will reset fetched directly from program Flash memory. For the Command Interface to Read Mode. update of the Flash memory a temporary disable of Flash Read Protection is supported. Status Register The device also features a block write protection. This register is used to flag the status of the Software locking of selectable memory blocks is memory and the result of an operation. This provided to protect code and data. This feature register can be accessed by read cycles during will disable both program and erase operations in the Erase-Program Controller (EPC) operation. the selected block(s) of the memory. Block Erase Operation Protection is accomplished by block specific This Flash memory features a block erase lock-bit which are programmed by executing a four architecture with a chip erase capability too. Erase cycle command sequence. The locked state of is accomplished by executing the six cycle erase blocks is indicated by specific flags in the command sequence. Additional command write according block status registers. A block may only 18/184 ST10F269 5 - INTERNAL FLASH MEMORY be temporarily unlocked for update (write) In the standard read mode read accesses are operations. directly controlled by the Flash memory array, delivering a 32-bit double Word from the With the two possibilities for write protection - addressed position. Read accesses are always whole memory or block specific - a flexible aligned to double Word boundaries. Thus, both installation of write protection is supported to low order address bit A1 and A0 are not used in protect the Flash memory or parts of it from the Flash array for read accesses. The high order unauthorized programming or erase accesses address bit A17/A16 define the physical 64K Byte and to provide virus-proof protection for all system segment being accessed within the Flash array. code blocks. All write protection also is enabled during boot operation. 5.3.2 - Command Mode Power Supply, Reset The Flash module uses a single power supply for Every operation besides standard read operations both read and write functions. Internally is initiated by commands written to the Flash generated and regulated voltages are provided for command register. The addresses used for the program and erase operations from 5V supply. command cycles define in conjunction with the Once a program or erase cycle has been actual state the specific step within command completed, the device resets to the standard read sequences. With the last command of a command mode. At power-on, the Flash memory has a sequence, the Erase-Program Controller (EPC) setup phase of some microseconds (dependent starts the execution of the command. The EPC on the power supply ramp-up). During this phase, status is indicated during command execution by: Flash can not be read. Thus, if EA pin is high (execution will start from Flash memory), the CPU – The Status Register, will remains in reset state until the Flash can be accessed. – The Ready/Busy signal. 5.3 - Architectural Description 5.3.3 - Ready/Busy Signal The Flash module distinguishes two basic operating modes, the standard read mode and the The Ready/Busy (R/B) signal is connected to the command mode. The initial state after power-on XPER2 interrupt node (XP2IC). When R/B is high, and after reset is the standard read mode. the Flash is busy with a Program or Erase operation and will not accept any additional 5.3.1 - Read Mode program or erase instruction. When R/B is Low, The Flash module enters the standard operating the Flash is ready for any Read/Write or Erase mode, the read mode: operation. The R/B will also be low when the – After Reset command memory is put in Erase Suspend mode. – After every completed erase operation This signal can be polled by reading XP2IC – After every completed programming operation register, or can be used to trigger an interrupt – After every other completed command when the Flash goes from Busy to Ready. execution – Few microseconds after a CPU-reset has 5.3.4 - Flash Status Register started – After incorrect address and data values of The Flash Status register is used to flag the status command sequences or writing them in an of the Flash memory and the result of an improper sequence operation. This register can be accessed by Read cycles during the program-Erase Controller – After incorrect write access to a read protected operations. The program or erase operation can Flash memory be controlled by data polling on bit FSB.7 of The read mode remains active until the last Status Register, detection of Toggle on FSB.6 and command of a command sequence is decoded FSB.2, or Error on FSB.5 and Erase Time-out on which starts directly a Flash array operation, such FSB.3 bit. Any read attempt in Flash during EPC as: operation will automatically output these five bits. – erase one or several blocks The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 – program a word into Flash array and FSB.7. Other bits are reserved for future use – protect / temporary unprotect a block. and should be masked. 19/184 5 - INTERNAL FLASH MEMORY ST10F269 Flash Status (see note for address) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- -- - - FSB.7 FSB.6 FSB.5 - FSB.3 FSB.2 - - RR R R R FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion. If the block selected for erasure is (are) protected, FSB.7 will be set to ‘0’ for about 100 µs, and then return to the previous addressed memory data value. FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the Erase Suspend. During Program operation in Erase Suspend Mode, FSB.7 will have the same behaviour as in normal Program execution outside the Suspend mode. FSB.6 Flash Status bit 6: Toggle Bit Programming or Erasing Operations: successive read operations of Flash Status register will deliver complementary values. FSB.6 will toggle each time the Flash Status register is read. The Program operation is completed when two successive reads yield the same value. The next read will output the bit last programmed, or a ‘1’ after Erase operation FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In addition, an Erase Suspend/Resume command will cause FSB.6 to toggle. FSB.5 Flash Status bit 5: Error Bit This bit is set to ‘1’ when there is a failure of Program, block or chip erase operations.This bit will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently programmed with ‘0’. The error bit resets after Read/Reset instruction. In case of success, the Error bit will be set to ‘0’ during Program or Erase and then will output the bit last programmed or a ‘1’ after erasing FSB.3 Flash Status bit 3: Erase Time-out Bit This bit is cleared by the EPC when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the time-out period is finished, after 96 µs, FSB.3 returns back to ‘1’. FSB.2 Flash Status bit 2: Toggle Bit This toggle bit, together with FSB.6, can be used to determine the chip status during the Erase Mode or Erase Suspend Mode. It can be used also to identify the block being Erased Suspended. A Read operation will cause FSB.2 to Toggle during the Erase Mode. If the Flash is in Erase Suspend Mode, a Read operation from the Erase suspended block or a Program operation into the Erase suspended block will cause FSB.2 to toggle. When the Flash is in Program Mode during Erase Suspend, FSB.2 will be read as ‘1’ if address used is the address of the word being programmed. After Erase completion with an Error status, FSB.2 will toggle when reading the faulty sector. Note: The Address of Flash Status Register is the address of the word being programmed when Programming operation is in progress, or an address within block being erased when Erasing operation is in progress. 20/184 ST10F269 5 - INTERNAL FLASH MEMORY 5.3.5 - Flash Protection Register The Flash Protection register is a non-volatile register that contains the protection status. This register can be read by using the Read Protection Status (RP) command, and programmed by using the dedi- cated Set Protection command. Flash Protection Register (PR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP - - - - - - - - BP6* BP5* BP4 BP3 BP2 BP1 BP0 *Not avalaible for 128K versions (reserved areas) BPx Block x Protection Bit (x = 0...6) ‘0’: the Block Protection is enabled for block x. Programming or erasing the block is not possible, unless a Block Temporary Unprotection command is issued. 1’: the Block Protection is disabled for block x. Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the Block Protection using the Block Temporary Unprotection instruction. CP Code Protection Bit ‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for execution not performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the content of the Flash is. 1’: the Flash Code Protection is disabled: read accesses to the Flash from external or internal RAM are allowed Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the Code Protection using the Code Temporary Unprotection instruction. Status is checked by reading the Flash Status bit FSB.2, FSB.5, FSB.6 and FSB.7 which show the status of the EPC. FSB.2, FSB.6 and FSB.7 5.3.6 - Instructions Description determine if programming is on going or has completed, and FSB.5 allows a check to be made Twelve instructions dedicated to Flash memory for any possible error. accesses are defined as follow: Block Erase (BE). This instruction uses a Read/Reset (RD). The Read/Reset instruction minimum of six command cycles. The erase consist of one write cycle with data XXF0h. it can enable command xx80h is written at address be optionally preceded by two CI enable coded 1554h after the two-cycle CI enable sequence. cycles (data xxA8h at address 1554h + data xx54h at address 2AA8h). Any successive read The erase confirm code xx30h must be written at cycle following a Read/Reset instruction will read an address related to the block to be erased the memory array. A Wait cycle of 10µs is preceded by the execution of a second CI enable necessary after a Read/Reset command if the sequence. Additional erase confirm codes must memory was in program or Erase mode. be given to erase more than one block in parallel. Additional erase confirm commands must be Program Word (PW). This instruction uses four written within a defined time-out period. The input write cycles. After the two Cl enable coded cycles, of a new Block Erase command will restart the the Program Word command xxA0h is written at time-out period. address 1554h. The following write cycle will latch the address and data of the word to be When this time-out period has elapsed, the erase programmed. Memory programming can be done starts. The status of the internal timer can be only by writing 0's instead of 1's, otherwise an monitored through the level of FSB.3, if FSB.3 is error occurs. During programming, the Flash ‘0’, the Block Erase command has been given and 21/184 5 - INTERNAL FLASH MEMORY ST10F269 the time-out is running; if FSB.3 is ‘1’, the time-out has expired and the EPC is erasing the block(s). 22/184 ST10F269 5 - INTERNAL FLASH MEMORY If the second command given is not an erase after the Erase Suspend Command has been confirm or if the coded cycles are wrong, the written. The Flash will then go in normal Read instruction aborts, and the device is reset to Read Mode, and read from blocks not being erased is Mode. It is not necessary to program the block valid, while read from block being erased will with 0000h as the EPC will do this automatically output FSB.2 toggling. During a Suspend phase before the erasing to FFFFh. Read operations the only instructions valid are Erase Resume and after the EPC has started, output the Flash Status Program Word. A Read / Reset instruction during Register. Erase suspend will definitely abort the Erase and result in invalid data in the block being erased. During the execution of the erase by the EPC, the Erase Resume (ER). This instruction can be device accepts only the Erase Suspend and given when the memory is in Erase Suspend Read/Reset instructions. Data Polling bit FSB.7 State. Erase can be resumed by writing the returns ‘0’ while the erasure is in progress, and ‘1’ command xx30h at any address without any when it has completed. The Toggle bit FSB.2 and Cl-enable sequence. FSB.6 toggle during the erase operation. They stop when erase is completed. After completion, Program during Erase Suspend. The Program the Error bit FSB.5 returns ‘1’ if there has been an Word instruction during Erase Suspend is allowed erase failure because erasure has not completed only on blocks that are not Erase-suspended. This even after the maximum number of erase cycles instruction is the same than the Program Word have been executed by the EPC, in this case, it instruction. will be necessary to input a Read/Reset to the Set Protection (SP). This instruction can be used Command Interface in order to reset the EPC. to enable both Block Protection (to protect each Chip Erase (CE). This instruction uses six write block independently from accidental Erasing-Pro- cycles. The Erase Enable command xx80h, must gramming Operation) and Code Protection (to be written at address 1554h after CI-Enable avoid code dump). The Set Protection Command cycles. The Chip Erase command xx10h must be must be given after a special CI-Protection Enable given on the sixth cycle after a second CI-Enable cycles (see instruction table). The following Write sequence. An error in command sequence will cycle, will program the Protection Register. To pro- reset the CI to Read mode. It is NOT necessary to tect the block x (x = 0 to 6), the data bit x must be program the block with 0000h as the EPC will do at ‘0’. To protect the code, bit 15 of the data must this automatically before the erasing to FFFFh. be ‘0’. Enabling Block or Code Protection is per- Read operations after the EPC has started output manent and can be cleared only by STM. Block the Flash Status Register. During the execution of Temporary Unprotection and Code Temporary the erase by the EPC, Data Polling bit FSB.7 Unprotection instructions are available to allow the returns ‘0’ while the erasure is in progress, and ‘1’ customer to update the code. when it has completed. The FSB.2 and FSB.6 bit Notes:1. The new value programmed in toggle during the erase operation. They stop when protection register will only become active erase is finished. The FSB.5 error bit returns "1" in after a reset. case of failure of the erase operation. The error 2. Bit that are already at ’0’ in protection flag is set after the maximum number of erase register must be confirmed at ’0’ also in cycles have been executed by the EPC. In this data latched during the 4th cycle of set case, it will be necessary to input a Read/Reset to protection command, otherwise an error the Command Interface in order to reset the EPC. may occur. Erase Suspend (ES). This instruction can be Read Protection Status (RP). This instruction is used to suspend a Block Erase operation by used to read the Block Protection status and the giving the command xxB0h without any specific Code Protection status. To read the protection address. No CI-Enable cycles is required. Erase register (see Table 3), the CI-Protection Enable Suspend operation allows reading of data from cycles must be executed followed by the another block and/or the programming in another command xx90h at address x2A54h. The block while erase is in progress. If this command following Read Cycles at any odd word address is given during the time-out period, it will terminate will output the Block Protection Status. The Read/ the time-out period in addition to erase Suspend. Reset command xxF0h must be written to reset The Toggle bit FSB.6, when monitored at an the protection interface. address that belongs to the block being erased, stops toggling when Erase Suspend Command is Note: After a modification of protection register effective, It happens between 0.1μs and 15μs (using Set Protection command), the Read 23/184 5 - INTERNAL FLASH MEMORY ST10F269 Protection Status will return the new PR value only after a reset. Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset command xxF0h. Set Code Protection (SCP). This kind of protection allows the customer to protect the proprietary code written in Flash. If installed and active, Flash Code Protection prevents data operand accesses and program branches into the on-chip Flash area from any location outside the Flash memory itself. Data operand accesses and branches to Flash locations are only and exclusively allowed for instructions executed from the Flash memory itself. Every read or jump to Flash performed from another memory (like internal RAM, external memory) while Code Protection is enabled, will give the opcode 009Bh related to TRAP #00 illegal instruction. The CI-Protection Enable cycles must be sent to set the Code Protection. By writing data 7FFFh at any odd word address, the Code Protected status is stored in the Flash Protection Register (PR). Protection is permanent and cannot be cleared by the user. It is possible to temporarily disable the Code Protection using Code Temporary Unprotection instruction. Note: Bits that are already at ’0’ in protection register must be confirmed at ’0’ also in data latched during the 4th cycle of set protection command, otherwise an error may occur. Code Temporary Unprotection (CTU). This instruction must be used to temporary disable Code Protection. This instruction is effective only if executed from Flash memory space. To restore the protection status, without using a reset, it is necessary to use a Code Temporary Protection instruction. System reset will reset also the Code Temporary Unprotected status. The Code Temporary Unprotection command consists of the following write cycle: MOV MEM, Rn ; This instruction MUST be executed from Flash memory space Where MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFFh. Code Temporary Protection (CTP). This instruction allows to restore Code Protection. This operation is effective only if executed from Flash memory and is necessary to restore the protection status after the use of a Code Temporary Unprotection instruction. The Code Temporary Protection command consists of the following write cycle: MOV MEM, Rn ; This instruction MUST be executed from Flash memory space Where MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFBh. Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the Flash with protected code (SCP), since the write/erase routines must be executed from a memory external to Flash space. Usually, the write/erase routines, executed in RAM, ends with a return to Flash space where a CTP instruction restore the protection. 24/184 ST10F269 5 - INTERNAL FLASH MEMORY Table 3 : Instructions st nd th th th 1 2 5 6 7 rd th Instruction Mne Cycle 3 Cycle 4 Cycle Cycle Cycle Cycle Cycle Cycle 1 2 Addr. X Read/Reset RD 1+ Read Memory Array until a new write cycle is initiated Data xxF0h 1 x1554h x2AA8h xxxxxh Addr. Read Memory Array until a new write Read/Reset RD 3+ cycle is initiated Data xxA8h xx54h xxF0h 1 3 x1554h x2AA8h x1554h Read Data Polling or Tog- Addr. WA Program Word PW 4 gle bit until Program com- 4 Data xxA8h xx54h xxA0h WD pletes. 1 5 x1554h x2AA8h x1554h x1554h x2AA8h BA Addr. BA’ Block Erase BE 6 Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h 1 x1554h x2AA8h x1554h x1554h x2AA8h x1554h Addr. 6 Chip Erase CE 6 Note Data xxA8h xx54h xx80h xxA8h xx54h xx10h 1 2 Addr. X Read until Toggle stops, then read or program all data needed Erase Suspend ES 1 from block(s) not being erased then Resume Erase. Data xxB0h 1 2 Addr. X Read Data Polling or Toggle bit until Erase completes or Erase is Erase Resume ER 1 suspended another time. Data xx30h 1 Set Block/Code x2A54h x15A8h x2A54h Any odd Addr. Protection word 9 SP 4 address 7 Data xxA8h xx54h xxC0h WPR 1 Read x2A54h x15A8h x2A54h Any odd Addr. Read Protection Register Protection word 9 RP 4 until a new write cycle is Status address initiated. Data xxA8h xx54h xx90h Read PR 1 2 Block x2A54h x15A8h x2A54h Addr. X Temporary BTU 4 Data xxA8h xx54h xxC1h xxF0h Unprotection 1 8 Code Addr. MEM Temporary CTU 1 Write cycles must be executed from Flash. Data FFFFh Unprotection 1 8 Code Addr. MEM Temporary CTP 1 Write cycles must be executed from Flash. Data FFFBh Protection Notes 1. Address bit A14, A15 and above are don’t care for coded address inputs. 2. X = Don’t Care. 3. WA = Write Address: address of memory location to be programmed. 4. WD = Write Data: 16-bit data to be programmed 5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, time-out statu s can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 6. Read Data Polling or Toggle bit until Erase completes. 7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR must be ‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a ‘1’ in a bit already programmed at ‘0’). 25/184 5 - INTERNAL FLASH MEMORY ST10F269 8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction must be executed from Flash memory space. 9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h... – Generally, command sequences cannot be performs the setting of ROMEN bit must be written to Flash by instructions fetched from the executed either in the segment 0 but above Flash itself. Thus, the Flash commands must be address 00’8000h, or from the internal RAM. written by instructions, executed from internal Bit ROMS1 only affects the mapping of the first RAM or external memory. 32K Bytes of the Flash memory. All other parts of – Command cycles on the CPU interface need not the Flash memory (addresses 01’8000h - to be consecutively received (pauses allowed). 04’FFFFh) remain unaffected. The CPU interface delivers dummy read data for The SGTDIS Segmentation Disable / Enable must not used cycles within command sequences. also be set to 0 to allow the use of the full – All addresses of command cycles shall be 256K Bytes of on-chip memory in addition to the defined only with Register-indirect addressing external boot memory. The correct procedure on mode in the according move instructions. Direct changing the segmentation registers must also be addressing is not allowed for command observed to prevent an unwanted trap condition: sequences. Address segment or data page pointer are taken into account for the command – Instructions that configure the internal memory must only be executed from external memory or address value. from the internal RAM. 5.3.7 - Reset Processing and Initial State – An Absolute Inter-Segment Jump (JMPS) The Flash module distinguishes two kinds of CPU instruction must be executed after Flash reset types enabling, to the next instruction, even if this next The lengthening of CPU reset: instruction is located in the consecutive address. – Is not reported to external devices by – Whenever the internal Memory is disabled, bidirectional pin enabled or remapped, the DPPs must be – Is not enabled in case of external start of CPU explicitly (re)loaded to enable correct data after reset. accesses to the internal memory and/or external memory. 5.4 - Flash Memory Configuration The default memory configuration of the 5.5 - Application Examples ST10F269 Memory is determined by the state of the EA pin at reset. This value is stored in the 5.5.1 - Handling of Flash Addresses Internal ROM Enable bit (named ROMEN) of the All command, Block, Data and register addresses SYSCON register. to the Flash have to be located within the active When ROMEN = 0, the internal Flash is disabled Flash memory space. The active space is that and external ROM is used for startup control. address range to which the physical Flash Flash memory can later be enabled by setting the addresses are mapped as defined by the user. ROMEN bit of SYSCON to 1. The code When using data page pointer (DPP) for block performing this setting must not run from a addresses make sure that address bit A15 and segment of the external ROM to be replaced by a A14 of the block address are reflected in both segment of the Flash memory, otherwise LSBs of the selected DPPS. unexpected behaviour may occur. Note: - For Command Instructions, address bit For example, if external ROM code is located in A14, A15, A16 and A17 are don’t care. the first 32K Bytes of segment 0, the first This simplify a lot the application software, 32K Bytes of the Flash must then be enabled in because it minimize the use of DPP regis- segment 1. This is done by setting the ROMS1 bit ters when using Command in the Com- of SYSCON to 0 before or simultaneously with mand Interface. setting of ROMEN bit. This must be done in the externally supplied program before the execution - Direct addressing is not allowed for of the EINIT instruction. Command sequence operations to the If program execution starts from external memory, Flash. Only Register-indirect addressing but access to the Flash memory mapped in can be used for command, block or segment 0 is later required, then the code that write-data accesses. 26/184 ST10F269 5 - INTERNAL FLASH MEMORY 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that address bit A15 and A14 of the command addresses are reflected in both LSBs of the selected data page pointer (A15 - DPPx.1 and A14 - DPPx.0). In case of the command write addresses, address bit A14, A15 and above are don’t care. Thus, command writes can be performed by only using one DPP register. This allow to have a more simple and compact application software. Another - advantageous - possibility is to use the extended segment instruction for addressing. Note: The direct addressing mode is not allowed for write access to the Flash address/command register. Be aware that the C compiler may use this kind of addressing. For write accesses to Flash module always the indirect addressing mode has to be selected. The following basic instruction sequences show examples for different addressing possibilities. Principle example of address generation for Flash commands and registers: When using data page pointer (DPP0 is this example) MOV DPP0,#08h ;adjust data page pointers according to the ;addresses: DPP0 is used in this example, thus ;ADDRESS must have A14 and A15 bit set to ‘0’. MOV Rw ,#ADDRESS ;ADDRESS could be a dedicated command sequence m ;address 2AA8h, 1554h ... ) or the Flash write ;address MOV Rw ,#DATA ;DATA could be a dedicated command sequence data n ;(xxA0h,xx80h ... ) or data to be programmed MOV [Rw ],Rw ;indirect addressing m n When using the extended segment instruction: MOV Rw ,#ADDRESS ;ADDRESS could be a dedicated command sequence m ;address (2AA8h, 1554h ... ) or the Flash write ;address MOV Rw ,#DATA ;DATA could be a dedicated command sequence data o ;(xxA0h,xx80h ... ) or data to be programmed MOV Rw ,#SEGMENT ;the value of SEGMENT represents the segment n ;number and could be 0, 1, 2, 3 or 4 (depending ;on sector mapping) for 256KByte Flash. EXTS Rw ,#LENGTH ;the value of Rwn determines the 8-bit segment n ;valid for the corresponding data access for any ;long or indirect address in the following(s) ;instruction(s). LENGTH defines the number of ;the effected instruction(s) and has to be a value ;between 1...4 MOV [Rw ],Rw ;indirect addressing with segment number from m o ;EXTS 27/184 5 - INTERNAL FLASH MEMORY ST10F269 5.5.3 - Programming Examples Most of the microcontroller programs are written in the C language where the data page pointers are automatically set by the compiler. But because the C compiler may use the not allowed direct addressing mode for Flash write addresses, it is necessary to program the organizational Flash accesses (command sequences) with assembler in-line routines which use indirect addressing. Example 1 Performing the command Read/Reset We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1. According to the usual way of ST10 data addressing with data page pointers, address bit A15 and A14 of a 16-bit command write address select the data page pointer (DPP) which contains the upper 10-bit for building the 24-bit physical data address. Address bit A13...A0 represent the address offset. As the bit A14...A17 are "don’t care" when written a Flash command in the Command Interface (CI), we can choose the most convenient DPPx register for address handling. The following examples are making usage of DPP0. We just have to make sure, that DPP0 points to active Flash memory space. To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash address handling, to point to segment 2. For this reason we load DPP0 with value 08h (00 0000 l000b). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SCXT DPPO, #08h ;push data page pointer 0 and load it to point to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #0F0h ;load register R7 with Read/Reset command MOV [R5], R7 ;command cycle 3. Address is don’t care POP DPP0 ;restore DPP0 value In the example above the 16-bit registers R5 and R6 are used as auxiliary registers for indirect addressing. Example 2 Performing a Program Word command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The data to be written is loaded in register R13, the address to be programmed is loaded in register R11/R12 (segment number in R11, segment offset in R12). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SXCT DPPO, #08h ;push data page pointer 0 and load it to point to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #0A0h ;load register R7 with Program Word command MOV [R5], R7 ;command cycle 3 POP DPP0 ;restore DPP0: following addressing to the Flash ;will use EXTended instructions ;R11 contains the segment to be programmed 28/184 ST10F269 5 - INTERNAL FLASH MEMORY ;R12 contains the segment offset address to be ;programmed ;R13 contains the data to be programmed EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R13 ;command cycle 4: the EPC starts execution of ;Programming Command Data_Polling: EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV R7, [R12] ;read Flash Status register (FSB) in R7 MOV R6, R7 ;save it in R6 register ;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7) XOR R7, R13 JNB R7.7, Prog_OK ;Check if FSB.5 = 1 (Programming Error) JNB R6.5, Data_Polling ;Programming Error: verify is Flash programmed ;data is OK EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV R7, [R12] ;read Flash Status register (FSB) in R7 ;Check if FSB.7 = Data.7 XOR R7, R13 JNB R7.7, Prog_OK ;Programming failed: Flash remains in Write ;Operation. ;To go back to normal Read operations, a Read/Reset ;command ;must be performed Prog_Error: MOV R7, #0F0h ;load register R7 with Read/Reset command EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;address is don’t care for Read/Reset command ... ;here place specific Error handling code ... ... ;When programming operation finished succesfully, ;Flash is set back automatically to normal Read Mode Prog_OK: .... .... 29/184 5 - INTERNAL FLASH MEMORY ST10F269 Example 3 Performing the Block Erase command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased (segment number in R11, segment offset in R12, for example R11 = 01h, R12= 4000h will erase the block 1 - first 8K byte block). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SXCT DPPO, #08h ;push data page pointer 0 and load it to point ;to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #080h ;load register R7 with Block Erase command MOV [R5], R7 ;command cycle 3 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 4 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 5 POP DPP0 ;restore DPP0: following addressing to the Flash ;will use EXTended instructions ;R11 contains the segment of the block to be erased ;R12 contains the segment offset address of the ;block to be erased MOV R7, #030h ;load register R7 with erase confirm code EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;command cycle 6: the EPC starts execution of ;Erasing Command Erase_Polling: EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV R7, [R12] ;read Flash Status register (FSB) in R7 ;Check if FSB.7 = ‘1’ (i.e. R7.7 = ‘1’) JB R7.7, Erase_OK ;Check if FSB.5 = 1 (Erasing Error) JNB R7.5, Erase_Polling ;Programming failed: Flash remains in Write ;Operation. ;To go back to normal Read operations, a Read/Reset ;command ;must be performed Erase_Error: MOV R7, #0F0h ;load register R7 with Read/Reset command EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;address is don’t care for Read/Reset command ... ;here place specific Error handling code ... ... ;When erasing operation finished succesfully, ;Flash is set back automatically to normal Read Mode Erase_OK: .... 30/184 ST10F269 5 - INTERNAL FLASH MEMORY .... 5.6 - Bootstrap Loader 5.6.1 - Entering the Bootstrap Loader The built-in bootstrap loader (BSL) of the The ST10F269 enters BSL mode when pin P0L.4 ST10F269 provides a mechanism to load the is sampled low at the end of a hardware reset. In startup program through the serial interface after this case the built-in bootstrap loader is activated reset. In this case, no external memory or internal independent of the selected bus mode. Flash memory is required for the initialization code starting at location 00’0000h (see Figure 5). The bootstrap loader code is stored in a special Boot-ROM. No part of the standard mask Memory The bootstrap loader moves code/data into the or Flash Memory area is required for this. internal RAM, but can also transfer data via the serial interface into an external RAM using a After entering BSL mode and the respective second level loader routine. Flash Memory initialization the ST10F269 scans the RXD0 line to (internal or external) is not necessary, but it may receive a zero Byte, one start bit, eight ‘0’ data bits be used to provide lookup tables or “core-code” and one stop bit. like a set of general purpose subroutines for I/O operations, number crunching, system From the duration of this zero Byte it calculates initialization, etc. the corresponding Baud rate factor with respect to the current CPU clock, initializes the serial The bootstrap loader can be used to load the interface ASC0 accordingly and switches pin complete application software into ROMless TxD0 to output. systems, to load temporary software into complete systems for testing or calibration, or to Using this Baud rate, an identification Byte is load a programming routine for Flash devices. returned to the host that provides the loaded data. The BSL mechanism can be used for standard system startup as well as for special occasions This identification Byte identifies the device to like system maintenance (firmer update) or bebooted. The identification byte is D5h for end-of-line programming or testing. ST10F269. Figure 5 : Bootstrap Loader Sequence RSTIN P0L.4 1) 2) 4) RxD0 3) TxD0 5) CSP:IP Internal Boot Memory (BSL) routine 32 Byte user software 6) 1) BSL initialization time 2) Zero Byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host. 3) Identification Byte (D5h), sent by ST10F269. 4) 32 Bytes of code / data, sent by host. 5) Caution: TxD0 is only driven a certain time after reception of the zero Byte. 6) Internal Boot ROM. 31/184 5 - INTERNAL FLASH MEMORY ST10F269 When the ST10F269 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Disabled Register SYSCON: 0E00h Context Pointer CP: FA00h Register STKUN: FA40h Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C Register S0CON: 8011h Register BUSCON0: acc. to startup configuration P3.10 / TXD0: ‘1’ Register S0BG: Acc. to ‘00’ Byte DP3.10: ‘1’ In this case, the watchdog timer is disabled, so the 5.6.2 - Memory Configuration After Reset bootstrap loading sequence is not time limited. The configuration (and the accessibility) of the Pin TXD0 is configured as output, so the ST10F269’s memory areas after reset in ST10F269 can return the identification Byte. Bootstrap-Loader mode differs from the standard case. Pin EA is not evaluated when BSL mode is Even if the internal Flash is enabled, no code can selected, and accesses to the internal Flash area be executed out of it. are partly redirected, while the ST10F269 is in The hardware that activates the BSL during reset BSL mode (see Figure 7). All code fetches are may be a simple pull-down resistor on P0L.4 for made from the special Boot-ROM, while data systems that use this feature upon every accesses read from the internal user Flash. Data hardware reset. accesses will return undefined values on ROMless devices. A switchable solution (via jumper or an external signal) can be used for systems that The code in the Boot-ROM is not an invariant onlytemporarily use the bootstrap loader (see feature of the ST10F269. User software should Figure 6). not try to execute code from the internal Flash area while the BSL mode is still active, as these After sending the identification Byte the fetches will be redirected to the Boot-ROM. The ASC0receiver is enabled and is ready to Boot-ROM will also “move” to segment 1, when receive the initial 32 Bytes from the host. A half duplex connection is therefore sufficient to feed the internal Flash area is mapped to segment 1 the BSL. (see Figure 7). Figure 6 : Hardware Provisions to Activate the BSL External Signal Normal Boot POL.4 POL.4 BSL R POL.4 8kΩ R POL.4 8kΩ Circuit 2 Circuit 1 32/184 ST10F269 5 - INTERNAL FLASH MEMORY Figure 7 : Memory Configuration after Reset 16M Bytes 16M Bytes 16M Bytes Access: Segment Access to: Segment Access to: Segment 255 255 255 depends on external external bus bus reset config disabled enabled 2 2 EA, Port0 2 1 1 1 IRAM IRAM IRAM 0 0 0 depends on User internal User internal User Test Test Flash Flash reset config enabled enabled Flash Flash Flash Flash Flash EA, Port0 BSL mode active Yes (P0L.4=’0’) Yes (P0L.4=’0’) No (P0L.4=’1’) EA pin High Low Access to application Code fetch from internal Test-Flash access Test-Flash access User Flash access Flash area Data fetch from internal User Flash access User Flash access User Flash access Flash area 5.6.3 - Loading the Startup Code cases the ST10F269 will still run in BSL mode, that means with the watchdog timer disabled and After sending the identification Byte the BSL limited access to the internal Flash area. enters a loop to receive 32 Bytes via ASC0. These Byte are stored sequentially into locations All code fetches from the internal Flash area 00’FA40h through 00’FA5Fh of the internal RAM. (00’0000h...00’7FFFh or 01’0000h...01’7FFFh, if So up to 16 instructions may be placed into the mapped to segment 1) are redirected to the RAM area. To execute the loaded code the BSL special Boot-ROM. Data fetches access will then jumps to location 00’FA40h, which is the first access the internal Boot-ROM of the ST10F269, if loaded instruction. any is available, but will return undefined data on ROMless devices. The bootstrap loading sequence is now terminated, the ST10F269 remains in BSL mode, 5.6.4 - Exiting Bootstrap Loader Mode however. Most probably the initially loaded routine In order to execute a program in normal mode, the will load additional code or data, as an average BSL mode must be terminated first. The application is likely to require substantially more ST10F269 exits BSL mode upon a software reset than 16 instructions. This second receive loop (ignores the level on P0L.4) or a hardware reset may directly use the pre-initialized interface ASC0 (P0L.4 must be high). After a reset the ST10F269 to receive data and store it to arbitrary will start executing from location 00’0000h of the user-defined locations. internal Flash or the external memory, as This second level of loaded code may be the final programmed via pin EA. application code. It may also be another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data. It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory. This process may go through several iterations or may directly execute the final application. In all 33/184 5 - INTERNAL FLASH MEMORY ST10F269 5.6.5 - Choosing the Baud Rate for the BSL Note: Function (F ) does not consider the B tolerances of oscillators and other devices The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is supporting the serial communication. received, allows the operation of the bootstrap This Baud rate deviation is a nonlinear function loader of the ST10F269 with a wide range of Baud rates. However, the upper and lower limits have to depending on the CPU clock and the Baud rate of be kept, in order to insure proper data transfer. the host. The maxima of the function (F ) B increase with the host Baud rate due to the f CPU smaller Baud rate pre-scaler factors and the B = ------------------------------------------------ ST10F269 32 ×() S0BRL+ 1 implied higher quantization error (see Figure 8). The ST10F269 uses timer T6 to measure the The minimum Baud rate (B in the Figure 8) is Low length of the initial zero Byte. The quantization determined by the maximum count capacity of uncertainty of this measurement implies the first timer T6, when measuring the zero Byte, and it deviation from the real Baud rate, the next depends on the CPU clock. Using the maximum deviation is implied by the computation of the 16 T6 count 2 in the formula the minimum Baud S0BRL reload value from the timer contents. The rate can be calculated. The lowest standard Baud formula below shows the association: rate in this case would be 1200 Baud. Baud rates below B would cause T6 to overflow. In this Low f T6– 36 9 CPU case ASC0 cannot be initialized properly. ------------- ------ - S0BRL= , T6=--- ×----------------- 72 4 B Host The maximum Baud rate (B in the Figure 8) High is the highest Baud rate where the deviation still For a correct data transfer from the host to the does not exceed the limit, so all Baud rates ST10F269 the maximum deviation between the between B and B are below the deviation internal initialized Baud rate for ASC0 and the real Low High limit. The maximum standard Baud rate that fulfills Baud rate of the host should be below 2.5%. The deviation (F , in percent) between host Baud rate this requirement is 19200 Baud. B and ST10F269 Baud rate can be calculated via Higher Baud rates, however, may be used as the formula below: long as the actual deviation does not exceed the B– B limit. A certain Baud rate (marked ’I’ in Figure 8) Contr Host F= × 100 % -------------------------------------------- , B may violate the deviation limit, while an even B Contr higher Baud rate (marked ’II’ in Figure 8) stays very well below it. This depends on the host F ≤ 2.5 % B interface. Figure 8 : Baud Rate Deviation Between Host and ST10F269 I F B 2.5% B B B Low High HOST II 34/184 ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) 6 - CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a The CPU uses a bank of 16 word registers to run 16-bit arithmetic and logic unit (ALU) and dedi- the current context. This bank of General Purpose cated SFRs. Additional hardware has been added Registers (GPR) is physically stored within the for a separate multiply and divide unit, a bit-mask on-chip Internal RAM (IRAM) area. A Context generator and a barrel shifter. Pointer (CP) register determines the base address of the active register bank to be accessed Most of the ST10F269 instructions can be exe- by the CPU. cuted in one instruction cycle which requires 50ns The number of register banks is only restricted by at 40MHz CPU clock (PQFP144 devices) and the available Internal RAM space. For easy 62.5ns at 32MHz CPU clock (TQFP144 devices). parameter passing, a register bank may overlap For example, shift and rotate instructions are pro- others. cessed in one instruction cycle independent of the A system stack of up to 1024 bytes is provided as number of bits to be shifted. a storage for temporary data. The system stack is Multiple-cycle instructions have been optimized: allocated in the on-chip RAM area, and it is branches are carried out in 2 cycles, 16 x 16-bit accessed by the CPU via the stack pointer (SP) multiplication in 5 cycles and a 32/16-bit division register. in 10 cycles. Two separate SFRs, STKOV and STKUN, are The jump cache reduces the execution time of implicitly compared against the stack pointer repeatedly performed jumps in a loop, from value upon each stack access for the detection of 2 cycles to 1 cycle. a stack overflow or underflow. Figure 9 : CPU Block Diagram (MAC Unit not included) 16 CPU 2K Byte Internal SP MDH R15 RAM STKOV MDL STKUN Mul./Div.-HW 128K/256K Byte Bit-Mask Gen. Bank Exec. Unit General n Flash Instr. Ptr Purpose memory Registers 4-Stage ALU Pipeline 16-Bit 32 PSW R0 Bank Barrel-Shift i SYSCON CP BUSCON 0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 Bank ADDRSEL 3 BUSCON 3 BUSCON 4 ADDRSEL 4 0 16 Data Pg. Ptrs Code Seg. Ptr. 35/184 6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset. SYSCON (FF12h / 89h) SFR Reset Value: 0xx0h 15 14 13 12 11 10 9876543210 STKSZ ROM SGT ROM BYT CLK WR CS PWD OWD BDR XPEN VISI XPER- S1 DIS EN DIS EN CFG CFG CFG DIS STEN BLE SHARE 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW Notes: 1. These bits are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. 2. Register SYSCON cannot be changed after execution of the EINIT instruction. Bit Function XPEN XBUS Peripheral Enable Bit 0 Accesses to the on-chip X-Peripherals and their functions are disabled 1 The on-chip X-Peripherals are enabled and can be accessed. BDRSTEN Bidirectional Reset Enable 0 RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin 1 RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence. OWDDIS Oscillator Watchdog Disable Control 0 Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 μs, the CPU clock is switched automatically to PLL’s base frequency (2 to 10MHz). 1 OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The PLL is turned off to reduce power supply current. PWDCFG Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth- erwise the instruction has no effect. To exit Power Down Mode, an external reset must occurs by asserting the RSTIN pin. 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin. CSCFG Chip Select Configuration Control 0 Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines: CSx change with rising edge of ALE 6.1 - Multiplier-accumulator Unit (MAC) The existing ST10 CPU has been modified to include new addressing capabilities which enable The MAC co-processor is a specialized co-pro- the CPU to supply the new co-processor with up cessor added to the ST10 CPU Core in order to to 2 operands per instruction cycle. improve the performances of the ST10 Family in signal processing algorithms. This new co-processor (so-called MAC) contains Signal processing needs at least three specialized a fast multiply-accumulate unit and a repeat unit. units operating in parallel to achieve maximum The co-processor instructions extend the ST10 performance: CPU instruction set with multiply, multiply-accu- – A Multiply-Accumulate Unit, mulate, 32-bit signed arithmetic operations. – An Address Generation Unit, able to feed the MAC Unit with 2 operands per cycle, A new transfer instruction CoMOV has also been – A Repeat Unit, to execute series of multiply-ac- added to take benefit of the new addressing capa- cumulate instructions. bilities. 36/184 ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) 6.1.1 - Features – 16 x 16-bit signed/unsigned parallel multiplier. – 40-bit signed arithmetic unit with automatic sat- 6.1.1.1 - Enhanced Addressing Capabilities uration mode. – New addressing modes including a double indi- – 40-bit accumulator. rect addressing mode with pointer post-modifi- – 8-bit left/right shifter. cation. – Full instruction set with multiply and multiply-ac- – Parallel Data Move: this mechanism allows one cumulate, 32-bit signed arithmetic and compare operand move during Multiply-Accumulate in- instructions. structions without penalty. 6.1.1.3 - Program Control – New transfer instructions CoSTORE (for fast ac- – Repeat Unit: allows some MAC co-processor in- cess to the MAC SFRs) and CoMOV (for fast structions to be repeated up to 8192 times. Re- memory to memory table transfer). peated instructions may be interrupted. 6.1.1.2 - Multiply-Accumulate Unit – MAC interrupt (Class B Trap) on MAC condition – One-cycle execution for all MAC operations. flags. Figure 10 : MAC Unit Architecture Operand 1 Operand 2 16 16 GPR Pointers * IDX0 Pointer IDX1 Pointer QR0 GPR Offset Register 16 x 16 QR1 GPR Offset Register signed/unsigned Multiplier QX0 IDX Offset Register Concatenation QX1 IDX Offset Register 32 32 Mux Sign Extend MRW Scaler 0h 08000h 0h 40 40 40 40 40 Repeat Unit Mux Mux Interrupt 40 40 Controller MCW AB ST10 CPU 40-bit Signed Arithmetic Unit MSW 40 Flags MAE MAH MAL Control Unit 40 8-bit Left/Right Shifter Note: * Shared with standard ALU. 37/184 6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 6.2 - Instruction Set Summary The Table 4 lists the instructions of the ST10F269. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruc- tion can be found in the “ST10 Family Programming Manual”. Table 4 : Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bit-wise AND, (word/byte operands) 2 / 4 OR(B) Bit-wise OR, (word/byte operands) 2 / 4 XOR(B) Bit-wise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bit-wise modify masked high/low byte of bit-addressable direct word memory 4 with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result 2 in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 38/184 ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) Table 4 : Instruction Set Summary Mnemonic Description Bytes JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word 4 operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct 2 word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2 6.3 - MAC Coprocessor Specific Instructions two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1 and QX0/QX1 are asso- The following table gives an overview of the MAC ciated with each pointer (GPR or IDX ). instruction set. All the mnemonics are listed with i the addressing modes that can be used with each The GPR pointer allows access to the entire instruction. memory space, but IDX are limited to the internal i Dual-Port RAM, except for the CoMOV instruction. For each combination of mnemonic and address- ing mode this table indicates if it is repeatable or not. New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per instruc- tion cycle. MAC instructions: multiply, multi- ply-accumulate, 32-bit signed arithmetic operations and the CoMOV transfer instruction have been added to the standard instruction set. Full details are provided in the ‘ST10 Family Pro- gramming Manual’. Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the other pointer is provided by one of 39/184 6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 Mnemonic Addressing Modes Repeatability CoMUL CoMULu CoMULus CoMULsu CoMUL- Rw , Rw n m No CoMULu- [IDX ⊗], [Rw ⊗] No i m CoMULus- No Rw , [Rw ⊗] n m CoMULsu- CoMUL, rnd CoMULu, rnd CoMULus, rnd CoMULsu, rnd CoMAC CoMACu CoMACus CoMACsu CoMAC- CoMACu- Rw , Rw n m No CoMACus- [IDX ⊗], [Rw ⊗] Yes i m CoMACsu- Yes Rw , [Rw ⊗] n m CoMAC, rnd CoMACu, rnd CoMACus, rnd CoMACsu, rnd CoMACR CoMACRu CoMACRus CoMACRsu Rw , Rw n m No CoMACR, rnd [IDX ⊗], [Rw ⊗] No i n CoMACRu, rnd No Rw , [RW ⊗] n m CoMACRus, rnd CoMACRsu, rnd [Rw ⊗] Yes m [IDX ⊗] CoNOP Yes i [IDX ⊗], [Rw ⊗] Yes i m CoNEG CoNEG, rnd -No CoRND Rw , CoReg No n CoSTORE [Rw ⊗], Coreg Yes n CoMOV [IDX ⊗], [Rw ⊗] Yes i m 40/184 ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) Mnemonic Addressing Modes Repeatability CoMACM CoMACMu CoMACMus CoMACMsu CoMACM- CoMACMu- CoMACMus- CoMACMsu- CoMACM, rnd CoMACMu, rnd [IDX ⊗], [Rw ⊗] Yes i m CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB Rw , Rw n m No CoSUB2 [IDX ⊗], [Rw ⊗] Yes i m CoSUBR Yes Rw , [Rw ⊗] n m CoSUB2R CoMAX CoMIN CoLOAD CoLOAD- No Rw , Rw n m CoLOAD2 [IDX ⊗], [Rw ⊗] No i m Rw , [Rw ⊗] CoLOAD2- n m No CoCMP CoSHL Rw m Yes CoSHR #data4 No CoASHR [Rw ⊗] Yes m CoASHR, rnd - Rw , Rw n m No CoABS [IDX ⊗], [Rw ⊗] i m No Rw , [Rw ⊗] No n m 41/184 6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 The Table 5 shows the various combinations of pointer post-modification for each of these 2 new address- ing modes. In this document the symbols “[Rw ⊗]” and “[IDX ⊗]” refer to these addressing modes. n i Table 5 : Pointer Post-modification Combinations for IDXi and Rwn Symbol Mnemonic Address Pointer Operation “[IDX ⊗]” stands for [IDX](IDX ) ← (IDX ) (no-op) i i i i [IDX +](IDX ) ← (IDX ) + 2 (i=0,1) i i i [IDX -] (IDX ) ← (IDX ) - 2 (i=0,1) i i i [IDX + QX](IDX ) ← (IDX ) + (QX ) (i, j =0,1) i j i i j [IDX - QX](IDX ) ← (IDX ) - (QX ) (i, j =0,1) i j i i j “[Rw ⊗]” stands for [Rwn] (Rwn) ← (Rwn) (no-op) n [Rwn+] (Rwn) ← (Rwn) + 2 (n=0-15) [Rwn-] (Rwn) ← (Rwn) - 2 (n=0-15) [Rwn + QR ] (Rwn) ← (Rwn) + (QR ) (n=0-15; j =0,1) j j [Rwn - QR ] (Rwn) ← (Rwn) - (QR ) (n=0-15; j =0,1) j j Table 6 : MAC Registers Referenced as ‘CoReg‘ Registers Description Address in Opcode MSW MAC-Unit Status Word 00000b MAH MAC-Unit Accumulator High 00001b MAS “limited” MAH /signed 00010b MAL MAC-Unit Accumulator Low 00100b MCW MAC-Unit Control Word 00101b MRW MAC-Unit Repeat Word 00110b 42/184 ST10F269 7 - EXTERNAL BUS CONTROLLER 7 - EXTERNAL BUS CONTROLLER All of the external memory accesses are Port 4 outputs all 8 address lines if an address performed by the on-chip external bus controller. space of 16M Bytes is used, otherwise four, two or no address lines. The EBC can be programmed to single chip mode Chip select timing can be made programmable. when no external memory is required, or to one of By default (after reset), the CSx lines change half four different external memory access modes: a CPU clock cycle after the rising edge of ALE. – 16- / 18- / 20- / 24-bit addresses and 16-bit data, With the CSCFG bit set in the SYSCON register demultiplexed the CSx lines change with the rising edge of ALE. – 16- / 18- / 20- / 24-bit addresses and 16-bit data, The active level of the READY pin can be set by bit multiplexed RDYPOL in the BUSCONx registers. When the – 16- / 18- / 20- / 24-bit addresses and 8-bit data, READY function is enabled for a specific address multiplexed window, each bus cycle within the window must – 16- / 18- / 20- / 24-bit addresses and 8-bit data, be terminated with the active level defined by bit demultiplexed RDYPOL in the associated BUSCON register. In demultiplexed bus modes addresses are output 7.1 - Programmable Chip Select Timing on PORT1 and data is input / output on PORT0 or Control P0L, respectively. In the multiplexed bus modes The ST10F269 allows the user to adjust the both addresses and data use PORT0 for input / position of the CSx line changes. By default (after output. reset), the CSx lines change half a CPU clock Timing characteristics of the external bus cycle (12.5ns at 40MHz of CPU clock on interface (memory cycle time, memory tri-state PQFP144 devices and 31.25ns at 32MHz of CPU time, length of ALE and read / write delay) are clock on TQFP144 devices ) after the rising edge programmable giving the choice of a wide range of ALE. With the CSCFG bit set in the SYSCON of memories and external peripherals. register the CSx lines change with the rising edge of ALE, thus the CSx lines and the address lines Up to 4 independent address windows may be change at the same time (see Figure 11). defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus 7.2 - READY Programmable Polarity characteristics. The active level of the READY pin can be selected These address windows are arranged by software via the RDYPOL bit in the BUSCONx hierarchically where BUSCON4 overrides registers. BUSCON3 and BUSCON2 overrides BUSCON1. When the READY function is enabled for a All accesses to locations not covered by these 4 specific address window, each bus cycle within address windows are controlled by BUSCON0. this window must be terminated with the active Up to 5 external CS signals (4 windows plus level defined by this RDYPOL bit in the associated default) can be generated in order to save external BUSCON register. glue logic. Access to very slow memories is BUSCONx registers are described in Section 20.2 supported by a ‘Ready’ function. -: System Configuration Registers. A HOLD / HLDA protocol is available for bus Note ST10F269 as no internal pull-up resistor arbitration which shares external resources with on READY pin. other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1M Byte, 256K Bytes or to 64K Bytes. 43/184 7 - EXTERNAL BUS CONTROLLER ST10F269 Figure 11 : Chip Select Delay Normal Demultiplexed ALE Lengthen Demultiplexed Segment (P4) Bus Cycle Bus Cycle Address (P1) ALE Normal CSx Unlatched CSx Data Data BUS (P0) RD Data Data BUS (P0) WR Read/Write Read/Write Delay Delay 44/184 ST10F269 8 - INTERRUPT SYSTEM 8 - INTERRUPT SYSTEM The interrupt response time for internal program them offers such fast interrupt-driven data transfer execution is from 125ns to 300ns at 40MHz CPU capabilities. clock on PQFP144 devices and 156.25ns to An interrupt control register which contains an 375ns at 32MHz of CPU clock on TQFP144 interrupt request flag, an interrupt enable flag and devices. an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related The ST10F269 architecture supports several register, each source can be programmed to one mechanisms for fast and flexible response to of sixteen interrupt priority levels. Once starting to service requests that can be generated from be processed by the CPU, an interrupt service various sources (internal or external) to the can only be interrupted by a higher prioritized microcontroller. Any of these interrupt requests service request. For the standard interrupt can be serviced by the Interrupt Controller or by processing, each of the possible interrupt sources the Peripheral Event Controller (PEC). has a dedicated vector location. In contrast to a standard interrupt service where Software interrupts are supported by means of the the current program execution is suspended and a ‘TRAP’ instruction in combination with an branch to the interrupt vector table is performed, individual trap (interrupt) number. just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service 8.1 - External Interrupts implies a single Byte or Word data transfer Fast external interrupt inputs are provided to between any two memory locations with an service external interrupts with high precision additional increment of either the PEC source or requirements. These fast interrupt inputs feature destination pointer. An individual PEC transfer programmable edge detection (rising edge, falling counter is implicitly decremented for each PEC edge or both edges). service except when performing in the continuous transfer mode. When this counter reaches zero, a Fast external interrupts may also have interrupt standard interrupt is performed to the sources selected from other peripherals; for corresponding source related vector location. example the CANx controller receive signal PEC services are very well suited to perform the (CANx_RxD) can be used to interrupt the system. transmission or the reception of blocks of data. This new function is controlled using the ‘External The ST10F269 has 8 PEC channels, each of Interrupt Source Selection’ register EXISEL. EXISEL (F1DAh / EDh) ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection (x=7...0) ‘00’: Input from associated Port 2 pin. ‘01’: Input from “alternate source”. ‘10’: Input from Port 2 pin ORed with “alternate source”. ‘11’: Input from Port 2 pin ANDed with “alternate source”. EXIxSS Port 2 pin Alternate Source 0P2.8 CAN1_RxD 1P2.9 CAN2_RxD 2 P2.10 RTCSI (Timed) 3 P2.11 RTCAI (Alarm) 4...7 P2.12...15 Not used (zero) 45/184 8 - INTERRUPT SYSTEM ST10F269 8.2 - Interrupt Registers and Vectors Location List Table 7 shows all the available ST10F269 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 7 : Interrupt Sources Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h 46/184 ST10F269 8 - INTERRUPT SYSTEM Table 7 : Interrupt Sources (continued) Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh CAN1 Interface XP0IR XP0IE XP0INT 00’0100h 40h CAN2 Interface XP1IR XP1IE XP1INT 00’0104h 41h FLASH Ready / Busy XP2IR XP2IE XP2INT 00’0108h 42h PLL Unlock/OWD XP3IR XP3IE XP3INT 00’010Ch 43h Hardware traps are exceptions or error conditions required during one round of prioritization, the that arise during run-time. They cause immediate upper 8 bits of the respective register are non-maskable system reaction similar to a reserved. All interrupt control registers are bit standard interrupt service (branching to a addressable and all bits can be read or written via dedicated vector table location). software. The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag This allows each interrupt source to be register (TFR). Except when another higher programmed or modified with just one instruction. prioritized trap service is in progress, a hardware When accessing interrupt control registers trap will interrupt any other program execution. through instructions which operate on Word data Hardware trap services cannot not be interrupted types, their upper 8 bits (15...8) will return zeros, by standard interrupt or by PEC interrupts. when read, and will discard written data. 8.3 - Interrupt Control Registers The layout of the Interrupt Control registers shown All interrupt control registers are identically below applies to each xxIC register, where xx organized. The lower 8 bits of an interrupt control stands for the mnemonic for the respective register contain the complete interrupt status information of the associated source, which is source. 47/184 8 - INTERRUPT SYSTEM ST10F269 xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h 15 14 13 12 11 10 9876543210 -------- xxIR xxIE ILVL GLVL RW RW RW RW Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. Fh: Highest priority level 0h: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) ‘0’: Interrupt Request is disabled ‘1’: Interrupt Request is enabled xxIR Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request 8.4 - Exception and Error Traps List Table 8 shows all of the possible exceptions or error conditions that can arise during run-time: Table 8 : Trap Priorities Trap Trap Vector Trap Trap* Exception Condition Flag Vector Location Number Priority Reset Functions: Hardware Reset RESET 00’0000h 00h III Software Reset RESET 00’0000h 00h III Watchdog Timer Overflow RESET 00’0000h 00h III Class A Hardware Traps: Non-Maskable Interrupt NMI NMITRAP 00’0008h 02h II Stack Overflow STKOF STOTRAP 00’0010h 04h II Stack Underflow STKUF STUTRAP 00’0018h 06h II Class B Hardware Traps: Undefined Opcode UNDOPC BTRAP 00’0028h 0Ah I Protected Instruction Fault PRTFLT BTRAP 00’0028h 0Ah I Illegal word Operand Access ILLOPA BTRAP 00’0028h 0Ah I Illegal Instruction Access ILLINA BTRAP 00’0028h 0Ah I Illegal External Bus Access ILLBUS BTRAP 00’0028h 0Ah I Reserved [002Ch - 003Ch] [0Bh - 0Fh] Software Traps Any Any Current TRAP Instruction 0000h – 01FCh [00h - 7Fh] CPU in steps of 4h Priority * - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets. - Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. - The resets have the highest priority level and the same trap number. - The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced. 48/184 ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS 9 - CAPTURE/COMPARE (CAPCOM) UNITS The ST10F269 has two 16 channels CAPCOM underflow of timer T6 in module GPT2. This units as described in Figure 12. These support provides a wide range of variation for the timer generation and control of timing sequences on up period and resolution and allows precise to 32 channels with a maximum resolution of adjustments to application specific requirements. 200ns at 40MHz CPU clock on PQFP144 devices In addition, external count inputs for CAPCOM and 250ns at 32MHz CPU clock on TQFP144 timers T0 and T7 allow event scheduling for the devices. The CAPCOM units are typically used to capture/compare registers relative to external handle high speed I/O tasks such as pulse and events. waveform generation, pulse width modulation Each of the two capture/compare register arrays (PMW), Digital to Analog (D/A) conversion, contain 16 dual purpose capture/compare software timing, or time recording relative to registers, each of which may be individually external events. allocated to either CAPCOM timer T0 or T1 (T7 or Four 16-bit timers (T0/T1, T7/T8) with reload T8, respectively), and programmed for capture or registers provide two independent time bases for compare functions. Each of the 32 registers has the capture/compare register array (See Figures one associated port pin which serves as an input Figure 13 and Figure 14). pin for triggering the capture function, or as an The input clock for the timers is programmable to output pin to indicate the occurrence of a compare several prescaled values of the internal system event. Figure 12 shows the basic structure of the clock, or may be derived from an overflow/ two CAPCOM units. Figure 12 : CAPCOM Unit Block Diagram Reload Register TxREL x = 0, 7 CPU n 2 n = 3...10 Clock Interrupt Tx Request Input Pin CAPCOM Timer Tx TxIN Control GPT2 Timer T6 Over / Underflow Pin Mode 16 Control Sixteen 16-bit 16 Capture inputs (Capture (Capture/Compare) Capture / Compare* Compare outputs or Registers Interrupt Requests Compare) Pin CPU n 2 n = 3...10 Clock Interrupt Ty Request Input CAPCOM Timer Ty Control GPT2 Timer T6 Over / Underflow y = 1, 8 Reload Register TyREL 49/184 9 - CAPTURE/COMPARE (CAPCOM) UNITS ST10F269 * The CAPCOM2 unit provides 16 capture inputs, but only 12 compare outputs. CC24I to CC27I are inputs only. Figure 13 : Block Diagram of CAPCOM Timers T0 and T7 Reload Register TxREL Txl Input Control CPU X Clock GPT2 Timer T6 Interrupt MUX CAPCOM Timer Tx TxIR Over / Underflow Request Edge Select TxR Txl TxM TxIN Pin x = 0, 7 Txl Figure 14 : Block Diagram of CAPCOM Timers T1 and T8 Reload Register TxREL Txl CPU X Clock MUX GPT2 Timer T6 Interrupt CAPCOM Timer Tx TxIR Over / Underflow Request TxM TxR x = 1, 8 Note: When an external input signal is compared with the contents of the allocated connected to the input lines of both T0 and timers. T7, these timers count the input signal When a match occurs between the timer value synchronously. Thus the two timers can be and the value in a capture/compare register, regarded as one timer whose contents can be compared with 32 capture registers. specific actions will be taken based on the selected compare mode (see Table 9). When a capture/compare register has been selected for capture mode, the current contents of The input frequencies f , for the timer input Tx the allocated timer will be latched (captured) into selector Tx, are determined as a function of the the capture/compare register in response to an CPU clocks. The timer input frequencies, external event at the port pin which is associated resolution and periods which result from the with this register. In addition, a specific interrupt selected pre-scaler option in TxI when using a request for this capture/compare register is 40MHz CPU clock on PQFP144 devices (or a generated. 32MHz CPU clock on TQFP144 devices) are Either a positive, a negative, or both a positive and listed in Table 10 and Table 11 . a negative external signal transition at the pin can be selected as the triggering event. The contents The numbers for the timer periods are based on a of all registers which have been selected for one reload value of 0000h. Note that some numbers of the five compare modes are continuously may be rounded to 3 significant figures. 50/184 ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS Table 9 : Compare Modes Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double Register Two registers operate on one pin; pin toggles on each compare match; several compare events Mode per timer period are possible. Table 10 : CAPCOM Timer Input Frequencies, Resolution and Periods (PQFP144 devices) Timer Input Selection TxI f = 40MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Pre-scaler for f CPU Input Frequency 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs Period 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s Table 11 : CAPCOM Timer Input Frequencies, Resolution and Periods (TQFP144 devices) Timer Input Selection TxI f = 32MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Pre-scaler for f CPU Input Frequency 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.125KHz Resolution 250ns 500ns 1μs2μs4μs8μs16μs32μs Period 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 2.1s 51/184 10 - GENERAL PURPOSE TIMER UNIT ST10F269 10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ applies to the Gated Timer Mode of T3 and to the counter structure which is used for time related auxiliary timers T2 and T4 in Timer and Gated tasks such as event timing and counting, pulse Timer Mode. The count direction (up/down) for width and duty cycle measurements, pulse each timer is programmable by software or may generation, or pulse multiplication. The GPT unit be altered dynamically by an external signal on a contains five 16-bit timers organized into two port pin (TxEUD). separate modules GPT1 and GPT2. Each timer in each module may operate independently in In Incremental Interface Mode, the GPT1 timers several different modes, or may be concatenated (T2, T3, T4) can be directly connected to the with another timer of the same module. incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. 10.1 - GPT1 Direction and count signals are internally derived Each of the three timers T2, T3, T4 of the GPT1 from these two input signals so that the contents module can be configured individually for one of of the respective timer Tx corresponds to the four basic modes of operation: timer, gated timer, sensor position. The third position sensor signal counter mode and incremental interface TOP0 can be connected to an interrupt input. mode. Timer T3 has output toggle latches (TxOTL) which In timer mode, the input clock for a timer is derived changes state on each timer over flow / underflow. from the CPU clock, divided by a programmable The state of this latch may be output on port pins prescaler. (TxOUT) for time out monitoring of external hardware components, or may be used internally In counter mode, the timer is clocked in reference to clock timers T2 and T4 for high resolution of to external events. long duration measurements. Pulse width or duty cycle measurement is In addition to their basic operating modes, timers supported in gated timer mode where the T2 and T4 may be configured as reload or capture operation of a timer is controlled by the ‘gate’ level registers for timer T3. When used as capture or on an external input pin. For these purposes, each reload registers, timers T2 and T4 are stopped. timer has one associated port pin (TxIN) which The contents of timer T3 is captured into T2 or T4 serves as gate or clock input. in response to a signal at their associated input pins (TxIN). Table12 GPT1 Timer Input Frequencies, Resolution and Periods (PQFP144 devices) and Timer T3 is reloaded with the contents of T2 or T4 Table13 GPT1 Timer Input Frequencies, triggered either by an external signal or by a Resolution and Periods (TQFP144 devices) list selectable state transition of its toggle latch the timer input frequencies, resolution and periods T3OTL. When both T2 and T4 are configured to for each pre-scaler option at 40MHz (Table 12 alternately reload T3 on opposite state transitions GPT1 Timer Input Frequencies, Resolution and Periods (PQFP144 devices)) or 32MHz (Table 13 of T3OTL with the low and high times of a PWM signal, this signal canbeconstantly generated GPT1 Timer Input Frequencies, Resolution and Periods (TQFP144 devices)) CPU clock. This also without software intervention. Table 12 : GPT1 Timer Input Frequencies, Resolution and Periods (PQFP144 devices) Timer Input Selection T2I / T3I / T4I f = 40MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 8 16 32 64 128 256 512 1024 Input Freq 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs Period maximum 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s 52/184 ST10F269 10 - GENERAL PURPOSE TIMER UNIT Table 13 : GPT1 Timer Input Frequencies, Resolution and Periods (TQFP144 devices) Timer Input Selection T2I / T3I / T4I f = 32MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 8 16 32 64 128 256 512 1024 Input Freq 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.125KHz Resolution 250ns 500ns 1μs2μs4μs8μs16μs32μs Period maximum 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 2.1s Figure 15 : Block Diagram of GPT1 T2EUD U/D Interrupt GPT1 Timer T2 Request CPU Clock n 2 n=3...10 T2 Mode Reload T2IN Control Capture CPU Clock n T3OUT 2 n=3...10 T3 Mode GPT1 Timer T3 T3OTL T3IN Control U/D T3EUD Capture T4 Reload Interrupt T4IN Request Mode CPU Clock Control n 2 n=3...10 Interrupt GPT1 Timer T4 Request T4EUD U/D 10.2 - GPT2 be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The GPT2 module provides precise event control The CAPREL register may capture the contents of and time measurement. It includes two timers (T5, timer T5 based on an external signal transition on T6) and a capture/reload register (CAPREL). Both the corresponding port pin (CAPIN), and timer T5 timers can be clocked with an input clock which is may optionally be cleared after the capture derived from the CPU clock via a programmable procedure. This allows absolute time differences prescaler or with external signals. The count to be measured or pulse multiplication to be direction (up/down) for each timer is performed without software overhead. programmable by software or may additionally be altered dynamically by an external signal on a port The capture trigger (timer T5 to CAPREL) may pin (TxEUD). Concatenation of the timers is also be generated upon transitions of GPT1 timer supported via the output toggle latch (T6OTL) of T3 inputs T3IN and/or T3EUD. This is timer T6 which changes its state on each timer advantageous when T3 operates in Incremental overflow/underflow. Interface Mode. The state of this latch may be used to clock timer Table14 GPT2 Timer Input Frequencies, T5, or it may be output on a port pin (T6OUT). The Resolution and Period (PQFP144 devices) and overflow / underflow of timer T6 can additionally Table15 GPT2 Timer Input Frequencies, 53/184 10 - GENERAL PURPOSE TIMER UNIT ST10F269 Resolution and Period (TQFP144 devices) list the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz (or 32MHz) CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. Table 14 : GPT2 Timer Input Frequencies, Resolution and Period (PQFP144 devices) Timer Input Selection T5I / T6I f = 40MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 4 8 16 32 64 128 256 512 Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms Table 15 : GPT2 Timer Input Frequencies, Resolution and Period (TQFP144 devices) Timer Input Selection T5I / T6I f = 32MHz CPU 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 4 8 16 32 64 128 256 512 Input Freq 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz Resolution 125ns 250ns 500ns 1μs2μs4μs8μs16μs Period maximum 8.19ms 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 54/184 ST10F269 10 - GENERAL PURPOSE TIMER UNIT Figure 16 : Block Diagram of GPT2 T5EUD U/D CPU Clock n T5 2 n=2...9 Interrupt GPT2 Timer T5 Mode Request T5IN Control Clear Capture Interrupt CAPIN Request GPT2 CAPREL Reload Interrupt Request Toggle FF T6IN T6 T60TL GPT2 Timer T6 T6OUT Mode CPU Clock n 2 n=2...9 Control U/D to CAPCOM T6EUD Timers 55/184 11 - PWM MODULE ST10F269 11 - PWM MODULE The pulse width modulation module can generate single shot outputs. Table 16 and Table 17 show up to four PWM output signals using edge-aligned the PWM frequencies for different resolutions. The or centre-aligned PWM. In addition, the PWM level of the output signals is selectable and the module can generate PWM burst signals and PWM module can generate interrupt requests. Figure 17 : Block Diagram of PWM Module PPx Period Register * Match Comparator Clock 1 * PTx Up/Down/ Input 16-bit Up/Down Counter Clear Control Control Clock 2 Run Match POUTx Comparator Output Control Enable Shadow Register Write Control PWx Pulse Width Register* User readable / writeable register * Table 16 : PWM Unit Frequencies and Resolution at 40MHz CPU Clock (PQFP144 devices) Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 156.25kHz 39.1kHz 9.77kHz 2.44Hz 610Hz CPU Clock/64 1.6μs 2.44Hz 610Hz 152.6Hz 38.15Hz 9.54Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz CPU Clock/64 1.6μs 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz Table 17 : PWM Unit Frequencies and Resolution at 32MHz CPU Clock (TQFP144 devices) Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 31.25ns 125KHz 31.25KHz 7.81KHz 1.953KHz 976.6Hz CPU Clock/64 2.00μs 1.953KHz 488.3Hz 122.1Hz 30.52Hz 7.63Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 31.25ns 62.5KHz 15.62KHz 3.90KHz 976.6Hz 244.1Hz CPU Clock/64 2.00μs 976.6Hz 244.1Hz 61Hz 15.26Hz 3.81Hz 56/184 ST10F269 12 - PARALLEL PORTS 12 - PARALLEL PORTS 12.1 - Introduction the value of the output latch, modifies it, and writes it back to the output latch, thus also The ST10F269 MCU provides up to 111 I/O lines modifying the level at the pin. with programmable features. These capabilities bring very flexible adaptation of this MCU to wide I/O lines support an alternate function which is range of applications. detailed in the following description of each port. ST10F269 has 9 groups of I/O lines gathered as following: – Port 0 is a 2 time 8-bit port named P0L (Low as less significant Byte) and P0H (high as most sig- nificant Byte) – Port 1 is a 2 time 8-bit port named P1L and P1H – Port 2 is a 16-bit port – Port 3 is a 15-bit port (P3.14 line is not imple- mented) – Port 4 is a 8-bit port – Port 5 is a 16-bit port input only – Port 6, Port 7 and Port 8 are 8-bit port These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. For example the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bit-wise) for push-pull or open drain operation using ODPx registers. In addition, the sink and the source capability and the rise / fall time of the transition of the signal of some of the push-pull buffers can be programmed to fit the driving requirements of the application and to minimize EMI. This feature is implemented on Port 0, 1, 2, 3, 4, 6, 7 and 8 with the control registers POCONx. The output drivers capabilities of ALE, RD, WR control lines are programmable with the dedicated bits of POCON20 control register. The input threshold levels are programmable (TTL/CMOS) for 5 ports (2, 3, 4, 7, 8). The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with the PICON register control bits. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A read-modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads 57/184 12 - PARALLEL PORTS ST10F269 Figure 18 : SFRs and Pins Associated with the Parallel Ports 58/184 Data Input / Output Register Direction Control Registers Threshold / Open Drain Control Output Driver Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P0L - - - - - - - - Y Y Y Y Y Y Y Y DP0L E - - - - - - - - Y Y Y Y Y Y Y Y PICON E - - - - - - - - Y Y - Y Y Y Y Y POCON0L E - - - - - - - - Y Y Y Y Y Y Y Y P0H ---- - - - - YY YY YY YY DP0H E ---- - - - - YY YY YY YY POCON0H E ---- - - - - YY YY YY YY P1L ---- - - - - YY YY YY YY DP1L E ---- - - - - YY YY YY YY POCON1L E ---- - - - - YY YY YY YY P1H ---- - - - - YY YY YY YY DP1H E ---- - - - - YY YY YY YY POCON1H E ---- - - - - YY YY YY YY P2 YYYY Y Y YY YY YY YY YY DP2 YYY Y Y Y YY YY YY YY YY ODP2 E YYYY Y Y YY YY YY YY YY POCON2 E YYY Y Y Y YY YY YY YY YY P3 Y-Y Y Y Y YY YY YY YY YY DP3 Y- Y Y Y Y YY YY YY YY YY ODP3 E -- Y - Y Y YY YY YY YY YY POCON3 E Y- Y Y Y Y YY YY YY YY YY P4 ---- - - - - YY YY YY YY DP4 ---- - - - - YY YY YY YY ODP4 E ---- - - -- YY -- -- -- POCON4 E ---- - - - - YY YY YY YY P5DIDIS YYYY Y Y YY YY YYY YY Y P5 YYYY Y Y YY YY YY YY YY P6 ---- - - - - YY YY YY YY DP6 - --- - - - - Y YYY YY YY ODP6 E ---- - - - - YY YY YYY Y POCON6 E - --- - - - - Y YYY YY YY P7 ---- - - - - YY YY YY YY DP7 ---- - - - - YY YY YY YY ODP7 E ---- - - - - YY YY YY YY POCON7 E ---- - - - - YY YY YY YY P8 ---- - - - - YY YY YY YY DP8 - --- - - - - Y YYY YY YY ODP8 E ---- - - - - YY YY YYY Y POCON8 E - --- - - - - Y YYY YY YY POCON20 * E - --- - - - - Y YYY YY YY PICON: P2LIN P2HIN P3LIN P3HIN P4LIN P6LIN (to be implemented) * RD, WR, ALE lines only P7LIN P8LIN Y : Bit has an I/O function - : Bit has no I/O dedicated function or is not implemented E: Register belongs to ESFR area ST10F269 12 - PARALLEL PORTS 12.2 - I/O’s Special Features 12.2.2 - Input Threshold Control The standard inputs of the ST10F269 determine 12.2.1 - Open Drain Mode the status of input signals according to TTL levels. In order to accept and recognize noisy signals, Some of the I/O ports of ST10F269 support the CMOS-like input thresholds can be selected open drain capability. This programmable feature instead of the standard TTL thresholds for all pins may be used with an external pull-up resistor, in of Port 2, Port 3, Port 4, Port 7 and Port 8. These special thresholds are defined above the TTL order to get an AND wired logical function. thresholds and feature a defined hysteresis to prevent the inputs from toggling while the This feature is implemented for ports P2, P3, P4, respective input signal level is near the thresholds. P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain The Port Input Control register PICON is used to select these thresholds for each Byte of the Control Registers ODPx. These registers allow indicated ports, this means the 8-bit ports P4, P7 the individual bit-wise selection of the open drain and P8 are controlled by one bit each while ports mode for each port line. If the respective control P2 and P3 are controlled by two bits each. bit ODPx.y is ‘0’ (default after reset), the output All options for individual direction and output mode driver is in the push-pull mode. If ODPx.y is ‘1’, the control are available for each pin, independent of open drain configuration is selected. Note that all the selected input threshold. The input hysteresis ODPx registers are located in the ESFR space provides stable inputs from noisy or slowly (See Figure 19). changing external signals (See Figure 20). PICON (F1C4h / E2h) ESFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- P8LINP7LIN - P4LINP3HINP3LINP2HINP2LIN RW RW RW RW RW RW RW Bit Function PxLIN Port x Low Byte Input Level Selection 0: Pins Px.7...Px.0 switch on standard TTL input levels 1: Pins Px.7...Px.0 switch on special threshold input levels PxHIN Port x High Byte Input Level Selection 0: Pins Px.15...Px.8 switch on standard TTL input levels 1: Pins Px.15...Px.8 switch on special threshold input levels Figure 19 : Output Drivers in Push-pull Mode and in Open Drain Mode External Pullup Pin Pin Q Q Push-Pull Output Driver Open Drain Output Driver 59/184 12 - PARALLEL PORTS ST10F269 Figure 20 : Hysteresis for Special Input Thresholds Hysteresis Input level Bit state 12.2.3 - Output Driver Control driver strength is reduced after the target output level has been reached or not. Reducing the The port output control registers POCONx allow driver strength increases the output’s internal to select the port output driver characteristics of a resistance, which attenuates noise that is port. The aim of these selections is to adapt the imported via the output line. For driving LEDs or output drivers to the application’s requirements, power transistors, however, a stable high output and to improve the EMI behaviour of the device. current may still be required as described below. Two characteristics may be selected: Edge characteristic defines the rise/fall time for This rise / fall time of 4 I/O pads (a nibble) is the respective output. Slow edges reduce the selected using 2-bit named PNxEC. That means peak currents that are sinked/sourced when Port Nibble (x = nibble number, it could be 3 as for changing the voltage level of an external Port 2.15 to 2.12) Edge Characteristic. capacitive load. For a bus interface or pins that are changing at frequency higher than 1MHz, The sink / source capability of the same 4 I/O however, fast edges may still be required. pads is selected using 2-bit named PNxDC. That Driver characteristic defines either the general means Port Nibble (x = nibble number) Drive driving capability of the respective driver, or if the Characteristic (See Table 18). POCONx (F0yyh / zzh) for 8-bit Ports ESFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- PN1DC PN1EC PN0DC PN0EC RW RW RW RW POCONx (F0yyh / zzh) for 16-bit Ports ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PN0DC PN0EC RW RW RW RW RW RW RW RW Bit Function PNxEC Port Nibble x Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the size of the driver. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PNxDC Port Nibble x Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved Note: In case of reading an 8 bit P0CONX register, high Byte (bit 15..8) is read as 00h 60/184 ST10F269 12 - PARALLEL PORTS The table lists the defined POCON registers and the allocation of control bit-fields and port pins. Table 18 : Port Control Register Allocation Controlled Port Nibble Control Physical 8-bit Register Address Address 3 210 POCON0L F080h 40h P0L.7...4 P0L.3...0 POCON0H F082h 41h P0H.7...4 P0H.3...0 POCON1L F084h 42h P1L.7...4 P1L.3...0 POCON1H F086h 43h P1H.7...4 P1H.3...0 POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0 POCON3 F08Ah 45h P3.15, 3.13, 3.12 P3.11...8 P3.7...4 P3.3...0 POCON4 F08Ch 46h P4.7...4 P4.3...0 POCON6 F08Eh 47h P6.7...4 P6.3...0 POCON7 F090h 48h P7.7...4 P7.3...0 POCON8 F092h 49h P8.7...4 P8.3...0 Dedicated Pins Output Control Programmable pad drivers also are supported for the dedicated pins ALE, RD and WR. For these pads, a special POCON20 register is provided. POCON20 (F0AAh / 55h) ESFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- PN1DC PN1EC PN0DC PN0EC RW RW RW RW PN0EC RD, WR Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the size of the driver. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PN0DC RD, WR Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved PN1EC ALE Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the size of the driver. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PN1DC ALE Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved 61/184 12 - PARALLEL PORTS ST10F269 12.2.4 - Alternate Port Functions In this case, the pin reflects the state of the port output latch. Thus, the alternate input function Each port line has one associated programmable reads the value stored in the port output latch. alternate input or output function. This can be used for testing purposes to allow a software trigger of an alternate input function by – PORT0 and PORT1 may be used as address writing to the port output latch. and data lines when accessing external memory. On most of the port lines, the application software – Port 2, Port 7 and Port 8 are associated with the must set the proper direction when using an capture inputs or compare outputs of the CAP- COM units and/or with the outputs of the PWM alternate input or output function of a pin. This is module. done by setting or clearing the direction control bit Port 2 is also used for fast external interrupt in- DPx.y of the pin before enabling the alternate puts and for timer 7 input. function. There are port lines, however, where the direction of the port line is switched automatically. – Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal For instance, in the multiplexed external bus BHE and the system clock output (CLKOUT). modes of PORT0, the direction must be switched several times for an instruction fetch in order to – Port 4 outputs the additional segment address output the addresses and to input the data. bit A16 to A23 in systems where segmentation Obviously, this cannot be done through is enabled to access more than 64K Bytes of memory. instructions. In these cases, the direction of the port line is switched automatically by hardware if – Port 5 is used as analog input channels of the the alternate function of such a pin is enabled. A/D converter or as timer control signals. To determine the appropriate level of the port output latches check how the alternate data – Port 6 provides optional bus arbitration signals output is combined with the respective port latch (BREQ, HLDA, HOLD) and chip select signals. output. If an alternate output function of a pin is to be There is one basic structure for all port lines used, the direction of this pin must be supporting only one alternate input function. Port programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset and lines with only one alternate output function, are configured automatically. Otherwise the pin however, have different structures. It has to be remains in the high-impedance state and is not adapted to support the normal and the alternate effected by the alternate output function. The function features. respective port latch should hold a ‘1’, because its output is ANDed with the alternate output data All port lines that are not used for these alternate (except for PWM output signals). functions may be used as general purpose I/O lines. When using port pins for general purpose If an alternate input function of a pin is used, the output, the initial output value should be written to direction of the pin must be programmed for input the port latch prior to enabling the output drivers, (DPx.y=‘0’) if an external device is driving the pin. in order to avoid undesired transitions on the The input direction is the default after reset. If no output pins. This applies to single pins as well as external device is connected to the pin, however, one can also set the direction for this pin to output. to pin groups (see examples below). SINGLE_BIT: BSET P4.7 ; Initial output level is "high" BSET DP4.7 ; Switch on the output driver BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high" BFLDH DP4, #24H, #24H ; Switch on the output drivers Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not apply to the respective port (See Chapter : Central Processing Unit (CPU) on page 35). 62/184 ST10F269 12 - PARALLEL PORTS 12.3 - PORT0 The two 8-bit ports P0H and P0L represent the If this port is used for general purpose I/O, the higher and lower part of PORT0, respectively. direction of each line can be configured via the Both halves of PORT0 can be written (via a PEC corresponding direction registers DP0H and transfer) without effecting the other half. DP0L. P0L (FF00h / 80h) SFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- P0L.7P0L.6P0L.5P0L.4P0L.3P0L.2P0L.1P0L.0 RW RW RW RW RW RW RW RW P0H (FF02h / 81h) SFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- P0H.7P0H.6P0H.5P0H.4P0H.3P0H.2P0H.1P0H.0 RW RW RW RW RW RW RW RW P0X.y Port Data Register P0H or P0L Bit y DP0L (F100h / 80h) ESFR Reset Value: --00h 15141312111098 76543 210 -------- DP0L.7DP0L.6DP0L.5DP0L.4DP0L.3DP0L.2DP0L.1DP0L.0 RW RW RW RW RW RW RW RW DP0H (F102h / 81h) ESFR Reset Value: --00h 15141312111098 76543 210 -------- DP0H.7DP0H.6DP0H.5DP0H.4DP0H.3DP0H.2DP0H.1DP0H.0 RW RW RW RW RW RW RW RW DP0X.y Port Direction Register DP0H or DP0L Bit y DP0X.y = 0: Port line P0X.y is an input (high-impedance) DP0X.y = 1: Port line P0X.y is an output 63/184 12 - PARALLEL PORTS ST10F269 12.3.1 - Alternate Functions of PORT0 With the end of reset, the selected bus configuration will be written to the BUSCON0 When an external bus is enabled, PORT0 is used register. as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only The configuration of the high byte of PORT0, will uses P0L, while P0H is free for I/O (provided that be copied into the special register RP0H. This no other bus mode is enabled). read-only register holds the selection for the PORT0 is also used to select the system start-up number of chip selects and segment addresses. configuration. During reset, PORT0 is configured Software can read this register in order to react to input, and each line is held high through an according to the selected configuration, if internal pull-up device. required. Each line can now be individually pulled to a low When the reset is terminated, the internal pull-up level (see Section 21.3 -: DC Characteristics) devices are switched off, and PORT0 will be through an external pull-down device. A default switched to the appropriate operating mode. configuration is selected when the respective During external accesses in multiplexed bus PORT0 lines are at a high level. Through pulling modes PORT0 first outputs the 16-bit individual lines to a low level, this default can be intra-segment address as an alternate output changed according to the needs of the function. PORT0 is then switched to applications. high-impedance input mode to read the incoming The internal pull-up devices are designed in such instruction or data. In 8-bit data bus mode, two way that an external pull-down resistors (see Data memory cycles are required for word accesses, Sheet specification) can be used to apply a the first for the low Byte and the second for the correct low level. high Byte of the Word. These external pull-down resistors can remain connected to the PORT0 pins also during normal During write cycles PORT0 outputs the data Byte operation, however, care has to be taken in order or Word after outputting the address. During to not disturb the normal function of PORT0 (this external accesses in demultiplexed bus modes might be the case, for example, if the external PORT0 reads the incoming instruction or data resistor value is too low). Word or outputs the data Byte or Word. Figure 21 : PORT0 I/O and Alternate Functions Alternate Function a) b) c) d) AD15 P0H.7 D15 A15 AD14 P0H.6 D14 A14 P0H.5 AD13 D13 A13 AD12 P0H.4 D12 A12 P0H P0H.3 AD11 D11 A11 AD10 P0H.2 D10 A10 AD9 P0H.1 D9 A9 P0H.0 AD8 D8 A8 PORT0 AD7 P0L.7 D7 D7 AD7 D6 AD6 P0L.6 D6 AD6 P0L.5 D5 AD5 D5 AD5 AD4 P0L.4 D4 D4 AD4 P0L P0L.3 D3 AD3 D3 AD3 AD2 P0L.2 D2 D2 AD2 D1 AD1 P0L.1 D1 AD1 P0L.0 D0 AD0 D0 AD0 General Purpose 8-bit 16-bit 8-bit 16-bit Input/Output Demultiplexed Bus Demultiplexed Bus Multiplexed Bus Multiplexed Bus 64/184 ST10F269 12 - PARALLEL PORTS When an external bus mode is enabled, the “Alternate Data Input”. While an external bus direction of the port pin and the loading of data mode is enabled, the user software should not into the port output latch are controlled by the bus write to the port output latch, otherwise controller hardware. unpredictable results may occur. The input of the port output Buffer is disconnected When the external bus modes are disabled, the from the internal bus and is switched to the line contents of the direction register last written by the labeled “Alternate Data Output” via a multiplexer. user becomes active. The alternate data can be the 16-bit intra-segment address or the 8/16-bit data information. The The Figure 22 shows the structure of a PORT0 incoming data on PORT0 is read on the line pin. Figure 22 : Block Diagram of a PORT0 Pin Write DP0H.y / DP0L.y Alternate 1 Direction MUX Direction 0 Latch Read DP0H.y / DP0L.y Alternate Function Enable Alternate Data Output Write P0H.y / P0L.y 1 P0H.y Port Data MUX P0L.y Output Output Port Output 0 Buffer Latch Read P0H.y / P0L.y Clock 1 MUX Input 0 y = 7...0 Latch 65/184 Internal Bus 12 - PARALLEL PORTS ST10F269 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. P1L (FF04h / 82h) SFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- P1L.7P1L.6P1L.5P1L4P1L.3P1L.2P1L.1P1L.0 RW RW RW RW RW RW RW RW P1H (FF06h / 83h) SFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- P1H.7P1H.6P1H.5P1H.4P1H.3P1H.2P1H.1P1H.0 RW RW RW RW RW RW RW RW P1X.y Port Data Register P1H or P1L Bit y DP1L (F104h / 82h) ESFR Reset Value: --00h 1514131211109 8 76543210 - - - - - - - - DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0 RW RW RW RW RW RW RW RW DP1H (F106h / 83h) ESFR Reset Value: --00h 1514131211109 8 76543210 - - - - - - - - DP1H.7 DP1H.6 DP1H.5 DP1H.4 DP1H.3 DP1H.2 DP1H.1 DP1H.0 RW RW RW RW RW RW RW RW DP1X.y Port Direction Register DP1H or DP1L Bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output 12.4.1 - Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note: Demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose I/O. The upper 4 pins of PORT1 (P1H.7...P1H.4) are used as capture input lines (CC27IO...CC24IO). During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intra-segment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a demultiplexed bus mode, PORT1 is not used and is available for general purpose I/O. 66/184 ST10F269 12 - PARALLEL PORTS Figure 23 : PORT1 I/O and Alternate Functions Alternate Function a) b) P1H.7 A15 CC27IO P1H.6 A14 CC26IO P1H.5 A13 CC25IO P1H.4 A12 CC24IO P1H P1H.3 A11 P1H.2 A10 P1H.1 A9 P1H.0 A8 PORT1 P1L.7 A7 P1L.6 A6 P1L.5 A5 P1L.4 A4 P1L P1L.3 A3 P1L.2 A2 P1L.1 A1 P1L.0 A0 General Purpose Input/Output 8/16-bit Demultiplexed Bus CAPCOM2 Capture Inputs only When an external bus mode is enabled, the address. While an external bus mode is enabled, direction of the port pin and the loading of data the user software should not write to the port into the port output latch are controlled by the bus output latch, otherwise unpredictable results may controller hardware. occur. When the external bus modes are disabled, the contents of the direction register last written by The input of the port Buffer latch is disconnected the user becomes active. from the internal bus and is switched to the line labeled “Alternate Data Output” via a multiplexer. The Figure 24 shows the structure of a PORT1 The alternate data is the 16-bit intra-segment pin. Figure 24 : Block Diagram of a PORT1 Pin Write DP1H.y / DP1L.y “1” 1 MUX Direction 0 Latch Read DP1H.y / DP1L.y Alternate Function Enable Alternate Data Output Write P1H.y / P1L.y 1 P1H.y Port Data MUX P1L.y Output Output Port Output 0 Buffer Latch Read P1H.y / P1L.y Clock 1 MUX Input 0 Latch y = 7...0 67/184 Internal Bus 12 - PARALLEL PORTS ST10F269 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. P2 (FFC0h / E0h) SFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P2.y Port Data Register P2 Bit y DP2 (FFC2h / E1h) SFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 .15 .14 .13 .12 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DP2.y Port Direction Register DP2 Bit y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 .15 .14 .13 .12 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ODP2.y Port 2 Open Drain Control Register Bit y ODP2.y = 0: Port line P2.y output driver in push/pull mode ODP2.y = 1: Port line P2.y output driver in open drain mode 12.5.1 - Alternate Functions of Port 2 external device may drive the pin, otherwise conflicts would occur. All Port 2 lines (P2.15...P2.0) serve as capture When a Port 2 line is used as a compare output inputs or compare outputs (CC15IO...CC0IO) for (compare modes 1 and 3), the compare event (or the CAPCOM1 unit. the timer overflow in compare mode 3) directly When a Port 2 line is used as a capture input, the effects the port output latch. In compare mode 1, state of the input latch, which represents the state when a valid compare match occurs, the state of of the port pin, is directed to the CAPCOM unit via the port output latch is read by the CAPCOM the line “Alternate Pin Data Input”. If an external control hardware via the line “Alternate Latch Data capture trigger signal is used, the direction of the Input”, inverted, and written back to the latch via respective pin must be set to input. the line “Alternate Data Output”. The port output latch is clocked by the signal If the direction is set to output, the state of the port “Compare Trigger” which is generated by the output latch will be read since the pin represents CAPCOM unit. In compare mode 3, when a match the state of the output latch. occurs, the value '1' is written to the port output This can be used to trigger a capture event latch via the line “Alternate Data Output”. When through software by setting or clearing the port an overflow of the corresponding timer occurs, a latch. Note that in the output configuration, no '0' is written to the port output latch. In both cases, 68/184 ST10F269 12 - PARALLEL PORTS the output latch is clocked by the signal “Compare multiplexer of the port output latch is switched to Trigger”. the line connected to the internal bus. The port output latch will receive the value from the internal The direction of the pin should be set to output by bus and the hardware triggered change will be the user, otherwise the pin will be in the lost. high-impedance state and will not reflect the state of the output latch. As all other capture inputs, the capture input As can be seen from the port structure in function of pins P2.15...P2.0 can also be used as Figure26, the user software always has free external interrupt inputs (200ns sample rate at access to the port pin even when it is used as a 40MHz CPU clock on PQFP144 devices and compare output. This is useful for setting up the 250ns sample rate at 32MHz CPU clock on initial level of the pin when using compare mode 1 TQFP144 devices). or the double-register mode. In these modes, The upper eight Port 2 lines (P2.15...P2.8) also unlike in compare mode 3, the pin is not set to a can serve as Fast External Interrupt inputs from specific value when a compare match occurs, but EX0IN to EX7IN (Fast external interrupt sampling is toggled instead. rate is 25ns at 40MHz CPU clock and 31.25ns at When the user wants to write to the port pin at the 32MHz CPU clock). same time a compare trigger tries to clock the output latch, the write operation of the user P2.15 in addition serves as input for CAPCOM2 software has priority. Each time a CPU write timer T7 (T7IN). The Table 19 summarizes the access to the port output latch occurs, the input alternate functions of Port 2. Table 19 : Alternate Functions of Port 2 Port 2 Pin Alternate Function a) Alternate Function b) Alternate Function c) P2.0 CC0IO - - P2.1 CC1IO - - P2.2 CC2IO - - P2.3 CC3IO - - P2.4 CC4IO - - P2.5 CC5IO - - P2.6 CC6IO - - P2.7 CC7IO - - P2.8 CC8IO EX0IN Fast External Interrupt 0 Input - P2.9 CC9IO EX1IN Fast External Interrupt 1 Input - P2.10 CC10IO EX2IN Fast External Interrupt 2 Input - P2.11 CC11IO EX3IN Fast External Interrupt 3 Input - P2.12 CC12IO EX4IN Fast External Interrupt 4 Input - P2.13 CC13IO EX5IN Fast External Interrupt 5 Input - P2.14 CC14IO EX6IN Fast External Interrupt 6 Input - P2.15 CC15IO EX7IN Fast External Interrupt 7 Input T7IN T7 External Count Input 69/184 12 - PARALLEL PORTS ST10F269 Figure 25 : Port 2 I/O and Alternate Functions Alternate Function a) b) c) P2.15 CC15IO EX7IN T7IN P2.14 CC14IO EX6IN P2.13 CC13IO EX5IN P2.12 CC12IO EX4IN P2.11 CC11IO EX3IN P2.10 CC10IO EX2IN P2.9 CC9IO EX1IN P2.8 CC8IO EX0IN Port 2 P2.7 CC7IO P2.6 CC6IO P2.5 CC5IO P2.4 CC4IO P2.3 CC3IO P2.2 CC2IO P2.1 CC1IO P2.0 CC0IO General Purpose CAPCOM1 Fast External CAPCOM2 Input / Output Capture Input / Compare Output Interrupt Input Timer T7 Input 70/184 ST10F269 12 - PARALLEL PORTS The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 26 : Block Diagram of a Port 2 Pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Direction Latch Read DP2.y 1 P2.y Output CCyIO MUX Latch Alternate Output EXxIN 0 Data Buffer Output ≥ 1 Write Port P2.y Compare Trigger Read P2.y Clock 1 MUX Input 0 Latch Alternate Data Input x = 7...0 y = 15...0 Fast External Interrupt Input 12.6 - Port 3 corresponding direction register DP3. Most port lines can be switched into push-pull or open drain If this 15-bit port is used for general purpose I/O, the direction of each line can be configured by the mode by the open drain control register ODP2 71/184 Internal Bus 12 - PARALLEL PORTS ST10F269 (pins P3.15, P3.14 and P3.12 do not support open Due to pin limitations register bit P3.14 is not drain mode). connected to an output pin. P3 (FFC4h / E2h) SFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 P3.15 - P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P3.y Port Data Register P3 Bit y DP3 (FFC6h / E3h) SFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 DP3 -DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 .15 .13 .12 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DP3.y Port Direction Register DP3 Bit y DP3.y = 0: Port line P3.y is an input (high-impedance) DP3.y = 1: Port line P3.y is an output ODP3 (F1C6h / E3h) ESFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 -- ODP3 -ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 .13 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ODP3.y Port 3 Open Drain Control Register Bit y ODP3.y = 0: Port line P3.y output driver in push-pull mode ODP3.y = 1: Port line P3.y output driver in open drain mode 72/184 ST10F269 12 - PARALLEL PORTS 12.6.1 - Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 20 : Port 3 Alternative Functions Port 3 Pin Alternate Function P3.0 T0IN CAPCOM1 Timer 0 Count Input P3.1 T6OUT Timer 6 Toggle Output P3.2 CAPIN GPT2 Capture Input P3.3 T3OUT Timer 3 Toggle Output P3.4 T3EUD Timer 3 External Up/Down Input P3.5 T4IN Timer 4 Count Input P3.6 T3IN Timer 3 Count Input P3.7 T2IN Timer 2 Count Input P3.8 MRST SSC Master Receive / Slave Transmit P3.9 MTSR SSC Master Transmit / Slave Receive P3.10 TxD0 ASC0 Transmit Data Output P3.11 RxD0 ASC0 Receive Data Input (Output in synchronous mode) P3.12 BHE/WRH Byte High Enable / Write High Output P3.13 SCLK SSC Shift Clock Input/Output P3.14 --- No pin assigned P3.15 CLKOUT System Clock Output Figure 27 : Port 3 I/O and Alternate Functions Alternate Function a) b) CLKOUT P3.15 No Pin SCLK P3.13 WRH BHE P3.12 RxD0 P3.11 TxD0 P3.10 MTSR P3.9 MRST P3.8 Port 3 T2IN P3.7 P3.6 T3IN T4IN P3.5 T3EUD P3.4 P3.3 T3OUT CAPIN P3.2 T6OUT P3.1 T0IN P3.0 General Purpose Input/Output The structure of the Port 3 pins depends on their with the port output latch line. When using these alternate function (see figures Figure 28 and alternate functions, the user must set the direction Figure 29). When the on-chip peripheral of the port line to output (DP3.y=1) and must set associated with a Port 3 pin is configured to use the port output latch (P3.y=1). Otherwise the pin is the alternate input function, it reads the input in its high-impedance state (when configured as latch, which represents the state of the pin, via the input) or the pin is stuck at '0' (when the port line labeled “Alternate Data Input”. Port 3 pins with output latch is cleared). When the alternate output alternate input functions are: T0IN, T2IN, T3IN, functions are not used, the “Alternate Data T4IN, T3EUD and CAPIN. Output” line is in its inactive state, which is a high level ('1'). When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate output Port 3 pins with alternate output functions are: function, its “Alternate Data Output” line is ANDed T6OUT, T3OUT, TxD0, BHE and CLKOUT. 73/184 12 - PARALLEL PORTS ST10F269 When the on-chip peripheral associated with with alternate input/output functions are: MTSR, MRST, RxD0 and SCLK. a Port 3 pin is configured to use both the alternate input and output function, the descriptions above Note: Enabling the CLKOUT function automati- apply to the respective current operating mode. cally enables the P3.15 output driver. Set- The direction must be set accordingly. Port 3 pins ting bit DP3.15=’1’ is not required. Figure 28 : Block Diagram of Port 3 Pin with Alternate Input or Alternate Output Function Write ODP3.y Open Drain Latch Read ODP3.y Write DP3.y Direction Latch Read DP3.y Alternate Data Output Write DP3.y Port Data & P3.y Output Port Output Output Latch Buffer Read P3.y Clock 1 MUX Input 0 Latch Alternate Data y = 13, 11...0 Input 74/184 Internal Bus ST10F269 12 - PARALLEL PORTS Pin P3.12 (BHE/WRH) is another pin with an possibility to program any port latches before. alternate output function, however, its structure is Thus, the appropriate alternate function is slightly different. selected automatically. If BHE/WRH is not used in the system, this pin can be used for general After reset the BHE or WRH function must be purpose I/O by disabling the alternate function used depending on the system start-up configuration. In either of these cases, there is no (BYTDIS = ‘1’ / WRCFG=’0’). Figure 29 : Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) Write DP3.x 1 “1” MUX Direction 0 Latch Read DP3.x Alternate Function Enable Write P3.x Alternate Data 1 Output P3.12/BHE MUX P3.15/CLKOUT Output Port Output 0 Buffer Latch Read P3.x Clock 1 MUX Input 0 Latch x = 15, 12 Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit DP3.12=’1’ is not required. During bus hold pin P3.12 is switched back to its standard function and is then controlled by DP3.12 and P3.12. Keep DP3.12 = ’0’ in this case to ensure floating in hold mode. 75/184 Internal Bus 12 - PARALLEL PORTS ST10F269 12.7 - Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. P4 (FFC8h / E4h) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 - - - - - - - - P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 RW RW RW RW RW RW RW RW P4.y Port Data Register P4 Bit y DP4 (FFCAh / E5h) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 --- -- --- DP4.7DP4.6DP4.5DP4.4DP4.3DP4.2DP4.1DP4.0 RW RW RW RW RW RW RW RW DP4.y Port Direction Register DP4 Bit y DP4.y = 0: Port line P4.y is an input (high-impedance) DP4.y = 1: Port line P4.y is an output For CAN configuration support (see section 15), Port 4 has an open drain function, controlled with the ODP4 register: ODP4 (F1CAh / E5h) ESFR Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - ODP4.7 ODP4.6 - - - - - - RW RW ODP4.y Port 4 Open Drain Control Register Bit y ODP4.y = 0: Port line P4.y output driver in push/pull mode ODP4.y = 1: Port line P4.y output driver in open drain mode if P4.y is not a segment address line output Note: Only bit 6 and 7 are implemented, all other bit will be read as “0”. 76/184 ST10F269 12 - PARALLEL PORTS 12.7.1 - Alternate Functions of Port 4 The number of segment address lines is selected via PORT0 during reset. The selected value can During external bus cycles that use segmentation be read from bitfield SALSEL in register RP0H (address space above 64K Bytes) a number of (read only) in order to check the configuration Port 4 pins may output the segment address lines. during run time. The number of pins that is used for segment The CAN interfaces use 2 or 4 pins of Port 4 to address output determines the external address interface each CAN Modules to an external CAN space which is directly accessible. The other pins transceiver. In this case the number of possible of Port 4 may be used for general purpose I/O. If segment address lines is reduced. segment address lines are selected, the alternate function of Port 4 may be necessary to access The Table 21 summarizes the alternate functions external memory directly after reset. For this of Port 4 depending on the number of selected reason Port 4 will be switched to this alternate segment address lines (coded via bitfield function automatically. SALSEL) Table 21 : Port 4 Alternate Functions Standard Function Alternate Function Alternate Function Alternate Function Port 4 SALSEL = 01 SALSEL = 11 SALSEL = 00 SALSEL = 10 64K Bytes 256K Bytes 1M Byte 16M Bytes P4.0 GPIO Segment Address A16 Segment. Address A16 Segment Address A16 P4.1 GPIO Segment Address A17 Segment Address A17 Segment Address A17 P4.2 GPIO GPIO Segment Address A18 Segment Address A18 P4.3 GPIO GPIO Segment Address A19 Segment Address A19 P4.4 GPIO/CAN2_RxD GPIO/CAN2_RxD GPIO/CAN2_RxD Segment Address A20 P4.5 GPIO/CAN1_RxD GPIO/CAN1_RxD GPIO/CAN1_RxD Segment Address A21 P4.6 GPIO/CAN1_TxD GPIO/CAN1_TxD GPIO/CAN1_TxD Segment Address A22 P4.7 GPIO/CAN2_TxD GPIO/CAN2_TxD GPIO/CAN2_TxD Segment Address A23 Figure 30 : Port 4 I/O and Alternate Functions Alternate Function b) a) Port 4 CAN2_TxD P4.7 A23 P4.6 CAN1_TxD A22 P4.5 CAN1_RxD A21 P4.4 CAN2_RxD A20 P4.3 A19 - P4.2 A18 - P4.1 A17 - P4.0 A16 - Segment Address Cans I/O and General Purpose General Purpose Lines Input / Output Input / Output 77/184 12 - PARALLEL PORTS ST10F269 Figure 31 : Block Diagram of a Port 4 Pin Write DP4.y “1” 1 MUX Direction 0 Latch Read DP4.y Alternate Function Enable Write P4.y Alternate Data 1 Output P4.y MUX Output Port Output 0 Buffer Latch Read P4.y Clock 1 MUX Input 0 Latch y = 7...0 78/184 Internal Bus ST10F269 12 - PARALLEL PORTS Figure 32 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x “1” 1 “0” 1 MUX MUX Direction 0 0 Latch Read DP4.x “0” 1 MUX Alternate Function 0 Enable Write P4.x Alternate Data 1 Output P4.x MUX Port Output 0 Latch Output Buffer Read P4.x Clock 1 MUX Input 0 Latch CANy.RxD & XPERCON.a (CANyEN) x = 5, 4 y = 1, 2 (CAN Channel) ≤ 1 z = 2, 1 XPERCON.b (CANzEN) a = 0, 1 b = 1, 0 79/184 Internal Bus 12 - PARALLEL PORTS ST10F269 Figure 33 : Block Diagram of P4.6 and P4.7 Pins Write ODP4.x Open Drain 1 Latch MU MUX X Read ODP4.x "0" 0 Write DP4.x 1 1 "1" "1" MUX MU MUX X Direction 0 0 Latch Read DP4.x "0" 1 MUX Alternate Function 0 Enable Write P4.x Alternate 1 Data 1 Output MUX MU MUX X Port Output 0 Latch 0 Output P4.x Buffer Read P4.x Clock 1 MUX Input 0 Latch CANy.TxD Data output XPERCON.a (CANyEN) x = 6, 7 y = 1, 2 (CAN Channel) z = 2, 1 ≤ 1 a = 0, 1 XPERCON.b b = 1, 0 (CANzEN) 12.8 - Port 5 This 16-bit input port can only read data. There is no output latch and no direction register. Data written to P5 will be lost. P5 (FFA2h / D1h) SFR Reset Value: XXXXh 15 14 13 12 11 10 98 765 432 10 P5.15 P5.14 P5.13 P5.12 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 RRR RRR RR RRR RRR RR P5.y Port Data Register P5 Bit y (Read only) 80/184 Internal Bus ST10F269 12 - PARALLEL PORTS 12.8.1 - Alternate Functions of Port 5 shall be used as analog inputs. Some pins of Port 5 also serve as external timer control lines for Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All GPT1 and GPT2. port lines (P5.15...P5.0) can accept analog The Table 22 summarizes the alternate functions signals (AN15...AN0) to be converted by the ADC. No special programming is required for pins that of Port 5. Table 22 : Port 5 Alternate Functions Port 5 Pin Alternate Function a) Alternate Function b) P5.0 Analog Input AN0 - P5.1 Analog Input AN1 - P5.2 Analog Input AN2 - P5.3 Analog Input AN3 - P5.4 Analog Input AN4 - P5.5 Analog Input AN5 - P5.6 Analog Input AN6 - P5.7 Analog Input AN7 - P5.8 Analog Input AN8 - P5.9 Analog Input AN9 - P5.10 Analog Input AN10 T6EUD Timer 6 external Up/Down Input P5.11 Analog Input AN11 T5EUD Timer 5 external Up/Down Input P5.12 Analog Input AN12 T6IN Timer 6 Count Input P5.13 Analog Input AN13 T5IN Timer 5 Count Input P5.14 Analog Input AN14 T4EUD Timer 4 external Up/Down Input P5.15 Analog Input AN15 T2EUD Timer 2 external Up/Down Input Figure 34 : Port 5 I/O and Alternate Functions Alternate Function a) b) P5.15 AN15 T2EUD P5.14 AN14 T4EUD T5IN P5.13 AN13 P5.12 AN12 T6IN P5.11 AN11 T5EUD T6EUD P5.10 AN10 P5.9 AN9 P5.8 AN8 Port 5 P5.7 AN7 P5.6 AN6 P5.5 AN5 P5.4 AN4 P5.3 AN3 P5.2 AN2 P5.1 AN1 P5.0 AN0 A/D Converter Inputs General Purpose Inputs Timer Inputs 81/184 12 - PARALLEL PORTS ST10F269 Port 5 pins have a special port structure (see Figure 35), first because it is an input only port, and second because the analog input channels are directly connected to the pins rather than to the input latches. Figure 35 : Block Diagram of a Port 5 Pin Channel Select Analog to Sample + Hold Switch Circuit P5.y/ANy Read Port P5.y Clock Input Latch Read y = 15...0 Buffer 12.8.2 - Port 5 Schmitt Trigger Analog Inputs A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register P5DIDIS. P5DIDIS (FFA4h / D2h) SFR Reset Value: 0000h 15 14 13 12 11 10 98 765 432 10 P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI P5DI DIS.15 DIS.14 DIS.13 DIS.12 DIS.11 DIS.10 DIS.9 DIS.8 DIS.7 DIS.6 DIS.5 DIS.4 DIS.3 DIS.2 DIS.1 DIS.0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P5DIDIS.y Port 5 Digital Disable Register Bit y P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled) P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage current reduction) 12.9 - Port 6 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6. P6 (FFCCh / E6h) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 - - - - - - - - P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 RW RW RW RW RW RW RW RW P6.y Port Data Register P6 Bit y DP6 (FFCEH / E7H) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 --- -- --- DP6.7DP6.6DP6.5DP6.4DP6.3DP6.2DP6.1DP6.0 RW RW RW RW RW RW RW RW 82/184 Internal Bus ST10F269 12 - PARALLEL PORTS DP6.y Port Direction Register DP6 Bit y DP6.y = 0: Port line P6.y is an input (high impedance) DP6.y = 1: Port line P6.y is an output ODP6 (F1CEH / E7H) ESFR Reset Value: --00h 1514131211109 8 76543210 - ------- ODP6.7ODP6.6ODP6.5ODP6.4ODP6.3ODP6.2ODP6.1ODP6.0 RW RW RW RW RW RW RW RW ODP6.y Port 6 Open Drain Control Register Bit y ODP6.y = 0: Port line P6.y output driver in push-pull mode ODP6.y = 1: Port line P6.y output driver in open drain mode 12.9.1 - Alternate Functions of Port 6 A programmable number of chip select signals (CS4...CS0) derived from the bus control registers (BUSCON4...BUSCON0) can be output on 5 pins of Port 6. The number of chip select signals is selected via PORT0 during reset. The selected value can be read from bit-field CSSEL in register RP0H (read only) in order to check the configuration during run time. The Table 23 summarizes the alternate functions of Port 6 depending on the number of selected chip select lines (coded via bit-field CSSEL). Table 23 : Port 6 Alternate Functions Alternate Function Alternate Function Alternate Function Alternate Function Port 6 CSSEL = 10 CSSEL = 01 CSSEL = 00 CSSEL = 11 P6.0 General purpose I/O Chip select CS0 Chip select CS0 Chip select CS0 P6.1 General purpose I/O Chip select CS1 Chip select CS1 Chip select CS1 P6.2 General purpose I/O General purpose I/O Chip select CS2 Chip select CS2 P6.3 General purpose I/O General purpose I/O General purpose I/O Chip select CS3 P6.4 General purpose I/O General purpose I/O General purpose I/O Chip select CS4 P6.5 HOLD External hold request input P6.6 HLDA Hold acknowledge output P6.7 BREQ Bus request output Figure 36 : Port 6 I/O and Alternate Functions Alternate Function a) Port 6 BREQ P6.7 P6.6 HLDA P6.5 HOLD CS4 P6.4 P6.3 CS3 P6.2 CS2 P6.1 CS1 P6.0 CS0 General Purpose Input/Output 83/184 12 - PARALLEL PORTS ST10F269 The chip select lines of Port 6 have an internal alternate function (CS) is selected automatically in weak pull-up device. This device is switched on this case. during reset. This feature is implemented to drive Note: The open drain output option can only be the chip select lines high during reset in order to selected via software earliest during the avoid multiple chip selection. After reset the CS function must be used, if initialization routine; at least signal CS0 will be in push/pull output driver mode selected so. In this case there is no possibility to program any port latches before. Thus the directly after reset. Figure 37 : Block Diagram of Port 6 Pins with an Alternate Output Function Write ODP6.y Open Drain 1 Latch MU MUX X Read ODP6.y "0" 0 Write DP6.y "1" 1 MUX Direction 0 Latch Read DP6.y Alternate Function Enable Write DP6.y Alternate 1 Data Output MUX P6.y Port Output Output Latch 0 Buffer Read P6.y Clock 1 MUX Input 0 Latch y = (0...4, 6, 7) 84/184 Internal Bus ST10F269 12 - PARALLEL PORTS Figure 38 : Block Diagram of Pin P6.5 (HOLD) Write ODP6.5 Open Drain Latch Read ODP6.5 Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output P6.5/HOLD Latch Output Buffer Read P6.5 Clock 1 MUX Input 0 Latch Alternate Data Input 85/184 Internal Bus 12 - PARALLEL PORTS ST10F269 12.10 - Port 7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push-pull or open drain mode via the open drain control register ODP7. P7 (FFD0h / E8h) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 - - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 RW RW RW RW RW RW RW RW P7.y Port Data Register P7 Bit y DP7 (FFD2h / E9h) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 --- -- --- DP7.7DP7.6DP7.5DP7.4DP7.3DP7.2DP7.1DP7.0 RW RW RW RW RW RW RW RW DP7.y Port Direction Register DP7 Bit y DP7.y = 0: Port line P7.y is an input (high impedance) DP7.y = 1: Port line P7.y is an output ODP7 (F1D2h / E9h) ESFR Reset Value: --00h 151413121110 9 8 76543 210 ----- --- ODP7.7ODP7.6ODP7.5ODP7.4ODP7.3ODP7.2ODP7.1ODP7.0 RW RW RW RW RW RW RW RW ODP7.y Port 7 Open Drain Control Register Bit y ODP7.y = 0: Port line P7.y output driver in push-pull mode ODP7.y = 1: Port line P7.y output driver in open drain mode 86/184 ST10F269 12 - PARALLEL PORTS 12.10.1 - Alternate Functions of Port 7 The lower 4 lines of Port 7 (P7.3...P7.0) serve as outputs from the PWM module The upper 4 lines of Port 7 (P7.7...P7.4) serve as (POUT3...POUT0). capture inputs or compare outputs At these pins the value of the respective port (CC31IO...CC28IO) for the CAPCOM2 unit. output latch is EXORed with the value of the PWM The usage of the port lines by the CAPCOM unit, output rather than ANDed, as the other pins do. its accessibility via software and the precautions This allows to use the alternate output value either are the same as described for the Port 2 lines. as it is (port latch holds a ‘0’) or to invert its level at As all other capture inputs, the capture input the pin (port latch holds a ‘1’). function of pins P7.7...P7.4 can also be used as Note that the PWM outputs must be enabled via external interrupt inputs (200ns sample rate at the respective PENx bit in PWMCON1. 40MHz CPU clock on PQFP144 devices and 250ns sample rate at 32MHz CPU clock on The Table 24 summarizes the alternate functions TQFP144 devices). of Port 7. Table 24 : Port 7 Alternate Functions Port 7 Alternate Function P7.0 POUT0 PWM mode channel 0 output P7.1 POUT1 PWM mode channel 1 output P7.2 POUT2 PWM mode channel 2 output P7.3 POUT3 PWM mode channel 3 output P7.4 CC28IO Capture input / compare output channel 28 P7.5 CC29IO Capture input / compare output channel 29 P7.6 CC30IO Capture input / compare output channel 30 P7.7 CC31IO Capture input / compare output channel 31 Figure 39 : Port 7 I/O and Alternate Functions Port 7 P7.7 CC31IO P7.6 CC30IO P7.5 CC29IO P7.4 CC28IO P7.3 POUT3 P7.2 POUT2 P7.1 POUT1 P7.0 POUT0 Alternate Function General Purpose Input/Output 87/184 12 - PARALLEL PORTS ST10F269 The structure of Port 7 differs in the way the output EXOR the alternate data output with the port latch latches are connected to the internal bus and to output, which allows to use the alternate data the pin driver. Pins P7.3...P7.0 (POUT3...POUT0) directly or inverted at the pin driver. Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y Alternate Data Output Write DP7.y =1 Port Data P7.y/POUTy Output Port Output Output EXOR Latch Buffer Read P7.y Clock 1 MUX Input 0 Latch y = 0...3 88/184 Internal Bus ST10F269 12 - PARALLEL PORTS Figure 41 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y 1 Output P7.y MUX Latch CCzIO Alternate Output Data 0 Buffer Output Write Port P7.y ≥ 1 Compare Trigger Read P7.y Clock 1 MUX Input 0 Latch Alternate Latch Data Input y = (4...7) z = (28...31) Alternate Pin Data Input 89/184 Internal Bus 12 - PARALLEL PORTS ST10F269 12.11 - Port 8 corresponding direction register DP8. Each port line can be switched into push/pull or open drain If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the mode via the open drain control register ODP8. P8 (FFD4h / EAh) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 - - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 RW RW RW RW RW RW RW RW P8.y Port Data Register P8 Bit y DP8 (FFD6h / EBh) SFR Reset Value: --00h 15 14 13 12 11 10 98 765 432 10 --- -- --- DP8.7DP8.6DP8.5DP8.4DP8.3DP8.2DP8.1DP8.0 RW RW RW RW RW RW RW RW DP8.y Port Direction Register DP8 Bit y DP8.y = 0: Port line P8.y is an input (high impedance) DP8.y = 1: Port line P8.y is an output ODP8 (F1D6h / EBh) ESFR Reset Value: --00h 1514131211109 8 76543210 - ------- ODP8.7ODP8.6ODP8.5ODP8.4ODP8.3ODP8.2ODP8.1ODP8.0 RW RW RW RW RW RW RW RW ODP8.y Port 8 Open Drain Control Register Bit y ODP8.y = 0: Port line P8.y output driver in push-pull mode ODP8.y = 1: Port line P8.y output driver in open drain mode 90/184 ST10F269 12 - PARALLEL PORTS 12.11.1 - Alternate Functions of Port 8 As all other capture inputs, the capture input function of pins P8.7...P8.0 can also be used as The 8 lines of Port 8 serve as capture inputs or as external interrupt inputs (200ns sample rate at compare outputs (CC23IO...CC16IO) for the 40MHz CPU clock on PQFP144 devices and CAPCOM2 unit. 250ns sample rate at 32MHz CPU clock on TQFP144 devices). The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions The Table 25 summarizes the alternate functions of Port 8. are the same as described for the Port 2 lines. Table 25 : Port 8 Alternate Functions Port 7 Alternate Function P8.0 CC16IO Capture input / compare output channel 16 P8.1 CC17IO Capture input / compare output channel 17 P8.2 CC18IO Capture input / compare output channel 18 P8.3 CC19IO Capture input / compare output channel 19 P8.4 CC20IO Capture input / compare output channel 20 P8.5 CC21IO Capture input / compare output channel 21 P8.6 CC22IO Capture input / compare output channel 22 P8.7 CC23IO Capture input / compare output channel 23 Figure 42 : Port 8 I/O and Alternate Functions Port 8 P8.7 CC23IO P8.6 CC22IO P8.5 CC21IO P8.4 CC20IO P8.3 CC19IO P8.2 CC18IO P8.1 CC17IO P8.0 CC16IO General Purpose Input / Output Alternate Function 91/184 12 - PARALLEL PORTS ST10F269 The structure of Port 8 differs in the way the output (CC23IO...CC16IO) combine internal bus data latches are connected to the internal bus and to and alternate data output before the port latch the pin driver (see Figure 43). Pins P8.7...P8.0 input, as do the Port 2 pins. Figure 43 : Block Diagram of Port 8 Pins P8.7...P8.0 Write ODP8.y Open Drain Latch Read ODP8.y Write DP8.y Direction Latch Read DP8.y 1 Output P8.y MUX Latch CCzIO Alternate Output 0 Data Buffer Output Write Port P8.y ≥ 1 Compare Trigger Read P8.y Clock 1 MUX Input 0 Latch Alternate Latch Data Input y = (7...0) z = (16...23) Alternate Pin Data Input 92/184 Internal Bus ST10F269 13 - A/D CONVERTER 13 - A/D CONVERTER A 10-bit A/D converter with 16 multiplexed input converted. After each conversion the result is channels and a sample and hold circuit is stored in the ADDAT register. The data can be integrated on-chip. The sample time (for loading transferred to the RAM by interrupt software the capacitors) and the conversion time is management or using the powerful Peripheral programmable and can be adjusted to the Event Controller (PEC) data transfer. external circuitry. – Auto scan continuous conversion: the analog To remove high frequency components from the level of the selected channels are repeatedly analog input signal, a low-pass filter must be con- sampled and converted. The result of the con- nected at the ADC input. version is stored in the ADDAT register. The data can be transferred to the RAM by interrupt Overrun error detection / protection is controlled software management or using the PEC data by the ADDAT register. Either an interrupt request transfer. is generated when the result of a previous conversion has not been read from the result – Wait for ADDAT read mode: when using con- register at the time the next conversion is tinuous modes, in order to avoid to overwrite complete, or the next conversion is suspended the result of the current conversion by the next until the previous result has been read. For one, the ADWR bit of ADCON control register applications which require less than 16 analog must be activated. Then, until the ADDAT regis- input channels, the remaining channel inputs can ter is read, the new result is stored in a tempo- be used as digital input port pins. The A/D rary buffer and the conversion is on hold. converter of the ST10F269 supports different conversion modes: – Channel injection mode: when using continuous modes, a selected channel can be – Single channel single conversion: the analog level of the selected channel is sampled once converted in between without changing the and converted. The result of the conversion is current operating mode. The 10-bit data of the stored in the ADDAT register. conversion are stored in ADRES field of ADDAT2. The current continuous mode remains – Single channel continuous conversion: the active after the single conversion is completed analog level of the selected channel is repeated- ly sampled and converted. The result of the con- version is stored in the ADDAT register. – Auto scan single conversion: the analog level of the selected channels are sampled once and Table 26 : ADC Sample Clock and Conversion Clock (PQFP144 devices) Conversion Clock t Sample Clock t CC SC ADCTC ADSTC 1 At f = 40MHz t =At f = 40MHz TCL = 1/2 x f CPU SC CPU XTAL 2 00 TCL x 24 0.3μs00 t CC 0.3μs 2 01 Reserved, do not use Reserved 01 t x 2 CC 0.6μs 2 10 TCL x 96 1.2 μs10 t x 4 CC 1.2μs 2 11 TCL x 48 0.6 μs11 t x 8 CC 2.4μs Notes: 1. Section 21.4.5 -: Direct Drive for TCL definition. 2. t = TCL x 24 CC 93/184 13 - A/D CONVERTER ST10F269 Table 27 : ADC Sample Clock and Conversion Clock (TQFP144 devices) Conversion Clock t Sample Clock t CC SC ADCON 15/14 ADCON 13/12 ADCTC ADSTC 1 At f = 32MHz t =At f = 32MHz TCL = 1/2 x f CPU SC CPU XTAL 2 00 TCL x 24 0.375μs00 t CC 0.375μs 2 01 Reserved, do not use Reserved 01 t x 2 CC 0.75μs 2 10 TCL x 96 1.5 μs10 t x 4 CC 1.50μs 2 11 TCL x 48 0.75 μs11 t x 8 CC 3.00μs Notes: 1. Section 21.4.5 -: Direct Drive for TCL definition. 2. t = TCL x 24 CC 94/184 ST10F269 14 - SERIAL CHANNELS 14 - SERIAL CHANNELS Serial communication with other microcontrollers, – P3, DP3, ODP3 for pin configuration microprocessors, terminals or external peripheral – SOBG for Baud rate generator components is provided by two serial interfaces: – SOTBUF for transmit buffer the asynchronous / synchronous serial channel – SOTIC for transmit interrupt control – SOTBIC for transmit buffer interrupt control (ASCO) and the high-speed synchronous serial – SOCON for control channel (SSC). Two dedicated Baud rate – SORBUF for receive buffer (read only) generators set up all standard Baud rates without – SORIC for receive interrupt control the requirement of oscillator tuning. For – SOEIC for error interrupt control transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each 14.1.1 - ASCO in Asynchronous Mode serial channel. In asynchronous mode, 8 or 9-bit data transfer, 14.1 - Asynchronous / Synchronous Serial parity generation and the number of stop bit can Interface (ASCO) be selected. Parity framing and overrun error The asynchronous / synchronous serial interface detection is provided to increase the reliability of (ASCO) provides serial communication between data transfers. Transmission and reception of data the ST10F269 and other microcontrollers, is double-buffered. Full-duplex communication up microprocessors or external peripherals. to 1.25M Bauds (at 40MHz f on PQFP144 CPU A set of registers is used to configure and to devices) and up to 1MBaud (at 32MHz f on CPU control the ASCO serial interface: TQFP144 devices) is supported in this mode. Figure 44 : Asynchronous Mode of Serial Channel ASC0 Reload Register CPU 2 16 Baud Rate Timer Clock S0R S0M S0STP S0FE S0PE S0OE Receive Interrupt Clock S0RIR Request S0REN S0FEN Transmit Interrupt S0PEN Serial Port Control S0TIR Request S0OEN Input RXD0/P3.11 S0LB Error Interrupt Shift Clock S0EIR Request Pin 0 Receive Shift Transmit Shift Pin MUX Sampling Register Register 1 TXD0 / P3.10 Output Receive Buffer Transmit Buffer Register S0RBUF Register S0TBUF Internal Bus 95/184 14 - SERIAL CHANNELS ST10F269 Asynchronous Mode Baud rates f CPU B = For asynchronous operation, the Baud rate Async 16 x [2 + (S0BRS)] x [(S0BRL) + 1] generator provides a clock with 16 times the rate of the established Baud rate. Every received bit is f CPU sampled at the 7th, 8th and 9th cycle of this clock. S0BRL = ( ) - 1 16 x [2 + (S0BRS)] x B Async The Baud rate for asynchronous operation of serial channel ASC0 and the required reload value for a given Baud rate can be determined by Using the above equation, the maximum Baud the following formulas: rate can be calculated for any given clock speed. Baud rate versus reload register value (SOBRS=0 (S0BRL) represents the content of the reload and SOBRS=1) is described in Table28. and register, taken as unsigned 13-bit integer, Table 29 (S0BRS) represents the value of bit S0BRS (‘0’ or ‘1’), taken as integer. Table 28 : Commonly Used Baud Rates by Reload Value and Deviation Errors (PQFP144 devices) S0BRS = ‘0’, f = 40MHz S0BRS = ‘1’, f = 40MHz CPU CPU Reload Value Reload Value Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error (hexa) (hexa) 1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007 56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E 38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015 19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B 9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056 4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD 2 400 +0.2% / -0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B 1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6 600 0.0% / 0.0% 0822 / 0823 600 +0.1% / -0.0% 056B / 056C 300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9 153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9 Note: The deviation errors given in the Table 28 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency). 96/184 ST10F269 14 - SERIAL CHANNELS Table 29 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, f = 32MHz S0BRS = ‘1’, f = 32MHz CPU CPU Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value 1000 000 ±0.0% 0000h 666 667 ±0.0% 0000h 56000 +5.0% / -0.8% 0010h / 001h 56000 +8.2% / -0.8% 000Ah / 000Bh 38400 +0.2% / -3.5% 0019h / 0020h 38400 +2.1% / -3.5% 0010h / 0011h 19200 +0.2% / -1.7% 0033h / 0034h 19200 +2.1% / -0.8% 0021h / 0022h 9600 +0.2% / -0.8% 0067h/ 0068h 9600 +0.6% / -0.8% 0044h / 0045h 4800 +0.5% / -0.3% 00CFh / 00CEh 4800 +0.6% / -0.1% 0089h / 008Ah 2400 +0.2% / -0.1% 019Fh / 01A0h 2400 +0.3% / -0.1% 0114h / 0115h 1200 +0.1% / -0.1% 0340h / 0341h 1200 +0.1% / -0.1% 022Ah / 022Bh 600 +0.1% / -0.1% 0681h / 0682h 600 +0.1% / -0.1% 0456h / 0457h 95 +0.1% / -0.1% 291Dh / 291Eh 75 +0.1% / 0.1% 22B7h / 22B8h 63 +0.1% / -0.1% 2955h / 2956h Note: The deviation errors given in the Table 29 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency). 97/184 14 - SERIAL CHANNELS ST10F269 14.1.2 - ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F269. Half-duplex communication up to 5M Baud (at 40MHz f ) or 4M Baud (at 32MHz) is CPU possible in this mode. Figure 45 : Synchronous Mode of Serial Channel ASC0 Reload Register CPU 2 4 Baud Rate Timer Clock S0R S0M = 000B S0OE Receive Interrupt S0RIR Clock Request S0REN S0OEN Output Transmit Interrupt Serial Port Control S0TIR S0LB TDX0/P3.10 Request Pin Shift Clock Error Interrupt S0EIR Request Input/Output Receive RXD0/P3.11 0 Pin Receive Shift Transmit Shift MUX Register Register 1 Transmit Receive Buffer Transmit Buffer Register S0RBUF Register S0TBUF Internal Bus 98/184 ST10F269 14 - SERIAL CHANNELS Synchronous Mode Baud Rates f CPU For synchronous operation, the Baud rate B = Sync generator provides a clock with 4 times the rate of 4 x [2 + (S0BRS)] x [(S0BRL) + 1] the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 f CPU can be determined by the following formula: S0BRL = ( ) - 1 4 x [2 + (S0BRS)] x B Sync (S0BRL) represents the content of the reload register, taken as unsigned 13-bit integers, Using the above equation, the maximum Baud (S0BRS) represents the value of bit S0BRS (‘0’ or rate can be calculated for any clock speed as ‘1’), taken as integer. given in Table 30.and Table 31 Table 30 : Commonly Used Baud Rates by Reload Value and Deviation Errors (PQFP144 devices) S0BRS = ‘0’, f = 40MHz S0BRS = ‘1’, f = 40MHz CPU CPU Reload Value Reload Value Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error (hexa) (hexa) 5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D 56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B 38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056 19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD 9 600 +0.2% / -0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B 4 800 +0.1% / -0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6 2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / -0.0% 056B / 056C 1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9 900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3 612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE Note: The deviation errors given in the Table 30 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency) 99/184 14 - SERIAL CHANNELS ST10F269 Table 31 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, f = 32MHz S0BRS = ‘1’, f = 32MHz CPU CPU Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value 4 000 000 ±0.0% 0000h 2 666 667 ±0.0% 0000h 224 000 +5.0% / -0.8% 0011h / 0012h 224 000 +8.2% / -0.8% 000Bh / 000Ch 112 000 +2.0% / -0.8% 0023h / 0024h 112 000 +3.5% / -0.8% 0017h / 0018h 56 000 +0.6% / -0.8% 0046h / 0047h 56 000 +1.3% / -0.8% 002Fh / 0030h 38 400 +0.2% / -0.85% 0077h / 0078h 38 400 +0.6% / -0.8% 0044h / 0045h 19 200 +0.2% / -0.3% 00BFh / 00C0h 19 200 +0.6% / -0.1% 008Ah / 008Bh 9 600 +0.2% / -0.1% 01A0h/ 01A1h 9 600 +0.3% / -0.1% 0115h / 0116h 4 800 +0.0% / -0.1% 0340h / 0341h 4 800 +0.1% / -0.1% 022Bh / 022Ch 2 400 +0.0% / -0.0% 0682h / 0683h 2 400 +0.0% / -0.1% 0456h / 0457h 1 200 +0.0% / -0.0% 004h / 0D05h 1 200 +0.0% / -0.0% 08ACh / 08ADh 600 +0.0% / -0.0% 1A0Ah / 1A0Bh 600 +0.0% / -0.0% 115Bh / 115C7h 490 +0.0% / -0.0% 1FE2h / 1FE3h 320 +0.2% 1FFFh Note: The deviation errors given in the Table 31 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency) 100/184 ST10F269 14 - SERIAL CHANNELS 14.2 - High Speed Synchronous Serial Channel (slave mode). Data width, shift direction, clock (SSC) polarity and phase are programmable. The High-Speed Synchronous Serial Interface This allows communication with SPI-compatible SSC provides flexible high-speed serial devices. Transmission and reception of data is communication between the ST10F269 and other double-buffered. A 16-bit Baud rate generator microcontrollers, microprocessors or external provides the SSC with a separate serial clock peripherals. signal. The serial channel SSC has its own The SSC supports full-duplex and half-duplex dedicated 16-bit Baud rate generator with 16-bit synchronous communication. The serial clock reload capability, allowing Baud rate generation signal can be generated by the SSC itself (master mode) or be received from an external master independent from the timers. Figure 46 : Synchronous Serial Channel SSC Block Diagram Slave Clock CPU Baud Rate Generator Clock Control Pin SCLK Clock Master Clock Shift Clock Receive Interrupt Request SSC Control Transmit Interrupt Request Block Error Interrupt Request Status Control Pin MTSR Pin Control MRST Pin 16-Bit Shift Register Transmit Buffer Receive Buffer Register SSCTB Register SSCRB Internal Bus 101/184 14 - SERIAL CHANNELS ST10F269 Baud Rate Generation . The Baud rate generator is clocked by f /2. The Table 33 : Synchronous Baud Rate and Reload CPU timer is counting downwards and can be started Values (TQFP144 devices) or stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the Baud Rate Bit Time Reload Value dual-function Baud Rate Generator/Reload Reserved use a --- --- register. Reading SSCBR, while the SSC is reload value > 0. enabled, returns the content of the timer. Reading SSCBR, while the SSC is disabled, returns the 8MBaud 125ns 0001h programmed reload value. In this mode the 4MBaud 250ns 0003h desired reload value can be written to SSCBR. Note Never write to SSCBR, while the SSC is 2MBaud 500ns 0007h enabled. 1MBaud 1μs000Fh The formulas below calculate the resulting Baud 500KBaud 2μs001Fh rate for a given reload value and the required reload value for a given Baud rate: 100KBaud 10μs009Fh 10KBaud 100μs030Ch f CPU Baud rate = SSC 1K Baud 1ms 3E7Fh 2 x [(SSCBR) + 1] f 244.14 Baud 5.24ms FFFFh CPU SSCBR = ( ) - 1 2 x Baud rate SSC (SSCBR) represents the content of the reload register, taken as unsigned 16-bit integer. Table 32 lists some possible Baud rates against the required reload values and the resulting bit times for a 40MHz CPU clock. Table 32 : Synchronous Baud Rate and Reload Values (PQFP144 devices) Baud Rate Bit Time Reload Value Reserved use a --- --- reload value > 0. 10M Baud 100ns 0001h 5M Baud 200ns 0003h 2.5M Baud 400ns 0007h 1M Baud 1μs 0013h 100K Baud 10μs 00C7h 10K Baud 100μs 07CFh 1K Baud 1ms 4E1Fh 306 Baud 3.26ms FF4Eh Table 33 lists some possible Baud rates against the required reload values and the resulting bit times for a 32MHz CPU clock. 102/184 ST10F269 15 - CAN MODULES 15 - CAN MODULES The two integrated CAN modules (CAN1 and to the CAN Module use demultiplexed addresses CAN2) are identical and handle the completely and a 16-bit data bus (Byte accesses are autonomous transmission and reception of CAN possible). Two wait states give an access time of frames according to the CAN specification V2.0 125ns at 40MHz or 32MHz CPU clock. No tri-state part B (active). wait states are used. Each on-chip CAN module can receive and Note: If one or both CAN modules is used, transmit standard frames with 11-bit identifiers as Port 4 cannot be programmed to output all well as extended frames with 29-bit identifiers. 8segment address lines. Thus, only These two CAN modules are both identical to the 4segment address lines can be used, CAN module of the ST10F167. reducing the external memory space to 5M Bytes (1M Byte per CS line). Because of duplication of the CAN controllers, the following adjustments are to be considered: 15.2 - CAN Bus Configurations – Same internal register addresses of both CAN Depending on application, CAN bus configuration controllers, but with base addresses differing in may be one single bus with a single or multiple address bit A8; separate chip select for each interfaces or a multiple bus with a single or CAN module. Refer to Chapter : Memory Organ- multiple interfaces. The ST10F269 is able to ization on page 14. support these 2 cases. – The CAN1 transmit line (CAN1_TxD) is the Single CAN Bus alternate function of the Port P4.6 pin and the The single CAN Bus multiple interfaces receive line (CAN1_RxD) is the alternate configuration may be implemented using 2 CAN function of the Port P4.5 pin. transceivers as shown in Figure 47. – The CAN2 transmit line (CAN2_TxD) is the Figure 47 : Single CAN Bus Multiple Interfaces, alternate function of the Port P4.7 pin and the Multiple Transceivers receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin. CAN1 CAN2 – Interrupt request line of the CAN1 module is RxD RxD TxD TxD connected to the XBUS interrupt line XP0, interrupt of the CAN2 module is connected to the line XP1. – The CAN modules must be selected with CAN CAN corresponding CANxEN bit of XPERCON register Transceiver Transceiver before the bit XPEN of SYSCON register is set. – The reset default configuration is: CAN1 is CAN_H enabled, CAN2 is disabled. CAN bus CAN_H 15.1 - CAN Modules Memory Mapping 15.1.1 - CAN1 Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting bit 0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (Byte accesses are possible). Two wait states give an access time of 125ns at 40MHz CPU clock or at 32MHz CPU clock. No tri-state wait states are used. 15.1.2 - CAN2 Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting bit 1 of the XPERCON register. Accesses 103/184 15 - CAN MODULES ST10F269 The ST10F269 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 48. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. Figure 48 : Single CAN Bus, Dual Interfaces, Single Transceiver CAN2 CAN1 RxD RxD TxD TxD * * +5V 2.7kΩ CAN Transceiver CAN_H CAN_H CAN bus * Open drain output Multiple CAN Bus The ST10F269 provides 2 CAN interfaces to support such kind of bus configuration as shown in Figure 49. Figure 49 : Connection to Two Different CAN Buses (e.g. for gateway application) CAN1 CAN2 RxD RxD TxD TxD CAN CAN Transceiver Transceiver CAN_H CAN CAN CAN_H bus 1 bus 2 104/184 ST10F269 16 - REAL TIME CLOCK 16 - REAL TIME CLOCK The Real Time Clock is an independent timer, 20-bit PRESCALER register (4-bit MSB RTCPH which clock is directly derived from the clock register and 16-bit LSB RTCPL register). The oscillator on XTAL1 input so that it can keep on value of the 20-bit RTCP register determines the running even in Idle or Power down mode (if period of the basic reference clock. enabled to). Registers access is implemented A timed interrupt request (RTCSI) may be sent on onto the XBUS. This module is designed for the following purposes: each basic reference clock period. The second block of the RTC is a 32-bit counter (16-bit RTCH – Generate the current time and date for the system and 16-bit RTCL). This counter may be initialized – Cyclic time based interrupt, provides Port with the current system time. RTCH/RTCL counter 2 external interrupts every second and every is driven with the basic reference clock signal. In n seconds (n is programmable) if enabled. order to provide an alarm function the contents of – 58-bit timer for long term measurement RTCH/RTCL counter is compared with a 32-bit – Capable to exit the ST10 chip from power down alarm register (16-bit RTCAH register and 16-bit mode (if PWDCFG of SYSCON set) after a pro- RTCAL register). The alarm register may be grammed delay. loaded with a reference date. An alarm interrupt The real time clock is base on two main blocks of request (RTCAI), may be generated when the counters. The first block is a prescaler which value of RTCH/RTCL counter matches the generates a basic reference clock (for example a reference date of RTCAH/RTCAL register. 1 second period). This basic reference clock is The timed RTCSI and the alarm RTCAI interrupt coming out of a 20-bit DIVIDER (4-bit MSB requests can trigger a fast external interrupt via RTCDH counter and 16-bit LSB RTCDL counter). EXISEL register of port 2 and wake-up the ST10 This 20-bit counter is driven by an input clock chip when running power down mode. Using the derived from the on-chip high frequency CPU clock, predivided by a 1/64 fixed counter (see RTCOFF bit of RTCCON register, the user may Figure 51). This 20-bit counter is loaded at each switch off the clock oscillator when entering the basic reference clock period with the value of the power down mode. Figure 50 : ESFRs and Port Pins Associated with the RTC EXISEL CCxIC -- -- - - - - YYYY ---- -- -- - - - - YYYYYYYY EXISEL External Interrupt Source Selection register (Port 2) 1 second timed interrupt request (RTCSI) triggers firq[2] and alarm interrupt request (RTCAI) triggers firq[3] RTC data and control registers are implemented onto the XBUS. 105/184 16 - REAL TIME CLOCK ST10F269 Figure 51 : RTC Block Diagram RTCAI RTCSI Clock Oscillator RTCCON AlarmIT Basic Clock IT Programmable ALARM Register Programmable PRESCALER Register RTCAH RTCAL RTCPH RTCPL = Reload RTCH RTCDH RTCDL /64 RTCL 32 bit COUNTER 20 bit DIVIDER 16.1 - RTC registers be switch off. The RTC has 2 interrupt sources, one is triggered every basic clock period, the 16.1.1 - RTCCON: RTC Control Register other one is the alarm. The functions of the RTC are controlled by the RTCCON control register. If the RTOFF bit is set, RTCCON includes an interrupt request flag and the RTC dividers and counters clock is disabled an interrupt enable bit for each of them. This and registers can be written, when the ST10 chip enters power down mode the clock oscillator will register is read and written via the XBUS. RTCCON (EC00h) XBUS Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - RTCOFF - - - RTCAEN RTCAIR RTCSEN RTCSIR RW RW RW RW RW 2 RTCOFF RTC Switch Off Bit ‘0’: clock oscillator and RTC keep on running even if ST10 in power down mode ‘1’: clock oscillator is switch off if ST10 enters power down mode, RTC dividers and counters are stopped and registers can be written 2 RTCAEN RTC Alarm Interrupt ENable ‘0’: RTCAI is disabled ‘1’: RTCAI is enabled, it is generated every n seconds 1 RTCAIR RTC Alarm Interrupt Request flag (when the alarm is triggered) ‘0’: the bit was reseted less than a n seconds ago ‘1’: the interrupt was triggered 2 RTCSEN RTC Second interrupt ENable ‘0’: RTCSI is disabled ‘1’: RTCSI is enabled, it is generated every second 1 RTCSIR RTC Second Interrupt Request flag (every second) ‘0’: the bit was reseted less than a second ago ‘1’: the interrupt was triggered Notes: 1. As RTCCON register is not bit-addressable, the value of these bits must be read by checking their associated CCxIC register. The 2 RTC interrupt signals are connected to Port2 in order to trigger an external interrupt that wake up the chip when in power down 106/184 ST10F269 16 - REAL TIME CLOCK mode. 2. All the bit of RTCCON are active high. 107/184 16 - REAL TIME CLOCK ST10F269 16.1.2 - RTCPH & RTCPL: RTC PRESCALER RTCPL. In order to keep the system clock, those Registers registers are not reset. The 20-bit programmable prescaler divider is They are write protected by bit RTOFF of loaded with 2 registers. RTCCON register, write operation is allowed if The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in RTOFF is set. RTCPL (EC06h) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCPL RW RTCPH (EC08h) XBUS Reset Value: ---Xh 15 14 13 12 11 10 9876543210 RESERVED RTCPH RW Figure 52 : PRESCALER Register 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCPH RTCPL 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20 bit word counter The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). The dividing ratio of the Prescaler divider is: ratio = 64 x (RTCP) 16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters Every basic reference clock the DIVIDER counters are reloaded with the value stored RTCPH and RTCPL registers. To get an accurate time measurement it is possible to read the value of the DIVIDER, reading the RTCDH, RTCDL. Those counters are read only. After any bit changed in the programmable PRESCALER register, the new value is loaded in the DIVIDER. RTCDL (EC0Ah) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCDL R RTCDH (EC0Ch) XBUS Reset Value: ---Xh 15 14 13 12 11 10 9876543210 RESERVED RTCDH R Note: Those registers are not reset, and are read only. 108/184 ST10F269 16 - REAL TIME CLOCK When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL registers is loaded in RTCD. Figure 53 : DIVIDER Counters 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCDH RTCDL 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20 bit word internal value of the Prescaler divider Bit 15 to bit 4 of RTCPH and RTCDH are not The only way to force their value is to write them used. When reading, the return value of those bit via the XBUS. will be zeros. Those counters are write protected as well. The bit RTOFF of the RTCCON register must be set 16.1.4 - RTCH & RTCL: RTC Programmable (RTC dividers and counters are stopped) to COUNTER Registers enable a write operation on RTCH or RTCL. The RTC has 2 x 16-bit programmable counters A write operation on RTCH or RTCL register loads which count rate is based on the basic time directly the corresponding counter. When reading, reference (for example 1 second). As the clock the current value in the counter (system date) is oscillator may be kept working, even in power returned. down mode, the RTC counters may be used as a system clock. In addition RTC counters and The counters keeps on running while the clock registers are not modified at any system reset. oscillator is working. RTCL (EC0Eh) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCL RW RTCH (EC10h) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCH RW Note: Those registers are nor reset 109/184 16 - REAL TIME CLOCK ST10F269 16.1.5 - RTCAH & RTCAL: RTC ALARM Registers When the programmable counters reach the 32-bit value stored into RTCAH & RTCAL registers, an alarm is triggered and the interrupt request RTAIR is generated. Those registers are not protected. RTCAL (EC12h) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCAL RW RTCAH (EC14h) XBUS Reset Value: XXXXh 15 14 13 12 11 10 9876543210 RTCAH RW Note: Those registers are not reset 16.2 - Programming the RTC RTC interrupt request signals are connected to Port2, pad 10 (RTCSI) and pad 11 (RTCAI). An alternate function Port2 is to generate fast interrupts firq[7:0]. To trigger firq[2] and firq[3] the following configuration has to be set. EXICON ESFR controls the external interrupt edge selection, RTC interrupt requests are rising edge active. EXICON (F1C0h) ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 1 2 1 3 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES RW RW RW RW RW RW RW RW Notes: 1. EXI2ES and EXI3ES must be configured as "01b" because RCT interrupt request lines are rising edge active. 2. Alarm interrupt request line (RTCAI) is linked with EXI3ES. 3. Timed interrupt request line (RTCSI) is linked with EXI2ES. EXISEL ESFR enables the Port2 alternate sources. RTC interrupts are alternate sources 2 and 3. EXISEL (F1DAh) ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 2 3 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection (x=7...0) ‘00’: Input from associated Port 2 pin. 1 ‘01’: Input from “alternate source”. 1 ‘10’: Input from Port 2 pin ORed with “alternate source”. ‘11’: Input from Port 2 pin ANDed with “alternate source”. Notes: 1. Advised configuration. 2. Alarm interrupt request (RTCAI) is linked with EXI3SS. 3. Timed interrupt request (RTCSI) is linked with EXI2SS. 110/184 ST10F269 16 - REAL TIME CLOCK Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC (RTCAI). CCxIC SFR Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- CCxIRCCxIE ILVL GLVL RW RW RW RW CC10IC: FF8Ch/C6h CC11IC: FF8Eh/C7h Source of interrupt Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External interrupt 2 CC10IR CC10IE CC10INT 00’0068h 1Ah/26 External interrupt 3 CC11IR CC11IE CC11INT 00’006Ch 1Bh/27 111/184 17 - WATCHDOG TIMER ST10F269 17 - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism due to hardware or software related failures, the which prevents the microcontroller from software fails to do so, the watchdog timer malfunctioning for long periods of time. overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow The Watchdog Timer is always enabled after a external hardware components to be reset. reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) Each of the different reset sources is indicated in instruction has been executed. the WDTCON register. Therefore, the chip start-up procedure is always The indicated bits are cleared with the EINIT monitored. The software must be designed to instruction. The origin of the reset can be service the watchdog timer before it overflows. If, identified during the initialization phase. WDTCON (FFAEh / D7h) SFR Reset Value: 00xxh 151413121110 9 8 765 4321 0 WDTREL - - PONR LHWR SHWR SWR WDTR WDTIN RW HR HR HR HR HR RW WDTIN Watchdog Timer Input Frequency Selection ‘0’: Input Frequency is f /2. CPU ‘1’: Input Frequency is f /128. CPU 1-3 Watchdog Timer Reset Indication Flag WDTR Set by the watchdog timer on an overflow. Cleared by a hardware reset or by the SRVWDT instruction. 1-3 Software Reset Indication Flag SWR Set by the SRST execution. Cleared by the EINIT instruction. 1-3 Short Hardware Reset Indication Flag SHWR Set by the input RSTIN. Cleared by the EINIT instruction. 1-3 Long Hardware Reset Indication Flag LHWR Set by the input RSTIN. Cleared by the EINIT instruction. 1- 2-3 Power-On (Asynchronous) Reset Indication Flag PONR Set by the input RSTIN if a power-on condition has been detected. Cleared by the EINIT instruction. Notes: 1. More than one reset indication flag may be set. After EINIT, all flags are cleared. 2. Power-on is detected when a rising edge from V = 0 V to V > 2.0 V is recognized on the internal 3.3V supply. DD DD 3. These bits cannot be directly modified by software. 112/184 ST10F269 17 - WATCHDOG TIMER The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set. This could be the case on fast switch-off / switch-on of the 5V supply. The time needed for such a sequence to activate the PONR flag depends on the value of the capacitors connected to the supply and on the exact value of the internal threshold of the detection circuit. Table 34 : WDTCON Bit Value on Different Resets Reset Source PONR LHWR SHWR SWR WDTR Power On Reset X X X X 1) 2) Power on after partial supply failure XXX Long Hardware Reset X X X Short Hardware Reset X X Software Reset X Watchdog Reset XX Notes: 1. PONR bit may not be set for short supply failure. 2. For power-on reset and reset after supply partial failure, asynchronous reset must be used. In case of bi-directional reset is enabled, and if the RSTIN pin is latched low after the end of the internal reset sequence, then a Short hardware reset, a software reset or a watchdog reset will trigger a Long hardware reset. Thus, Reset Indications flags will be set to indicate a Long Hardware Reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced Table 35 shows the watchdog time range for 40MHz CPU clock and Table 36 shows the watchdog time range for 32MHz CPU clock. Table 35 : WDTREL Reload Value (PQFP144 devices) Prescaler for f = 40MHz CPU Reload value in WDTREL 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) FFh 12.8μs819.2ms 00h 3.276ms 209.7ms Table 36 : WDTREL Reload Value (TQFP144 devices) Prescaler for f = 32MHz CPU Reload value in WDTREL 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) FFh 16.0μs 1.024ms 00h 4.096ms 262.1ms The watchdog timer period is calculated with the following formula: 1 -------- ------ - P = × 512 × (1W + [ DTIN ] × 63 ) × (256– [WDTREL]) WDT f CPU 113/184 18 - SYSTEM RESET ST10F269 18 - SYSTEM RESET System reset initializes the MCU in a predefined The system start-up configuration is different for state. There are five ways to activate a reset state. each case as shown in Table 37. Table 37 : Reset Event Definition Reset Source Short-cut Conditions Power-on reset PONR Power-on LHWR t > 1040 TCL Long Hardware reset (synchronous & asynchronous) RSTIN SHWR 4 TCL < t < 1038 TCL Short Hardware reset (synchronous reset) RSTIN Watchdog Timer reset WDTR WDT overflow Software reset SWR SRST execution 18.1 - Long Hardware Reset pin determines an asynchronous reset while a high level leads to a synchronous reset. The reset is triggered when RSTIN pin is pulled low, then the MCU is immediately forced in reset Note A reset can be entered as synchronous default state. It pulls low RSTOUT pin, it cancels and exit as asynchronous if V voltage RPD pending internal hold states if any, it aborts drops below the RPD pin threshold external bus cycle, it switches buses (data, (typically 2.5V for V = 5V) when RSTIN DD address and control signals) and I/O pin drivers to pin is low or when RSTIN pin is internally high-impedance, it pulls high PORT0 pins and the pulled low. reset sequence starts. To get a long hardware reset, the duration of the 18.1.1 - Asynchronous Reset external RSTIN signal must be longer than 1040 TCL. The level of RPD pin is sampled during the Figure54 and Figure55 show asynchronous whole RSTIN pulse duration. A low level on RPD reset condition (RPD pin is at low level). Figure 54 : Asynchronous Reset Sequence External Fetch 12 3459 6 7 8 CPU Clock 1) 6 or 8 TCL Asynchronous Reset Condition RSTIN RPD RSTOUT 5 TCL ALE RD Reset Configuration PORT0 1st Instruction External Fetch Latching point of PORT0 for system start-up EXTERNAL FETCH Internal reset configuration Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (f =f / 2), else it is 4 CPU clock cycles (8 TCL). CPU XTAL 114/184 ST10F269 18 - SYSTEM RESET Figure 55 : Asynchronous Reset Sequence Internal Fetch 12 3 CPU Clock 1) 6 or 8 TCL Asynchronous Reset Condition RSTIN Flash under reset for internal charge pump ramping up 2) 2.5µs max. RPD RSTOUT Reset Configuration PORT0 Latching point of PORT0 for PLL configuration PLL factor latch command Latching point of PORT0 Internal reset signal for remaining bits INTERNAL FETCH 1st fetch Flash read signal from Flash Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (f =f / 2), else it is 4 CPU clock cycles (8 TCL). CPU XTAL 2) 2.1µs typical value. Then the I/O pins are set to high impedance and RSTOUT pin is driven low. After the RSTIN level is Power-on reset detected, a short duration of 12 TCL (6 CPU The asynchronous reset must be used during the clocks) maximum elapses, during which pending power-on of the MCU. Depending on the crystal internal hold states are cancelled and the current frequency, the on-chip oscillator needs about internal access cycle, if any, is completed. 10ms to 50ms to stabilize. The logic of the MCU External bus cycle is aborted. does not need a stabilized clock signal to detect The internal pull-down of RSTIN pin is activated if an asynchronous reset, so it is suitable for bit BDRSTEN of SYSCON register was previously power-on conditions. To ensure a proper reset set by software. This bit is always cleared on sequence, the RSTIN pin and the RPD pin must power-on or after any reset sequence. be held at low level until the MCU clock signal is stabilized and the system configuration value on The internal sequence lasts for 1024 TCL (512 PORT0 is settled. periods of CPU clock). After this duration the Hardware reset pull-down of RSTIN pin for the bidirectional reset The asynchronous reset must be used to recover function is released and the RSTIN pin level is from catastrophic situations of the application. It sampled. At this step the sequence lasts 1040 may be triggered by the hardware of the applica- TCL (4 TCL + 12 TCL + 1024 TCL). If the RSTIN tion. Internal hardware logic and application cir- pin level is low, the reset sequence is extended cuitry are described in Section 18.6 - and until RSTIN level becomes high. Refer to Figure 58, Figure 59 and Figure 60. Figure 56 Note If V voltage drops below the RPD pin 18.1.2 - Synchronous Reset (RSTIN pulse > RPD 1040TCL and RPD pin at high level) threshold (typically 2.5V for V = 5V) DD The synchronous reset is a warm reset. It may be when RSTIN pin is low or when RSTIN pin generated synchronously to the CPU clock. To be is internally pulled low, the ST10 reset detected by the reset logic, the RSTIN pulse must circuitry disables the bidirectional reset be low at least for 4 TCL (2 periods of CPU clock). function and RSTIN pin is no more pulled 115/184 18 - SYSTEM RESET ST10F269 low. The reset is processed as an asynchronous reset. Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL) 4 TCL 12 TCL 1) 6 or 8 TCL min. max. 15 2 3 46789 CPU Clock 1024 TCL 2) Internally pulled low RSTIN RPD 200μA Discharge If V > 2.5V Asynchronous RPD 3) RSTOUT Reset is not entered. 5 TCL ALE RD Reset Configuration PORT0 Latching point of PORT0 for system start-up configuration Internal reset signal Note 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU prescaler is on (f =f / 2), else it is 4 CPU clock CPU XTAL clock cycles (6 TCL) if the PLL is bypassed and the cycles (8 TCL). 2) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 3) If during the reset condition (RSTIN low), V voltage drops below the threshold voltage (typically 2.5V for 5V operation), the RPD ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low. The short hardware is triggered when RSTIN signal duration is shorter or equal to 1038 18.1.3 - Exit of Long Hardware Reset TCL, the RPD pin must be pulled high. To properly activate the internal reset logic of the - If the RPD pin level is low when the RSTIN pin MCU, the RSTIN pin must be held low, at least, is sampled high, the MCU completes an asynchronous reset sequence. during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is - If the RPD pin level is high when the RSTIN pin driven low. After RSTIN level is detected, a short is sampled high, the MCU completes a duration of 12 TCL (6 CPU clocks) maximum synchronous reset sequence. elapses, during which pending internal hold states The system configuration is latched from PORT0 are cancelled and the current internal access after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 cycle if any is completed. External bus cycle is CPU clocks if PLL is bypassed) and in case of aborted. The internal pull-down of RSTIN pin is external fetch, ALE, RD and R/W pins are driven activated if bit BDRSTEN of SYSCON register to their inactive level. The MCU starts program was previously set by software. This bit is always execution from memory location 00'0000h in code cleared on power-on or after any reset sequence. segment0. This starting location will typically The internal reset sequence starts for 1024 TCL point to the general initialization routine. Refer to (512 periods of CPU clock). Table 38 for PORT0 latched configuration. After that duration the pull-down of RSTIN pin for the bidirectional reset function is released and the RSTIN pin level is sampled high while RPD level is 18.2 - Short Hardware Reset high. A short hardware reset is a warm reset. It may be The short hardware reset ends and the MCU generated synchronously to the CPU clock restarts.To be processed as a short hardware (synchronous reset). reset, the external RSTIN signal must last a 116/184 ST10F269 18 - SYSTEM RESET maximum of 1038 TCL (4 TCL + 10 TCL + 1024 Note - If the RSTIN pin level is sampled low, the TCL). The system configuration is latched from reset sequence is extended until RSTIN PORT0 after a duration of 8 TCL / 4 CPU clocks (6 level becomes high leading to a long TCL / 3 CPU clocks if PLL is bypassed) and in hardware reset (synchronous or case of external fetch, ALE, RD and R/W pins are asynchronous reset) because RSTIN driven to their inactive level. Program execution signal duration has lasted longer than starts from memory location 00'0000h in code 1040TCL. segment0. This starting location will typically point to the general initialization routine. Timings - If the V voltage has dropped below of synchronous reset sequence are summarized RPD the RPD pin threshold, the reset is in Figure 57. Refer to Table 38 for PORT0 latched configuration. processed as an asynchronous reset. Figure 57 : Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL) 2) 4) 4 TCL 10 TCL 6 or 8 TCL 1024 TCL min. min. 1 2 3 4 5 6789 CPU Clock 1) 3) Internally pulled low RSTIN RPD 200μA Discharge 5 TCL If V > 2.5V Asynchronous RPD 5) RSTOUT Reset is not entered. ALE RD Reset Configuration 1st Instr. PORT0 Latching point of PORT0 for system start-up configuration Internal reset signal Note 1) RSTIN assertion can be released there. 2) Maximum internal synchronization is 6 CPU cycles (12 TCL). 3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (f =f / 2), else it is 4 CPU clock cycles (8 TCL). CPU XTAL 5) If during the reset condition (RSTIN low), V voltage drops below the threshold voltage (typically 2.5V for 5V operation), the RPD ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low. 18.3 - Software Reset reset sequence, while previously latched values of P0.5...P0.2 are cleared. The reset sequence can be triggered at any time using the protected instruction SRST (software 18.4 - Watchdog Timer Reset reset). This instruction can be executed When the watchdog timer is not disabled during deliberately within a program, for example to leave the initialization or when it is not regularly serviced bootstrap loader mode, or upon a hardware trap during program execution it will overflow and it will that reveals a system failure. trigger the reset sequence. Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started. Unlike hardware and software resets, the The microcontroller behavior is the same as for a watchdog reset completes a running external bus short hardware reset, except that only cycle if this bus cycle either does not use READY , P0.12...P0.6 bits are latched at the end of the or if READY is sampled active (low) after the 117/184 18 - SYSTEM RESET ST10F269 programmed wait states. When READY is – to make visible SW or WDT resets at RSTIN pin sampled inactive (high) after the programmed wait whenever RSTIN is the only reset signal used by states the running external bus cycle is aborted. the application (RSTOUT not used). Then the internal reset sequence (1024 TCL) is – to get a die-activated reset signal before CPU started. The microcontroller behaviour is the starts its first instruction fetch. same as for a short hardware reset, except that The configuration latched from PORT0 is only P0.12...P0.6 bits are latched, while determined by the kind of reset generated by the previously latched values of P0.5...P0.2 are application. (Refer to Table 38). cleared. Converting a SW or WDT reset to a hardware 18.5 - RSTOUT, RSTIN, Bidirectional Reset reset allows the PLL to re-lock or the PLL configuration to be re-latched, provided a SW or 18.5.1 - RSTOUT Pin WDT reset is generated by the application program is case of PLL unlock or input clock fail. The RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/ 18.6 - Reset Circuitry asynchronous hardware, software and watchdog The internal reset circuitry is described in timer resets). RSTOUT pin stays active low Figure 58. beyond the end of the initialization routine, until An internal pull-up resistor is implemented on the protected EINIT instruction (End of RSTIN pin. (50kΩ minimum, to 250kΩ maximum). Initialization) is completed. The minimum reset time must be calculated using 18.5.2 - Bidirectional Reset the lowest value. In addition, a programmable pull-down (SYSCON.BDRSTEN bit 3) drives the The bidirectional reset function is enabled by RSTIN pin according to the internal reset state. setting SYSCON.BDRSTEN (bit 3). This function The RSTOUT pin provides a signals to the is disabled by any reset sequence which always application. (Refer to Section 18.5 -). clears the SYSCON.BDRSTEN bit. A weak internal pull-down is connected to the It can only be enabled during the initialization RPD pin to discharge external capacitor to V at SS routine, before EINIT instruction is completed. a rate of 100μA to 200μA. This Pull-down is turned on when RSTIN pin is low If V voltage drops below the RPD pin RPD threshold (typically 2.5V for V = 5V) when DD If bit PWDCFG of SYSCON register is set, an RSTIN pin is low or when RSTIN pin is internally internal pull-up resistor is activated at the end of pulled low, the ST10 reset circuitry disables the the reset sequence. This pull-up charges the bidirectional reset function and RSTIN pin is no capacitor connected to RPD pin. more pulled low. The reset is processed as an If the bidirectional reset function is not used, the asynchronous reset. simplest way to reset ST10F269 is to connect The bidirectional reset function is useful for external components as shown in Figure 59. It external peripherals with on-chip memory works with reset from application (hardware or because the reset signal output on RSTIN pin is manual) and with power-on. The value of C1 de-activated before the CPU starts its first capacitor, connected on RSTIN pin with internal instruction fetch. pull-up resistor (50kΩ to 250kΩ), must lead to a charging time long enough to let the internal or 18.5.3 - RSTIN pin external oscillator and / or the on-chip PLL to stabilize. When the bidirectional reset function is enabled, The R0-C0 components on RPD pin are mainly the open-drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of implemented to provide a time delay to exit Power the internal reset sequence. See Figure 56 and down mode (see Chapter: Power Reduction Figure57. At the end of the sequence the Modes on page 122). Nevertheless, they drive RPD pin level during resets and they lead to pull-down is released and the RSTIN pin gets back its input function. different reset modes as explained hereafter. On power-on, C0 is total discharged, a low level on The bidirectional reset function can be used: RPD pin forces an asynchronous hardware reset. – to convert SW or WD resets to a hardware reset C0 capacitor starts to charge through R0 and at the end of reset sequence ST10F269 restarts. so that the configuration can be (re-)latched from PORT0. RPD pin threshold is typically 2.5V. 118/184 ST10F269 18 - SYSTEM RESET Depending on the delay of the next applied reset, C1 capacitor at power-off during repetitive the MCU can enter a synchronous reset or an switch-on / switch-off sequences. D2 diode asynchronous reset. If RPD pin is below 2.5V an performs an OR-wired connection, it can be asynchronous reset starts, if RPD pin is above replaced with an open drain buffer. R2 resistor 2.5V a synchronous reset starts. (See Section may be added to increase the pull-up current to 18.1 - and Section 18.2 -). the open drain in order to get a faster rise time on RSTIN pin when bidirectional function is activated. Note that an internal pull-down is connected to RPD pin and can drive a 100μA to 200μA current. The start-up configurations and some system This Pull-down is turned on when RSTIN pin is features are selected on reset sequences as low. described in Table 38 and Table 39. To properly use the bidirectional reset features, Table38 describes what is the system the schematic (or equivalent) of Figure 60 must be configuration latched on PORT0 in the five implemented. R1-C1 only work for power-on or different reset ways. Table39 summarizes the manual reset in the same way as explained state of bits of PORT0 latched in RP0H, previously. D1 diode brings a faster discharge of SYSCON, BUSCON0 registers. Figure 58 : Internal (simplified) Reset Circuitry. EINIT Instruction Clr Q RSTOUT Set Reset State Machine Clock V DD SRST instruction Internal Trigger watchdog overflow Reset RSTIN Signal Clr BDRSTEN Reset Sequence (512 CPU Clock Cycles) V DD Asynchronous Reset RPD From/to Exit Weak pull-down Powerdown (~200μA) Circuit 119/184 18 - SYSTEM RESET ST10F269 Figure 59 : Minimum External Reset Circuitry V DD External RSTOUT ST10F269 Hardware R0 RSTIN RPD + + b) a) a) Manual hardware reset1 C0 C1 b) For automatic power-up and interruptible power-down mode Figure 60 : External Reset Hardware Circuitry V V R2 V DD DD DD External RSTIN RSTOUT D1 R0 Hardware R1 ST10F269 D2 RPD + + C0 C1 Open - drain External Inverter Reset Source Table 38 : PORT0 Latched Configuration for the Different Resets PORT0 X: Pin is sampled -: Pin is not sampled Sample event Software Reset - - - XX XXX XX - - - - - - Watchdog Reset - - - X X X X X X X - - - - - - Short Hardware Reset - - - XX XXX XX XXX XX X Long Hardware Reset XXX XX XXX XX XXX XX X Power-On Reset XXX XX XXX XX XXX XX X Table 39 : PORT0 Bits Latched into the Different Registers After Reset PORT0 bit h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0 Nebr. PORT0 bit CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU Name 2 1 1 1 1 1 1 1 1 RP0H X X X X X X X X CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC 1 1 1 1 1 1 3 1 3 1 1 1 1 1 1 1 SYSCON X X X X X X BYTDIS X WRCFG X X X X X X X 1 1 1 1 1 1 1 1 1 1 BUSCON0 X X X X -BUS ALE -BTYP BTYP X X X X X X 4 4 ACT0 CTL0 1 1 1 1 1 1 Internal To Clock Generator To Port 4 Logic To Port 6 Logic X X X X Internal X X Internal Internal Logic Notes: 1. Not latched from PORT0. 2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte. 120/184 P0H.7 P0H.6 Clock Options P0H.5 P0H.4 Seem. Add. Lines P0H.3 P0H.2 Chip Selects P0H.1 P0H.0 WR confide. P0L.7 Bus Type P0L.6 P0L.5 Reserved P0L.4 BSL P0L.3 Reserved P0L.2 Reserved P0L.1 Adapt Mode P0L.0 Emu Mode ST10F269 18 - SYSTEM RESET 3. Indirectly depend on PORT0. 4. Bits set if EA pin is 1. 121/184 19 - POWER REDUCTION MODES ST10F269 19 - POWER REDUCTION MODES Two different power reduction modes with different through the voltage supplied via the V pins. To DD levels of power reduction have been implemented verify RAM integrity, some dedicated patterns in the ST10F269. In Idle mode only CPU is may be written before entering the Power Down stopped, while peripheral still operate. In Power mode and have to be checked after Power Down Down mode both CPU and peripherals are is resumed. stopped. It is mandatory to keep V = +5V ±10% during DD Both mode are software activated by a protected power-down mode, because the on-chip instruction and are terminated in different ways as voltage regulator is turned in power saving described in the following sections. mode and it delivers 2.5V to the core logic, but it must be supplied at nominal V = +5V. Note: All external bus actions are completed DD before Idle or Power Down mode is 19.2.1 - Protected Power Down Mode entered. However, Idle or Power Down mode is not entered if READY is enabled, This mode is selected when PWDCFG (bit 5) of but has not been activated (driven low for SYSCON register is cleared. The Protected negative polarity, or driven high for Power Down mode is only activated if the NMI pin positive polarity) during the last bus is pulled low when executing PWRDN instruction access. (this means that the PWRD instruction belongs to the NMI software routine). This mode is only 19.1 - Idle Mode deactivated with an external hardware reset on Idle mode is entered by running IDLE protected RSTIN pin. instruction. The CPU operation is stopped and the Note: During power down the on-chip voltage peripherals still run. regulator automatically lowers the internal Idle mode is terminate by any interrupt request. logic supply voltage to 2.5V, to save power Whatever the interrupt is serviced or not, the and to keep internal RAM and registers instruction following the IDLE instruction will be contents. executed after return from interrupt (RETI) instruction, then the CPU resumes the normal 19.2.2 - Interruptible Power Down Mode program. This mode is selected when PWDCFG (bit 5) of Note that a PEC transfer keep the CPU in Idle SYSCON register is set (See Chapter : Special mode. If the PEC transfer does not succeed, the Function Register Overview on page 125). Idle mode is terminated. Watchdog timer must be The Interruptible Power Down mode is only properly programmed to avoid any disturbance activated if all the enabled Fast External Interrupt during Idle mode. pins are in their inactive level (see EXICON 19.2 - Power Down Mode register description below). Power Down mode starts by running PWRDN This mode is deactivated with an external reset protected instruction. Internal clock is stopped, all applied to RSTIN pin or with an interrupt request MCU parts are on hold including the watchdog applied to one of the Fast External Interrupt pins. timer. To allow the internal PLL and clock to stabilize, There are two different operating Power Down the RSTIN pin must be held low according modes: protected mode and interruptible mode. therecommendations described in Chapter: The internal RAM contents can be preserved System Reset on page 114. EXICON (F1C0h / E0h ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES RW RW RW RW RW RW RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 0 0: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. 122/184 ST10F269 19 - POWER REDUCTION MODES EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 0 1: Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level) 1 0: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level) 1 1: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. the Interrupt Request Flag (bit CCxIR in the EXxIN inputs are normally sampled interrupt inputs. However, the Power Down mode circuitry respective CCxIC register) remains set until it is uses them as level-sensitive inputs. cleared by software. Note: Due to the internal pipeline, the An EXxIN (x=3...0) Interrupt Enable bit (bit instruction that follows the PWRDN CCxIE in respective CCxIC register) need not be instruction is executed before the CPU set to bring the device out of Power Down mode. performs a call of the interrupt service An external RC circuit must be connected to RPD routine when exiting power-down mode pin, as shown in the Figure 61. Figure 61 : External R0C0 Circuit on RPD Pin For Exiting Powerdown Mode with External Interrupt V DD ST10F269-Q3 R0 220kΩ minimum RPD + C0 1μF Typical To exit Power Down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns. This signal enables the internal oscillator and PLL circuitry, and also turns on the weak pull-down (see Figure 62). The discharge of the external capacitor provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and Peripheral clocks are enabled. When the RPD voltage drops below the threshold voltage (about 2.5V), the Schmitt trigger clears Q2 flip-flop, thus enabling the CPU and Peripheral clocks, and the device resumes code execution. If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering Power Down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction (see note below). If the interrupt was disabled, the device executes the instruction following PWRDN instruction, and 123/184 19 - POWER REDUCTION MODES ST10F269 Figure 62 : Simplified Powerdown Exit Circuitry V DD stop pll DQ stop oscillator V DD Q1 enter Q Pull-up cd PowerDown RPD Weak Pull-down (~ 200μA) external interrupt reset V DD DQ CPU and Peripherals clocks Q2 System clock Q cd Figure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) XTAL1 CPU clk Internal Powerdown signal External Interrupt RPD ~ 2.5 V ExitPwrd delay for oscillator/pll (internal) stabilization 124/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW 20 - SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are physical address (using the Data Page Pointers), implemented in the ST10F269 in alphabetical or via its short 8-bit address (without using the order. Bit-addressable SFRs are marked with the Data Page Pointers). letter “b” in column “Name”. SFRs within the The reset value is defined as following: Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. X : Means the full nibble is not defined at reset. A SFR can be specified by its individual mnemonic name. Depending on the selected x : Means some bits of the nibble are not addressing mode, a SFR can be accessed via its defined at reset. Table 40 : Special Function Registers Listed by Name Physical 8-bit Reset Name Description address address value ADCIC b FF98h CCh A/D Converter end of Conversion Interrupt Control Register - - 00h ADCON b FFA0h D0h A/D Converter Control Register 0000h ADDAT FEA0h 50h A/D Converter Result Register 0000h ADDAT2 F0A0h E 50h A/D Converter 2 Result Register 0000h ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register - - 00h BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0xx0h BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h CC0 FE80h 40h CAPCOM Register 0 0000h CC0IC b FF78h BCh CAPCOM Register 0 Interrupt Control Register - - 00h CC1 FE82h 41h CAPCOM Register 1 0000h CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register - - 00h CC2 FE84h 42h CAPCOM Register 2 0000h CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register - - 00h CC3 FE86h 43h CAPCOM Register 3 0000h CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register - - 00h CC4 FE88h 44h CAPCOM Register 4 0000h CC4IC b FF80h C0h CAPCOM Register 4 Interrupt Control Register - - 00h CC5 FE8Ah 45h CAPCOM Register 5 0000h CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register - - 00h CC6 FE8Ch 46h CAPCOM Register 6 0000h CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control Register - - 00h CC7 FE8Eh 47h CAPCOM Register 7 0000h CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control Register - - 00h CC8 FE90h 48h CAPCOM Register 8 0000h CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register - - 00h 125/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical 8-bit Reset Name Description address address value CC9 FE92h 49h CAPCOM Register 9 0000h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register - - 00h CC10 FE94h 4Ah CAPCOM Register 10 0000h CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register - - 00h CC11 FE96h 4Bh CAPCOM Register 11 0000h CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h CC12 FE98h 4Ch CAPCOM Register 12 0000h CC12IC b FF90h C8h CAPCOM Register 12 Interrupt Control Register - - 00h CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC13IC b FF92h C9h CAPCOM Register 13 Interrupt Control Register - - 00h CC14 FE9Ch 4Eh CAPCOM Register 14 0000h CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register - - 00h CC15 FE9Eh 4Fh CAPCOM Register 15 0000h CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register - - 00h CC16 FE60h 30h CAPCOM Register 16 0000h CC16IC b F160h E B0h CAPCOM Register 16 Interrupt Control Register - - 00h CC17 FE62h 31h CAPCOM Register 17 0000h CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register - - 00h CC18 FE64h 32h CAPCOM Register 18 0000h CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register - - 00h CC19 FE66h 33h CAPCOM Register 19 0000h CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register - - 00h CC20 FE68h 34h CAPCOM Register 20 0000h CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register - - 00h CC21 FE6Ah 35h CAPCOM Register 21 0000h CC21IC b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register - - 00h CC22 FE6Ch 36h CAPCOM Register 22 0000h CC22IC b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register - - 00h CC23 FE6Eh 37h CAPCOM Register 23 0000h CC23IC b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register - - 00h CC24 FE70h 38h CAPCOM Register 24 0000h CC24IC b F170h E B8h CAPCOM Register 24 Interrupt Control Register - - 00h CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register - - 00h CC26 FE74h 3Ah CAPCOM Register 26 0000h CC26IC b F174h E BAh CAPCOM Register 26 Interrupt Control Register - - 00h CC27 FE76h 3Bh CAPCOM Register 27 0000h CC27IC b F176h E BBh CAPCOM Register 27 Interrupt Control Register - - 00h CC28 FE78h 3Ch CAPCOM Register 28 0000h CC28IC b F178h E BCh CAPCOM Register 28 Interrupt Control Register - - 00h CC29 FE7Ah 3Dh CAPCOM Register 29 0000h CC29IC b F184h E C2h CAPCOM Register 29 Interrupt Control Register - - 00h 126/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical 8-bit Reset Name Description address address value CC30 FE7Ch 3Eh CAPCOM Register 30 0000h CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register - - 00h CC31 FE7Eh 3Fh CAPCOM Register 31 0000h CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h CP FE10h 08h CPU Context Pointer Register FC00h CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register - - 00h CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h DP0L b F100h E 80h P0L Direction Control Register - - 00h DP0H b F102h E 81h P0h Direction Control Register - - 00h DP1L b F104h E 82h P1L Direction Control Register - - 00h DP1H b F106h E 83h P1h Direction Control Register - - 00h DP2 b FFC2h E1h Port 2 Direction Control Register 0000h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Control Register 00h DP6 b FFCEh E7h Port 6 Direction Control Register 00h DP7 b FFD2h E9h Port 7 Direction Control Register 00h DP8 b FFD6h EBh Port 8 Direction Control Register 00h DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10-bit) 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10-bit) 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10-bit) 0002h DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10-bit) 0003h EXICON b F1C0h E E0h External Interrupt Control Register 0000h EXISEL b F1DAh E EDh External Interrupt Source Selection Register 0000h IDCHIP F07Ch E 3Eh Device Identifier Register (n is the device revision) 10Dnh IDMANUF F07Eh E 3Fh Manufacturer Identifier Register 0401h IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 3040h IDPROG F078h E 3Ch Programming Voltage Identifier Register 0040h IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h IDX1 b FF0Ah 85h MAC Unit Address Pointer 1 0000h MAH FE5Eh 2Fh MAC Unit Accumulator - High Word 0000h MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h MCW b FFDCh EEh MAC Unit Control Word 0000h MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h 127/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical 8-bit Reset Name Description address address value MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MSW b FFDEh EFh MAC Unit Status Word 0200h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h ODP4 b F1CAh E E5h Port 4 Open Drain Control Register - - 00h ODP6 b F1CEh E E7h Port 6 Open Drain Control Register - - 00h ODP7 b F1D2h E E9h Port 7 Open Drain Control Register - - 00h ODP8 b F1D6h E EBh Port 8 Open Drain Control Register - - 00h ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh P0L b FF00h 80h PORT0 Low Register (Lower half of PORT0) - - 00h P0H b FF02h 81h PORT0 High Register (Upper half of PORT0) - - 00h P1L b FF04h 82h PORT1 Low Register (Lower half of PORT1) - - 00h P1H b FF06h 83h PORT1 High Register (Upper half of PORT1) - - 00h P2 b FFC0h E0h Port 2 Register 0000h P3 b FFC4h E2h Port 3 Register 0000h P4 b FFC8h E4h Port 4 Register (8-bit) 00h P5 b FFA2h D1h Port 5 Register (read only) XXXXh P6 b FFCCh E6h Port 6 Register (8-bit) - - 00h P7 b FFD0h E8h Port 7 Register (8-bit) - - 00h P8 b FFD4h EAh Port 8 Register (8-bit) - - 00h P5DIDIS b FFA4h D2h Port 5 Digital Disable Register 0000h POCON0L F080h E 40h PORT0 Low Outpout Control Register (8-bit) - - 00h POCON0H F082h E 41h PORT0 High Output Control Register (8-bit) - - 00h POCON1L F084h E 42h PORT1 Low Output Control Register (8-bit) - - 00h POCON1H F086h E 43h PORT1 High Output Control Register (8-bit) - - 00h POCON2 F088h E 44h Port2 Output Control Register 0000h POCON3 F08Ah E 45h Port3 Output Control Register 0000h POCON4 F08Ch E 46h Port4 Output Control Register (8-bit) - - 00h POCON6 F08Eh E 47h Port6 Output Control Register (8-bit) - - 00h POCON7 F090h E 48h Port7 Output Control Register (8-bit) - - 00h POCON8 F092h E 49h Port8 Output Control Register (8-bit) - - 00h POCON20 F0AAh E 55h ALE, RD, WR Output Control Register (8-bit) 0000h PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PICON b F1C4h E E2h Port Input Threshold Control Register - - 00h 128/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical 8-bit Reset Name Description address address value PP0 F038h E 1Ch PWM Module Period Register 0 0000h PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h PSW b FF10h 88h CPU Program Status Word 0000h PT0 F030h E 18h PWM Module Up/Down Counter 0 0000h PT1 F032h E 19h PWM Module Up/Down Counter 1 0000h PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h PW0 FE30h 18h PWM Module Pulse Width Register 0 0000h PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E BFh PWM Module Interrupt Control Register - - 00h QR0 F004h E 02h MAC Unit Offset Register QR0 0000h QR1 F006h E 03h MAC Unit Offset Register QR1 0000h QX0 F000h E 00h MAC Unit Offset Register QX0 0000h QX1 F002h E 01h MAC Unit Offset Register QX1 0000h RP0H b F108h E 84h System Start-up Configuration Register (read only) - - XXh S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register - - 00h S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) - - XXh S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register - - 00h S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register - - 00h S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 0000h S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register - - 00h SP FE12h 09h CPU System Stack Pointer Register FC00h SSCBR F0B4h E 5Ah SSC Baud Rate Register 0000h SSCCON b FFB2h D9h SSC Control Register 0000h SSCEIC b FF76h BBh SSC Error Interrupt Control Register - - 00h SSCRB F0B2h E 59h SSC Receive Buffer (read only) XXXXh SSCRIC b FF74h BAh SSC Receive Interrupt Control Register - - 00h SSCTB F0B0h E 58h SSC Transmit Buffer (write only) 0000h SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register - - 00h STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h 1 SYSCON b FF12h 89h CPU System Configuration Register 0xx0h T0 FE50h 28h CAPCOM Timer 0 Register 0000h T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h 129/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical 8-bit Reset Name Description address address value T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register - - 00h T3 FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register - - 00h T4 FE44h 22h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register - - 00h T5 FE46h 23h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register - - 00h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register - - 00h T7 F050h E 28h CAPCOM Timer 7 Register 0000h T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register - - 00h T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h T8 F052h E 29h CAPCOM Timer 8 Register 0000h T8IC b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register - - 00h T8REL F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h TFR b FFACh D6h Trap Flag Register 0000h WDT FEAEh 57h Watchdog Timer Register (read only) 0000h 2 WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh 3 XP0IC b F186h E C3h CAN1 Module Interrupt Control Register - - 00h 3 XP1IC b F18Eh E C7h CAN2 Module Interrupt Control Register - - 00h 3 XP2IC b F196h E CBh Flash ready/busy interrupt control register - - 00h 3 XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register - - 00h XPERCON F024h E 12h XPER Configuration Register - - 05h ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h Notes: 1. The system configuration is selected during reset. 2. Bit WDTR indicates a watchdog timer triggered reset. 3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-peripheral nodes. 130/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW 20.1 - Identification Registers The ST10F269 has four Identification registers, Note: 256K and 128K versions of ST10F269 have mapped in ESFR space. These registers contain: the same IDMEM corresponding to 256K. Both versions are based on the same device with – A manufacturer identifier, the only difference that the two upper banks of – A chip identifier, with its revision, Flash are not tested on 128K versions. Therefore, – A internal memory and size identifier and pro- there is no way to detect by software if a device is gramming voltage description. a 128K version or a 256K version. 1 IDMANUF (F07Eh / 3Fh) ESFR Reset Value: 0401h 15 14 13 12 11 10 9876543210 MANUF 00001 R MANUF Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide normalization). 1 IDCHIP (F07Ch / 3Eh) ESFR Reset Value: 10DXh 15 14 13 12 11 10 9876543210 CHIPID REVID RR REVID Device Revision Identifier CHIPID Device Identifier - 10Dh: ST10F269 identifier. 1 IDMEM (F07Ah / 3Dh) ESFR Reset Value: 3040h 15 14 1312 11 10 987654 3210 MEMTYP MEMSIZE RR MEMSIZE Internal Memory Size is calculated using the following formula: Size = 4 x [MEMSIZE] (in K Byte) - 040h for ST10F269 (256K Byte) MEMTYP Internal Memory Type - 3h for ST10F269 (Flash memory). 1 IDPROG (F078h / 3Ch) ESFR Reset Value: 0040h 15 14 13 12 11 10 9876543210 PROGVPP PROGVDD RR PROGVDD Programming V Voltage DD V voltage when programming EPROM or FLASH devices is calculated using the DD following formula: V = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F269 (5V). DD PROGVPP Programming V Voltage (no need of external V ) - 00h PP PP Note : 1. All identification words are read only registers. 131/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 20.2 - System Configuration Registers The ST10F269 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h) SFR Reset Value: 0xx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWD OWD BDR XPER- STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG XPEN VISIBLE CFG DIS STEN SHARE 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. 2. Register SYSCON cannot be changed after execution of the EINIT instruction. XPER-SHARE XBUS Peripheral Share Mode Control ‘0’: External accesses to XBUS peripherals are disabled ‘1’: XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control ‘0’: Accesses to XBUS peripherals are done internally ‘1’: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable bit ‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled ‘1’: The on-chip X-Peripherals are enabled. BDRSTEN Bidirectional Reset Enable ‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin) ‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence. OWDDIS Oscillator Watchdog Disable Control ‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 μs, the CPU clock is switched automatically to PLL’s base frequency (from 2 to 10MHz). ‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The PLL is turned off to reduce power supply current. PWDCFG Power Down Mode Configuration Control ‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. Exit power down only with reset. ‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset. CSCFG Chip Select Configuration Control ‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE ‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE. WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H) 132/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW ‘0’: Pins WR and BHE retain their normal function ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System Clock Output Enable (CLKOUT) ‘0’: CLKOUT disabled: pin may be used for general purpose I/O ‘1’: CLKOUT enabled: pin outputs the system clock signal. BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width) ‘0’: Pin BHE enabled ‘1’: Pin BHE disabled, pin may be used for general purpose I/O. ROMEN Internal Memory Enable (Set according to pin EA during reset) ‘0’: Internal Memory disabled: accesses to the Memory area use the external bus ‘1’: Internal Memory enabled. SGTDIS Segmentation Disable/Enable Control ‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) ‘1’: Segmentation disabled (Only IP is saved/restored). ROMS1 Internal Memory Mapping ‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH) ‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH). STKSZ System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words. BUSCON0 (FF0Ch / 86h) SFR Reset Value: 0xx0h 15 14 13 12 11 10 9 876 5 4 3210 CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BUS ACT0 ALE CTL0 - BTYP MTTC0 RWDC0 MCTC 2 2 1 RW RW RW RW RW RW RW RW RW RW BUSCON1 (FF14h / 8Ah) SFR Reset Value: 0000h 15 14 13 12 11 10 9 8 76 5 4 3210 CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC RW RW RW RW RW RW RW RW RW RW BUSCON2 (FF16h / 8Bh) SFR Reset Value: 0000h 15 14 13 12 11 10 9 8 76 5 4 3210 CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC RW RW RW RW RW RW RW RW RW RW BUSCON3 (FF18h / 8Ch) SFR Reset Value: 0000h 15 14 13 12 11 10 9 8 76 5 4 3210 CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC RW RW RW RW RW RW RW RW RW RW 133/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 BUSCON4 (FF1Ah / 8Dh) SFR Reset Value: 0000h 15 14 13 12 11 10 9 8 76 5 4 3210 CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 - BTYP MTTC4 RWDC4 MCTC RW RW RW RW RW RW RW RW RW RW Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence. 2. BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are set (’1’) and bit field BTYP is loaded with the bus configuration selected via PORT0. MCTC Memory Cycle Time Control (Number of memory cycle time wait states) 0 0 0 0: 15 wait states (Nber = 15 - [MCTC]) . . . 1 1 1 1: No wait state RWDCx Read/Write Delay Control for BUSCONx ‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE ‘1’: No read/write delay: activate command with falling edge of ALE MTTCx Memory Tristate Time Control ‘0’: 1 wait state ‘1’: No wait state BTYP External Bus Configuration 0 0: 8-bit Demultiplexed Bus 0 1: 8-bit Multiplexed Bus 1 0: 16-bit Demultiplexed Bus 1 1: 16-bit Multiplexed Bus Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset. ALECTLx ALE Lengthening Control ‘0’: Normal ALE signal ‘1’: Lengthened ALE signal BUSACTx Bus Active Control ‘0’: External bus disabled ‘1’: External bus enabled (within the respective address window, see ADDRSEL) RDYENx READY Input Enable ‘0’: External bus cycle is controlled by bit field MCTC only ‘1’: External bus cycle is controlled by the READY input signal RDYPOLx Ready Active Level Control ‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY pin, ‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY pin. CSRENx Read Chip Select Enable ‘0’: The CS signal is independent of the read command (RD) ‘1’: The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable ‘0’: The CS signal is independent of the write command (WR,WRL,WRH) ‘1’: The CS signal is generated for the duration of the write command 134/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW RP0H (F108h / 84h) ESFR Reset Value: --XXH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -------- CLKSEL SALSEL CSSEL WRC 1 - 2 2 2 2 R R R R 2 Write Configuration Control WRC ‘0’: Pin WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function 2 Chip Select Line Selection (Number of active CS outputs) CSSEL 0 0: 3 CS lines: CS2...CS0 0 1: 2 CS lines: CS1...CS0 1 0: No CS line at all 1 1: 5 CS lines: CS4...CS0 (Default without pull-downs) 2 Segment Address Line Selection (Number of active segment address outputs) SALSEL 0 0: 4-bit segment address: A19...A16 0 1: No segment address lines at all 1 0: 8-bit segment address: A23...A16 1 1: 2-bit segment address: A17...A16 (Default without pull-downs) 1 - 2 System Clock Selection CLKSEL 000: f = 2.5 x f CPU OSC 001: f = 0.5 x f CPU OSC 010: f = 1.5 x f CPU OSC 011: f = f CPU OSC 100: f = 5 x f CPU OSC 101: f = 2 x f CPU OSC 110: f = 3 x f CPU OSC 111: f = 4 x f CPU OSC Notes: 1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pins during reset, RP0H default value is "FFh". 2. These bits are set according to Port 0 configuration during any reset sequence. 3. RP0H is a read only register. 135/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 EXICON (F1C0h / E0h ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES RW RW RW RW RW RW RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 0 0: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. 0 1: Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level) 1 0: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level) 1 1: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. EXISEL (F1DAh / EDh) ESFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS RW RW RW RW RW RW RW RW EXIxSS External Interrupt x Source Selection (x=7...0) ‘00’: Input from associated Port 2 pin. ‘01’: Input from “alternate source”. ‘10’: Input from Port 2 pin ORed with “alternate source”. ‘11’: Input from Port 2 pin ANDed with “alternate source”. EXIxSS Port 2 pin Alternate Source 0P2.8 CAN1_RxD 1P2.9 CAN2_RxD 2P2.10 RTCSI 3P2.11 RTCAI 4...7 P2.12...15 Not used (zero) 1 XP3IC (F19Eh / CFh) ESFR Reset Value: --00h 15 14 13 12 11 10 9876543210 - - - - - - - - XP3IR XP3IE XP3ILVL GLVL RW RW RW RW Note: 1. XP3IC register has the same bit field as xxIC interrupt registers 136/184 ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW xxIC (yyyyh / zzh) SFR Area Reset Value: --00h 15 14 13 12 11 10 9876543210 -------- xxIR xxIE ILVL GLVL RW RW RW RW Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. Fh: Highest priority level 0h: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) ‘0’: Interrupt Request is disabled ‘1’: Interrupt Request is enabled xxIR Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request XPERCON (F024h / 12h) ESFR Reset Value: --05h 15141312111098765 4 3210 ---- --- - RTCEN - -- XRAM2EN XRAM1EN CAN2EN CAN1EN RW RW RW RW RW CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN is also ‘0’. ‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed. CAN2EN CAN2 Enable Bit ‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if CAN1EN is also ‘0’. ‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed. XRAM1EN XRAM1 Enable Bit ‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1 are disabled. ’1’: Accesses to the internal 2K Bytes of XRAM1. XRAM2EN XRAM2 Enable Bit ‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal XRAM2 are disabled. ’1’: Accesses to the internal 8K Bytes of XRAM2. RTCEN RTC Enable Bit ’0’: Accesses to the on-chip Real Time Clock are disabled, external access performed. Address range 00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also 137/184 20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 ’1’: The on-chip Real Time Clock is enabled and can be accessed. When both CAN are disabled via XPERCON setting, then any access in the address range 00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General Purpose I/O when CAN1 is not enabled. The default XPER selection after Reset is identical to XBUS configuration of ST10C167: XCAN1 is enabled, XCAN2 is disabled, XRAM1 (2K Byte compatible XRAM) is enabled, XRAM2 (new 8K Byte XRAM) is disabled. Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after setting of bit XPEN in SYSCON register. In EMUlation mode, all the XPERipherals are enabled (XPERCON bit are all set). When the Real Time Clock is disabled (RTCEN = 0), the clock oscillator is switch off if ST10 enters in power-down mode. Otherwise, when the Real Time Clock is enabled, the bit RTCOFF of the RTCCON register allows to choose the power-down mode of the clock oscillator. 138/184 ST10F269 21 - ELECTRICAL CHARACTERISTICS 21 - ELECTRICAL CHARACTERISTICS 21.1 - Absolute Maximum Ratings Symbol Parameter Value Unit 1 V -0.5, +6.5 V DD Voltage on V pins with respect to ground DD 1 V -0.5, (V +0.5) V IO Voltage on any pin with respect to ground DD 1 V -0.3, (V +0.3) Voltage on V pin with respect to ground V AREF DD AREF 1 I -10, +10 mA OV Input Current on any pin during overload condition 1 I |100| mA TOV Absolute Sum of all input currents during overload condition 1 P 1.5 W tot Power Dissipation T Ambient Temperature under bias -40, +125 °C A 1 T -65, +150 °C stg Storage Temperature Note: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V > V or V < V ) the voltage on pins with respect to ground (V ) must not exceed the values IN DD IN SS SS defined by the Absolute Maximum Ratings. 21.2 - Parameter Interpretation The parameters listed in the following tables represent the characteristics of the ST10F269 and its demands on the system. Where the ST10F269 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the ST10F269, the symbol “SR” for System Requirement, is included in the “Symbol” column. 21.3 - DC Characteristics V = 5V ± 10%, V = 0V , Reset active, f = 40MHz with T = -40 to + 125°C (PQFP144 devices) or DD SS CPU A f = 32MHz with T = -40 to + 125°C (TQFP144 devices) CPU A Test Symbol Parameter Min. Max. Unit Conditions V SR Input low voltage – -0.5 0.2 V -0.1 V IL DD V SR Input low voltage (special threshold) – -0.5 2.0 V ILS 0.2 V + Input high voltage DD V V + 0.5 SR – V IH DD (all except RSTIN and XTAL1) 0.9 V SR Input high voltage RSTIN – 0.6 V V + 0.5 V IH1 DD DD V 0.7 V V + 0.5 SR Input high voltage XTAL1 – V IH2 DD DD 0.8 V DD V V + 0.5 SR Input high voltage (special threshold) – V IHS DD -0.2 3 HYS Input Hysteresis (special threshold) – 250 – mV Output low voltage (PORT0, PORT1, Port 4, V 1 I = 2.4mA CC –0.45 V OL OL ALE, RD, WR, BHE, CLKOUT, RSTOUT) 139/184 21 - ELECTRICAL CHARACTERISTICS ST10F269 Test Symbol Parameter Min. Max. Unit Conditions V 1 I = 1.6mA CC Output low voltage (all other outputs) –0.45 V OL1 OL1 1 Output high voltage (PORT0, PORT1, Port4, I = -500μA 0.9 V OH – DD V CC V OH ALE, RD, WR, BHE, CLKOUT, RSTOUT) I = -2.4mA 2.4 – OH 1/2 I = – 250μA 0.9 V – V OH DD V CC Output high voltage (all other outputs) OH1 I = – 1.6mA 2.4 – V OH 0V < V < V  I CC Input leakage current (Port 5) – 200 nA IN DD OZ1 0V < V < V  I CC Input leakage current (all other) –1 μA IN DD OZ2 3/4  I SR Overload current –5 mA OV 3 – R CC 50 250 kΩ RST RSTIN pull-up resistor 5/6 V = 2.4V I –-40 μA RWH Read / Write inactive current OUT 5/7 V = V -500 – μA I OUT OLmax Read / Write active current RWL 5/6 V = V 40 – μA I ALE inactive current OUT OLmax ALEL 5/7 V = 2.4V I OUT – 500 μA ALE active current ALEH 5/6 V = 2.4V I OUT –-40 μA Port 6 inactive current P6H 5/7 V = V Port 6 active current OUT OL1max -500 – μA I P6L 5/6 V = V I IN IHmin –-10 μA P0H PORT0 configuration current 5/7 V = V I IN ILmax -100 – μA P0L 0V < V < V  I CC XTAL1 input current –20 μA IL IN DD 3 gm On-chip oscillator transconductance 5- mA/V f = 1MHz, 3/5 C CC Pin capacitance (digital inputs / outputs) –10 pF IO T = 25°C A 8 RSTIN = V 20 + 2.5 x f Power supply current (PQFP144 devices) – mA IH1 CPU I CC f in [MHz] CPU 20 + 2.3 x f Power supply current (TQFP144 devices) – mA CPU 9 RSTIN = V IH1 I 20 + f Idle mode supply current – mA ID CPU f in [MHz] CPU 10 V = 5.5V DD 11 T = 25°C 15 – μA A I Power-down mode supply current PD 11 T = 85°C _ μA 50 A _ 11 μA T = 125°C A 190 140/184 ST10F269 21 - ELECTRICAL CHARACTERISTICS Test Symbol Parameter Min. Max. Unit Conditions 10 V = 5.5V DD Power-down mode supply current (Real time I 12 T = 55°C 2 + f / 4 – mA PD2 A OSC clock enabled, oscillator enabled) f = 25MHz OSC Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column “Test Conditions” is delivered in any cases. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 3. Partially tested, guaranteed by design characterization. 4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. V > V +0.5V or V < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The OV DD OV supply voltage must remain within the specified limits. 5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for CS output and if their open drain function is not enabled. 6. The maximum current may be drawn while the respective signal line remains inactive. 7. The minimum current must be drawn in order to drive the respective signal line active. 8. The power supply current is a function of the operating frequency. This dependency is illustrated in Figure 65 and Figure 65. These parameters are tested at V max and 40MHz (or 32MHz) CPU clock with all outputs disconnected and all inputs at VIL or VIH. The DD chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-states, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated. 9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 65. These parameters are tested at V max and 40MHz (or 32MHz) CPU clock with all outputs disconnected and all inputs at V or V . DD IL IH 10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0V to 0.1V or at V – 0.1V to V , V = 0V, all outputs (including pins configured as outputs) disconnected. DD DD REF 11. Typical I value is 5µA @ T =25°C, 20µA @ T =85°C and 60µA @ T =125°C. PD A A A 12. Partially tested, guaranteed by design characterization using 22pF loading capacitors on crystal pins. 141/184 21 - ELECTRICAL CHARACTERISTICS ST10F269 Figure 64 : Supply / Idle Current as a Function of Operating Frequency (PQFP144 devices) I CCmax 120mA I [mA] I CCtyp 100 60mA IIDmax IIDtyp 10 0 40 20 10 30 f [MHz] CPU 142/184 ST10F269 21 - ELECTRICAL CHARACTERISTICS Figure 65 : Supply / Idle Current as a Function of Operating Frequency (TQFP144 devices) I [mA] I 100 CCmax 93.6mA ICCtyp 52mA I IDmax 50 I IDtyp 0 0 10 20 30 f [MHz] CPU 143/184 ST10F269 21.3.1 - A/D Converter Characteristics V = 5V ± 10%, V = 0V, T = -40 to +85°C or -40 to +125°C, 4.0V ≤ V ≤ V + 0.1V; V 0.1V ≤ DD SS A AREF DD SS V ≤ V + 0.2V AGND SS Table 41 : A/D Converter Characteristics Limit Values Symbol Parameter Test Condition Unit minimum maximum V SR Analog Reference voltage 4.0 V + 0.1 V AREF DD 1 - 8 V SR Analog input voltage V V V AIN AGND AREF 7 I CC Reference supply current AREF running mode – 500 μA power-down mode – 1 μA 7 C CC ADC input capacitance AIN Not sampling – 10 pF Sampling – 15 pF 2 - 4 t CC Sample time 48 TCL 1 536 TCL S 3 - 4 t CC Conversion time 388 TCL 2 884 TCL C 5 DNL CC Differential Nonlinearity -0.5 +0.5 LSB 5 INL CC Integral Nonlinearity -1.5 +1.5 LSB 5 OFS CC Offset Error -1.0 +1.0 LSB 5 TUE CC Total unadjusted error -2.0 +2.0 LSB 2 - 7 R SR Internal resistance of analog source t in [ns] –(t / 150) - 0.25 kΩ ASRC S S 6 - 7 K CC Coupling Factor between inputs –1/500 Notes: 1. V may exceed V or V up to the absolute maximum ratings. However, the conversion result in these cases will be AIN AGND AREF X000h or X3FFh, respectively. 2. During the t sample time the input capacitance C can be charged/discharged by the external source. The internal resistance of S ain the analog source must allow the capacitance to reach its final voltage level within the t sample time. After the end of the t sample S S time, changes of the analog input voltage have no effect on the conversion result. Values for the t sample clock depend on the SC programming. Referring to the t conversion time formula of Section 21.3.2 - ‘Conversion Timing Control’ on page 145 and to C Table 42 on page 145: - t min. = 2 t min. = 2 t min. = 2 x 24 x TCL = 48 TCL S SC CC - t max = 2 t max = 2 x 8 t max = 2 x 8 x 96 TCL = 1536 TCL S SC CC TCL is defined in Section 21.4.2 -, Section 21.4.4 -, and Section 21.4.5 - ‘Direct Drive’ on page 149: 3. The conversion time formula is: - t = 14 t + t + 4 TCL (= 14 t + 2 t + 4 TCL) C CC S CC SC The t parameter includes the t sample time, the time for determining the digital result and the time to load the result register with C S the result of the conversion. Values for the t conversion clock depend on the programming. Referring to Table 42 on page 145: CC - t min. = 14 t min. + t min. + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL C CC S - t max = 14 t max + t max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL C CC S 4. This parameter is fixed by ADC control logic. 5. DNL, INL, TUE are tested at V =5.0V, V =0V, V = 4.9V. It is guaranteed by design characterization for all other AREF AGND CC voltages within the defined voltage range. ‘LSB’ has a value of V / 1024. AREF The specified TUE is guaranteed only if an overload condition (see I specification) occurs on maximum 2 not selected analog input OV pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA. 6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an absolute overload current less than 10mA. 7. Partially tested, guaranteed by design characterization. 8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the t sampling time of the ST10 ADC: s - f ≤ 1 / 5 t to 1/10 t cut-off s s where t is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the t conversion time. s c 144/184 ST10F269 21.3.2 - Conversion Timing Control Fast Conversion can be achieved by programming the respective times to their When a conversion is started, first the absolute possible minimum. This is preferable for capacitances of the converter are loaded via the scanning high frequency signals. The internal respective analog input pin to the current analog resistance of analog source and analog supply input voltage. The time to load the capacitances is must be sufficiently low, however. referred to as the sample time t . Next the s sampled voltage is converted to a digital value in High Internal Resistance can be achieved by 10 successive steps, which correspond to the programming the respective times to a higher 10-bit resolution of the ADC. The next 4 steps are value, or the possible maximum. This is preferable used for equalizing internal levels (and are kept for when using analog sources and supply with a high exact timing matching with the 10-bit A/D internal resistance in order to keep the current as converter module implemented in the ST10F168). low as possible. However the conversion rate in The current that has to be drawn from the sources this case may be considerably lower. for sampling and changing charges depends on the time that each respective step takes, because The conversion times are programmed via the the capacitors must reach their final voltage level upper four bit of register ADCON. Bit field ADCTC within the given time, at least with a certain (conversion time control) selects the basic approximation. The maximum current, however, conversion clock t , used for the 14 steps of CC that a source can deliver, depends on its internal converting. The sample time t is a multiple of this S resistance. conversion time and is selected by bit field The sample time t (= 2 t ) and the conversion ADSTC (sample time control). The table below S SC time t (= 14 t + 2 t + 4 TCL) can be lists the possible combinations. The timings refer c CC SC programmed relatively to the ST10F269 CPU to the unit TCL, where f = 1/2TCL. CPU clock. This allows adjusting the A/D converter of the ST10F269 to the properties of the system: Table 42 : ADC Sampling and Conversion Timing (PQFP144 devices) Conversion Clock t Sample Clock t CC SC ADCTC ADSTC At f = 40MHz CPU At f = 40MHz t = TCL = 1/2 x f CPU SC XTAL and ADCTC = 00 00 TCL x 24 0.3μs00 t 0.3μs CC 01 Reserved, do not use Reserved 01 t x 2 0.6μs CC 10 TCL x 96 1.2 μs10 t x 4 1.2μs CC 11 TCL x 48 0.6 μs11 t x 8 2.4μs CC A complete conversion will take 14 t + 2 t + 4 TCL (fastest conversion rate = 4.85μs at 40MHz). This CC SC time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. 145/184 ST10F269 Table 43 : ADC Sampling and Conversion Timing (TQFP144 devices) Conversion Clock t Sample Clock t CC SC ADCON.15/14 ADCON.13/12 ADCTC At f = 32MHz ADSTC CPU At f = 32MHz t = TCL = 1/2 x f CPU SC XTAL and ADCTC = 00 00 TCL x 24 0.375μs00 t 0.375μs CC 01 Reserved, do not use Reserved 01 t x 2 0.75μs CC 10 TCL x 96 1.5 μs10 t x 4 1.50μs CC 11 TCL x 48 0.75 μs11 t x 8 3.00μs CC A complete conversion will take 14 t + 2 t + 4 TCL (fastest convertion rate = 6.06μs at 32MHz). This CC SC time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. 21.4 - AC characteristics 21.4.1 - Test Waveforms Figure 66 : Input / Output Waveforms 2.4V 0.2V +0.9 0.2V +0.9 DD DD Test Points 0.2V -0.1 0.2V -0.1 DD DD 0.45V AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’. IH IL Figure 67 : Float Waveforms V OH V -0.1V OH V +0.1V Load Timing V Load Reference V -0.1V Points Load V +0.1V OL V OL For timing purposes a port pin is no longer floating when V changes of ±100mV. LOAD It begins to float when a 100mV change from the loaded V /V level occurs (I /I = 20mA). OH OL OH OL 21.4.2 - Definition of Internal Timing example pipeline) or external (for example bus cycles) operations. The internal operation of the ST10F269 is controlled by the internal CPU clock f The specification of the external timing (AC . Both CPU edges of the CPU clock can trigger internal (for Characteristics) therefore depends on the time 146/184 ST10F269 between two consecutive edges of the CPU clock, depends on the mechanism used to generate f . called “TCL”. CPU This influence must be regarded when calculating The CPU clock signal can be generated by the timings for the ST10F269. different mechanisms. The duration of TCL and its The example for PLL operation shown in variation (and also the derived external timing) Figure 68 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 68 : Generation Mechanisms for the CPU Clock Phase locked loop operation f XTAL f CPU TCL TCL Direct Clock Drive f XTAL f CPU TCL TCL Prescaler Operation f XTAL f CPU TCL TCL 147/184 ST10F269 21.4.3 - Clock Generation Modes The Table 44 associates the combinations of these three bits with the respective clock generation mode. Table 44 : CPU Frequency Generation (PQFP144 devices) 1 CPU Frequency f = f x F P0H.7 P0H.6 P0H.5 Notes CPU XTAL External Clock Input Range 11 1 f x 4 2.5 to 10MHz Default configuration XTAL f x 3 3.33 to 13.33MHz 11 0 XTAL f x 2 5 to 20MHz 10 1 XTAL f x 5 2 to 8MHz 10 0 XTAL 2 f x 1 1 to 40MHz 01 1 XTAL Direct drive f x 1.5 6.66 to 26.66MHz 01 0 XTAL 3 f x 0.5 2 to 80MHz 00 1 XTAL CPU clock via prescaler f x 2.5 4 to 16MHz 00 0 XTAL Notes: 1. The external clock input range refers to a CPU clock range of 1...40MHz. 2. The maximum input frequency depends on the duty cycle of the external clock signal. 3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40Ω. However, higher frequencies can be applied with an external clock source on pin XTAL1, but in this case, the input clock signal must reach the defined levels V and V . IL IH2. . Table 45 : CPU Frequency Generation (TQFP144 devices) 1 P0H.7 P0H.6 P0H.5 CPU Frequency f = f x F Notes CPU XTAL External Clock Input Range f x 4 11 1 2.5 to 8MHz Default configuration XTAL 11 0 f x 3 3.33 to 10.67MHz XTAL 10 1 f x 2 5 to 16MHz XTAL 10 0 f x 5 2 to 6.4MHz XTAL 2 01 1 f x 1 1 to 32MHz Direct drive XTAL 01 0 f x 1.5 6.67 to 21.33MHz XTAL 3 00 1 f x 0.5 2 to 64MHz CPU clock via prescaler XTAL f x 2.5 00 0 4 to 12.8MHz XTAL Notes: 1. The external clock input range refers to a CPU clock range of 1...32MHz. 2. The maximum input frequency depends on the duty cycle of the external clock signal. 3. The maximum input frequency is 32MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40Ω. However, higher frequencies can be applied with an external clock source on pin XTAL1, but in this case, the input clock signal must reach the defined levels V and V . IL IH2. 148/184 ST10F269 21.4.4 - Prescaler Operation 21.4.6 - Oscillator Watchdog (OWD) When pins P0.15-13 (P0H.7-5) equal ’001’ during An on-chip watchdog oscillator is implemented in reset, the CPU clock is derived from the internal the ST10F269. This feature is used for safety oscillator (input clock signal) by a 2:1 prescaler. operation with external crystal oscillator (using The frequency of f is half the frequency of CPU direct drive mode with or without prescaler). This f and the high and low time of f (i.e. the XTAL CPU watchdog oscillator operates as following: duration of an individual TCL) is defined by the period of the input clock f . The reset default configuration enables the XTAL watchdog oscillator. It can be disabled by setting The timings listed in the AC Characteristics that the OWDDIS (bit 4) of SYSCON register. refer to TCL therefore can be calculated using the period of f for any TCL. XTAL When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the Note that if the bit OWDDIS in SYSCON register watchdog counter. The PLL free-running is cleared, the PLL runs on its free-running frequency is between 2 and 10MHz. On each frequency and delivers the clock signal for the transition of external clock, the watchdog counter Oscillator Watchdog. If bit OWDDIS is set, then is cleared. If an external clock failure occurs, then the PLL is switched off. the watchdog counter overflows (after 16 PLL 21.4.5 - Direct Drive clock cycles). When pins P0.15-13 (P0H.7-5) equal ’011’ during The CPU clock signal will be switched to the PLL reset the on-chip phase locked loop is disabled free-running clock signal, and the oscillator and the CPU clock is directly driven from the watchdog Interrupt Request (XP3INT) is flagged. internal oscillator with the input clock signal. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 The frequency of f directly follows the CPU pin. Only a hardware reset can switch the CPU frequency of f so the high and low time of f XTAL CPU clock source back to direct clock input. (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock f . XTAL When the OWD is disabled, the CPU clock is Therefore, the timings given in this chapter refer to always external oscillator clock and the PLL is the minimum TCL. This minimum value can be switched off to decrease consumption supply calculated by the following formula: current. TCL = 1f ⁄ xlDC 21.4.7 - Phase Locked Loop min XTALl min DC= duty cycle For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked For two consecutive TCLs, the deviation caused loop is enabled and it provides the CPU clock (see by the duty cycle of f is compensated, so the Table 44 and Table 45). The PLL multiplies the XTAL duration of 2TCL is always 1/f . input frequency by the factor F which is selected XTAL via the combination of pins P0.15-13 (f = f CPU XTAL The minimum value TCL has to be used only min x F). With every F’th transition of f the PLL XTAL once for timings that require an odd number of circuit synchronizes the CPU clock to the input TCLs (1,3,...). Timings that require an even clock. This synchronization is done smoothly, so number of TCLs (2,4,...) may use the formula: the CPU clock frequency does not change 2TCL= 1 ⁄ f abruptly. XTAL Due to this adaptation to the input clock the Note: The address float timings in Multiplexed frequency of f is constantly adjusted so it is CPU bus mode (t and t ) use the maximum 11 45 locked to f . The slight variation causes a jitter XTAL duration of TCL (TCL = 1/f x max XTAL of f which also effects the duration of CPU DC ) instead of TCL . max min individual TCLs. If the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running The timings listed in the AC Characteristics that frequency and delivers the clock signal for refer to TCLs therefore must be calculated using the Oscillator Watchdog. If bit OWDDIS is the minimum TCL that is possible under the set, then the PLL is switched off. respective circumstances. 149/184 ST10F269 The real minimum value for TCL depends on the where N = number of consecutive TCL periods and 1 ≤ N ≤ 40. So for a period of 3 TCL periods jitter of the PLL. The PLL tunes f to keep it CPU (N = 3): locked on f . The relative deviation of TCL is XTAL D = 4 - 3/15 = 3.8% the maximum when it is referred to one TCL 3 period. It decreases according to the formula and 3TCL =3TCL x (1 - 3.8/100) min NOM =3TCL x 0.962 to the Figure 69 given below. For N periods of TCL NOM the minimum value is computed using the 3TCL = 36.075ns (at f = 40MHz) min CPU corresponding deviation D : 3TCL = 45.1ns (at f = 32MHz) N min CPU D  This is especially important for bus cycles using N  TCL= TCL × 1–------------- wait states and e.g. for the operation of timers, MIN NOM 100  serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the D= ±(4N– ⁄15 )[] % N deviation caused by the PLL jitter is negligible. Figure 69 : Approximated Maximum PLL Jitter Max.jitter [%] This approximated formula is valid for 1 ≤ N ≤ 40 and 10MHz ≤ f ≤ 40MHz CPU ±4 ±3 ±2 ±1 8 2 4 16 32 N 21.4.8 - External Clock Drive XTAL1 V = 5V ± 10%, V = 0V, T = -40 to +125 °C (PQFP144 devices) DD SS A f = f x F CPU XTAL f = f f = f / 2 CPU XTAL CPU XTAL F = 1.5/2,/2.5/3/4/5 Parameter Symbol Unit min max min max min max 1 Oscillator period t SR – 12.5 – 40 x N 100 x N ns OSC 25 2 2 2 High time t SR – – –ns 1 10 5 10 2 2 2 Low time t SR – – –ns 2 10 5 10 2 2 2 Rise time t SR – – – ns 3 3 3 3 2 2 2 Fall time t SR – – – ns 4 3 3 3 Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source. 2. The input clock signal must reach the defined levels V and V . IL IH2 150/184 ST10F269 V = 5V ± 10%, V = 0V, T = -40 to +125 °C (TQFP144 devices) DD SS A f = f x F CPU XTAL f = f f = f / 2 CPU XTAL CPU XTAL F = 1.5/2,/2.5/3/4/5 Parameter Symbol Unit Minimum Maximum Minimum Maximum Minimum Maximum 1 Oscillator period t SR ns 31.25 – 15.625 – 31.25 x N – OSC 2 2 2 High time t SR ns 12.5 –6.25 – 12.5 – 1 2 2 2 Low time t SR ns 12.5 –6.25 – 12.5 – 2 2 2 2 Rise time t SR ns – 3.125 –1.56 –3.125 3 2 2 2 Fall time t SR ns – 3.125 –1.56 –3.125 4 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 32MHz is the maximum input frequency when using an external crystal oscillator. However, 32MHz can be applied with an external clock source. 2. The input clock signal must reach the defined levels V and V . IL IH2 Figure 70 : External Clock Drive XTAL1 t t t 3 4 1 V V IL IH2 t 2 t OSC 21.4.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description Symbol Values ALE Extension t TCL x [ALECTL] A Memory Cycle Time wait states t 2TCL x (15 - [MCTC]) C Memory Tri-state Time t 2TCL x (1 - [MTTC]) F 151/184 ST10F269 21.4.10 - Multiplexed Bus V = 5V ± 10%, V = 0V, T = -40 to +125°C, C = 50pF, DD SS A L ALE cycle time = 6 TCL + 2t + t + t (75ns at 40MHz CPU clock without wait states, PQFP144 devices). A C F Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) Max. CPU Clock Variable CPU Clock = 40MHz 1/2 TCL = 1 to 40MHz Symbol Parameter min. max. min. max. t CC ALE high time 4 + t – TCL - 8.5 + t –ns 5 A A t CC Address setup to ALE 2 + t – TCL - 10.5 + t –ns 6 A A t CC Address hold after ALE 1 4 + t – TCL - 8.5 + t –ns 7 A A t CC ALE falling edge to RD, WR 4 + t – TCL - 8.5 + t –ns 8 A A (with RW-delay) t CC ALE falling edge to RD, WR (no -8.5 + t –-8.5 + t –ns 9 A A RW-delay) t CC Address float after RD, WR –6 – 6 ns 10 (with RW-delay) 1 t CC Address float after RD, WR –18.5 – TCL + 6 ns 11 (no RW-delay) 1 t CC RD, WR low time 15.5 + t – 2 TCL -9.5 + t –ns 12 C C (with RW-delay) t CC RD, WR low time 28 + t – 3 TCL -9.5 + t –ns 13 C C (no RW-delay) t SR RD to valid data in –6 + t – 2 TCL - 19 + t ns 14 C C (with RW-delay) t SR RD to valid data in – 18.5 + t – 3 TCL - 19 + t ns 15 C C (no RW-delay) t SR ALE low to valid data in – 18.5 – 3 TCL - 19 ns 16 + t + t + t + t A C A C t SR Address/Unlatched CS to valid – 22 + 2t + – 4 TCL - 28 ns 17 A data in + 2t + t t A C C t SR Data hold after RD 0– 0 – ns 18 rising edge t SR –16.5 + t – 2 TCL - 8.5 + t ns Data float after RD 1 19 F F t CC Data valid to WR 10 + t – 2 TCL -15 + t –ns 22 C C t CC Data hold after WR 4 + t – 2 TCL - 8.5 + t –ns 23 F F t CC ALE rising edge after RD, WR 15 + t – 2 TCL -10 + t –ns 25 F F t CC Address/Unlatched CS hold 10 + t – 2 TCL -15 + t –ns 27 F F after RD, WR t CC ALE falling edge to Latched CS -4 - t 10 - t -4 - t 10 - t ns 38 A A A A t SR Latched CS low to Valid Data In – 18.5 + t + – 3 TCL - 19 ns 39 C + t + 2t 2t C A A t CC Latched CS hold after RD, WR 27 + t – 3 TCL - 10.5 + t –ns 40 F F 152/184 Unit ST10F269 Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) Max. CPU Clock Variable CPU Clock = 40MHz 1/2 TCL = 1 to 40MHz Symbol Parameter min. max. min. max. t CC ALE fall. edge to RdCS, WrCS 7 + t – TCL - 5.5+ t –ns 42 A A (with RW delay) t CC ALE fall. edge to RdCS, WrCS -5.5 + t –-5.5 + t –ns 43 A A (no RW delay) t CC Address float after RdCS, –0 – 0 ns 44 WrCS (with RW delay) 1 t CC Address float after RdCS, –12.5 – TCL ns 45 WrCS (no RW delay) 1 t SR RdCS to Valid Data In –4 + t – 2 TCL - 21 + t ns 46 C C (with RW delay) t SR RdCS to Valid Data In – 16.5 + t – 3 TCL - 21 + t ns 47 C C (no RW delay) t CC RdCS, WrCS Low Time 15.5 + t – 2 TCL - 9.5 + t –ns 48 C C (with RW delay) t CC RdCS, WrCS Low Time 28 + t – 3 TCL - 9.5 + t –ns 49 C C (no RW delay) t CC Data valid to WrCS 10 + t – 2 TCL - 15+ t –ns 50 C C t SR Data hold after RdCS 0– 0 – ns 51 t SR –16.5 + t – 2 TCL - 8.5+t ns Data float after RdCS 1 52 F F t CC Address hold after 6 + t – 2 TCL - 19 + t –ns 54 F F RdCS, WrCS t CC Data hold after WrCS 6 + t – 2 TCL - 19 + t –ns 56 F F Note: 1. Partially tested, guaranteed by design characterization. ALE cycle time = 6 TCL + 2t + t + t (187.5ns at A C F 32MHz CPU clock without wait states). V = 5V ± 10%, V = 0V, T = -40 to +125°C, C DD SS A L = 50pF, Table 47 : Multiplexed Bus Characteristics (TQFP144 devices) Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Minimum Maximum Minimum Maximum t ALE high time 5.625 + t – TCL - 10 + t –ns 5 A A CC t Address setup to ALE 0.625 + t –TCL - 15+ t –ns 6 A A CC t 5.625 + t – TCL - 10 + t –ns Address hold after ALE 1 7 A A CC t ALE falling edge to RD, WR 5.625 + t – TCL - 10 + t –ns 8 A A (with RW-delay) CC 153/184 Unit Unit ST10F269 Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Minimum Maximum Minimum Maximum t ALE falling edge to RD, WR (no -10 + t –-10 + t –ns 9 A A RW-delay) CC t Address float after RD, WR –6 – 6 ns 10 (with RW-delay) 1 CC t Address float after RD, WR – 21.625 – TCL + 6 ns 11 (no RW-delay) 1 CC t RD, WR low time 21.25 + t – 2TCL - 10 + t –ns 12 C C (with RW-delay) CC t RD, WR low time 36.875 + t – 3TCL - 10 + t –ns 13 C C (no RW-delay) CC t RD to valid data in – 11.25 + t – 2TCL - 20+ t ns 14 C C (with RW-delay) SR t RD to valid data in – 26.875 + t – 3TCL - 20+ t ns 15 C C (no RW-delay) SR t ALE low to valid data in – 26.875 + t + t – 3TCL - 20 ns 16 A C + t + t SR A C t Address/Unlatched CS to valid – 32.5 + 2t + t – 4TCL - 30 ns 17 A C data in + 2t + t SR A C t Data hold after RD 0– 0 – ns 18 rising edge SR t – 17.25 + t – 2TCL - 14 + t ns Data float after RD 1 19 F F SR t Data valid to WR 11.25 + t – 2TCL - 20 + t –ns 22 C C CC t Data hold after WR 17.25 + t – 2TCL - 14 + t –ns 23 F F CC t ALE rising edge after RD, WR 17.25 + t – 2TCL - 14 + t –ns 25 F F CC t Address/Unlatched CS hold 17.25 + t – 2TCL - 14 + t –ns 27 F F after RD, WR CC t ALE falling edge to Latched CS -4 - t 10 - t -4 - t 10 - t ns 38 A A A A CC t Latched CS low to Valid Data In – 26.875 + t + 2t – 3TCL - 20 ns 39 C A + t + 2t SR C A t Latched CS hold after RD, WR 32.875 + t – 3TCL - 14 + t –ns 40 F F CC t ALE fall. edge to RdCS, WrCS 11.625 + t –TCL - 4 + t –ns 42 A A (with RW delay) CC t ALE fall. edge to RdCS, WrCS -4 + t –-4 + t –ns 43 A A (no RW delay) CC 154/184 Unit ST10F269 Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Minimum Maximum Minimum Maximum t Address float after RdCS, –0 – 0 ns 44 WrCS (with RW delay) 1 CC t Address float after RdCS, – 15.625 – TCL ns 45 WrCS (no RW delay) 1 CC t RdCS to Valid Data In – 7.25 + t – 2TCL - 24 + t ns 46 C C (with RW delay) SR t RdCS to Valid Data In – 22.875 + t – 3TCL - 24 + t ns 47 C C (no RW delay) SR t RdCS, WrCS Low Time 21.25 + t – 2TCL - 10 + t –ns 48 C C (with RW delay) CC t RdCS, WrCS Low Time 36.875 + t – 3TCL - 10 + t –ns 49 C C (no RW delay) CC t Data valid to WrCS 17.25 + t –2TCL - 14+ t –ns 50 C C CC t Data hold after RdCS 0– 0 – ns 51 SR t – 11.25 + t – 2TCL - 20 + t ns Data float after RdCS 1 52 F F SR t Address hold after 11.25 + t – 2TCL - 20 + t –ns 54 F F RdCS, WrCS CC t Data hold after WrCS 11.25 + t – 2TCL - 20 + t –ns 56 F F CC 1. Partially tested, guaranted by design characterization. 155/184 Unit ST10F269 Figure 71 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t t 5 t 25 16 ALE t 6 t t 38 40 t 17 t t 27 39 CSx t 6 t t 27 17 A23-A16 (A15-A8) Address BHE t 16 t 6m Read Cycle t 7 t 18 Address/Data Address Data In Address Bus (P0) t 10 t 19 t 8 t 14 RD t 12 t 13 t 9 t 11 t 15 Write Cycle t 23 Address/Data Address Data Out Bus (P0) t t 8 22 WR WRL t 9 t 12 WRH t 13 156/184 ST10F269 Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t t t 5 16 25 ALE t 6 t 38 t 40 t 17 t t 39 27 CSx t 6 t 17 A23-A16 Address (A15-A8) BHE t 27 Read Cycle t 6 t 7 Address/Data Address Data In Bus (P0) t 18 t t 8 10 t 19 t t 9 11 t 14 RD t 15 t 12 t 13 Write Cycle Address/Data Address Data Out Bus (P0) t 23 t t 8 10 t t 11 t 9 22 WR WRL t 12 WRH t 13 157/184 ST10F269 Figure 73 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t t 5 t 25 16 ALE t 6 t t 27 17 A23-A16 (A15-A8) Address BHE t 16 t 6 Read Cycle t 7 t 51 Address/Data Address Address Data In Bus (P0) t 44 t 52 t 42 t 46 RdCSx t 48 t 49 t 43 t 45 t 47 Write Cycle t 56 Address/Data Address Data Out Bus (P0) t t 42 50 WrCSx t 43 t 48 t 49 158/184 ST10F269 Figure 74 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t t t 5 16 25 ALE t 6 t 17 A23-A16 Address (A15-A8) BHE t 54 Read Cycle t 6 t 7 Address/Data Data In Bus (P0) Address t 18 t t 42 44 t t 19 43 t 45 t 46 RdCSx t 48 t 47 t 49 Write Cycle Address/Data Address Data Out Bus (P0) t t t 42 44 56 t 43 t t 45 50 WrCSx t 48 t 49 159/184 ST10F269 21.4.11 - Demultiplexed Bus ALE cycle time = 4 TCL + 2t + t + t (50ns at A C F 40MHz CPU clock without wait states), PQFP144 V = 5V ± 10%, V = 0V, T = -40 to +125°C, C DD SS A L = 50pF, devices. Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) Maximum CPU Clock Variable CPU Clock = 40MHz 1/2 TCL = 1 to 40MHz Symbol Parameter Minimum Maximum Minimum Maximum t CC ALE high time 4 + t –TCL - 8.5 + t –ns 5 A A t CC Address setup to ALE 2 + t – TCL - 10.5 + t –ns 6 A A t CC Address/Unlatched CS setup to 16.5 + 2t – 2 TCL - 8.5 + 2t –ns 80 A A RD, WR (with RW-delay) t CC Address/Unlatched CS setup to 4 + 2t – TCL - 8.5 + 2t –ns 81 A A RD, WR (no RW-delay) t CC RD, WR low time 15.5 + t – 2 TCL - 9.5 + t –ns 12 C C (with RW-delay) t CC RD, WR low time 28 + t – 3 TCL - 9.5 + t –ns 13 C C (no RW-delay) t SR RD to valid data in –6 + t – 2 TCL - 19 + t ns 14 C C (with RW-delay) t SR RD to valid data in – 18.5 + t – 3 TCL - 19 + t ns 15 C C (no RW-delay) t SR ALE low to valid data in – 18.5 + t + –3 TCL - 19 ns 16 A + t + t t A C C t SR Address/Unlatched CS to valid –22 + 2t + –4 TCL - 28 ns 17 A data in + 2t + t t A C C t SR Data hold after RD 0– 0 – ns 18 rising edge t SR Data float after RD rising edge – 16.5 + t –2 TCL - 8.5 ns 20 F 1 3 1 (with RW-delay) + t + 2t F A t SR Data float after RD rising edge –4 + t –TCL - 8.5 ns 21 F 1 3 1 (no RW-delay) + t + 2t F A t CC Data valid to WR 10 + t – 2 TCL - 15 + t –ns 22 C C t CC Data hold after WR 4 + t – TCL - 8.5 + t –ns 24 F F t CC ALE rising edge after RD, WR -10 + t – -10 + t –ns 26 F F t CC Address/Unlatched CS hold 0 (no t ) – 0 (no t ) –ns 28 F F 2 -5 + t -5 + t after RD, WR F F (t > 0) (t > 0) F F t CC Address/Unlatched CS hold -5 + t –-5 + t –ns 28h F F after WRH t CC ALE falling edge to Latched CS -4 - t 6 - t -4 - t 6 - t ns 38 A A A A t SR Latched CS low to Valid Data In – 18.5 –3 TCL - 19 ns 39 + t + 2t + t + 2t C A C A 160/184 Unit ST10F269 Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) Maximum CPU Clock Variable CPU Clock = 40MHz 1/2 TCL = 1 to 40MHz Symbol Parameter Minimum Maximum Minimum Maximum t CC Latched CS hold after RD, WR 2 + t – TCL - 10.5 + t –ns 41 F F t CC Address setup to RdCS, WrCS 14.5 + 2t – 2 TCL - 10.5 + –ns 82 A (with RW-delay) 2t A t CC Address setup to RdCS, WrCS 2 + 2t – TCL - 10.5 + 2t –ns 83 A A (no RW-delay) t SR RdCS to Valid Data In –4 + t – 2 TCL - 21 + t ns 46 C C (with RW-delay) t SR RdCS to Valid Data In – 16.5 + t – 3 TCL - 21 + t ns 47 C C (no RW-delay) t CC RdCS, WrCS Low Time 15.5 + t –2 TCL - 9.5 –ns 48 C (with RW-delay) + t C t CC RdCS, WrCS Low Time 28 + t – 3 TCL - 9.5 + t –ns 49 C C (no RW-delay) t CC Data valid to WrCS 10 + t – 2 TCL - 15 + t –ns 50 C C t SR Data hold after RdCS 0– 0 – ns 51 t SR Data float after RdCS – 16.5 + t – 2 TCL - 8.5 + t ns 53 F F 3 (with RW-delay) t SR Data float after RdCS –4 + t – TCL - 8.5 + t ns 68 F F 3 (no RW-delay) t CC Address hold after -8.5 + t – -8.5 + t –ns 55 F F RdCS, WrCS t CC Data hold after WrCS 2 + t – TCL - 10.5 + t –ns 57 F F Notes: 1. RW-delay and t refer to the next following bus cycle. A 2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3. Partially tested, guaranteed by design characterization. V = 5V ± 10%, V = 0V, T = -40 to +85°C, C = 50pF, DD SS A L ALE cycle time = 4 TCL + 2t + t + t (125ns at 32MHz CPU clock without wait states) RW-delay and t A C F A refer to the next following bus cycle. Table 49 : Demultiplexed Bus Characteristics (TQFP144 devices) Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Unit Minimum Maximum Minimum Maximum t CC ALE high time 5.625 + t –TCL - 10+ t –ns 5 A A t CC Address setup to ALE 0.625 + t –TCL - 15+ t –ns 6 A A t CC Address/Unlatched CS setup 21.25 + 2t – 2TCL - 10 + 2t –ns 80 A A to RD, WR (with RW-delay) 161/184 Unit ST10F269 Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Unit Minimum Maximum Minimum Maximum t CC Address/Unlatched CS setup 5.625 + 2t –TCL -10 + 2t –ns 81 A A to RD, WR (no RW-delay) t CC RD, WR low time 21.25 + t – 2TCL - 10 + t –ns 12 C C (with RW-delay) t CC RD, WR low time 36.875 + t – 3TCL - 10 + t –ns 13 C C (no RW-delay) t SR RD to valid data in – 11.25 + t – 2TCL - 20 + t ns 14 C C (with RW-delay) t SR RD to valid data in – 26.875 + t – 3TCL - 20 + t ns 15 C C (no RW-delay) t SR ALE low to valid data in – 26.875 + t + –3TCL - 20 ns 16 A t + t + t C A C t SR Address/Unlatched CS to – 32.5 + 2t + – 4TCL - 30 ns 17 A valid data in t + 2t + t C A C t SR Data hold after RD 0– 0 – ns 18 rising edge t SR Data float after RD rising – 26 + t – 2TCL - 14 ns 20 F 1 1 - 3 + t + 2t edge (with RW-delay) F A t SR Data float after RD rising – 5.625 + t –TCL - 10 ns 21 F 1 1 - 3 + t + 2t edge (no RW-delay) F A t CC Data valid to WR 11.25 + t – 2TCL- 20 + t –ns 22 C C t CC Data hold after WR 5.625 + t –TCL - 10+ t –ns 24 F F t CC ALE rising edge after RD, WR -10 + t – -10 + t –ns 26 F F t CC Address/Unlatched CS hold 0 (no t ) – 0 (no t ) –ns F F 28 2 -5 + t -5 + t after RD, WR F F (t > 0) (t > 0) F F t CC Address/Unlatched CS hold -5 + t –-5 + t –ns 28h F F after WRH t CC ALE falling edge to Latched -4 - t 10 - t -4 - t 10 - t ns 38 A A A A CS t SR Latched CS low to Valid Data – 26.875 + t + – 3TCL - 20 ns 39 C In 2t + t + 2t A C A t CC Latched CS hold after RD, 1.625 + t –TCL - 14 + t –ns 41 F F WR t CC Address setup to RdCS, 17.25 + 2t – 2TCL - 14 + 2t –ns 82 A A WrCS (with RW-delay) t CC Address setup to RdCS, 1.625 + 2t –TCL -14 + 2t –ns 83 A A WrCS (no RW-delay) t SR RdCS to Valid Data In – 7.25 + t – 2TCL - 24 + t ns 46 C C (with RW-delay) t SR RdCS to Valid Data In – 22.875 + t – 3TCL - 24 + t ns 47 C C (no RW-delay) 162/184 ST10F269 Maximum CPU Clock = Variable CPU Clock 32MHz 1/2 TCL = 1 to 32MHz Symbol Parameter Unit Minimum Maximum Minimum Maximum t CC RdCS, WrCS Low Time 21.25 + t – 2TCL - 10 + t –ns 48 C C (with RW-delay) t CC RdCS, WrCS Low Time 36.875 + t – 3TCL - 10 + t –ns 49 C C (no RW-delay) t CC Data valid to WrCS 17.25 + t – 2TCL - 14 + t –ns 50 C C t SR Data hold after RdCS 0– 0 – ns 51 t SR Data float after RdCS – 21.25 + t – 2TCL - 10 + t ns 53 F F 3 (with RW-delay) t SR Data float after RdCS –0 + t –TCL - 10 + t ns 68 F F 3 (no RW-delay) t CC Address hold after -10 + t – -10 + t –ns 55 F F RdCS, WrCS t CC Data hold after WrCS 1.625 + t –TCL - 14 + t –ns 57 F F Notes: 1. RW-delay and t refer to the next following bus cycle. A 2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3. Partially tested, guaranteed by design characterization. 163/184 ST10F269 Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t t 26 5 t 16 ALE t 6 t t 38 41 t 17 1) t 41u t 39 CSx t 6 t (or t ) t 28 28h 17 A23-A16 A15-A0 (P1) Address BHE t 18 Read Cycle Data Bus (P0) Data In (D15-D8) D7-D0 t t t 20 80 14 t t 81 21 t 15 RD t 12 t 13 Write Cycle Data Bus (P0) Data Out (D15-D8) D7-D0 t 80 t t 22 24 t 81 WR WRL WRH t 12 t 13 Note: 1. Un-latched CSx = t = t TCL =10.5 + t . 41u 41 F 164/184 ST10F269 Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t t 5 26 t 16 ALE t 6 t 38 t 41 t 17 t 28 t 39 CSx t 6 t t 28 17 A23-A16 A15-A0 (P1) Address BHE t 18 Read Cycle Data Bus (P0) Data In (D15-D8) D7-D0 t t t 20 80 14 t t t 81 15 21 RD t 12 t 13 Write Cycle Data Bus (P0) Data Out (D15-D8) D7-D0 t 80 t t 81 t 24 22 WR WRL WRH t 12 t 13 165/184 ST10F269 Figure 77 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t t 26 5 t 16 ALE t 6 t t 17 55 A23-A16 A15-A0 (P1) Address BHE t 51 Read Cycle Data Bus (P0) Data In (D15-D8) D7-D0 t t t 82 46 53 t t 83 68 t 47 RdCSx t 48 t 49 Write Cycle Data Bus (P0) Data Out (D15-D8) D7-D0 t 82 t t 50 57 t 83 WrCSx t 48 t 49 166/184 ST10F269 Figure 78 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t t 5 26 t 16 ALE t 6 t t 55 17 A23-A16 A15-A0 (P1) Address BHE t 51 Read Cycle Data Bus (P0) Data In (D15-D8) D7-D0 t t t 53 82 46 t t t 83 47 68 RdCSx t 48 t 49 Write Cycle Data Bus (P0) Data Out (D15-D8) D7-D0 t 82 t t t 83 57 50 WrCSx t 48 t 49 167/184 ST10F269 21.4.12 - CLKOUT and READY V = 5V ± 10%, V = 0V, T = -40 to + 125°C, C = 50pF, PQFP144 devices DD SS A L Table 50 : CLKOUT and READY Characteristics (PQFP144 devices) Maximum CPU Clock Variable CPU Clock = 40 MHz 1/2TCL = 1 to 40 MHz Symbol Parameter Minimum Maximum Minimum Maximum t CC CLKOUT cycle time 25 25 2TCL 2TCL ns 29 t CC CLKOUT high time 4 – TCL – 8.5 – ns 30 t CC CLKOUT low time 3 – TCL – 9.5 – ns 31 t CC CLKOUT rise time – 4 – 4 ns 32 t CC CLKOUT fall time – 4 – 4 ns 33 t CC CLKOUT rising edge to -2 + t 8 + t -2 + t 8 + t ns 34 A A A A ALE falling edge t SR Synchronous READY 12.5 – 12.5 – ns 35 setup time to CLKOUT t SR Synchronous READY 2– 2 – ns 36 hold time after CLKOUT t SR Asynchronous READY 35 – 2TCL + 10 – ns 37 low time t SR Asynchronous READY 12.5 – 12.5 – ns 58 1) setup time t SR Asynchronous READY 2– 2 – ns 59 1) hold time t SR Async. READY hold time after 0 0 TCL - 12.5 ns 60 0 + 2t + t + t A F C 2) RD, WR high (Demultiplexed + 2t + t + t 2) A F C 2) Bus) Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2t and t refer to the next following bus cycle, t refers to the current bus cycle. A C F 168/184 Unit ST10F269 V = 5V ± 10%, V = 0V, T = -40 to + 125°C, C = 50pF, TQFP144 devices DD SS A L Table 51 : CLKOUT and READY Characteristics (TQFP144 devices) Maximum CPU Clock Variable CPU Clock = 32MHz 1/2TCL = 1 to 32MHz Symbol Parameter Minimum Maximum Minimum Maximum t CC CLKOUT cycle time 31.25 31.25 2TCL 2TCL ns 29 t CC CLKOUT high time 9.625 – TCL – 6 – ns 30 t CC CLKOUT low time 5.625 – TCL – 10 – ns 31 t CC CLKOUT rise time – 4 – 4 ns 32 t CC CLKOUT fall time – 4 – 4 ns 33 t CC CLKOUT rising edge to -3 + t +7 + t -3 + t +7 + t ns 34 A A A A ALE falling edge t SR Synchronous READY 14 – 14 – ns 35 setup time to CLKOUT t SR Synchronous READY 4– 4 – ns 36 hold time after CLKOUT t SR Asynchronous READY 45.25 – 2TCL + 14 – ns 37 low time t SR Asynchronous READY 14 – 14 – ns 58 1) setup time t SR Asynchronous READY 4– 4 – ns 59 1) hold time t SR Async. READY hold time after 00 + 2t 0 TCL - 15.625 + ns 60 A 2 2 RD, WR high (Demultiplexed + t + t 2t + t + t C F A C F 2) Bus) Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Note 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2t and t refer to the next following bus cycle, t refers to the current bus cycle. A C F 169/184 Unit ST10F269 Figure 79 : CLKOUT and READY READY Running cycle 1) MUX / Tri-state 6) wait state t t 32 33 CLKOUT t 30 t 29 t 31 t 34 ALE 7) RD, WR 2) t t t t 35 36 35 36 Synchronous READY 3) 3) t t t t t 4) 58 59 58 59 60 Asynchronous READY 3) 3) 6) t 5) 37 Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t in order to be safely synchronized. This is guaranteed, if READY is removed in response to 37 the command (see Note 4)). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here. 170/184 ST10F269 21.4.13 - External Bus Arbitration V = 5V ± 10%, V = 0V, T = -40 to +125°C, C = 50pF (PQFP144 devices) DD SS A L Maximum CPU Clock Variable CPU Clock = 40 MHz 1/2TCL = 1 to 40 MHz Symbol Parameter Minimum Maximum Minimum Maximum t HOLD input setup time 15 – 15 – ns 61 SR to CLKOUT t CLKOUT to HLDA high – 12.5 – 12.5 ns 62 CC or BREQ low delay t CLKOUT to HLDA low – 12.5 – 12.5 ns 63 CC or BREQ high delay 1 t – 15 – 15 ns 64 CC CSx release t CSx drive -4 15 -4 15 ns 65 CC 1 t – 15 – 15 ns 66 CC Other signals release t Other signals drive -4 15 -4 15 ns 67 CC Note: 1. Partially tested, guaranteed by design characterization V = 5V ± 10%, V = 0V, T = -40 to +125°C, C = 50pF (TQFP144 devices) DD SS A L Maximum CPU Clock Variable CPU Clock = 32MHz 1/2TCL = 1 to 32MHz Symbol Parameter Unit Minimum Maximum Minimum Maximum t HOLD input setup time 20 – 20 – ns 61 SR to CLKOUT t CLKOUT to HLDA high – 15.625 – 15.625 ns 62 CC or BREQ low delay t CLKOUT to HLDA low – 15.625 – 15.625 ns 63 CC or BREQ high delay 1 t –15 – 15 ns CSx release 64 CC t CSx drive -4 15 -4 15 ns 65 CC 1 t –15 – 15 ns 66 CC Other signals release t Other signals drive -4 15 -4 15 ns 67 CC Note: 1. Partially tested, guaranteed by design characterization 171/184 Unit ST10F269 . Figure 80 : External Bus Arbitration (Releasing the Bus) CLKOUT t 61 HOLD t 63 1) HLDA t 62 BREQ 2) t 64 3) CSx (P6.x) t 66 1) Others Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t . 64 172/184 ST10F269 Figure 81 : External Bus Arbitration (Regaining the Bus) 2) CLKOUT t 61 HOLD t 62 HLDA t t t 62 62 63 1) BREQ t 65 CSx (On P6.x) t 67 Other Signals Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F269 requesting the bus. 2. The next ST10F269 driven bus cycle may start here. 173/184 ST10F269 21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing 21.4.14.1 Master Mode V = 5V ±10%, V = 0V, CPU clock = 40MHz, T = -40 to +125°C, C = 50pF (PQFP144 devices) CC SS A L Maximum Baud rate = 10M Baud Variable Baud rate ( = 0001h) (=0001h-FFFFh) Symbol Parameter Unit Minimum Maximum Minimum Maximum CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns t 300 –ns CC SSC clock high time 40 – t t /2 - 10 301 300 CC SSC clock low time 40 – –ns t t /2 - 10 302 300 CC SSC clock rise time – 10 – 10 ns t 303 CC SSC clock fall time – 10 – 10 ns t 304 CC Write data valid after shift edge – 15 – 15 ns t 305 1 CC -2 – -2 – ns t Write data hold after shift edge 306 SR Read data setup time before 37.5 – 2TCL+12.5 – ns t 307p latch edge, phase error detection on (SSCPEN = 1) SR Read data hold time after latch 50 – 4TCL – ns t 308p edge, phase error detection on (SSCPEN = 1) SR Read data setup time before 25 – 2TCL – ns t 307 latch edge, phase error detection off (SSCPEN = 0) SR Read data hold time after latch 0– 0 – ns t 308 edge, phase error detection off (SSCPEN = 0) Note: 1. Timing guaranteed by design. The formula for SSC Clock Cycle time is: t = 4 TCL * ( + 1) 300 Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. V = 5V ±10%, V = 0V, CPU clock = 32MHz, T = -40 to +125°C, C = 50pF (TQFP144 devices) CC SS A L Maximum Baud rate=6.25MBd Variable Baud rate Symb ( = 0001h) (=0001h-FFFFh) Symbol Parameter ol Minimum Maximum Minimum Maximum SR SSC clock cycle time 125 – 8 TCL 262144 TCL t t 310 310 SR SSC clock high time 52.5 – – t t /2 - 10 t 311 310 311 SR SSC clock low time 52.5 – – t t /2 - 10 t 312 310 312 SR SSC clock rise time – 10 – 10 t t 313 313 SR SSC clock fall time – 10 – 10 t t 314 314 CC Write data valid after shift edge – 45.25 – 2 TCL + 14 t t 315 315 CC Write data hold after shift edge 0 – 0 – t t 316 316 SR Read data setup time before latch edge, 78.125 – 4TCL + – t t 317p 317p phase error detection on (SSCPEN = 1) 15.625 1 SR Read data hold time after latch edge, 109.375 – 6TCL + – 1 t t 318p 318p phase error detection on (SSCPEN = 1) 15.625 SR Read data setup time before latch edge, 6– 6 – t t 317 317 phase error detection off (SSCPEN = 0) 174/184 ST10F269 Maximum Baud rate=6.25MBd Variable Baud rate Symb ( = 0001h) (=0001h-FFFFh) Symbol Parameter ol Minimum Maximum Minimum Maximum SR Read data hold time after latch edge, 41.25 – 2TCL + 10 – t t 318 318 phase error detection off (SSCPEN = 0) Note: 1. Timing guaranteed by design. The formula for SSC Clock Cycle time is : t = 4 TCL * ( + 1) 300 Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer Figure 82 : SSC Master Timing t t t3003013022) 1) SCLK t t 304 303 t t t t 305 305 306 305 MTSR 1st Out Bit 2nd Out BitLast Out Bit t t t t 307 308 307 308 MRST 2nd.In Bit 1st.In Bit Last.In Bit Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 21.4.14.2 Slave mode V = 5V ±10%, V = 0V, CPU clock = 40MHz, T = -40 to +125°C, C = 50pF (PQFP144 devices) CC SS A L Maximum Baud rate=10MBd Variable Baud rate ( = 0001h) (=0001h-FFFFh) Symbol Parameter Unit Minimum Maximum Minimum Maximum SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns t 310 SR SSC clock high time 40 – –ns t t /2 - 10 311 310 SR SSC clock low time 40 – –ns t t /2 - 10 312 310 SR SSC clock rise time – 10 – 10 ns t 313 SR SSC clock fall time – 10 – 10 ns t 314 CC Write data valid after shift edge – 39 – 2 TCL + 14 ns t 315 CC Write data hold after shift edge 0 – 0 – ns t 316 SR Read data setup time before latch 62 – 4TCL + 12 – ns t 317p edge, phase error detection on (SSCPEN = 1) 1 SR Read data hold time after latch edge, 87 – 6TCL + 12 – ns t 318p phase error detection on (SSCPEN = 1) 175/184 ST10F269 Maximum Baud rate=10MBd Variable Baud rate ( = 0001h) (=0001h-FFFFh) Symbol Parameter Unit Minimum Maximum Minimum Maximum SR Read data setup time before latch6– 6 – ns t 317 edge, phase error detection off (SSCPEN = 0) SR Read data hold time after latch edge, 31 – 2TCL + 6 – ns t 318 phase error detection off (SSCPEN = 0) The formula for SSC Clock Cycle time is: t = 4 TCL * ( + 1) 310 Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. V = 5V ±10%, V = 0V, CPU clock = 32MHz, T = -40 to +125°C, C = 50pF (TQFP144 devices) CC SS A L Maximum Baud rate=6.25MBd Variable Baud rate ( = 0001h) (=0001h-FFFFh) Symbol Parameter Unit Minimum Maximum Minimum Maximum SR SSC clock cycle time 125 – 8 TCL 262144 TCL ns t 310 SR SSC clock high time 52.5 – –ns t t /2 - 10 311 310 SR SSC clock low time 52.5 – –ns t t /2 - 10 312 310 SR SSC clock rise time – 10 – 10 ns t 313 SR SSC clock fall time – 10 – 10 ns t 314 CC Write data valid after shift edge – 45.25 – 2 TCL + 14 ns t 315 CC Write data hold after shift edge 0 – 0 – ns t 316 SR Read data setup time before latch edge, 78.125 – 4TCL + –ns t 317p phase error detection on (SSCPEN = 1) 15.625 1 SR Read data hold time after latch edge, 109.375 – 6TCL + –ns t 318p phase error detection on (SSCPEN = 1) 15.625 SR Read data setup time before latch edge, 6– 6 – ns t 317 phase error detection off (SSCPEN = 0) SR Read data hold time after latch edge, 41.25 – 2TCL + 10 – ns t 318 phase error detection off (SSCPEN = 0) The formula for SSC Clock Cycle time is: t = 4 TCL * ( + 1) 310 Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer 176/184 ST10F269 Figure 83 : SSC Slave Timing t t t 310311 3122) 1) SCLK tt314 313 t t t t 315 315 316 315 MRST 1st Out Bit 2nd Out Bit Last Out Bit t t t t 317 318 317 318 1st.In Bit 2nd.In Bit Last.In Bit MTSR Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 177/184 c 22 - PACKAGE MECHANICAL DATA ST10F269 22 - PACKAGE MECHANICAL DATA Figure 84 : Package Outline PQFP144 (28 x 28mm) A A2 A1 e 144 109 0,10 mm .004 inch SEATING PLANE 108 1 36 73 37 72 D3 D1 D K 1 Inches (approx) Millimeters Dimensions Minimum Typical Maximum Minimum Typical Maximum A 4.07 0.160 A1 0.25 0.010 A2 3.17 3.42 3.67 0.125 0.133 0.144 B 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 D 30.95 31.20 31.45 1.219 1.228 1.238 D1 27.90 28.00 28.10 1.098 1.102 1.106 D3 22.75 0.896 e 0.65 0.026 E 30.95 31.20 31.45 1.219 1.228 1.238 E1 27.90 28.00 28.10 1.098 1.102 1.106 L 0.65 0.80 0.95 0.026 0.031 0.037 L1 1.60 0.063 K 0° (Minimum), 7° (Maximum) Note: 1. Package dimensions are in mm. The dimensions quoted in inches are rounded. 178/184 E3 L1 E1 L E B c ST10F269 22 - PACKAGE MECHANICAL DATA Figure 85 : Package Outline TQFP144 (20 x 20 x 1.40 mm) A A2 A1 e 144 109 0,076 mm 0.03 inch SEATING PLANE 1 108 36 73 37 72 D3 D1 D 0,25 mm .010 inch GAGE PLANE K 1 Inches (approx) Millimeters Dimensions Minimum Typical Maximum Minimum Typical Maximum A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.17 0.22 0.27 0.0067 0.0087 0.011 C 0.09 0.20 0.0035 0.008 D 22.00 0.866 D1 20.00 0.787 D3 17.50 0.689 e 0.50 0.020 E 22.00 0.866 E1 20.00 0.787 E3 17.50 0.689 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 0.039 K0° (Minimum), 7° (Maximum) 1. Package dimensions are in mm. The dimensions quoted in inches are rounded. 179/184 E3 L1 E1 L E B 23 - ORDERING INFORMATION ST10F269 23 - ORDERING INFORMATION Flash Program Salestype Memory Temperature range Package (Bytes) ST10F269Z2Q3 256K -40°C to +125°C PQFP144 (28 x 28 mm) ST10F269Z2Q6 256K -40°C to +85°C PQFP144 (28 x 28 mm) ST10F269Z2T3 256K -40°C to +125°C TQFP144 (20 x 20 x 1.40 mm) ST10F269Z2T6 256K -40°C to +85°C TQFP144 (20 x 20 x 1.40 mm) ST10F269Z1Q3 128K -40°C to +125°C PQFP144 (28 x 28 mm) ST10F269Z1Q6 128K -40°C to +85°C PQFP144 (28 x 28 mm) ST10F269Z1T3 128K -40°C to +125°C TQFP144 (20 x 20 x 1.40 mm) ST10F269Z1T6 128K -40°C to +85°C TQFP144 (20 x 20 x 1.40 mm) 180/184 ERRATA SHEET ST10F269Zxxx-D LIMITATIONS AND CORRECTIONS 1 - DESCRIPTION This Errata sheet describes the functional and electrical problems known in the D revision of the ST10F269Zxxx. The revision number can be found in the third line on the ST10F269 package. It looks like: ’xxxxxxxxx D’ where "D" identifies the revision number. 2 - FUNCTIONAL PROBLEMS The following malfunctions are known in this step: 2.1 - PWRDN.1 - Execution of PWRDN Instruction When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRD- CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the PWRDN instruction is ignored. However, under the conditions described below, the PWRDN instruction is not ignored, and no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This problem only occurs in the following situations: a) The instructions following the PWRDN instruction are located in an external memory, and a multi- plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used. Or b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral (XRAM,CAN), and the instructions following the PWRDN instruction are located in external memory. In this case, the problem occurs for any bus configuration. Note: The on-chip peripherals are still working correctly, in particular the Watchdog Timer, if not disabled, resets the device upon an overflow. Interrupts and PEC transfers, however, cannot be processed. In case NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered. No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all P2 pins used to exit from power-down mode are at inactive level (if PWRDCFG = 1): the chip normally enters powerdown mode. Workaround: Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM. September 2003 181/184 2 - FUNCTIONAL PROBLEMS ST10F269 2.2 - MAC.9 - CoCMP Instruction Inverted Operands The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a 40-bit signed operand from th 40-bit accumulator content (acc - op2\op1), and updates the N, Z and C flags in the MSW register, leaving the accumulator unchanged. On the device the reverse operation (op2\op1 - acc) has been implemented in the Mac Unit. Therefore, the N and C flags are set according to the reverse opera- tion (Z flag is not affected). Workaround: Change interpretation of the N and C flags in the MSW register. Example: MOV R12, #07h MOV R13, #06h MOV R14, #0 CoLOAD R14, R12 ; Accumulator = 70000h CoCMP R14, R13 ; Compares 70000h to 60000h Here the content of MSW is 0500h, i.e. C = 1, Z = 0 and N = 1. To test if the Accumulator was greater than or equal the compared value, the "normal" test, according to the description in the ST10 Programming Manual, would be: JNB MSW.10, Greater ; If C flag cleared, then greater than or equal With the implementation, this test does not provide the expected result. To obtain the correct comparison, use instead: JB MSW.10, Greater ; C flag set: 60000h < 70000h (60000h-70000h implemented) ; i.e. the accumulator is greater than or equal compared value 2.3 - MAC.10 - E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled The Logical and the Arithmetic Right Shift instructions (CoSHR/CoASHR) are specififed not to be affected by the saturation mode (MS bit of the MCW register): the shift operation is always made on the 40 bits of the accumulator. The result shifted in the accumulator is never saturated. Only when the saturation mode is enabled, the evaluation of the E Flag (in the MSW register) is erroneous. Comment to the example: In this example below (Table 1), the E Flag is kept cleared however MAE is used: bit 0 of MAE has been shifted into bit 15 of MAH. The MAE part has been used and it contents significant bits but the E Flag has not been set. The content of the flags is given after the execution of the instruction. Table 1 : MAC.10 Example MS Bit is Set, Saturation Mode is Enabled Status of Flags After Instruction Execution Accumulator Value Code SL E SV C Z N Remark (Hexa.) MOV R5, #5555h -- ---- ---- - ----- - CoLOAD R5, R5 00 5555 5555 0 00000 Right NOP 00 5555 5555 0 00000 Right MOV MSW, #007Fh 7F 5555 5555 0 00000 Right NOP 7F 5555 5555 0 00000 Right CoSHR #1 3F AAAA AAAA 0 0* 0000 *E is wrong Workaround: If the MAE flag is used, the saturation mode must be disabled before running Logical and/or Arihmetic Right Shift instructions and re-enable just after. 182/184 ST10F269 3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION 2.4 - ST_PORT.3 - Bad Behavior of Hysteresis Function on Input Falling Edge In the following conditions, a slow falling edge on a ST10F269 input may generate multiple events : – A falling edge is occuring. – AND the falling edge has a transition time between Vih and Vil longer than the CPU clock period. Vih Input signal Vil (falling edge) “1” Internal “0” signal t1 t2 PROBLEM (t2 - t1) > 1/Fcpu Workaround: Add external hardware on the ST10 input in order to have a fast falling edge (lower than 1/Fcpu). History of Fixed Functional Problems of the ST10F269Zxxx-D Name of the Short Description Fixed in Step Modification ST_PORT.2 Wrong Port Direction after Return From Power Down Mode D Summary of Remaining Functional Problems Known on the ST10F269Zxxx-D Name Short Description PWRDN.1 Execution of PWRDN Instruction MAC.9 CoCMP Instruction Inverted Operands MAC.10 E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled ST_PORT.3 Bad Behavior of Hysteresis Function on Input Falling Edge 3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION Note on on-chip oscillator The XTAL2 output is not designed to provide a valid signal when XTAL1 is supplied by an external clock signal. It may happen, if the external clock signal is not perfectly symetrical and centered on V / 2, that DD XTAL2 signal is not equal to XTAL1. This is due to the design of the oscillator, which has a auto-adapta- tion gain control dedicated to external crystal. If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin disconnected to achieve the lowest consumption of the on-chip oscillator. 4 - ERRATA SHEET VERSION INFORMATION This document was released in September 2003. It reflects the current silicon status of the ST10F269Zxxx-D. 183/184 ST10F269 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. 2 2 Purchase of I C Components by STMicroelectronics conveys a license under the Philips I C Patent. Rights to use these components in an 2 2 I C system is granted provided that the system conforms to the I C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 184/184 F269-Q3.REF