PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank Flash memories PQFP52 (M) – Up to 2 Mbit of primary Flash memory (8 uniform sectors, 32K x8) – Up to 256 Kbit secondary Flash memory (4 uniform sectors) – Concurrent operation: read from one memory while erasing and writing the other ■ Up to 256 Kbit SRAM ■ 27 reconfigurable I/Oports PLCC52 (J) ■ Enhanced JTAG serial port ■ PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) – DPLD - user defined internal chip select TQFP64 (U) decoding ■ 27 individually configurable I/O port pins ■ Programmable power management They can be used for the following functions: ® ■ Packages are ECOPACK – MCU I/Os – PLD I/Os Table 1. Device summary – Latched MCU address output Reference Part number – Special function I/Os. – 16 of the I/O ports may be configured as PSD813F2 open-drain outputs. PSD813F4 ■ In-system programming (ISP) with JTAG PSD813F5 – Built-in JTAG compliant serial port allows PSD8XXFX PSD833F2 full-chip in-system programmability – Efficient manufacturing allow easy product PSD834F2 testing and programming PSD853F2 – Use low cost FlashLINK cable with PC PSD854F2 ■ Page register – Internal page register that can be used to expand the microcontroller address space by a factor of 256 May 2009 Doc ID 7833 Rev 7 1/128 www.st.com 1 Contents PSD8XXFX Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24 6 Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 Description of primary Flash memory and secondary Flash memory . . . 27 6.3 Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.1 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.2 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5 Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 Reading the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/128 Doc ID 7833 Rev 7 PSD8XXFX Contents 7.8 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.9 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.10 Erase timeout flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3 Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . 36 9 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.3 Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . 41 11 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.2 Memory select configuration for MCUs with separate program and data spaces 43 12.3 Configuration modes for MCUs with separate program and data spaces 44 12.3.1 Separate Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3.2 Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 14 PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.1 The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.2 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.3 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Doc ID 7833 Rev 7 3/128 Contents PSD8XXFX 14.4 Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.5 Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.6 Loading and reading the Output macrocells (OMC) . . . . . . . . . . . . . . . . . 54 14.7 The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.8 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.9 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1 PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.2 PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 60 15.3 Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.4 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15.5 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15.6 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.7 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.8 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.1 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.2 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16.3 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.4 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.5 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.6 Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.7 Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.8 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.9 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4/128 Doc ID 7833 Rev 7 PSD8XXFX Contents 16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.18 Input macro (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.19 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.20 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . 75 16.21 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.23 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.1 Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 80 17.2 For users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.3 Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.4 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.5 PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 17.6 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 17.7 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18 Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 85 18.1 Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.3 I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.4 Reset of Flash memory erase and program cycles (on the PSD834Fx) . 85 19 Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 87 19.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 19.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 21 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 22 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 23 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Doc ID 7833 Rev 7 5/128 Contents PSD8XXFX 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Appendix A PQFP52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Appendix B PLCC52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Appendix C TQFP64 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6/128 Doc ID 7833 Rev 7 PSD8XXFX List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. PLCC52 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. JTAG SIgnals on port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Methods for programming different functional blocks of the PSD. . . . . . . . . . . . . . . . . . . . 22 Table 7. I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Register address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Sector Protection/Security Bit definition – Flash Protection register. . . . . . . . . . . . . . . . . . 41 Table 13. Sector Protection/Security Bit definition – PSD/EE Protection register . . . . . . . . . . . . . . . 41 Table 14. VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 15. DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 16. Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 17. MCUs and their control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 18. 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 19. 80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 20. Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 21. Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 22. I/O port Latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 23. Port configuration registers (PCR)t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 24. Port Pin Direction Control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 25. Port Pin Direction Control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 26. Port Direction assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 27. Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 28. Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 29. Power-down mode’s effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 30. PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 31. Power Management mode registers PMMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 32. Power Management mode registers PMMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 33. APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 34. Status during Power-on reset, Warm reset and Power-down mode. . . . . . . . . . . . . . . . . . 86 Table 35. JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 36. JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 37. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 38. Example of PSD typical power calculation at V =5.0 V (Turbo mode on) . . . . . . . . . . . . 93 CC Table 39. Example of PSD typical power calculation at V = 5.0 V (Turbo mode off) . . . . . . . . . . . 94 CC Table 40. Operating conditions (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 41. Operating conditions (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 42. AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 43. AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 44. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 45. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 46. DC characteristics (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 47. DC Characteristics (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 48. CPLD combinatorial timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Doc ID 7833 Rev 7 7/128 List of tables PSD8XXFX Table 49. CPLD combinatorial timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices) . . . . . . . . . . . . . . . . . . . 101 Table 51. CPLD macrocell synchronous clock mode timing (3 V devices). . . . . . . . . . . . . . . . . . . . 102 Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices). . . . . . . . . . . . . . . . . . . 103 Table 53. CPLD macrocell Asynchronous clock mode timing (3 V devices) . . . . . . . . . . . . . . . . . . 104 Table 54. Input macrocell timing (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 55. input macrocell timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 56. READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 57. READ timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 58. WRITE timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 59. WRITE timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 60. Program, WRITE and Erase times (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 61. Program, WRITE and Erase times (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 62. Port A Peripheral Data mode READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 63. Port A Peripheral Data mode READ timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 64. Port A Peripheral Data mode WRITE timing (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . 112 Table 65. Port A Peripheral Data mode WRITE timing (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . 113 Table 66. Reset (RESET) timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 67. Reset (RESET) timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 68. ISC timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 69. ISC timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 70. Power-down timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 71. Power-down timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 72. PQFP52 - 52-pin plastic quad flat package mechanical dimensions . . . . . . . . . . . . . . . . 117 Table 73. PLCC52-52-lead plastic lead chip carrier mechanical dimensions. . . . . . . . . . . . . . . . . . 118 Table 74. TQFP64 - 64-lead thin quad flatpack, package mechanical data . . . . . . . . . . . . . . . . . . . 119 Table 75. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 76. PQFP52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 77. PLCC52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 78. TQFP64 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 79. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8/128 Doc ID 7833 Rev 7 PSD8XXFX List of figures List of figures Figure 1. PQFP52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. PLCC52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. TQFP64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 5. PSDsoft Express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6. Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7. Data Toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 8. Priority level of memory and I/O components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 9. 8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 10. 8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 11. Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 12. PLD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 13. DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 14. Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 15. CPLD Output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 16. Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 17. Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18. An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 19. An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 20. Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 21. Interfacing the PSD with the 80C251, with One READ input . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN inputs. . . . . . . . . . . . . . . . . . . . 64 Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 24. Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 25. General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 26. Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 27. Port A and port B structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 28. Port C structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 29. Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 30. Port D external Chip Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 31. APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 32. Enable Power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 33. Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 34. PLD ICC /frequency consumption (5 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 35. PLD ICC /frequency consumption (3 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 36. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 37. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 38. Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 39. Input to output disable / enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 40. Synchronous clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 41. Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 42. Asynchronous Clock mode Timing (product term clock). . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 43. Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 44. READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 45. WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 46. Peripheral I/O READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 47. Peripheral I/O WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 48. Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Doc ID 7833 Rev 7 9/128 List of figures PSD8XXFX Figure 49. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 50. PQFP52 - 52-pin plastic quad flat package mechanical drawing . . . . . . . . . . . . . . . . . . . 117 Figure 51. PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing . . . . . . . . . . . . 118 Figure 52. TQFP64 - 64-lead thin quad flatpack, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10/128 Doc ID 7833 Rev 7 PSD8XXFX Summary description 1 Summary description The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings in-system- programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. Table 2 summarizes all the devices. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD device includes a JTAG serial programming interface, to allow in-system programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds. The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as: ● First-time in-system programming (ISP) ● Complex address decoding ● Simultaneous read and write to the device. The JTAG Serial Interface block allows in-system programming (ISP), and eliminates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP. ST makes available a software development tool, PSDsoft™ Express, that generates ANSI- C compliant code for use with your target MCU. This code allows you to manipulate the non- volatile memory (NVM) within the PSD. Code examples are also provided for: ● Flash memory IAP via the UART of the host MCU ● Memory paging to execute code across several PSD memory pages ● Loading, reading, and manipulation of PSD macrocells by the MCU. Table 2. Product range Number of Primary Flash Secondary Serial ISP I/O Turbo macrocells (1) memory Flash memory Part number SRAM JTAG/ISC ports mode port (8 sectors) (4 sectors) Input Output PSD813F2 1 Mbit 256 Kbit 16 Kbit 27 24 16 yes yes PSD813F4 1 Mbit 256 Kbit none 27 24 16 yes yes PSD813F5 1 Mbit none none 27 24 16 yes yes PSD833F2 1 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes PSD834F2 2 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes Doc ID 7833 Rev 7 11/128 Summary description PSD8XXFX Table 2. Product range (continued) Number of Primary Flash Secondary Serial ISP I/O Turbo macrocells (1) memory Flash memory Part number SRAM JTAG/ISC ports mode port (8 sectors) (4 sectors) Input Output PSD853F2 1 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes PSD854F2 2 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management Unit (PMU), Automatic Power-down (APD) Figure 1. PQFP52 connections PD2 1 39 AD15 PD1 2 38 AD14 PD0 3 37 AD13 PC7 4 36 AD12 PC6 5 35 AD11 PC5 6 34 AD10 PC4 7 33 AD9 V 8 32 AD8 CC GND 9 31 V CC PC3 10 30 AD7 PC2 11 29 AD6 PC1 12 28 AD5 PC0 13 27 AD4 AI02858 12/128 Doc ID 7833 Rev 7 PA7 14 52 PB0 PB1 PA6 15 51 PA5 16 50 PB2 PB3 PA4 17 49 PB4 PA3 18 48 GND 19 47 PB5 GND PA2 20 46 PA1 21 45 PB6 PB7 PA0 22 44 CNTL1 AD0 23 43 AD1 24 42 CNTL2 RESET AD2 25 41 AD3 26 40 CNTLO 47 48 49 50 51 52 1 2 3 4 5 6 7 PSD8XXFX Summary description Figure 2. PLCC52 connections 8 PD2 46 AD15 9 PD1 45 AD14 10 PD0 44 AD13 11 PC7 43 AD12 12 PC6 42 AD11 13 PC5 41 AD10 14 PC4 40 AD9 15 V 39 AD8 CC 16 GND V 38 CC 17 PC3 37 AD7 18 PC2 36 AD6 19 PC1 35 AD5 20 PC0 34 AD4 AI02857 Doc ID 7833 Rev 7 13/128 21 PA7 PB0 22 PA6 PB1 23 PA5 PB2 24 PA4 PB3 25 PA3 PB4 26 GND PB5 27 PA2 GND 28 PA1 PB6 29 PA0 PB7 30 AD0 CNTL1 31 AD1 CNTL2 32 AD2 RESET 33 AD3 CNTL0 Summary description PSD8XXFX Figure 3. TQFP64 connections PD2 1 48 CNTL0 PD1 2 47 AD15 PD0 3 46 AD14 PC7 4 45 AD13 PC6 5 44 AD12 PC5 6 43 AD11 7 PC4 42 AD10 V 8 41 AD9 CC V 9 40 AD8 CC GND 10 39 V CC GND 11 38 V CC PC3 12 37 AD7 PC2 13 36 AD6 PC1 14 35 AD5 PC0 15 34 AD4 NC 16 33 AD3 AI09645b 14/128 Doc ID 7833 Rev 7 NC 17 64 NC NC NC 18 63 PA7 19 62 PB0 PB1 PA6 20 61 PA5 21 60 PB2 PA4 22 59 PB3 PB4 PA3 23 58 GND 24 57 PB5 GND GND 25 56 PA2 26 55 GND PA1 27 54 PB6 PB7 PA0 28 53 AD0 29 52 CNTL1 CNTL2 AD1 30 51 ND 31 50 RESET AD2 32 49 NC PSD8XXFX Pin description 2 Pin description (1) Table 3. PLCC52 pin description Pin name Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 ADIO0-7 30-37 I/O in page mode, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. ADIO8-15 39-46 I/O If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: WR – active low Write Strobe input. CNTL0 47 I R_W – active high READ/active low write input. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: RD – active low Read Strobe input. E – E clock input. DS – active low Data Strobe input. CNTL1 50 I PSEN – connect PSEN to this port when it is being used as an active low READ signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the READ signal. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. This port can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select CNTL2 49 I Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Resets I/O ports, PLD macrocells and some of the Configuration registers. Must be low Reset 48 I at Power-up. Doc ID 7833 Rev 7 15/128 Pin description PSD8XXFX (1) Table 3. PLCC52 pin description (continued) Pin name Pin Type Description These pins make up port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. PA0 29 CPLD macrocell (McellAB0-7) outputs. PA1 28 Inputs to the PLDs. PA2 27 Latched address outputs (see Table 7). PA3 25 I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA PA4 24 in burst mode. PA5 23 As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs. PA6 22 D0/A16-D3/A19 in M37702M2 mode. PA7 21 Peripheral I/O mode. Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However, PA4-PA7 can be configured as CMOS or Open Drain outputs. PB0 7 These pins make up port B. These port pins are configurable and can have the PB1 6 following functions: PB2 5 MCU I/O – write to or read from a standard output or input port. PB3 4 CPLD macrocell (McellAB0-7 or McellBC0-7) outputs. I/O PB4 3 Inputs to the PLDs. PB5 2 Latched address outputs (see Table 7). PB6 52 Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However, PB4-PB7 can be configured as CMOS or Open Drain outputs. PB7 51 PC0 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC0) output. PC0 20 I/O Input to the PLDs. (2) TMS input for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC1 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC1) output. PC1 19 I/O Input to the PLDs. (2) TCK input for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC2 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PC2 18 I/O CPLD macrocell (McellBC2) output. Input to the PLDs. This pin can be configured as a CMOS or Open Drain output. 16/128 Doc ID 7833 Rev 7 PSD8XXFX Pin description (1) Table 3. PLCC52 pin description (continued) Pin name Pin Type Description PC3 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC3) output. PC3 17 I/O Input to the PLDs. (2) TSTAT output for the JTAG Serial Interface. Ready/Busy output for parallel in-system programming (ISP). This pin can be configured as a CMOS or Open Drain output. PC4 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC4) output. PC4 14 I/O Input to the PLDs. (2) TERR output for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC5 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC5) output. PC5 13 I/O Input to the PLDs. (2) TDI input for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC6 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC6) output. PC6 12 I/O Input to the PLDs. (2) TDO output for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC7 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC7) output. PC7 11 I/O Input to the PLDs. DBE – active low Data Byte Enable input from 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 pin of port D. This port pin can be configured to have the following functions: ALE/AS input latches address output from the MCU. PD0 10 I/O MCU I/O – write or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). PD1 pin of port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. PD1 9 I/O CPLD output (External Chip Select). CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. Doc ID 7833 Rev 7 17/128 Pin description PSD8XXFX (1) Table 3. PLCC52 pin description (continued) Pin name Pin Type Description PD2 pin of port D. This port pin can be configured to have the following functions: MCU I/O - write to or read from a standard output or input port. Input to the PLDs. PD2 8 I/O CPLD output (External Chip Select). PSD Chip Select input (CSI). When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. V 15, 38 Supply voltage CC 1, 16, GND Ground pins 26 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 73 onwards, for pin numbers on other package types. 2. These functions can be multiplexed with other functions. 18/128 Doc ID 7833 Rev 7 PSD8XXFX Pin description Figure 4. PSD block diagram AI02861f Doc ID 7833 Rev 7 19/128 ADDRESS/DATA/CONTROL BUS PLD INPUT BUS 1 OR 2 MBIT PRIMARY PAGE FLASH MEMORY REGISTER EMBEDDED ALGORITHM 8 SECTORS 8 CNTL0, 256 KBIT SECONDARY SECTOR CNTL1, NON-VOLATILE MEMORY SELECTS PROG. CNTL2 (BOOT OR DATA) FLASH DECODE MCU BUS 4 SECTORS ( ) PLD DPLD INTRF. 73 SECTOR SELECTS 256 KBIT SRAM SRAM SELECT PROG. PA0 – PA7 PORT PERIP I/O MODE SELECTS PORT CSIOP A RUNTIME CONTROL AD0 – AD15 ADIO AND I/O REGISTERS PORT 3 EXT CS TO PORT D FLASH ISP CPLD 73 (CPLD) 16 OUTPUT MACROCELLS PROG. PORT PB0 – PB7 PORT A ,B & C PORT 24 INPUT MACROCELLS B PORT A ,B & C CLKIN PROG. PORT PC0 – PC7 GLOBAL MACROCELL FEEDBACK OR PORT INPUT PORT C CONFIG. & SECURITY CLKIN PROG. PORT PD0 – PD2 PLD, CONFIGURATION JTAG CLKIN PORT & FLASH MEMORY SERIAL (PD1) D LOADER CHANNEL PSD architectural overview PSD8XXFX 3 PSD architectural overview PSD devices contain several major functional blocks. Figure 4 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 3.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in Section 6.1: Memory blocks. The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable. The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The optional SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. 3.2 Page register The 8-bit Page register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP. 3.3 PLDs The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 4, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs. The CPLD has 16 Output macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD input bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features. 20/128 Doc ID 7833 Rev 7 PSD8XXFX PSD architectural overview 3.4 I/O ports The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on port C for in-system programming (ISP). Ports A and B can also be configured as a data port for a non-multiplexed bus. 3.5 MCU bus interface PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU control signals, which are also used as inputs to the PLDs. For examples, please see Section 15.4: MCU bus interface examples. Table 4. PLD I/O Name Inputs Outputs Product terms Decode PLD (DPLD) 73 17 42 Complex PLD (CPLD) 73 19 140 3.6 JTAG port In-system programming (ISP) can be performed through the JTAG signals on port C. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on port C. Table 5 indicates the JTAG pin assignments. 3.7 In-system programming (ISP) Using the JTAG signals on port C, the entire PSD device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD configuration blocks can be programmed through the JTAG port or a device programmer. Table 6 indicates which programming methods can program different functional blocks of the PSD. 3.8 Power management unit (PMU) The power management unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD unit has a Power-down mode that helps reduce power consumption. Doc ID 7833 Rev 7 21/128 PSD architectural overview PSD8XXFX The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see Section 17: Power management for more details. Table 5. JTAG SIgnals on port C Port C pins JTAG signal PC0 TMS PC1 TCK PC3 TSTAT PC4 TERR PC5 TDI PC6 TDO Table 6. Methods for programming different functional blocks of the PSD JTAG Device Functional block IAP programming programmer Primary Flash memory Yes Yes Yes Secondary Flash memory Yes Yes Yes PLD array (DPLD and CPLD) Yes Yes No PSD configuration Yes Yes No 22/128 Doc ID 7833 Rev 7 PSD8XXFX Development system 4 Development system The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Figure 5. PSDsoft Express development tool PSDabel PLD DESCRIPTION MODIFY ABEL TEMPLATE FILE OR GENERATE NEW FILE PSD Configuration PSD TOOLS CONFIGURE MCU BUS GENERATE C CODE INTERFACE AND OTHER SPECIFIC TO PSD PSD ATTRIBUTES FUNCTIONS PSD Fitter USER'S CHOICE OF LOGIC SYNTHESIS FIRMWARE MICROCONTROLLER AND FITTING HEX OR S-RECORD COMPILER/LINKER ADDRESS TRANSLATION FORMAT AND MEMORY MAPPING *.OBJ FILE PSD Simulator PSD Programmer *.OBJ AND *.SVF FILES AVAILABLE FOR 3rd PARTY PSDsilos III PSDPro, or PROGRAMMERS DEVICE SIMULATION FlashLINK (JTAG) (CONVENTIONAL or (OPTIONAL) JTAG-ISC) AI04918 Doc ID 7833 Rev 7 23/128 PSD register description and address offset PSD8XXFX 5 PSD register description and address offset Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD registers. Table 8 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. (1)(2) Table 7. I/O port latched address output assignments Port A Port B MCU Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4) 8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A Address a15- 80C251 (page mode) N/A N/A Address a11-a8 a12 All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4 1. See Section 16: I/O ports, on how to enable the Latched Address Output function. 2. N/A = Not Applicable Table 8. Register address offset Register Other Port A Port B Port C Port D Description (1) name Reads port pin as input, MCU I/O input Data In 00 01 10 11 mode Selects mode between MCU I/O or Control 02 03 Address Out Stores data for output to port pins, MCU Data Out 04 05 12 13 I/O output mode Direction 06 07 14 15 Configures port pin as input or output Configures port pins as either CMOS or Drive Select 08 09 16 17 Open Drain on some pins, while selecting high slew rate on other pins. Input 0A 0B 18 Reads input macrocells macrocell Reads the status of the output enable to Enable Out 0C 0D 1A 1B the I/O port driver Output READ – reads output of macrocells AB macrocells 20 20 WRITE – loads macrocell flip-flops AB Output READ – reads output of macrocells BC macrocells 21 21 WRITE – loads macrocell flip-flops BC 24/128 Doc ID 7833 Rev 7 PSD8XXFX PSD register description and address offset Table 8. Register address offset (continued) Register Other Port A Port B Port C Port D Description (1) name Mask Blocks writing to the Output macrocells macrocells 22 22 AB AB Mask Blocks writing to the Output macrocells macrocells 23 23 BC BC Primary Flash Read only – Primary Flash Sector C0 Protection Protection Secondary Read only – PSD Security and Secondary Flash memory C2 Flash memory Sector Protection Protection JTAG Enable C7 Enables JTAG port PMMR0 B0 Power Management register 0 PMMR2 B4 Power Management register 2 Page E0 Page register Places PSD memory areas in program VM E2 and/or data space on an individual basis. 1. Other registers that are not part of the I/O ports. Doc ID 7833 Rev 7 25/128 Detailed operation PSD8XXFX 6 Detailed operation As shown in Figure 4, the PSD consists of six major types of functional blocks: ● Memory blocks ● PLD blocks ● MCU bus interface ● I/O ports ● Power management unit (PMU) ● JTAG interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 6.1 Memory blocks The PSD has the following memory blocks: ● Primary Flash memory ● Optional Secondary Flash memory ● Optional SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft Express. Table 9. Memory block size and organization Secondary Flash Primary Flash memory SRAM memory Sector number Sector Sector SRAM Sector size Sector size SRAM size select select select (Kbytes) (Kbytes) (Kbytes) signal signal signal 0 32 FS0 16 CSBOOT0 256 RS0 1 32 FS1 16 CSBOOT1 2 32 FS2 16 CSBOOT2 3 32 FS3 16 CSBOOT3 432 FS4 532 FS5 632 FS6 732 FS7 Total 512 8 sectors 64 4 sectors 256 26/128 Doc ID 7833 Rev 7 PSD8XXFX Detailed operation 6.2 Description of primary Flash memory and secondary Flash memory The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a program or erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration. 6.3 Memory block select signals The DPLD generates the Select signals for all the internal memory blocks (see Section 14: PLDS). Each of the eight sectors of the primary Flash memory has a Select signal (FS0- FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using a MCU with separate program and data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other. 6.3.1 Ready/Busy (PC3) This signal can be used to output the Ready/Busy status of the PSD. The output on Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress. 6.3.2 Memory operation The primary Flash memory and secondary Flash memory are addressed through the MCU bus interface. The MCU can access these memories in one of two ways: ● The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles. ● The MCU can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 10. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). Doc ID 7833 Rev 7 27/128 Detailed operation PSD8XXFX (1)(2)(3) Table 10. Instructions FS0-FS7 or CSBOOT0- Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 CSBOOT3 (4) “READ” (5) READ 1 RD @ RA Read Main AAh@ 55h@ 90h@ Read identifier 1 (6) Flash ID X555h XAAAh X555h (A6,A1,A0 = 0,0,1) Read Sector AAh@ 55h@ 90h@ Read identifier (6)(7) Protection 1 X555h XAAAh X555h (A6,A1,A0 = 0,1,0) (8) Program a AAh@ 55h@ A0h@ 1 PD@ PA (8) Flash Byte X555h XAAAh X555h 7 Flash Sector AAh@ 55h@ 80h@ 55h@ 30h@ 30h @ 1 AAh@ X555h (9)(8) Erase X555h XAAAh X555h XAAAh SA next SA Flash Bulk AAh@ 55h@ 80h@ 55h@ 10h@ 1 AAh@ X555h (8) Erase X555h XAAAh X555h XAAAh X555h Suspend B0h@ Sector 1 XXXXh (10) Erase Resume 30h@ Sector 1 XXXXh (11) Erase F0h@ (6) Reset 1 XXXXh AAh@ 55h@ 20h@ Unlock Bypass 1 X555h XAAAh X555h Unlock Bypass A0h@ 1 PD@ PA (12) Program XXXXh Unlock Bypass 90h@ 00h@ 1 (13) Reset XXXXh XXXXh 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label 2. All values are in hexadecimal: X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (high). 3. Only address bits A11-A0 are used in instruction decoding. 4. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express. 5. No Unlock or instruction cycles are required when the device is in the READ mode 6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error flag bit (DQ5/DQ13) goes high. 7. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 28/128 Doc ID 7833 Rev 7 PSD8XXFX Detailed operation 8. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 9. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs. 10. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 11. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. Doc ID 7833 Rev 7 29/128 Instructions PSD8XXFX 7 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the timeout period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or timeout between two consecutive bytes while addressing Flash memory resets the device logic into READ mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 10: Flash memory: ● Erase memory by chip or sector ● Suspend or resume sector erase ● Program a Byte ● Reset to READ mode ● Read primary Flash Identifier value ● Read Sector Protection Status ● Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2) These instructions are detailed in Table 10. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is high, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0-CSBOOT3) is high. 7.1 Power-up mode The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR, CNTL0) high, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when V is below V . CC LKO 7.2 READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a program or erase 30/128 Doc ID 7833 Rev 7 PSD8XXFX Instructions cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. 7.3 Read memory contents Primary Flash memory and secondary Flash memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see Table 10). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. 7.4 Read Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 10). During the READ operation, address bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be high. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. 7.5 Read Memory Sector Protection status The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 10). During the READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See Section 10.1: Flash Memory Sector Protect for register definitions. 7.6 Reading the Erase/Program Status bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 11. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See Section 8: Programming Flash memory for details. Doc ID 7833 Rev 7 31/128 Instructions PSD8XXFX (1)(2)(3) Table 11. Status bits FS0- Functional FS7/CSBOOT0- DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 block CSBOOT3 Data Toggle Error Erase Flash memory V X XX X IH Polling flag flag timeout 1. X = Not guaranteed value, can be read either '1' or ’0.’ 2. DQ7-DQ0 represent the data bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active high. 7.7 Data Polling flag (DQ7) When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling flag bit (DQ7, in a READ operation). ● Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. ● During an Erase cycle, the Data Polling flag bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). ● If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. ● If all the Flash memory sectors to be erased are protected, the Data Polling flag bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed. 7.8 Toggle flag (DQ6) The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data read on the data bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. ● The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). ● If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. ● If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte. 32/128 Doc ID 7833 Rev 7 PSD8XXFX Instructions 7.9 Error flag (DQ5) During a normal program or erase cycle, the Error flag bit (DQ5) is to ’0.’ This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, ’0,’ to the erased state, '1,' which is not valid. The Error flag bit (DQ5) may also indicate a timeout condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error flag bit (DQ5) is reset after a Reset Flash instruction. 7.10 Erase timeout flag (DQ3) The Erase timeout flag bit (DQ3) reflects the timeout period allowed between two consecutive Sector Erase instructions. The Erase timeout flag bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase timeout flag bit (DQ3) is set to '1.' Doc ID 7833 Rev 7 33/128 Programming Flash memory PSD8XXFX 8 Programming Flash memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-by-byte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 10). Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3). 8.1 Data Polling Polling on the Data Polling flag bit (DQ7) is a method of checking whether a program or erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling flag bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling flag bit (DQ7) and monitoring the Error flag bit (DQ5). When the Data Polling flag bit (DQ7) matches b7 of the original data, and the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU should test the Data Polling flag bit (DQ7) again since the Data Polling flag bit (DQ7) may have changed simultaneously with the Error flag bit (DQ5, see Figure 6). The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling flag bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error flag bit (DQ5) indicates a timeout condition on the Erase cycle; a 0 indicates no error. The MCU can read any location within the sector being erased to get the Data Polling flag bit (DQ7) and the Error flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms. 34/128 Doc ID 7833 Rev 7 PSD8XXFX Programming Flash memory Figure 6. Data Polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL PASS AI01369B 8.2 Data Toggle Checking the Toggle flag bit (DQ6) is a method of determining whether a program or erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle flag bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle flag bit (DQ6) and monitoring the Error flag bit (DQ5). When the Toggle flag bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU should test the Toggle flag bit (DQ6) again, since the Toggle flag bit (DQ6) may have changed simultaneously with the Error flag bit (DQ5, see Figure 7). The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle flag bit (DQ6) toggles until the Erase cycle is complete. A '1' on the Error flag bit (DQ5) indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read Doc ID 7833 Rev 7 35/128 Programming Flash memory PSD8XXFX any location within the sector being erased to get the Toggle flag bit (DQ6) and the Error flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. 8.3 Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 10). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode. 36/128 Doc ID 7833 Rev 7 PSD8XXFX Programming Flash memory Figure 7. Data Toggle flowchart START READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 DQ6 NO = TOGGLE YES FAIL PASS AI01370B Doc ID 7833 Rev 7 37/128 Erasing Flash memory PSD8XXFX 9 Erasing Flash memory 9.1 Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 10. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error flag bit (DQ5), the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in Section 8: Programming Flash memory. The Error flag bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. 9.2 Flash Sector Erase The Sector Erase instruction uses six WRITE operations, as described in Table 10. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the timeout period of about 100µs. The input of a new Sector Erase code restarts the timeout period. The status of the internal timer can be monitored through the level of the Erase timeout flag bit (DQ3). If the Erase timeout flag bit (DQ3) is ’0,’ the Sector Erase instruction has been received and the timeout period is counting. If the Erase timeout flag bit (DQ3) is '1,' the timeout period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase timeout, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing (byte = FFh). During a Sector Erase, the memory status may be checked by reading the Error flag bit (DQ5), the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in Section 8: Programming Flash memory. During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. 9.3 Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 10). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode. 38/128 Doc ID 7833 Rev 7 PSD8XXFX Erasing Flash memory A Suspend Sector Erase instruction executed during an Erase timeout period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle flag bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle flag bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ mode. If an Suspend Sector Erase instruction was executed, the following rules apply: ● Attempting to read from a Flash memory sector that was being erased outputs invalid data. ● Reading from a Flash sector that was not being erased is valid. ● The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). ● If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. 9.4 Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 10.) Doc ID 7833 Rev 7 39/128 Specific features PSD8XXFX 10 Specific features 10.1 Flash Memory Sector Protect Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all program or erase cycles. This mode can be activated through the JTAG port or a device programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG port or a device programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG port or a device programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and PSD/EE protection registers (in the CSIOP block). See Table 12 and Table 13. 10.2 Reset Flash The Reset Flash instruction consists of one WRITE cycle (see Table 10). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: ● Reading the Flash Protection Status or Flash ID ● An Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1') during a Flash memory program or erase cycle. On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into normal READ mode. It may take the Flash memory up to a few milliseconds to complete the Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within a few milliseconds. On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash memory back into normal READ mode. If an Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1') the Flash memory is put back into normal READ mode within 25μs of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within 25μs. 40/128 Doc ID 7833 Rev 7 PSD8XXFX Specific features 10.3 Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a program or erase cycle, the Flash memory takes up to 25μs to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described in Section 18: Reset timing and device status at reset) be at least 25 µs so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete. (1) Table 12. Sector Protection/Security Bit definition – Flash Protection register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1. Bit Definitions: Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write protected. (1) Table 13. Sector Protection/Security Bit definition – PSD/EE Protection register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Security_B not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot it 1. Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. Doc ID 7833 Rev 7 41/128 SRAM PSD8XXFX 11 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. 42/128 Doc ID 7833 Rev 7 PSD8XXFX Sector Select and SRAM Select 12 Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. 12.1 Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. 12.2 Memory select configuration for MCUs with separate program and data spaces The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for program memory (selected using Program Select Enable (PSEN, CNTL2)) and data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the data space at Boot-up, and secondary Flash memory in the program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM register by using Doc ID 7833 Rev 7 43/128 Sector Select and SRAM Select PSD8XXFX PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 14 describes the VM register. Figure 8. Priority level of memory and I/O components Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority AI02867D 12.3 Configuration modes for MCUs with separate program and data spaces 12.3.1 Separate Space modes Program space is separated from data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9). 12.3.2 Combined Space modes The program and data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1' (see Figure 10). Figure 9. 8031 memory modules – separate space Primary Secondary SRAM DPLD RS0 Flash Flash Memory Memory CSBOOT0-3 FS0-FS7 CS CS CS OE OE OE PSEN RD AI02869C 44/128 Doc ID 7833 Rev 7 PSD8XXFX Sector Select and SRAM Select Figure 10. 8031 memory modules – combined space DPLD Primary Secondary SRAM RS0 Flash Flash Memory Memory RD CSBOOT0-3 FS0-FS7 CS CS CS OE OE OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 RD VM REG BIT 2 VM REG BIT 0 AI02870C Table 14. VM register Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 Bit 0 Bit 6 Bit 5 Primary econdary Primary Secondary PIO_EN SRAM_Code FL_Data EE_Data FL_Code EE_Code 0 = PSEN 0 = RD can’t 0 = PSEN can’t 0 = PSEN 0 = RD cannot 0 = disable not not access access cannot cannot access access used used PIO mode secondary Flash secondary Flash access Flash memory Flash memory memory SRAM memory 1 = PSEN 1 = RD 1 = RD access 1 = PSEN access 1 = PSEN 1= enable not not access access Flash secondary Flash secondary Flash access used used PIO mode Flash memory memory SRAM memory memory Doc ID 7833 Rev 7 45/128 Page register PSD8XXFX 13 Page register The 8-bit Page register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Note AN1154. Figure 11 shows the Page register. The eight flip-flops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page register. The Page register can be accessed at address location CSIOP + E0h. Figure 11. Page register RESET PGR0 INTERNAL D0 Q0 SELECTS PGR1 D1 Q1 AND LOGIC PGR2 D0-D7 D2 Q2 DPLD PGR3 D3 Q3 AND PGR4 CPLD D4 Q4 PGR5 D5 Q5 PGR6 D6 Q6 PGR7 D7 Q7 R/W PAGE PLD REGISTER AI02871B 46/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS 14 PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in Section 14.2: Decode PLD (DPLD), and Section 14.3: Complex PLD (CPLD). Figure 12 shows the configuration of the PLDs. The DPLD performs address decoding for Select signals for internal components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDabel. An input bus consisting of 73 signals is connected to the PLDs. The signals are shown in Table 15. 14.1 The Turbo Bit in PSD The PLDs in the PSD can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See Section 17: Power management on how to set the Turbo Bit. Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Table 15. DPLD and CPLD inputs Number of Input source Input name signals (1) MCU address bus A15-A0 16 MCU control signals CNTL2-CNTL0 3 Reset RST 1 Power-down PDN 1 Port A input macrocells PA7-PA0 8 Port B input macrocells PB7-PB0 8 Port C input macrocells PC7-PC0 8 Port D inputs PD2-PD0 3 Doc ID 7833 Rev 7 47/128 PLDS PSD8XXFX Table 15. DPLD and CPLD inputs (continued) Number of Input source Input name signals Page register PGR7-PGR0 8 Macrocell AB feedback MCELLAB.FB7-FB0 8 Macrocell BC feedback MCELLBC.FB7-FB0 8 Secondary Flash memory Program Status Ready/Busy 1 Bit 1. The address inputs are A19-A4 in 80C51XA mode. 48/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS Figure 12. PLD diagram Doc ID 7833 Rev 7 49/128 8 PAGE DATA REGISTER BUS 8 DECODE PLD PRIMARY FLASH MEMORY SELECTS 73 4 SECONDARY NON-VOLATILE MEMORY SELECTS 1 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL SELECTS 1 JTAG SELECT OUTPUT MACROCELL FEEDBACK DIRECT MACROCELL ACCESS FROM MCU DATA BUS 16 CPLD MCELLAB 16 OUTPUT TO PORT A OR B MACROCELL 8 MACROCELL PT ALLOC. ALLOC. 73 MCELLBC TO PORT B OR C 8 24 INPUT MACROCELL (PORT A,B,C) 3 EXTERNAL CHIP SELECTS TO PORT D DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL & INPUT PORTS 3 PORT D INPUTS AI02872C PLD INPUT BUS I/O PORTS PLDS PSD8XXFX 14.2 Decode PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) ● 1 internal SRAM Select (RS0) signal (two product terms) ● 1 internal CSIOP Select (PSD Configuration register) signal ● 1 JTAG Select signal (enables JTAG on port C) ● 2 internal Peripheral Select signals (Peripheral I/O mode). Figure 13. DPLD logic array CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT 3 3 (INPUTS) 3 FS0 I/O PORTS (PORT A,B,C) (24) 3 FS1 (8) MCELLAB.FB [7:0] (FEEDBACKS) 3 FS2 (8) MCELLBC.FB [7:0] (FEEDBACKS) 3 FS3 8 PRIMARY FLASH (8) PGR0 -PGR7 MEMORY SECTOR SELECTS 3 FS4 (16) [ ] A 15:0 * 3 FS5 (3) PD[2:0] (ALE,CLKIN,CSI) 3 FS6 (1) PDN (APD OUTPUT) 3 FS7 [ ] ( (3) CNTRL 2:0 READ/WRITE CONTROL SIGNALS) RESET (1) RS0 2 SRAM SELECT RD_BSY (1) 1 CSIOP I/O DECODER SELECT PSEL0 1 PERIPHERAL I/O MODE SELECT 1 PSEL1 1 JTAGSEL AI02873D 50/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS 14.3 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to port D. Although External Chip Select (ECS0-ECS2) can be produced by any Output macrocell (OMC), these three External Chip Select (ECS0-ECS2) on port D do not consume any Output macrocells (OMC). As shown in Figure 12, the CPLD has the following blocks: ● 24 input macrocells (IMC) ● 16 Output macrocells (OMC) ● Macrocell Allocator ● Product Term Allocator ● AND Array capable of generating up to 137 product terms ● Four I/O ports. Each of the blocks are described in the sections that follow. The input macrocells (IMC) and Output macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output macrocells (OMC) or read data from both the input and Output macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. Doc ID 7833 Rev 7 51/128 PLDS PSD8XXFX Figure 14. Macrocell and I/O port 52/128 Doc ID 7833 Rev 7 PRODUCT TERMS MCU ADDRESS / DATA BUS FROM OTHER MACROCELLS TO OTHER I/O PORTS CPLD MACROCELLS I/O PORTS DATA LOAD LATCHED PT PRESET CONTROL MCU DATA IN ADDRESS OUT PRODUCT TERM ALLOCATOR I/O PIN DATA MCU LOAD D Q MUX WR UP TO 10 PRODUCT TERMS MACROCELL CPLD OUTPUT OUT TO MCU POLARITY SELECT PR DI LD SELECT D/T Q PT CPLD PDR CLOCK D/T/JK FF INPUT COMB. OUTPUT SELECT /REG GLOBAL SELECT CLOCK MACROCELL CK TO I/O PORT CL CLOCK ALLOC. D Q SELECT DIR WR REG. PT CLEAR ( ) PT OUTPUT ENABLE OE MACROCELL FEEDBACK INPUT MACROCELLS I/O PORT INPUT Q D PT INPUT LATCH GATE/CLOCK QD ALE/AS G AI02874 PLD INPUT BUS PLD INPUT BUS AND ARRAY MUX MUX MUX MUX PSD8XXFX PLDS 14.4 Output macrocell (OMC) Eight of the Output macrocells (OMC) are connected to ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDabel, the macrocell Allocator block assigns it to either port A or B. The same is true for a McellBC output on port B or C. Table 16 shows the macrocells and port assignment. The Output macrocell (OMC) architecture is shown in Figure 15. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDabel program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active high inputs. Each clear input can use up to two product terms. Table 16. Output macrocell port and data bit assignments Maximum Output Port Native product Data bit for loading borrowed product terms or reading macrocell assignment terms McellAB0 Port A0, B0 3 6 D0 McellAB1 Port A1, B1 3 6 D1 McellAB2 Port A2, B2 3 6 D2 McellAB3 Port A3, B3 3 6 D3 McellAB4 Port A4, B4 3 6 D4 McellAB5 Port A5, B5 3 6 D5 McellAB6 Port A6, B6 3 6 D6 McellAB7 Port A7, B7 3 6 D7 McellBC0 Port B0, C0 4 5 D0 McellBC1 Port B1, C1 4 5 D1 McellBC2 Port B2, C2 4 5 D2 McellBC3 Port B3, C3 4 5 D3 McellBC4 Port B4, C4 4 6 D4 McellBC5 Port B5, C5 4 6 D5 McellBC6 Port B6, C6 4 6 D6 McellBC7 Port B7, C7 4 6 D7 Doc ID 7833 Rev 7 53/128 PLDS PSD8XXFX 14.5 Product Term Allocator The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: ● McellAB0-McellAB7 all have three native product terms and may borrow up to six more ● McellBC0-McellBC3 all have four native product terms and may borrow up to five more ● McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms already in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then “external” product terms are required, which consume other Output macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. 14.6 Loading and reading the Output macrocells (OMC) The Output macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see Section 16: I/O ports). The flip-flops in each of the 16 Output macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the Output macrocells (OMC) on the trailing edge of Write Strobe (WR, CNTL0) (edge loading) or during the time that Write Strobe (WR, CNTL0) is active (level loading). The method of loading is specified in PSDsoft Express Configuration. 14.7 The OMC Mask register There is one Mask register for each of the two groups of eight Output macrocells (OMC). The Mask registers can be used to block the loading of data to individual Output macrocells (OMC). The default value for the Mask registers is 00h, which allows loading of the Output macrocells (OMC). When a given bit in a Mask register is set to a 1, the MCU is blocked from writing to the associated Output macrocells (OMC). For example, suppose McellAB0- McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask register for McellAB (Mask macrocell AB) with the value 0Fh. 14.8 The Output Enable of the OMC The Output macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. 54/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS If the Output macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Figure 15. CPLD Output macrocell Doc ID 7833 Rev 7 55/128 MASK REG. MACROCELL CS INTERNAL DATA BUS D[7:0] RD WR PT DIRECTION ALLOCATOR REGISTER ( ) ENABLE .OE ( ) PRESET .PR COMB/REG SELECT PT PT DIN PR MUX I/O PIN MACROCELL LD Q PT ALLOCATOR POLARITY IN SELECT PORT DRIVER CLR ( ) CLEAR .RE PROGRAMMABLE ( ) FF D/T/JK /SR PT CLK MUX CLKIN ( ) FEEDBACK .FB PORT INPUT INPUT MACROCELL AI02875B PLD INPUT BUS AND ARRAY PLDS PSD8XXFX 14.9 Input macrocells (IMC) The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The architecture of the input macrocells (IMC) is shown in Figure 16. The input macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the PLD input bus. The outputs of the input macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four input macrocells (IMC). port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the input macrocells (IMC) are specified by equations written in PSDabel (see Application Note AN1171). outputs of the input macrocells (IMC) can be read by the MCU via the IMC buffer (see Section 16: I/O ports). Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 17 shows a typical configuration where the Master MCU writes to the port A Data Out register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output enable product term. The Slave can also write to the port A input macrocells (IMC) and the Master can then read the input macrocells (IMC) directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and Slave_CS. 56/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS Figure 16. Input macrocell Doc ID 7833 Rev 7 57/128 INTERNAL DATA BUS [ ] D 7:0 _ INPUT MACROCELL RD DIRECTION REGISTER ( ) ENABLE .OE OUTPUT PT MACROCELLS BC AND MACROCELL AB I/O PIN PT PORT DRIVER MUX Q D PT MUX ALE/AS D FF FEEDBACK D Q G LATCH INPUT MACROCELL AI02876B PLD INPUT BUS AND ARRAY PLDS PSD8XXFX Figure 17. Handshaking communication using input macrocells 58/128 Doc ID 7833 Rev 7 PSD SLAVE–CS RD WR SLAVE–READ PORT A DATA OUT SLAVE REGISTER MCU [ ] D 7:0 CPLD MCU-RD DQ PORT A MCU-WR MCU-WR MASTER MCU SLAVE–WR [ ] D 7:0 PORT A INPUT MACROCELL QD MCU-RD AI02877C PSD8XXFX MCU bus interface 15 MCU bus interface The “no-glue logic” MCU bus interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 17. The interface type is specified using the PSDsoft Express Configuration. Table 17. MCUs and their control signals Data bus (1) MCU CNTL0 CNTL1 CNTL2 PC7 PD0 ADIO0 PA3-PA0 PA7-PA3 width (2) (2) (2) 8031 8 WR RD PSEN ALE A0 (2) (2) 80C51XA 8 WR RD PSEN ALE A4 A3-A0 (2) (2) (2) (2) 80C251 8 WR PSEN ALE A0 (2) (2) (2) 80C251 8 WR RD PSEN ALE A0 (2) (2) (2) (2) 80198 8 WR RD ALE A0 (2) (2) (2) (2) 68HC11 8 R/W E AS A0 (2) (2) (2) 68HC912 8 R/W E DBE AS A0 (2) (2) (2) Z80 8 WR RD A0 D3-D0 D7-D4 (2) (2) (2) (2) Z8 8 R/W DS AS A0 (2) (2) (2) (2) 68330 8 R/W DS AS A0 (2) (2) M37702M2 8 R/W E ALE A0 D3-D0 D7-D4 1. ALE/AS input is optional for MCUs with a non-multiplexed bus 2. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O functions. Doc ID 7833 Rev 7 59/128 MCU bus interface PSD8XXFX 15.1 PSD interface to a multiplexed 8-bit bus Figure 18 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to port A or B. The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active. Should the system address bus exceed sixteen bits, ports A, B, C, or D may be used as additional address inputs. Figure 18. An example of a typical 8-bit multiplexed bus interface MCU PSD [ ] AD 7:0 [ ] A 7:0 PORT A (OPTIONAL) ADIO PORT A[15:8] [ ] A 15:8 PORT B (OPTIONAL) WR ( ) WR CNTRL0 RD ( ) RD CNTRL1 ( ) BHE BHE CNTRL2 PORT C RST ALE ( ) ALE PD0 PORT D RESET AI02878C 15.2 PSD interface to a non-multiplexed 8-bit bus Figure 19 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO port, and the data bus is connected to port A. port A is in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bits, ports B, C, or D may be used for additional address inputs. 15.3 Data Byte Enable reference MCUs have different data byte orientations. Table 18 shows how the PSD interprets byte/word operations in different bus WRITE configurations. Even-byte refers to locations with address A0 equal to '0' and odd byte as locations with A0 equal to ’1.’ 60/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.4 MCU bus interface examples Figure 20, Figure 21, Figure 22, Figure 23, and Figure 24 show examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the PSDsoft Express Configuration. Table 18. 8-bit data bus BHE A0 D7-D0 X 0 Even byte X 1 Odd byte Figure 19. An example of a typical 8-bit non-multiplexed bus interface PSD MCU D[7:0] D[7:0] PORT A ADIO PORT [ ] A 15:0 A[23:16] PORT B (OPTIONAL) ( ) WR WR CNTRL0 RD ( ) RD CNTRL1 BHE BHE (CNTRL2) PORT C RST ALE ( ) ALE PD0 PORT D RESET AI02879C Doc ID 7833 Rev 7 61/128 MCU bus interface PSD8XXFX 15.5 80C31 Figure 20 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O ports blocks. Address Strobe (ALE/AS, PD0) latches the address. Figure 20. Interfacing the PSD with an 80C31 AD7-AD0 AD[7:0] 80C31 PSD AD0 30 29 ADIO0 PA0 31 39 AD0 AD1 31 28 EA/VP P0.0 ADIO1 PA1 38 AD1 AD2 32 27 19 P0.1 ADIO2 PA2 X1 37 AD3 33 25 AD2 P0.2 ADIO3 PA3 34 36 AD3 AD4 24 P0.3 ADIO4 PA4 18 35 AD4 AD5 35 23 X2 P0.4 ADIO5 PA5 34 AD5 AD6 36 22 P0.5 ADIO6 PA6 33 AD6 9 AD7 37 21 P0.6 ADIO7 PA7 RESET RESET 32 AD7 P0.7 12 INT0 21 A8 39 13 7 P2.0 ADIO8 PB0 INT1 22 A9 40 6 14 P2.1 ADIO9 PB1 T0 41 23 A10 5 15 P2.2 ADIO10 PB2 T1 24 A11 42 ADIO11 4 P2.3 PB3 25 A12 43 3 P2.4 ADIO12 1 PB4 26 A13 44 2 P1.0 P2.5 ADIO13 2 PB5 27 A14 45 52 P1.1 P2.6 ADIO14 PB6 3 28 A15 46 P1.2 P2.7 51 ADIO15 PB7 4 P1.3 17 RD 5 RD P1.4 6 16 WR 47 20 PC0 P1.5 WR CNTL0(WR) 19 7 29 PSEN 50 PC1 P1.6 PSEN CNTL1(RD) 18 8 PC2 P1.7 30 ALE 17 ALE/P 49 PC3 11 CNTL2(PSEN) 14 TXD PC4 13 10 10 PC5 RXD PD0-ALE 12 9 PC6 PD1 11 PC7 8 PD2 RESET 48 RESET RESET AI02880C 62/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.6 80C251 The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 19. The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure 20. The second and third configurations have the same bus connection as shown in Figure 21. There is only one Read Strobe (PSEN) connected to CNTL1 on the PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth configuration is shown in Figure 22. Read Strobe (RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to CNTL2. The 80C251 has two major operating modes: Page mode and Non-page mode. In Non- page mode, the data is multiplexed with the lower address byte, and Address Strobe (ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0) is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In Page mode, the PSD bus timing is identical to Non-Page mode except the address hold time and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0) valid to data in valid. Figure 21. Interfacing the PSD with the 80C251, with One READ input PSD 80C251SB 43 A0 A0 30 2 P0.0 ADIO0 1 P1.0 42 A1 A1 31 29 A16 3 P0.1 ADIO1 PA0 P1.1 41 A2 A2 32 28 4 P0.2 ADIO2 PA1 P1.2 40 A3 1 A3 33 27 5 A17 P0.3 ADIO3 PA2 P1.3 39 A4 A4 34 25 6 P0.4 ADIO4 PA3 P1.4 38 A5 A5 35 24 7 P0.5 ADIO5 PA4 P1.5 37 A6 A6 36 23 8 P0.6 ADIO6 PA5 P1.6 9 36 A7 A7 37 22 ADIO7 P1.7 P0.7 PA6 21 PA7 24 AD8 21 P2.0 X1 25 AD9 AD8 39 P2.1 ADIO8 7 26 AD10 AD9 40 20 P2.2 ADIO9 PB0 X2 6 27 AD11 AD10 41 P2.3 ADIO10 PB1 5 28 AD12 11 AD11 42 PB2 P2.4 P3.0/RXD ADIO11 4 13 29 AD13 AD12 43 PB3 P2.5 ADIO12 P3.1/TXD 3 30 AD14 AD13 44 14 PB4 P2.6 ADIO13 P3.2/INT0 2 31 AD15 AD14 45 15 PB5 P2.7 ADIO14 52 P3.3/INT1 AD15 46 16 PB6 ADIO15 51 P3.4/T0 PB7 17 ALE 47 P3.5/T1 33 ALE CNTL0 (WR) 10 32 RD 50 RST RESET ( ) PSEN CNTL1 RD 20 18 WR PC0 WR 19 PC1 35 19 A16 49 18 RD/A16 CNTL 2(PSEN) EA PC2 17 PC3 14 10 PC4 PD0-ALE 13 9 PC5 PD1 12 8 PC6 PD2 11 PC7 RESET 48 RESET RESET AI02881C 1. The A16 and A17 connections are optional. 2. In non-Page-mode, AD7-AD0 connects to ADIO7-ADIO0. Doc ID 7833 Rev 7 63/128 MCU bus interface PSD8XXFX Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN inputs 80C251SB PSD 43 A0 A0 30 2 P0.0 ADIO0 P1.0 42 A1 A1 31 29 3 P0.1 ADIO1 PA0 P1.1 41 A2 A2 32 28 4 P0.2 ADIO2 PA1 P1.2 40 A3 A3 33 5 27 P0.3 ADIO3 PA2 P1.3 39 A4 A4 34 25 6 P0.4 ADIO4 PA3 P1.4 38 A5 A5 35 24 7 P0.5 ADIO5 PA4 P1.5 37 A6 36 8 A6 23 P0.6 ADIO6 PA5 P1.6 36 A7 A7 37 9 22 P0.7 ADIO7 PA6 P1.7 21 PA7 AD8 21 24 P2.0 X1 AD9 AD8 25 39 P2.1 ADIO8 7 26 AD10 AD9 40 20 P2.2 PB0 ADIO9 X2 6 27 AD11 AD10 41 P2.3 PB1 ADIO10 5 28 AD12 11 AD11 42 P2.4 PB2 P3.0/RXD ADIO11 4 29 AD13 13 AD12 43 P2.5 PB3 ADIO12 P3.1/TXD 3 30 AD14 AD13 44 14 PB4 P2.6 ADIO13 P3.2/INT0 2 AD15 31 AD14 45 15 PB5 P2.7 ADIO14 P3.3/INT1 52 AD15 46 PB6 16 ADIO15 P3.4/T0 51 PB7 17 P3.5/T1 33 ALE 47 ( ) ALE CNTL0 WR 10 32 RD 50 RESET RST CNTL1(RD) PSEN 20 18 WR PC0 19 WR 19 PSEN PC1 35 49 18 CNTL 2(PSEN) EA RD/A16 PC2 17 PC3 14 10 PC4 PD0-ALE 13 9 PC5 PD1 12 8 PC6 PD2 11 PC7 48 RESET RESET RESET AI02882C Table 19. 80C251 configurations 80C251 READ/WRITE Configuration Connecting to PSD pins Page mode pins WR CNTL0 Non-Page mode, 80C31 compatible 1 RD CNTL1 A7-A0 multiplex with D7-D0 PSEN CNTL2 WR CNTL0 Non-Page mode 2 PSEN only CNTL1 A7-A0 multiplex with D7-D0 WR CNTL0 Page mode 3 PSEN only CNTL1 A15-A8 multiplex with D7-D0 WR CNTL0 Page mode 4 RD CNTL1 A15-A8 multiplex with D7-D0 PSEN CNTL2 64/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.7 80C51XA The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits (D7-D0). The 80C51XA can be configured to operate in eight-bit data mode (as shown in Figure 23). The 80C51XA improves bus throughput and performance by executing burst cycles for code fetches. In Burst mode, address A19-A4 are latched internally by the PSD, while the 80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus timing requirement in Burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply. Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus 80C51XA PSD 21 A4D0 30 2 A0 XTAL1 A0/WRH ADIO0 20 3 A1 A5D1 31 29 A0 XTAL2 A1 ADIO1 PA0 4 A2 A6D2 32 28 A1 PA1 A2 ADIO2 A3 33 5 A7D3 27 A2 A3 ADIO3 PA2 43 A4D0 A8D4 34 25 A3 AD104 A4D0 PA3 11 42 A5D1 A9D5 35 24 RXD0 A5D1 AD105 PA4 13 41 A6D2 A10D6 36 23 TXD0 A6D2 ADIO6 PA5 6 40 A7D3 A11D7 37 22 RXD1 A7D3 ADIO7 PA6 7 39 A8D4 21 TXD1 PA7 A8D4 38 A9D5 A9D5 37 A10D6 A12 39 A10D6 ADIO8 9 7 A11D7 36 A13 40 T2EX PB0 A11D7 8 ADIO9 6 24 A12 T2 A14 41 PB1 A12D8 16 ADIO10 5 25 A13 A15 42 T0 PB2 A13D9 ADIO11 4 26 A14 A16 43 PB3 A14D10 AD1012 3 27 A15 A17 44 PB4 A15D11 AD1013 2 28 A16 10 A18 45 PB5 A16D12 ADIO14 RST RESET 52 A17 29 A19 46 14 PB6 A17D13 ADIO15 INT0 51 30 A18 PB7 15 A18D14 INT1 31 A19 A19D15 47 ( ) CNTL0 WR 20 50 PC0 ( ) 19 CNTL1 RD PC1 18 PC2 32 PSEN 49 17 35 PSEN CNTL 2(PSEN) PC3 EA/WAIT 14 19 RD PC4 17 10 RD BUSW 13 PD0-ALE 18 WR PC5 8 12 WRL PD1 PC6 33 ALE 9 11 ALE PD2 PC7 48 RESET RESET AI02883C Doc ID 7833 Rev 7 65/128 MCU bus interface PSD8XXFX 15.8 68HC11 Figure 24 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR signals for external devices. Figure 24. Interfacing the PSD with a 68HC11 AD7-AD0 AD7-AD0 PSD AD0 30 29 ADIO0 PA0 AD1 31 28 68HC11 ADIO1 PA1 27 AD2 32 PA2 ADIO2 AD3 33 25 31 ADIO3 PA3 PA3 8 AD4 34 24 30 XT PA4 AD104 PA4 AD5 35 7 29 23 AD105 PA5 PA5 EX AD6 36 22 28 PA6 ADIO6 PA6 AD7 37 21 27 17 PA7 PA7 ADIO7 RESET RESET 19 IRQ 18 XIRQ 42 A8 39 7 PB0 ADIO8 PB0 41 6 A9 40 2 PB1 ADIO9 PB1 40 A10 41 5 MODB PB2 ADIO10 PB2 39 A11 42 4 PB3 ADIO11 PB3 34 3 38 A12 43 PA0 PB4 AD1012 PB4 33 2 37 A13 44 PA1 PB5 AD1013 PB5 32 36 A14 45 52 PA2 PB6 ADIO14 PB6 A15 51 35 46 PB7 ADIO15 PB7 9 AD0 PC0 43 20 10 AD1 PE0 PC0 47 PC1 44 _ 19 11 AD2 CNTL0 (R W) PE1 PC1 PC2 50 45 18 12 AD3 PE2 CNTL1(E) PC2 46 PC3 17 13 PE3 AD4 PC3 47 PC4 49 14 AD5 PE4 14 CNTL 2 PC4 48 PC5 13 15 AD6 PE5 PC5 10 49 PC6 12 16 AD7 PD0 AS PE6 – PC6 PC7 9 50 11 PE7 PD1 PC7 8 PD2 20 52 PD0 VRH 21 PD1 48 51 VRL 22 RESET PD2 23 PD3 24 PD4 25 PD5 3 MODA 5 E E 4 AS AS R/W 6 R/W RESET AI02884C 66/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16 I/O ports There are four programmable I/O ports: ports A, B, C, and D. Each of the ports is eight bits except port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. The topics discussed in this section are: ● General port architecture ● Port operating modes ● Port configuration registers (PCR) ● Port Data registers ● Individual port functionality. 16.1 General port architecture The general architecture of the I/O port block is shown in Figure 25. Individual port architectures are shown in Figure 27, Figure 28, Figure 29, and Figure 30. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 25, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control registers (Ports A and B only) and PSDsoft Express Configuration.Inputs to the multiplexer include the following: ● Output data from the Data Out register ● Latched address outputs ● CPLD macrocell output ● External Chip Select (ECS0-ECS2) from the CPLD. The port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The port Data Buffer (PDB) is connected to the Internal data bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control registers, and port pin input are all connected to the port data buffer (PDB). The port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, then the Direction register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the MCU (see Figure 16: Input macrocell). Doc ID 7833 Rev 7 67/128 I/O ports PSD8XXFX 16.2 Port operating modes The I/O ports have several modes of operation. Some modes can be defined using PSDabel, some by the MCU writing to the Control registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Express must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data port, Address input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 20 summarizes which modes are available on each port. Table 23 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. Figure 25. General I/O port architecture DATA OUT REG. DATA OUT DQ WR ADDRESS ADDRESS PORT PIN D Q OUTPUT ALE G MUX MACROCELL OUTPUTS EXT CS READ MUX P OUTPUT SELECT D DATA IN B CONTROL REG. ENABLE OUT DQ WR DIR REG. DQ WR ( ) ENABLE PRODUCT TERM .OE INPUT MACROCELL CPLD-INPUT AI02885 68/128 Doc ID 7833 Rev 7 INTERNAL DATA BUS PSD8XXFX I/O ports 16.3 MCU I/O mode In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in Table 8. A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the Control register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction register, or by the output enable product term (see Section 16.8: Peripheral I/O mode). When the pin is configured as an output, the content of the Data Out register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer (see Figure 25). Ports C and D do not have Control registers, and are in MCU I/O mode by default. They can be used for PLD I/O if equations are written for them in PSDabel. 16.4 PLD I/O mode The PLD I/O mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as an output from the CPLD’s Output macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction register to ’0.’ The corresponding bit in the Direction register must not be set to '1' if the pin is defined for a PLD input signal in PSDabel. The PLD I/O mode is specified in PSDabel by declaring the port pins, and then writing an equation assigning the PLD I/O to a port. 16.5 Address Out mode For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive latched addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction register and Control register must be set to a 1 for pins to use Address Out mode. This must be done by the MCU at run-time. See Table 22 for the address output pin assignments on ports A and B for various MCUs. For non-multiplexed 8-bit bus mode, address signals (A7-A0) are available to port B in Address Out mode. Note: Do not drive address signals with Address Out mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. Table 20. Port operating modes Port mode Port A Port B Port C Port D MCU I/O Yes Yes Yes Yes PLD I/O McellAB outputs Yes Yes No No McellBC outputs No Yes Yes No Additional Ext. CS outputs No No No Yes PLD inputs Yes Yes Yes Yes Doc ID 7833 Rev 7 69/128 I/O ports PSD8XXFX Table 20. Port operating modes (continued) Port mode Port A Port B Port C Port D Yes (A7 – 0) Address Out Yes (A7 – 0) No No or (A15 – 8) Address In Yes Yes Yes Yes Data port Yes (D7 – 0) No No No Peripheral I/O Yes No No No (1) JTAG ISP No No Yes No 1. Can be multiplexed with other I/O functions. Table 21. Port operating mode settings Control Direction VM Defined in Defined in PSD Mode register register register JTAG Enable PSDabel configuration setting setting setting 1 = output, (1) MCU I/O Declare pins only N/A 0 N/A N/A (2) 0 = input (2) PLD I/O Logic equations N/A N/A N/A N/A Data port (Port A) N/A Specify bus type N/A N/A N/A N/A Address Out (2) Declare pins only N/A 1 1 N/A N/A (Port A,B) Address In Logic for equation N/A N/A N/A N/A N/A input macrocells (Port A,B,C,D) Peripheral I/O Logic equations N/A N/A N/A PIO bit = 1 N/A (Port A) (PSEL0 & 1) JTAG (3) JTAG ISP JTAGSEL N/A N/A N/A JTAG_Enable Configuration 1. N/A = Not Applicable 2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable product term (.oe) from the CPLD AND Array. 3. Any of these three methods enables the JTAG pins on port C. Table 22. I/O port Latched address output assignments MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4) (1) 8051XA (8-Bit) N/A Address a7-a4 Address a11-a8 N/A 80C251 N/A N/A Address a11-a8 Address a15-a12 (Page mode) All Other Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 8-Bit Multiplexed 8-Bit N/A N/A Address a3-a0 Address a7-a4 Non-Multiplexed bus 1. N/A = Not Applicable 70/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16.6 Address In mode For MCUs that have more than 16 address signals, the higher addresses can be connected to port A, B, C, and D. The address input can be latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the SRAM, or primary or secondary Flash memory is considered to be an address input. 16.7 Data port mode Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus. The Data port is connected to the data bus of the MCU. The general I/O functions are disabled in port A if the port is configured as a Data port. 16.8 Peripheral I/O mode Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is enabled by setting Bit 7 of the VM register to a ’1.’ Figure 26 shows how port A acts as a bi- directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or PSEL1 is not active. Figure 26. Peripheral I/O mode RD PSEL0 PSEL PSEL1 D0-D7 VM REGISTER BIT 7 PA0 - PA7 DATA BUS WR AI02886 16.9 JTAG in-system programming (ISP) Port C is JTAG compliant, and can be used for in-system programming (ISP). You can multiplex JTAG operations with other functions on port C because in-system programming (ISP) is not performed in normal operating mode. For more information on the JTAG port, see Section 19: Programming in-circuit using the JTAG serial interface. Doc ID 7833 Rev 7 71/128 I/O ports PSD8XXFX 16.10 Port configuration registers (PCR) Each port has a set of port configuration registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 8. The addresses in Table 8 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three port configuration registers (PCR), shown in Table 23, are used for setting the port configurations. The default Power-up state for each register in Table 23 is 00h. 16.11 Control register Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode, and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only ports A and B have an associated Control register. 16.12 Direction register The Direction register, in conjunction with the output enable (except for port D), controls the direction of data flow in the I/O ports. Any bit set to '1' in the Direction register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input. Figure 27 and Figure 28 show the port architecture diagrams for ports A/B and C, respectively. The direction of data flow for ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction register has sole control of a given pin’s direction. An example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in Table 26. Since port D only contains three pins (shown in Figure 30), the Direction register for port D has only the three least significant bits active. 16.13 Drive Select register The Drive Select register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is set to a ’1.’ The default pin drive is CMOS. Note that the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive register is set to ’1.’ The default rate is slow slew. Table 27 shows the Drive register for ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. 72/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports Table 23. Port configuration registers (PCR)t Register name Port MCU access Control A,B WRITE/READ Direction A,B,C,D WRITE/READ (1) Drive Select A,B,C,D WRITE/READ 1. See Table 27 for Drive register bit definition. Table 24. Port Pin Direction Control, Output Enable P.T. not defined Direction register bit Port Pin mode 0 Input 1 Output Table 25. Port Pin Direction Control, Output Enable P.T. defined Direction register Bit Output Enable P.T. Port Pin mode 0 0 Input 0 1 Output 1 0 Output 1 1 Output Table 26. Port Direction assignment example Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 1 Table 27. Drive register pin assignment Drive Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 register Open Open Open Open Slew Slew Slew Slew Port A Drain Drain Drain Drain Rate Rate Rate Rate Open Open Open Open Slew Slew Slew Slew Port B Drain Drain Drain Drain Rate Rate Rate Rate Open Open Open Open Open Open Open Open Port C Drain Drain Drain Drain Drain Drain Drain Drain Slew Slew Slew (1) (1) (1) (1) (1) Port D NA NA NA NA NA Rate Rate Rate 1. NA = Not Applicable. Doc ID 7833 Rev 7 73/128 I/O ports PSD8XXFX 16.14 Port Data registers The port Data registers, shown in Table 28, are used by the MCU to write data to or read data from the ports. Table 28 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. 16.15 Data In Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer. 16.16 Data Out register Stores output data written by the MCU in the MCU I/O output mode. The contents of the register are driven out to the pins if the Direction register or the output enable product term is set to ’1.’ The contents of the register can also be read back by the MCU. Output macrocells (OMC) The CPLD Output macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the Output macrocells (OMC). If the OMC Mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops (see Section 14: PLDS). 16.17 OMC Mask register Each OMC Mask register bit corresponds to an Output macrocell (OMC) flip-flop. When the OMC Mask register bit is set to a 1, loading data into the Output macrocell (OMC) flip-flop is blocked. The default value is 0 or unblocked. Table 28. Port Data registers Register name Port MCU access Data In A,B,C,D READ – input on pin Data Out A,B,C,D WRITE/READ READ – outputs of macrocells Output macrocell A,B,C WRITE – loading macrocells flip-flop WRITE/READ – prevents loading into a given Mask macrocell A,B,C macrocell Input macrocell A,B,C READ – outputs of the input macrocells Enable Out A,B,C READ – the output enable control of the port driver 16.18 Input macro (IMC) The input macrocells (IMC) can be used to latch or store external inputs. The outputs of the input macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU (see Section 14: PLDS). 74/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16.19 Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state and the pin is in input mode. 16.20 Ports A and B – functionality and structure Ports A and B have similar functionality and structure, as shown in Figure 27. The two ports can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B. McellBC7-McellBC0 can be connected to port B or port C. ● CPLD input – Via the input macrocells (IMC). ● Latched Address output – Provide latched address output as per Table 22. ● Address In – Additional high address inputs using the input macrocells (IMC). ● Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode. ● Data port – port A to D7-D0 for 8 bit non-multiplexed bus ● Multiplexed Address/Data port for certain types of MCU bus interfaces. ● Peripheral mode – port A only Figure 27. Port A and port B structure DATA OUT REG. DATA OUT DQ WR PORT ADDRESS ADDRESS A OR B PIN D Q [ ] [ ] A 7:0 OR A 15:8 OUTPUT ALE G MUX MACROCELL OUTPUTS READ MUX P OUTPUT SELECT D DATA IN B CONTROL REG. ENABLE OUT DQ WR DIR REG. DQ WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD-INPUT AI02887 Doc ID 7833 Rev 7 75/128 INTERNAL DATA BUS I/O ports PSD8XXFX 16.21 Port C – functionality and structure Port C can be configured to perform one or more of the following functions (see Figure 28): ● MCU I/O mode ● CPLD Output – McellBC7-McellBC0 outputs can be connected to port B or port C. ● CPLD input – via the input macrocells (IMC) ● Address In – Additional high address inputs using the input macrocells (IMC). ● In-system programming (ISP) – JTAG port can be enabled for programming/erase of the PSD device (see Section 19: Programming in-circuit using the JTAG serial interface for more information on JTAG programming). ● Open Drain – port C pins can be configured in Open Drain mode Port C does not support Address Out mode, and therefore no Control register is required. Pin PC7 may be configured as the DBE input in certain MCU bus interfaces. Figure 28. Port C structure DATA OUT REG. DATA OUT DQ WR 1 PORT C PIN SPECIAL FUNCTION OUTPUT MUX [ ] MCELLBC 7:0 READ MUX P OUTPUT SELECT D DATA IN B ENABLE OUT DIR REG. DQ WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD-INPUT SPECIAL FUNCTION CONFIGURATION AI02888B BIT 16.22 Port D – functionality and structure Port D has three I/O pins. See Figure 29 and Figure 30. This port does not support Address Out mode, and therefore no Control register is required. port D can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Output – External Chip Select (ECS0-ECS2) ● CPLD input – direct input to the CPLD, no input macrocells (IMC) ● Slew rate – pins can be set up for fast slew rate 76/128 Doc ID 7833 Rev 7 INTERNAL DATA BUS PSD8XXFX I/O ports Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: ● Address Strobe (ALE/AS, PD0) ● CLKIN (PD1) as input to the macrocells flip-flops and APD counter ● PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory, SRAM and CSIOP. Figure 29. Port D structure DATA OUT REG. DATA OUT DQ WR PORT D PIN OUTPUT MUX ECS[ 2:0] READ MUX OUTPUT P SELECT D B DATA IN ENABLE PRODUCT TERM (.OE) DIR REG. DQ WR CPLD-INPUT AI02889 16.23 External Chip Select The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product term that can be configured active high or low. The output enable of the pin is controlled by either the output enable product term or the Direction register (see Figure 30). Doc ID 7833 Rev 7 77/128 INTERNAL DATA BUS I/O ports PSD8XXFX Figure 30. Port D external Chip Select signals ENABLE (.OE) DIRECTION REGISTER PD0 PIN PT0 ECS0 POLARITY BIT ENABLE (.OE) DIRECTION REGISTER PD1 PIN PT1 ECS1 POLARITY BIT ENABLE (.OE) DIRECTION REGISTER PT2 PD2 PIN ECS2 POLARITY BIT AI02890 78/128 Doc ID 7833 Rev 7 PLD INPUT BUS CPLD AND ARRAY PSD8XXFX Power management 17 Power management All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to Standby. The designer does not have to do anything special to achieve memory Standby mode when no inputs are changing—it happens automatically. The PLD sections can also achieve Standby mode when its inputs are not changing, as described in the sections on the Power Management mode registers (PMMR). ● As with the Power Management mode, the Automatic Power Down (APD) block allows the PSD to reduce to standby current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. This feature is available on all the devices of the PSD family. The APD Unit is described in more detail in Section 17.1: Automatic Power-down (APD) Unit and Power-down mode. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching PSD memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in Standby mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby mode, but not the memories. ● PSD Chip Select input (CSI, PD2) can be used to disable the internal memories, placing them in Standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select input (CSI, PD2) makes its initial transition from deselected to selected. ● The PMMRs can be written by the MCU at run-time to manage power. All PSD supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 34 and Figure 35). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher. Doc ID 7833 Rev 7 79/128 Power management PSD8XXFX 17.1 Automatic Power-down (APD) Unit and Power-down mode The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes high, and the PSD enters Power-down mode, as discussed next. Power-down mode By default, if you enable the APD Unit, Power-down mode is automatically enabled. The device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for fifteen periods of CLKIN (PD1). The following should be kept in mind when the PSD is in Power-down mode: ● If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal operating mode. The PSD also returns to normal operating mode if either PSD Chip Select input (CSI, PD2) is low or the Reset (RESET) input is high. ● The MCU address/data bus is blocked from all memory and PLDs. ● Various signals can be blocked (prior to Power-down mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit. ● All PSD memories enter Standby mode and are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby mode because you don’t want to have to wait for the logic and I/O to “wake up” before their outputs can change. See Table 29 for Power-down mode effects on PSD ports. ● Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. Table 29. Power-down mode’s effect on ports Port function Pin level MCU I/O No change PLD Out No change Address Out Undefined Data port Tri-state Peripheral I/O Tri-state 80/128 Doc ID 7833 Rev 7 PSD8XXFX Power management Figure 31. APD unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION DISABLE BUS INTERFACE ALE CLR PD EEPROM SELECT APD COUNTER RESET FLASH SELECT EDGE PD CSI DETECT PLD SRAM SELECT CLKIN POWER DOWN ( ) PDN SELECT DISABLE FLASH/EEPROM/SRAM AI02891 Table 30. PSD timing and standby current during Power-down mode Typical standby current Memory Access recovery time Mode PLD propagation delay access time to normal access 5V V 3V V CC CC (1) (2) (2) Power-down Normal t No access t 75 µA 25 µA PD LVDV 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’ 17.2 For users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power-down mode, you must not connect the E clock to CLKIN (PD1). You should instead connect a crystal oscillator to CLKIN (PD1). The crystal oscillator frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD keeps going into Power-down mode. 17.3 Other power saving options The PSD offers other reduced power saving options that are independent of the Power- down mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2. Doc ID 7833 Rev 7 81/128 Power management PSD8XXFX Figure 32. Enable Power-down flowchart RESET Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. ALE/AS idle No for 15 CLKIN clocks? Yes PSD in Power Down Mode AI02892 17.4 PLD power management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC power, AC power, and propagation delay. Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption. (1) Table 31. Power Management mode registers PMMR0 Bit Name Description Bit 0 X 0 Not used, and should be set to zero. 0 = Automatic Power-down (APD) is disabled. off Bit 1 APD Enable 1 = Automatic Power-down (APD) is enabled. on Bit 2 X 0 Not used, and should be set to zero. 0 = PLD Turbo mode is on on Bit 3 PLD Turbo 1 = PLD Turbo mode is off, saving power. off 82/128 Doc ID 7833 Rev 7 PSD8XXFX Power management (1) Table 31. Power Management mode registers PMMR0 (continued) Bit Name Description 0 = CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN on (PD1) Powers-up the PLD when Turbo Bit is ’0.’ Bit 4 PLD Array clk 1 = CLKIN (PD1) input to PLD AND Array is disconnected, saving power. off 0 = CLKIN (PD1) input to the PLD macrocells is connected. on Bit 5 PLD MCell clk 1 = CLKIN (PD1) input to PLD macrocells is disconnected, saving power. off Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. (1) Table 32. Power Management mode registers PMMR2 Bit Name Description Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on Cntl0 input to the PLD AND Array is connected. PLD Array Bit 2 CNTL0 1 = off Cntl0 input to PLD AND Array is disconnected, saving power. 0 = on Cntl1 input to the PLD AND Array is connected. PLD Array Bit 3 CNTL1 1 = off Cntl1 input to PLD AND Array is disconnected, saving power. 0 = on Cntl2 input to the PLD AND Array is connected. PLD Array Bit 4 CNTL2 1 = off Cntl2 input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. PLD Array Bit 5 ALE 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 = on DBE input to the PLD AND Array is connected. PLD Array Bit 6 DBE 1 = off DBE input to PLD AND Array is disconnected, saving power. Bit 7 X 0 Not used, and should be set to zero. 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. Doc ID 7833 Rev 7 83/128 Power management PSD8XXFX 17.5 PSD Chip Select input (CSI, PD2) PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input (CSI, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select input (CSI, PD2) is high. There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on the speed grade of the PSD that you are using. See the timing parameter t in Table 62 SLQV or Table 63. 17.6 Input clock The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output macrocells (OMC). During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the macrocells block by setting Bits 4 or 5 to a 1 in PMMR0. 17.7 Input control signals The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2. Table 33. APD counter operation APD Enable ALE PD ALE level APD counter bit polarity 0 X X Not counting 1 X Pulsing Not counting 1 1 1 Counting (generates PDN after 15 clocks) 1 0 0 Counting (generates PDN after 15 clocks) 84/128 Doc ID 7833 Rev 7 PSD8XXFX Reset timing and device status at reset 18 Reset timing and device status at reset 18.1 Power-up reset Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t after V is NLNH-PO CC steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. After the rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period, t , before the first OPR memory access is allowed. The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power On Reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE cycle initiation is prevented automatically when V is below V . CC LKO 18.2 Warm reset Once the device is up and running, the device can be reset with a pulse of a much shorter duration, t . NLNH The same t period is needed before the device is operational after warm reset. OPR Figure 33 shows the timing of the Power-up and warm reset. 18.3 I/O pin, register and PLD status at Reset Table 34 shows the I/O pin, register and PLD status during Power On Reset, warm reset and Power-down mode. PLD outputs are always valid during warm reset, and they are valid in Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long before the V ramps up to operating level. Once the PLD is active, CC the state of the outputs are determined by the PSDabel equations. 18.4 Reset of Flash memory erase and program cycles (on the PSD834Fx) A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory program or erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the Read mode within a period of t . NLNH-A Doc ID 7833 Rev 7 85/128 Reset timing and device status at reset PSD8XXFX Figure 33. Reset (RESET) timing V (min) CC V CC t NLNH t t t t NLNH-PO OPR NLNH-A OPR Power-On Reset Warm Reset RESET AI02866b Table 34. Status during Power-on reset, Warm reset and Power-down mode Port configuration Power-on reset Warm reset Power-down mode MCU I/O Input mode Input mode Unchanged Valid after internal PSD Depends on inputs to PLD PLD Output configuration bits are Valid (addresses are blocked in loaded PD mode) Address Out Tri-stated Tri-stated Not defined Data port Tri-stated Tri-stated Tri-stated Peripheral I/O Tri-stated Tri-stated Tri-stated Register Power-on reset Warm reset Power-down mode PMMR0 and PMMR2 Cleared to '0' Unchanged Unchanged Cleared to '0' by internal Depends on .re and .pr Depends on .re and .pr Macrocells flip-flop status Power-On Reset equations equations Initialized, based on the Initialized, based on the (1) VM register selection in PSDsoft selection in PSDsoft Unchanged Configuration menu Configuration menu All other registers Cleared to '0' Cleared to '0' Unchanged 1. The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset. 86/128 Doc ID 7833 Rev 7 PSD8XXFX Programming in-circuit using the JTAG serial interface 19 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface block can be enabled on port C (see Table 35). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. Note: By default, on a blank PSD (as shipped from the factory or after erasure), four pins on port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note AN1153 for more details on JTAG in-system programming (ISP). 19.1 Standard JTAG signals The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated Test Equipment). When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG signals, TSTAT and TERR. The following symbolic logic equation specifies the conditions enabling the four basic JTAG signals (TMS, TCK, TDI, and TDO) on their respective port C pins. For purposes of discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Express Configuration utility. This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1 */ Microcontroller_enabled + /* The microcontroller can set a bit at run-time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table 36 for bit definition. */ PSD_product_term_enabled; /* A dedicated product term (PT) inside the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the port C JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 1153 for details. */ The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However, Doc ID 7833 Rev 7 87/128 Programming in-circuit using the JTAG serial interface PSD8XXFX Reset (RESET) will prevent or interrupt JTAG operations if the JTAG enable register is used to enable the JTAG pins. The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Configuration (ISC) commands. A definition of these JTAG In-System-Configuration (ISC) commands and sequences is defined in a supplemental document available from ST. This document is needed only as a reference for designers who use a FlashLINK to program their PSD. 19.2 JTAG extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD signals instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes low (active) when an Error condition occurs, and stays low until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received after an “ISC_DISABLE” command. TSTAT behaves the same as Ready/Busy described in Section 6.3.1: Ready/Busy (PC3). TSTAT is high when the PSD device is in READ mode (primary and secondary Flash memory contents can be read). TSTAT is low when Flash memory program or erase cycles are in progress, and also when data is being written to the secondary Flash memory. TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE” command. This facilitates a wired-OR connection of TSTAT signals from multiple PSD devices and a wired-OR connection of TERR signals from those same devices. This is useful when several PSD devices are “chained” together in a JTAG environment. 19.3 Security and Flash memory protection When the security bit is set, the device cannot be read on a device programmer or through the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part to a non-secured blank state. The Security bit can be set in PSDsoft Express configuration. All primary and secondary Flash memory sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft Express configuration. 88/128 Doc ID 7833 Rev 7 PSD8XXFX Programming in-circuit using the JTAG serial interface Table 35. JTAG port signals Port C pin JTAG signals Description PC0 TMS mode Select PC1 TCK Clock PC3 TSTAT Status PC4 TERR Error flag PC5 TDI Serial Data In PC6 TDO Serial Data Out Doc ID 7833 Rev 7 89/128 Initial delivery state PSD8XXFX 20 Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. (1) Table 36. JTAG Enable register Bit Name Description 0 = JTAG port is disabled. off Bit 0 JTAG_Enable 1 = JTAG port is enabled. on Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. Bit 3 X 0 Not used, and should be set to zero. Bit 4 X 0 Not used, and should be set to zero. Bit 5 X 0 Not used, and should be set to zero. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals. 90/128 Doc ID 7833 Rev 7 PSD8XXFX Maximum rating 21 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 37. Absolute maximum ratings Symbol Parameter Min. Max. Unit T Storage temperature –65 125 °C STG Lead temperature during soldering (20 seconds T 235 °C (1) LEAD max.) V Input and output voltage (Q = V or Hi-Z) –0.6 7.0 V IO OH V Supply voltage –0.6 7.0 V CC V Device programmer supply voltage –0.6 14.0 V PP Electrostatic discharge voltage (human body model) V –2000 2000 V (2) ESD 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) Doc ID 7833 Rev 7 91/128 AC/DC parameters PSD8XXFX 22 AC/DC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device: ● DC electrical specifications ● AC timing specifications – PLD timings Combinatorial timings Synchronous clock mode Asynchronous clock mode Input macrocell timings – MCU timings READ timings WRITE timings Peripheral mode timings Power-down and Reset timings The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The following are issues concerning the parameters presented: ● In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo Bit is ’0.’ ● The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 34 and Figure 35 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. ● In the PLD timing parameters, add the required delay when Turbo Bit is ’0.’ 92/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Figure 34. PLD I /frequency consumption (5 V range) CC 110 100 V = 5V CC 90 80 70 60 50 40 30 PT 100% 20 PT 25% 10 0 01 5015 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) AI02894 Figure 35. PLD I /frequency consumption (3 V range) CC 60 V = 3V CC 50 40 30 20 PT 100% 10 PT 25% 0 01 5015 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) AI03100 (1) Table 38. Example of PSD typical power calculation at V =5.0 V (Turbo mode on) CC Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash memory access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational modes % Normal = 10% % Power-down mode = 90% Doc ID 7833 Rev 7 93/128 TURBO ON (25%) TURBO ON (100%) TURBO ON (25%) TURBO ON (100%) TURBO OFF TURBO OFF TURBO OFF TURBO OFF I – (mA) CC I – (mA) CC AC/DC parameters PSD8XXFX (1) Table 38. Example of PSD typical power calculation at V =5.0 V (Turbo mode on) CC Conditions Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo mode = ON Calculation (using typical values) I total = Ipwrdown x %pwrdown + %normal x (I (ac) + I (dc)) CC CC CC = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 µA/PT) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 µA + 0.1 x 42.9 = 45 µA + 4.29 mA = 4.34 mA 1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on I = 0 mA. OUT (1) Table 39. Example of PSD typical power calculation at V = 5.0 V (Turbo mode off) CC Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash memory access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational modes % Normal = 10% % Power-down mode = 90% Number of product terms used 94/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 39. Example of PSD typical power calculation at V = 5.0 V (Turbo mode off) CC Conditions (from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo mode = Off Calculation (using typical values) I total = Ipwrdown x %pwrdown + %normal x (I (ac) + I (dc)) CC CC CC = Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz + 0.15 x 1.5mA/MHz x 4 MHz + 24mA) = 45 µA + 0.1 x (8 + 0.9 + 24) = 45 µA + 0.1 x 32.9 = 45 µA + 3.29mA = 3.34mA 1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on I = 0 mA. OUT Table 40. Operating conditions (5 V devices) Symbol Parameter Min. Max. Unit V Supply voltage 4.5 5.5 V CC Ambient operating temperature (industrial) –40 85 °C T A Ambient operating temperature (commercial) 0 70 °C Table 41. Operating conditions (3 V devices) Symbol Parameter Min. Max. Unit V Supply voltage 3.0 3.6 V CC Ambient operating temperature (industrial) –40 85 °C T A Ambient operating temperature (commercial) 0 70 °C Doc ID 7833 Rev 7 95/128 AC/DC parameters PSD8XXFX (1) Table 42. AC signal letters for PLD timing Letter Signal description A Address input C CEout output D Input data E E output G Internal WDOG_ON signal I Interrupt input LALE input N RESET input or output P Port signal output Q Output data RWR, UDS, LDS, DS, IORD, PSEN inputs S Chip Select input TR/W input W Internal PDN signal M Output macrocell 1. Example: t = time from address valid to ALE invalid. AVLX (1) Table 43. AC signal behavior symbols for PLD timing Letter AC signal description tTime L Logic level low or ALE H Logic level high VValid (2) X No longer a valid logic level ZFloat PW Pulse width 1. Example: t = time from address valid to ALE invalid. AVLX 2. Output Hi-Z is defined as the point where data out is no longer driven. Table 44. AC measurement conditions Symbol Parameter Min. Max. Unit C Load capacitance 30 pF L 96/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters (1) Table 45. Capacitance (2) Symbol Parameter Test condition Typ. Max. Unit Input capacitance (for input C V = 0V 4 6 pF IN IN pins) Output capacitance (for C V = 0V 8 12 pF OUT OUT input/output pins) Capacitance (for C V = 0V 18 25 pF VPP PP CNTL2/V ) PP 1. Sampled only, not 100% tested. 2. Typical values are for T = 25°C and nominal supply voltages. A Figure 36. AC measurement I/O waveform 3.0V Test Point 1.5V 0V AI03103b Figure 37. AC measurement load circuit 2.01 V 195 Ω Device Under Test C = 30 pF L (Including Scope and Jig Capacitance) AI03104b Figure 38. Switching waveforms – key 2.01 V 195 Ω Device Under Test C = 30 pF L (Including Scope and Jig Capacitance) AI03104b Doc ID 7833 Rev 7 97/128 AC/DC parameters PSD8XXFX Table 46. DC characteristics (5 V devices) Test condition Symbol Parameter Min. Typ. Max. Unit (in addition to those in Table 40) V Input high voltage 4.5 V < V < 5.5 V 2 V +0.5 V IH CC CC V Input low voltage 4.5 V < V < 5.5 V –0.5 0.8 V IL CC (1) V Reset high level input voltage 0.8V V +0.5 V IH1 CC CC 0.2V – (1) CC V Reset low level input voltage –0.5 V IL1 0.1 V Reset pin hysteresis 0.3 V HYS V (min) for Flash Erase and CC V 2.5 4.2 V LKO Program I = 20 µA, V = 4.5 V 0.01 0.1 V OL CC V Output low voltage OL I = 8 mA, V = 4.5 V 0.25 0.45 V OL CC I = –20 µA, V = 4.5 V 4.4 4.49 V OH CC V Output high voltage OH I = –2 mA, V = 4.5 V 2.4 3.9 V OH CC Standby supply current (2)(3) I CSI >V –0.3 V 50 200 µA SB CC for Power-down mode I input leakage current V < V < V –1 ±0.1 1 µA LI SS IN CC I Output leakage current 0.45 < V < V –10 ±5 10 µA LO OUT CC PLD_TURBO = off, 0 µA/PT (4) f = 0 MHz PLD only PLD_TURBO = on, 400 700 µA/PT f = 0 MHz Operating I CC (4) (DC) supply current During Flash memory 15 30 mA WRITE/Erase only Flash memory Read only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA (5) PLD AC adder I CC Flash memory AC adder 2.5 3.5 mA/MHz (4) (AC) SRAM AC adder 1.5 3.0 mA/MHz 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V is valid at or above 0.8V . IL1 CC IH1 CC 2. CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. I = 0 mA OUT 5. Please see Figure 34 for the PLD current calculation. 98/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 47. DC Characteristics (3 V devices) Symbol Parameter Conditions Min. Typ. Max. Unit V High level input voltage 3.0 V < V < 3.6 V 0.7V V +0.5 V IH CC CC CC V Low level input voltage 3.0 V < V < 3.6 V –0.5 0.8 V IL CC (1) V Reset high level input voltage 0.8V V +0.5 V IH1 CC CC 0.2V – (1) CC V Reset low level input voltage –0.5 V IL1 0.1 V Reset pin hysteresis 0.3 V HYS V (min) for Flash Erase and CC V 1.5 2.2 V LKO Program I = 20 µA, V = 3.0 V 0.01 0.1 V OL CC V Output low voltage OL I = 4 mA, V = 3.0 V 0.15 0.45 V OL CC I = –20 µA, V = 3.0 V 2.9 2.99 V OH CC V Output high voltage OH I = –1 mA, V = 3.0 V 2.7 2.8 V OH CC Standby supply current (2)(3) I CSI >V –0.3 V 25 100 µA SB CC for Power-down mode I Input leakage current V < V < V –1 ±0.1 1 µA LI SS IN CC I Output leakage current 0.45 < V < V –10 ±5 10 µA LO IN CC PLD_TURBO = off, 0 µA/PT (3) f = 0 MHz PLD only PLD_TURBO = on, 200 400 µA/PT f = 0 MHz Operating I CC (4) (DC) supply current During Flash memory 10 25 mA WRITE/Erase only Flash memory Read only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA (5) PLD AC adder I CC Flash memory AC adder 1.5 2.0 mA/MHz (4) (AC) SRAM AC adder 0.8 1.5 mA/MHz 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V is valid at or above 0.8V . IL1 CC IH1 CC 2. CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. I = 0 mA OUT 5. Please see Figure 35 for the PLD current calculation. Doc ID 7833 Rev 7 99/128 AC/DC parameters PSD8XXFX Figure 39. Input to output disable / enable INPUT tER tEA INPUT TO OUTPUT ENABLE/DISABLE AI02863 Table 48. CPLD combinatorial timing (5 V devices) -70 -90 -15 Fast Slew Turbo Symbol Parameter Conditions PT rate Unit off (1) MinMax MinMax MinMax Aloc CPLD input pin/feedback to t 20 25 32 + 2 + 10 – 2 ns PD CPLD combinatorial output CPLD input to CPLD t 21 26 32 + 10 – 2 ns EA output enable CPLD input to CPLD t 21 26 32 + 10 – 2 ns ER output disable CPLD register clear t 21 26 33 + 10 – 2 ns ARP or preset delay CPLD register clear t 10 20 29 + 10 ns ARPW or preset pulse width Any t CPLD array delay 11 16 22 + 2 ns ARD macrocell 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Table 49. CPLD combinatorial timing (3 V devices) -12 -15 -20 Slew PT Turbo Symbol Parameter Conditions rate Unit Aloc off (1) Min Max Min Max Min Max CPLD input pin/feedback to t 40 45 50 + 4 + 20 – 6 ns PD CPLD combinatorial output CPLD input to CPLD t 43 45 50 + 20 – 6 ns EA output enable CPLD input to CPLD t 43 45 50 + 20 – 6 ns ER output disable CPLD register clear t 40 43 48 + 20 – 6 ns ARP or preset delay 100/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 49. CPLD combinatorial timing (3 V devices) (continued) -12 -15 -20 Slew PT Turbo Symbol Parameter Conditions rate Unit Aloc off (1) Min Max Min Max Min Max CPLD register clear t 25 30 35 + 20 ns ARPW or preset pulse width Any t CPLD array delay 25 29 33 + 4 ns ARD macrocell 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Figure 40. Synchronous clock mode timing – PLD t t CH CL CLKIN t t S H INPUT t CO REGISTERED OUTPUT AI02860 Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices) -70 -90 -15 Fast Slew Turbo PT Symbol Parameter Conditions rate Unit off (1) Min Max Min Max Min Max Aloc Maximum frequency 1/(t +t ) 40.0 30.30 25.00 MHz S CO External feedback Maximum frequency f MAX 1/(t +t –10) 66.6 43.48 31.25 MHz S CO Internal feedback (f ) CNT Maximum frequency 1/(t +t ) 83.3 50.00 35.71 MHz CH CL Pipelined data t Input setup time 12 15 20 + 2 + 10 ns S t Input hold time 0 0 0 ns H t Clock high time Clock input 6 10 15 ns CH t Clock low time Clock input 6 10 15 ns CL Clock to output t Clock input 13 18 22 – 2 ns CO delay Doc ID 7833 Rev 7 101/128 AC/DC parameters PSD8XXFX Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices) (continued) -70 -90 -15 Fast Slew Turbo PT Symbol Parameter Conditions rate Unit off (1) Min Max Min Max Min Max Aloc CPLD array t Any macrocell 11 16 22 + 2 ns ARD delay Minimum clock t t +t 12 20 30 ns (2) MIN CH CL period 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1) t = t + t . CLCL CH CL Table 51. CPLD macrocell synchronous clock mode timing (3 V devices) -12 -15 -20 Slew Turbo PT Symbol Parameter Conditions rate Unit Aloc off (1) Min Max Min Max Min Max Maximum frequency 1/(t +t ) 22.2 18.8 15.8 MHz S CO External feedback Maximum frequency f 1/(t +t –10) 28.5 23.2 18.8 MHz MAX S CO Internal feedback (f ) CNT Maximum frequency 1/(t +t ) 40.0 33.3 31.2 MHz CH CL Pipelined data t Input setup time 20 25 30 + 4 + 20 ns S t Input hold time 0 0 0 ns H t Clock high time Clock input 15 15 16 ns CH t Clock low time Clock input 10 15 16 ns CL Clock to output t Clock input 25 28 33 – 6 ns CO delay t CPLD array delay Any macrocell 25 29 33 + 4 ns ARD Minimum clock t t +t 25 29 32 ns MIN (2) CH CL period 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1) t = t + t . CLCL CH CL 102/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Figure 41. Asynchronous Reset / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 42. Asynchronous Clock mode Timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) -70 -90 -15 Turbo Slew PT Symbol Parameter Conditions Unit Aloc off rate Min Max Min Max Min Max Maximum frequency 1/(t +t ) 38.4 26.32 21.27 MHz SA COA External feedback Maximum frequency f MAXA Internal 1/(t +t –10) 62.5 35.71 27.78 MHz SA COA feedback (f ) CNTA Maximum frequency 1/(t +t ) 71.4 41.67 35.71 MHz CHA CLA Pipelined data Input setup t 7 8 12 + 2 + 10 ns SA time Input hold t 812 14 ns HA time Clock input t 9 12 15 + 10 ns CHA high time Clock input t 9 12 15 + 10 ns CLA low time Doc ID 7833 Rev 7 103/128 AC/DC parameters PSD8XXFX Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) (continued) -70 -90 -15 Turbo Slew PT Symbol Parameter Conditions Unit Aloc off rate Min Max Min Max Min Max Clock to t 21 30 37 + 10 – 2 ns COA output delay CPLD array t Any macrocell 11 16 22 + 2 ns ARDA delay Minimum t 1/f 16 28 39 ns MINA CNTA clock period Table 53. CPLD macrocell Asynchronous clock mode timing (3 V devices) -12 -15 -20 Turbo PT Slew Symbol Parameter Conditions Unit Aloc rate off Min Max Min Max Min Max Maximum frequency 1/(t +t ) 21.7 19.2 16.9 MHz SA COA External feedback Maximum frequency f MAXA 1/(t +t –10) 27.8 23.8 20.4 MHz Internal SA COA feedback (f ) CNTA Maximum frequency 1/(t +t ) 33.3 27 24.4 MHz CHA CLA Pipelined data t Input setup time 10 12 13 + 4 + 20 ns SA t Input hold time 12 15 17 ns HA t Clock high time 17 22 25 + 20 ns CHA t Clock low time 13 15 16 + 20 ns CLA Clock to output t 36 40 46 + 20 – 6 ns COA delay CPLD array t Any macrocell 25 29 33 + 4 ns ARD delay Minimum clock t 1/f 36 42 49 ns MINA CNTA period 104/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Figure 43. Input macrocell timing (product term clock) t t INH INL PT CLOCK t t IS IH INPUT OUTPUT t INO AI03101 Table 54. Input macrocell timing (5 V devices) -70 -90 -15 PT Turbo Symbol Parameter Conditions Unit Aloc off Min Max Min Max Min Max (1) t Input setup time 000 ns IS (1) t Input hold time 15 20 26 + 10 ns IH (1) t NIB input high time 912 18 ns INH (1) t NIB input low time 912 18 ns INL NIB input to combinatorial (1) t 34 46 59 + 2 + 10 ns INO delay 1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t and t . AVLX LXAX Table 55. input macrocell timing (3 V devices) -12 -15 -20 PT Turbo Symbol Parameter Conditions Unit Aloc off Min Max Min Max Min Max (1) t Input setup time 000 ns IS (1) t Input hold time 25 25 30 + 20 ns IH (1) t NIB input high time 12 13 15 ns INH (1) t NIB input low time 12 13 15 ns INL NIB input to combinatorial (1) t 46 62 70 + 4 + 20 ns INO delay 1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE latch timings refer to t and t . AVLX LXAX Doc ID 7833 Rev 7 105/128 AC/DC parameters PSD8XXFX Figure 44. READ timing 1 t t AVLX LXAX ALE/AS t LVLX A/D ADDRESS DATA MULTIPLEXED VALID VALID BUS t AVQV ADDRESS ADDRESS NON-MULTIPLEXED VALID BUS DATA DATA NON-MULTIPLEXED VALID BUS t SLQV CSI t RLQV t RHQX t RLRH RD tRHQZ (PSEN, DS) t EHEL E t t THEH ELTL R/W t AVPV ADDRESS OUT AI02895 1. t and t are not required for 80C251 in Page mode or 80C51XA in Burst mode. AVLX LXAX Table 56. READ timing (5 V devices) -70 -90 -15 Turbo Symbol Parameter Conditions Unit off Min Max Min Max Min Max t ALE or AS pulse width 15 20 28 ns LVLX (1) t Address setup time 4 6 10 ns AVLX (1) t Address hold time 7 8 11 ns LXAX (1) t Address valid to data valid 70 90 150 + 10 ns AVQV t CS valid to data valid 75 100 150 ns SLQV (2) RD to data valid 8-bit bus 24 32 40 ns t RLQV RD or PSEN to data valid (3) 31 38 45 ns 8-bit bus, 8031, 80251 (4) t RD data hold time 00 0 ns RHQX (4) t RD pulse width 27 32 38 ns RLRH (4) t RD to data high-Z 20 25 30 ns RHQZ t E pulse width 27 32 38 ns EHEL 106/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 56. READ timing (5 V devices) (continued) -70 -90 -15 Turbo Symbol Parameter Conditions Unit off Min Max Min Max Min Max t R/W setup time to Enable 6 10 18 ns THEH t R/W hold time After Enable 0 0 0 ns ELTL Address input valid to (5) t 20 25 30 ns AVPV Address output delay 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any port. Table 57. READ timing (3 V devices) -12 -15 -20 Turbo Symbol Parameter Conditions Unit off Min Max Min Max Min Max t ALE or AS pulse width 26 26 30 ns LVLX (1) t Address setup time 910 12 ns AVLX (1) t Address hold time 912 14 ns LXAX (1) t Address valid to data valid 120 150 200 + 20 ns AVQV t CS valid to data valid 120 150 200 ns SLQV (2) RD to data valid 8-bit bus 35 35 40 ns t RD or PSEN to data valid 8-bit bus, RLQV (3) 45 50 55 ns 8031, 80251 (4) t RD data hold time 00 0 ns RHQX t RD pulse width 38 40 45 ns RLRH (4) t RD to data high-Z 38 40 45 ns RHQZ t E pulse width 40 45 52 ns EHEL t R/W setup time to enable 15 18 20 ns THEH t R/W hold time after enable 0 0 0 ns ELTL Address input valid to (5) t 33 35 40 ns AVPV address output delay 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing for 8031. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode latched address generated from ADIO delay to address output on any port. Doc ID 7833 Rev 7 107/128 AC/DC parameters PSD8XXFX Figure 45. WRITE timing t t AVLX LXAX ALE/AS t LVLX A/D ADDRESS DATA MULTIPLEXED VALID VALID BUS t AVWL ADDRESS ADDRESS NON-MULTIPLEXED VALID BUS DATA DATA NON-MULTIPLEXED VALID BUS t SLWL CSI t DVWH t WHDX t WR WLWH t WHAX (DS) t EHEL E t t THEH ELTL R/ W t WLMV t t AVPV WHPV STANDARD ADDRESS OUT MCU I/O OUT AI02896 Table 58. WRITE timing (5 V devices) -70 -90 -15 Symbol Parameter Conditions Unit Min Max Min Max Min Max t ALE or AS pulse width 15 20 28 ns LVLX (1) t Address setup time 4 6 10 ns AVLX (1) t Address hold time 7 8 11 ns LXAX Address valid to leading (1)(2) t 815 20 ns AVWL edge of WR (2) t CS valid to leading edge of WR 12 15 20 ns SLWL (2) t WR data setup time 25 35 45 ns DVWH (2) t WR data hold time 45 5 ns WHDX (2) t WR pulse widthpulse width 31 35 45 ns WLWH (2) t Trailing edge of WR to address invalid 6 8 10 ns WHAX1 Trailing edge of WR to DPLD address (2)(3) t 00 0 ns WHAX2 invalid 108/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 58. WRITE timing (5 V devices) (continued) -70 -90 -15 Symbol Parameter Conditions Unit Min Max Min Max Min Max Trailing edge of WR to port output (2) t 27 30 38 ns WHPV valid using I/O port data register Data valid to port output valid (2)(4) t using macrocell register 42 55 65 ns DVMV Preset/Clear Address input valid to address (5) t 20 25 30 ns AVPV output delay WR valid to port output valid using (2)(6) t 48 55 65 ns WLMV macrocell register Preset/Clear 1. Any input used to select an internal PSD function. 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 3. t is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. WHAX2 4. Assuming WRITE is active before data becomes valid. 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port. 6. Assuming data is stable before active WRITE signal. Table 59. WRITE timing (3 V devices) -12 -15 -20 Symbol Parameter Conditions Unit MinMax MinMax MinMax t ALE or AS pulse width 26 26 30 LVLX (1) t Address setup time 910 12 ns AVLX (1) t Address hold time 912 14 ns LXAX Address valid to Leading (1)(2) t 17 20 25 ns AVWL Edge of WR (2) t CS valid to Leading Edge of WR 17 20 25 ns SLWL (2) t WR data setup time 45 45 50 ns DVWH (2) t WR data hold time 7 8 10 ns WHDX (2) t WR pulse width 46 48 53 ns WLWH (2) t Trailing edge of WR to address invalid 10 12 17 ns WHAX1 Trailing edge of WR to DPLD address (2)(3) t 00 0 ns WHAX2 invalid Trailing edge of WR to port output (2) t 33 35 40 ns WHPV valid using I/O port data register Data valid to port output valid (2)(4) t 70 70 80 ns DVMV using macrocell register Preset/Clear Doc ID 7833 Rev 7 109/128 AC/DC parameters PSD8XXFX Table 59. WRITE timing (3 V devices) (continued) -12 -15 -20 Symbol Parameter Conditions Unit Min Max Min Max Min Max (5) t Address input valid to address output delay 33 35 40 ns AVPV WR valid to port output valid using (2)(6) t 70 70 80 ns WLMV macrocell register Preset/Clear 1. Any input used to select an internal PSD function. 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 3. t is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. WHAX2 4. Assuming WRITE is active before data becomes valid. 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port. 6. Assuming data is stable before active WRITE signal. Table 60. Program, WRITE and Erase times (5 V devices) Symbol Parameter Min. Typ. Max. Unit Flash Program 8.5 s (1) Flash Bulk Erase (pre-programmed) 330 s Flash Bulk Erase (not pre-programmed) 5 s t Sector Erase (pre-programmed) 1 30 s WHQV3 t Sector Erase (not pre-programmed) 2.2 s WHQV2 t Byte Program 14 1200 µs WHQV1 Program/Erase cycles (per sector) 100,000 cycles t Sector Erase timeout 100 µs WHWLO (2) t DQ7 valid to output (DQ7-DQ0) valid (data polling) 30 ns Q7VQV 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 61. Program, WRITE and Erase times (3 V devices) Symbol Parameter Min. Typ. Max. Unit Flash Program 8.5 s (1) Flash Bulk Erase (pre-programmed) 330 s Flash Bulk Erase (not pre-programmed) 5 s t Sector Erase (pre-programmed) 1 30 s WHQV3 t Sector Erase (not pre-programmed) 2.2 s WHQV2 t Byte Program 14 1200 µs WHQV1 Program / Erase Cycles (per sector) 100,000 cycles t Sector Erase timeout 100 µs WHWLO (2) t DQ7 valid to Output (DQ7-DQ0) valid (data polling) 30 ns Q7VQV 110/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Figure 46. Peripheral I/O READ timing ALE/AS A/D BUS ADDRESS DATA VALID t (PA) AVQV t (PA) SLQV CSI t (PA) RLQV t (PA) QXRH t (PA) RHQZ RD t (PA) RLRH t (PA) DVQV DATA ON PORT A AI02897 Table 62. Port A Peripheral Data mode READ timing (5 V devices) -70 -90 -15 Turbo Symbol Parameter Conditions Unit off Min Max Min Max Min Max (1) t Address valid to data valid 37 39 45 + 10 ns AVQV–PA t CSI valid to data valid 27 35 45 + 10 ns SLQV–PA (2)(3) RD to data valid 21 32 40 ns t RLQV–PA RD to data valid 8031 mode 32 38 45 ns t Data In to data out valid 22 30 38 ns DVQV–PA t RD data hold time 0 0 0 ns QXRH–PA (2) t RD pulse width 27 32 38 ns RLRH–PA (2) t RD to data high-Z 23 25 30 ns RHQZ–PA 1. Any input used to select port A Data Peripheral mode. 2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). 3. Data is already stable on port A. Doc ID 7833 Rev 7 111/128 AC/DC parameters PSD8XXFX Table 63. Port A Peripheral Data mode READ timing (3V devices) -12 -15 -20 Turbo Symbol Parameter Conditions Unit off Min Max Min Max Min Max (1) t Address valid to data valid 50 50 50 + 20 ns AVQV–PA t CSI valid to data valid 37 45 50 + 20 ns SLQV–PA (2)(3) RD to data valid 37 40 45 ns t RLQV–PA RD to data valid 8031 mode 45 45 50 ns t Data In to data Out valid 38 40 45 ns DVQV–PA t RD data hold time 0 0 0 ns QXRH–PA (2) t RD pulse width 36 36 46 ns RLRH–PA (2) t RD to data high-Z 36 40 45 ns RHQZ–PA 1. Any input used to select port A Data Peripheral mode. 2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). 3. Data is already stable on port A. Figure 47. Peripheral I/O WRITE timing ALE/AS A/D BUS ADDRESS DATA OUT tWHQZ (PA) tWLQV (PA) WR tDVQV (PA) PORT A DATA OUT AI02898 Table 64. Port A Peripheral Data mode WRITE timing (5 V devices) -70 -90 -15 Symbol Parameter Conditions Unit Min Max Min Max Min Max (1) t WR to data propagation delay 25 35 40 ns WLQV–PA (2) t Data to port A data propagation delay 22 30 38 ns DVQV–PA (1) t WR invalid to port A tri-state 20 25 33 ns WHQZ–PA 1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 2. Data stable on ADIO pins to data on port A. 112/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 65. Port A Peripheral Data mode WRITE timing (3 V devices) -12 -15 -20 Symbol Parameter Conditions Unit Min Max Min Max Min Max (1) t WR to data propagation delay 42 45 55 ns WLQV–PA (2) t Data to port A data propagation delay 38 40 45 ns DVQV–PA (1) t WR invalid to port A tri-state 33 33 35 ns WHQZ–PA 1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 2. Data stable on ADIO pins to data on port A. Figure 48. Reset (RESET) timing V (min) CC V CC t NLNH t t t t NLNH-PO OPR NLNH-A OPR Power-On Reset Warm Reset RESET AI02866b Table 66. Reset (RESET) timing (5 V devices) Symbol Parameter Conditions Min Max Unit (1) t RESET active low time 150 ns NLNH t Power-on Reset active low time 1 ms NLNH–PO (2) t Warm Reset (on the PSD834Fx) 25 µs NLNH–A t RESET high to operational device 120 ns OPR 1. Reset (RESET) does not reset Flash memory program or erase cycles. 2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode. Table 67. Reset (RESET) timing (3 V devices) Symbol Parameter Conditions Min Max Unit (1) t RESET active low time 300 ns NLNH t Power-on Reset active low time 1 ms NLNH–PO (2) t Warm Reset (on the PSD834Fx) 25 µs NLNH–A t RESET high to operational device 300 ns OPR 1. Reset (RESET) does not reset Flash memory program or erase cycles. 2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode. Doc ID 7833 Rev 7 113/128 AC/DC parameters PSD8XXFX Figure 49. ISC timing t ISCCH TCK t ISCCL t t ISCPSU ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 68. ISC timing (5 V devices) -70 -90 -15 Symbol Parameter Conditions Unit Min Max Min Max Min Max Clock (TCK, PC1) frequency (except for (1) t 20 18 14 MHz ISCCF PLD) Clock (TCK, PC1) high time (except for (1) t 23 26 31 ns ISCCH PLD) Clock (TCK, PC1) low time (except for (1) t 23 26 31 ns ISCCL PLD) (2) t Clock (TCK, PC1) frequency (PLD only) 22 2MHz ISCCFP (2) t Clock (TCK, PC1) high time (PLD only) 240 240 240 ns ISCCHP (2) t Clock (TCK, PC1) low time (PLD only) 240 240 240 ns ISCCLP t ISC port setup time 7 8 10 ns ISCPSU t ISC port hold up time 5 5 5 ns ISCPH t ISC port clock to output 21 23 25 ns ISCPCO t ISC port high-impedance to valid output 21 23 25 ns ISCPZV ISC port valid output to t 21 23 25 ns ISCPVZ high-Impedance 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For program or erase PLD only. 114/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters Table 69. ISC timing (3 V devices) -12 -15 -20 Symbol Parameter Conditions Unit Min Max Min Max Min Max Clock (TCK, PC1) frequency (except for (1) t 12 10 9 MHz ISCCF PLD) Clock (TCK, PC1) high time (except for (1) t 40 45 51 ns ISCCH PLD) Clock (TCK, PC1) low time (except for (1) t 40 45 51 ns ISCCL PLD) (2) t Clock (TCK, PC1) frequency (PLD only) 22 2MHz ISCCFP (2) t Clock (TCK, PC1) high time (PLD only) 240 240 240 ns ISCCHP (2) t Clock (TCK, PC1) low time (PLD only) 240 240 240 ns ISCCLP t ISC port setup time 12 13 15 ns ISCPSU t ISC port hold up time 5 5 5 ns ISCPH t ISC port clock to output 30 36 40 ns ISCPCO t ISC port high-Impedance to valid Output 30 36 40 ns ISCPZV t ISC port valid Output to high-Impedance 30 36 40 ns ISCPVZ 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For program or erase PLD only. Table 70. Power-down timing (5 V devices) -70 -90 -15 Symbol Parameter Conditions Unit Min Max Min Max Min Max t ALE access time from Power-down 80 90 150 ns LVDV Maximum delay from APD Enable to Using CLKIN (1) t 15 * t µs CLWH CLCL Internal PDN valid signal (PD1) 1. t is the period of CLKIN (PD1). CLCL Table 71. Power-down timing (3 V devices) -12 -15 -20 Symbol Parameter Conditions Unit Min Max Min Max Min Max t ALE access time from Power-down 145 150 200 ns LVDV Maximum Delay from APD Enable to Using CLKIN (1) t 15 * t µs CLWH CLCL Internal PDN valid Signal (PD1) 1. t is the period of CLKIN (PD1). CLCL Doc ID 7833 Rev 7 115/128 Package mechanical PSD8XXFX 23 Package mechanical In order to meet environmental requirements, ST offers this device in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 116/128 Doc ID 7833 Rev 7 PSD8XXFX Package mechanical Figure 50. PQFP52 - 52-pin plastic quad flat package mechanical drawing D D1 D2 A2 e Ne E2 E1 E b N 1 Nd A CP L1 c A1 α L QFP-A 1. Drawing is not to scale. Table 72. PQFP52 - 52-pin plastic quad flat package mechanical dimensions mm inches Symbol Typ. Min. Max. Typ. Min. Max. A 2.350 0.0930 A1 0.250 0.0100 A2 2.000 1.800 2.100 0.0790 0.0770 0.0830 b 0.220 0.380 0.0090 0.0150 c 0.110 0.230 0.0040 0.0090 D 13.200 13.150 13.250 0.5200 0.5180 0.5220 D1 10.000 9.950 10.050 0.3940 0.3920 0.3960 D2 7.800 – – 0.3070 – – E 13.200 13.150 13.250 0.5200 0.5180 0.5220 E1 10.000 9.950 10.050 0.3940 0.3920 0.3960 E2 7.800 – – 0.3070 – – e 0.650 – – 0.0260 L 0.880 0.730 1.030 0.0350 0.0290 0.0410 L1 1.600 – – 0.0630 α 0° 7° 0° 7° N52 52 Nd 13 13 Ne 13 13 CP 0.100 0.0040 Doc ID 7833 Rev 7 117/128 Package mechanical PSD8XXFX Figure 51. PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing D A1 D1 A2 M1 M 1 N b1 e E1 E D2/E2 D3/E3 b L1 L C A CP PLCC-B 1. Drawing is not to scale. Table 73. PLCC52-52-lead plastic lead chip carrier mechanical dimensions mm inches Symbol Typ. Min. Max. Typ. Min. Max. A 4.190 4.570 0.1650 0.1800 A1 2.540 2.790 0.1000 0.1100 A2 – 0.910 – 0.0360 B 0.330 0.530 0.0130 0.0210 B1 0.660 0.810 0.0260 0.0320 C 0.2460 0.2610 0.0097 0.0103 D 19.940 20.190 0.7850 0.7950 D1 19.050 19.150 0.7500 0.7540 D2 17.530 18.540 0.6900 0.7300 E 19.940 20.190 0.7850 0.7950 E1 19.050 19.150 0.7500 0.7540 E2 17.530 18.540 0.6900 0.7300 e 1.270 – – 0.050 – – R 0.890 – – 0.035 – – N52 52 Nd 13 13 Ne 13 13 118/128 Doc ID 7833 Rev 7 PSD8XXFX Package mechanical Figure 52. TQFP64 - 64-lead thin quad flatpack, package outline D D1 D2 A2 e Ne E1 E E2 b N 1 Nd A CP L1 c A1 α L QFP-A 1. Drawing is not to scale. Table 74. TQFP64 - 64-lead thin quad flatpack, package mechanical data mm inches Symb. Typ. Min. Max. Typ. Min. Max. A 1.420 1.540 0.0560 0.0610 A1 0.100 0.070 0.140 0.0040 0.0030 0.0050 A2 1.400 1.360 1.440 0.0550 0.0540 0.0570 a 3.5°0.0°7.0°3.5°0.0°7.0° b 0.350 0.330 0.380 0.0140 0.0130 0.0150 c 0.170 0.006 D 16.000 15.900 16.100 0.6300 0.6260 0.6340 D1 14.000 13.980 14.030 0.5510 0.5500 0.5520 D2 12.000 11.950 12.050 0.4720 0.4700 0.4740 E 16.000 15.900 16.100 0.6300 0.6260 0.6340 E1 14.000 13.980 14.030 0.5510 0.5500 0.5520 E2 12.000 11.950 12.050 0.4720 0.4700 0.4740 e 0.800 0.750 0.850 0.0310 0.0300 0.0330 L 0.600 0.450 0.750 0.0240 0.0180 0.0300 L1 1.000 0.940 1.060 0.0390 0.0370 0.0420 CP 0.100 0.0040 N64 64 Nd 16 16 Ne 16 16 Doc ID 7833 Rev 7 119/128 Part numbering PSD8XXFX 24 Part numbering Table 75. Ordering information scheme Example: PSD8 1 3 F 2 V A – 15 J 1 T Device Type PSD8 = 8-bit PSD with register Logic SRAM Capacity 1 = 16 Kbit 3 = 64 Kbit 5 = 256 Kbit Flash Memory Capacity 3 = 1 Mbit (128K x 8) 4 = 2 Mbit (256K x 8) 2nd Flash Memory 2 = 256 Kbit Flash memory + SRAM 3 = SRAM but no Flash memory 4 = 256 Kbit Flash memory but no SRAM 5 = no Flash memory + no SRAM Operating voltage blank = V = 4.5 to 5.5V CC V = V = 3.0 to 3.6V CC Silicon Revision A = Revision A Speed 70 = 70ns 90 = 90ns 12 = 120ns 15 = 150ns 20 = 200ns Package J = ECOPACK-compliant PLCC52 M = ECOPACK-compliant PQFP52 U =ECOPACK-compliant TQFP64 Temperature Range blank = 0 to 70°C (commercial) I = –40 to 85°C (industrial) Option T = Tape & Reel Packing For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 120/128 Doc ID 7833 Rev 7 PSD8XXFX PQFP52 pin assignments Appendix A PQFP52 pin assignments Table 76. PQFP52 connections (see Features) Pin number Pin assignments 1PD2 2PD1 3PD0 4PC7 5PC6 6PC5 7PC4 8V CC 9GND 10 PC3 11 PC2 12 PC1 13 PC0 14 PA7 15 PA6 16 PA5 17 PA4 18 PA3 19 GND 20 PA2 21 PA1 22 PA0 23 AD0 24 AD1 25 AD2 26 AD3 27 AD4 28 AD5 29 AD6 30 AD7 31 V CC 32 AD8 Doc ID 7833 Rev 7 121/128 PQFP52 pin assignments PSD8XXFX Table 76. PQFP52 connections (see Features) (continued) Pin number Pin assignments 33 AD9 34 AD10 35 AD11 36 AD12 37 AD13 38 AD14 39 AD15 40 CNTL0 41 RESET 42 CNTL2 43 CNTL1 44 PB7 45 PB6 46 GND 47 PB5 48 PB4 49 PB3 50 PB2 51 PB1 52 PB0 122/128 Doc ID 7833 Rev 7 PSD8XXFX PLCC52 pin assignments Appendix B PLCC52 pin assignments Table 77. PLCC52 connections (see Features) Pin number Pin assignments 1GND 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 8PD2 9PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 15 V CC 16 GND 17 PC3 18 PC2 19 PC1 20 PC0 21 PA7 22 PA6 23 PA5 24 PA4 25 PA3 26 GND 27 PA2 28 PA1 29 PA0 30 AD0 31 AD1 32 AD2 Doc ID 7833 Rev 7 123/128 PLCC52 pin assignments PSD8XXFX Table 77. PLCC52 connections (see Features) (continued) Pin number Pin assignments 33 AD3 34 AD4 35 AD5 36 AD6 37 AD7 38 V CC 39 AD8 40 AD9 41 AD10 42 AD11 43 AD12 44 AD13 45 AD14 46 AD15 47 CNTL0 48 RESET 49 CNTL2 50 CNTL1 51 PB7 52 PB6 124/128 Doc ID 7833 Rev 7 PSD8XXFX TQFP64 pin assignments Appendix C TQFP64 pin assignments Table 78. TQFP64 connections (see Features) Pin number Pin assignments 1PD2 2PD1 3PD0 4PC7 5PC6 6PC5 7V CC 8V CC 9V CC 10 GND 11 GND 12 PC3 13 PC2 14 PC1 15 PC0 16 NC 17 NC 18 NC 19 PA7 20 PA6 21 PA5 22 PA4 23 PA3 24 GND 25 GND 26 PA2 27 PA1 28 PA0 29 AD0 30 AD1 31 N/D 32 AD2 Doc ID 7833 Rev 7 125/128 TQFP64 pin assignments PSD8XXFX Table 78. TQFP64 connections (see Features) (continued) Pin number Pin assignments 33 AD3 34 AD4 35 AD5 36 AD6 37 AD7 38 V CC 39 V CC 40 AD8 41 AD9 42 AD10 43 AD11 44 AD12 45 AD13 46 AD14 47 AD15 48 CNTL0 49 NC 50 RESET 51 CNTL2 52 CNTL1 53 PB7 54 PB6 55 GND 56 GND 57 PB5 58 PB4 59 PB3 60 PB2 61 PB1 62 PB0 63 NC 64 NC 126/128 Doc ID 7833 Rev 7 PSD8XXFX Revision history Revision history Table 79. Document revision history Date Revision Changes 15-Oct-99 1.0 Initial release as a WSI document 27-Oct-00 1.1 Port A Peripheral Data mode Read Timing, changed to 50 30-Nov-00 1.2 PSD85xF2 added 23-Oct-01 2.0 Document rewritten using the ST template 07-Apr-03 3.0 v2.2 Template applied; voltage correction (Table 75) 12-Jun-03 3.1 Fix errors in PQFQ52 Connections Correct Instructions (Table 10); update disclaimer, Title for EDOCS 02-Oct-03 3.2 application 17-Nov-03 3.3 Correct package references (Features) Reformatted (adjust RPN list); added Table 9; added ‘U’ package 04-Jun-04 4.0 (64-pin) (Features, Figure 3, Figure 52; Table 74, Table 75, Table 78); 5V split from original 05-Jan-06 5.0 Added Silicon Revision A into part numbering scheme. See Table 75 Document reformatted. Removed root part number PSD813F3. SRAM standby mode removed. Backup battery feature removed. 13-Feb-2009 6 All products are delivered in ECOPACK-compliant packages. Section 23: Package mechanical updated. Minor text modifications. Corrected pin 7 of TQFP64 package in Figure 3: TQFP64 05-May-2009 7 connections. Doc ID 7833 Rev 7 127/128 PSD8XXFX Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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