Digital Delay/Pulse Generator DG645 — Digital delay and pulse generator (4 or 8 channels) DG645 Digital Delay/Pulse Generator The DG645 is a versatile digital delay/pulse generator that · 4 pulse, 8 delay outputs (opt.) provides precisely defined pulses at repetition rates up to 10 MHz. The instrument offers several improvements over · <25 ps rms jitter older designs — lower jitter, higher accuracy, faster trigger rates, and more outputs. The DG645 also has Ethernet, GPIB and RS-232 interfaces for computer or network control of the · Trigger rates to 10 MHz instrument. · Precision rate generator Delay Generator Timing · Easy synchronization with All digital delay generators measure time intervals by 80 MHz mode locked lasers counting cycles of a fast clock (typically 100 MHz). Most digital delay generators also have short programmable analog · Fast transition times delays to achieve time intervals with finer resolution than the clock period. Unfortunately, one clock cycle of timing indeterminacy (typically 10 ns) can occur if the trigger is not · Ovenized crystal or Rb timebase (opt.) in phase with the clock. · Ethernet, GPIB and RS-232 interfaces The DG645 eliminates timing indeterminacy by measuring the timing of triggers with respect to the internal clock and compensating the analog delays. This approach reduces the jitter by about 100× and allows the internal rate generator to operate at any rate — not just a sub-multiple of the clock frequency. Triggering The DG645 has many trigger modes. An internal rate · DG645 ... $4195 (U.S. list) generator, with less than 100 ps period jitter, may be set Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com DG645 Digital Delay/Pulse Generator Front-panel outputs (50 ns/div) Combinatorial outputs showing 3 ns, 5 ns and 10 ns pulses with 1 ns transition times (5 ns/div) from 100 µHz to 10 MHz with 1 µHz resolution. An external and output offsets can range over ±2 VDC to source virtually trigger input, with adjustable threshold and slope, can trigger any logic level (NIM, ECL, PECL, CMOS, etc.). Output a timing cycle, a burst of cycles, or a single shot. A single transition times are less than 2 ns at any output amplitude. shot can be triggered with a key press. A line trigger operates synchronously with the AC mains. A rear-panel trigger inhibit Rear-Panel Outputs input can disable the trigger or any of the pulse outputs during a timing cycle. Optional rear-panel outputs are available to support diverse applications. Option 01 provides a T output and eight 0 The DG645 supports a number of complex triggering programmed delays (A, B, C, D, E, F, G and H) at 5 V requirements via a trigger holdoff and prescaling feature. logic levels, with transition times less than 1 ns. Option 02 provides these same outputs but as 30 V, 100 ns pulses with Trigger holdoff sets the minimum time between successive less than 5 ns transition times for timing distribution in high triggers. This is useful if a trigger event in your application noise environments. Option 03 provides eight combinatorial generates a significant noise transient that needs time to decay outputs which deliver one to four pulses at 5 V logic levels away before the next trigger is generated. Trigger holdoff can with less than 1 ns transition times. Each output has a 50 Ω also be used to trigger the DG645 at a sub-multiple of the source impedance. input trigger rate. Trigger prescaling enables the DG645 to be triggered 1 ms synchronously with a much faster source, but at a sub-multiple Standard Timebase of the original trigger frequency. For example, the DG645 can OCXO Timebase 100 µs be triggered at 1 kHz, but synchronously with a mode locked (opt. 4) laser running at 80 MHz, by prescaling the trigger input by Rubidium Timebase 10 µs 80,000. Furthermore, the DG645 also contains a separate (opt. 05) prescaler for each front-panel output, enabling each output to 1 µs operate at a sub-multiple of the trigger rate. Ideal External Timebase 100 ns Front-Panel Outputs 10 ns There are five front-panel outputs: T , AB, CD, EF and 0 1 ns GH. The T output is asserted for the duration of the timing 0 cycle. The leading edge of T is the zero time reference. The 0 100 ps programmed delays (A, B, C, D, E, F, G and H) are set from 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s 100 s 1000 s 0 s to 2000 s, with 5 ps resolution, to control the timing of the Delay leading and trailing edges of the four pulse outputs. Each front-panel output can drive a 50 Ω load and has a 50 Ω Timing error vs. programmed delay source impedance. Output amplitudes can be set from 0.5 to 5.0 V, Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com Max. Error (after 1 yr.) DG645 Digital Delay/Pulse Generator 10 µs Standard Timebase 1 µs OCXO Timebase (opt. 4) 100 ns Rubidium Timebase (opt. 05) 10 ns Ideal External Timebase 1 ns 100 ps 10 ps 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s 100 s 1000 s Delay Jitter vs. programmed delay Timebases The standard time base has an accuracy of 5 ppm, and a jitter –8 of 10 , which is suitable for many applications. Optional timebases are available for users who require better rate and delay accuracy or reduced rate and delay jitter. DG645 (cover removed) with optional Rb timebase. The timing error for a 1 s delay can be as large as 5 µs for the Rear panel shows the optional eight-channel outputs. standard timebase, 200 ns for the OCXO timebase, but is only 500 ps for the rubidium timebase (all 1 year after calibration.) For short delays the jitter is typically 20 ps. However, for a 1 s delay, the standard timebase can contribute up to 10 ns of jitter, while the optional timebases contribute less than 10 ps of additional jitter. Fast Rise Time Module The DG645 front-panel outputs have transition times of less than 2 ns. The SRD1 is an accessory, built into an in-line BNC Ordering Information connector, which reduces the rise time of a front-panel output DG645 Delay/pulse generator $4195 to less than 100 ps. Up to 5 SRD1s can be attached to the front Option 01 Eight delay channels (5 V) $750 panel to reduce the rise time of all of the outputs. Option 02 Eight delay channels (30 V) $950 Option 03 Combinatorial outputs $750 Option 04 OCXO timebase $750 Option 05 Rubidium timebase $1650 SRD1 100 ps rise time module $250 O645RMS Single rack mount kit $100 O645RMD Dual rack mount kit $100 SRD1 Fast Rise Time Module Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com Jitter (rms) DG645 Digital Delay/Pulse Generator SRS Tech More About the Outputs Note A timing cycle is initiated by an internal or external trigger. Option 02 rear-panel outputs provide 30 V, 100 ns timing The T output, whose leading edge is the zero-time reference, pulses at T , A, B, C, D, E, F, G and H. Output amplitudes are 0 0 is asserted 85 ns after the trigger. The delay settings (A, B, C, reduced to 15 V when driving 50 Ω loads. D, E, F, G and H) determine the timing of the front-panel and rear-panel outputs. 100 ns 30 V To 0 V A A The front-panel outputs have adjustable amplitude, offset, and B B polarity (non-inverted or inverted). C C D D E E F To Adj. F A B G AB G C D H CD H E F EF G H GH Opt. 02 rear-panel outputs (30 V) Front-panel outputs (adjustable) Option 03 rear-panel outputs provide outputs T , AB, CD, 0 Option 01 rear-panel outputs provide T and eight delay EF, GH (with the same definition as the front-panel outputs), 0 outputs (A, B, C, D, E, F, G and H) to allow the DG645 to be and (AB+CD), (EF+GH), (AB+CD+EF), (AB+CD+EF+GH) used as an 8-channel delay generator. The outputs go from which provide two, three, or four pulses per trigger. 0 to 5 V at their programmed delays, and return low 25 ns after the longest delay. 5 V 5 V To 0 V To A 0 V A B A AB B C D B CD C C AB+CD D E F D EF E G H E GH F F EF+GH G G AB+CD+EF H H AB+CD+EF+GH 25 ns Opt. 01 rear-panel outputs (5 V) Opt. 03 rear-panel combinatorial outputs (5 V) DG645 rear panel with Opt. 01 outputs Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com DG645 Specifications Delays General Channels 4 independent pulses controlled Computer interfaces GPIB (IEEE-488.2), RS-232, and in position and width. 8 delay Ethernet. All instrument functions channels available as an option can be controlled through the interfaces. (see Output Options). Non-volatile memory Nine sets of instrument configurations Range 0 to 2000 s can be stored and recalled. Resolution 5 ps Power <100 W, 90 to 264 VAC, 47 Hz to 63 Hz Accuracy 1 ns + (timebase error × delay) Dimensions 8.5" × 3.5" × 13" (WHD) Jitter (rms) Weight 9 lbs. Ext. trig. to any output 25 ps + (timebase jitter × delay) Warranty One year parts and labor on defects T to any output 15 ps + (timebase jitter × delay) in materials & workmanship 0 Trigger delay 85 ns (ext. trig. to T output) 0 Output Options Timebases Option 01 (8 Delay Outputs on Rear Panel) Model # Type Jitter Stability Aging Outputs (BNC) T , A, B, C, D, E, F, G and H (s/s) (20 to 30 °C) (ppm/yr) 0 Source impedance 50 Ω –8 –6 Std. crystal 10 2 × 10 5 Transition time <1 ns –11 –9 Opt. 4 OCXO 10 1 × 10 0.2 Overshoot <100 mV –11 –10 Opt. 5 Rb 10 1 × 10 0.0005 Level +5 V CMOS logic Pulse characteristics External input 10 MHz ± 10 ppm, sine >0.5 Vpp, Rising edge At programmed delay 1 kΩ impedance Falling edge 25 ns after longest delay Output 10 MHz, 2 Vpp sine into 50 Ω Option 02 (8 High-Voltage Delay Outputs on Rear Panel) External Trigger Outputs (BNC) T , A, B, C, D, E, F, G and H 0 Rate DC to 1/(100 ns + longest delay) Source impedance 50 Ω (maximum of 10 MHz) Transition time <5 ns Threshold ±3.50 VDC Levels 0 to 30 V into high impedance Slope Trigger on rising or falling edge 0 to 15 V into 50 Ω Impedance 1 MΩ + 15 pF (amplitude decreases by 1 %/kHz) Pulse Characteristics Internal Rate Generator Rising Edge At programmed delay Falling Edge 100 ns after the rising edge Trigger modes Continuous, line or single shot Rate 100 µHz to 10 MHz Option 03 (Combinatorial Outputs on Rear Panel) Resolution 1 µHz Accuracy Same as timebase Outputs (BNC) T , AB, CD, EF, GH, (AB + CD), 0 Jitter (rms) <25 ps (10 MHz/N trigger rate) (EF + GH), (AB + CD + EF), <100 ps (other trigger rates) (AB + CD + EF + GH) Source impedance 50 Ω Burst Generator Transition time <1 ns Overshoot <100 mV + 10 % of pulse amplitude Trigger to first T Pulse characteristics 0 Range 0 to 2000 s T , AB, CD, EF, GH Logic high for time between delays 0 Resolution 5 ps (AB + CD), (EF + GH) Two pulses created by the logic OR Period between pulses of the given channels Range 100 ns to 42.9 s (AB + CD + EF) Three pulses created by the logic OR Resolution 10 ns of the given channels 32 Delay cycles per burst 1 to 2 – 1 (AB + CD + EF + GH) Four pulses created by the logic OR of the given channels Outputs (T , AB, CD, EF, and GH) 0 Option SRD1 (Fast Rise Time Module) Source impedance 50 Ω Transition time <2 ns Rise time <100 ps Overshoot <100 mV + 10 % of pulse amplitude Fall time <3 ns Offset ±2 V Offset 0.8 V to 1.1 V Amplitude 0.5 to 5.0 V (level + offset <6.0 V) Amplitude 0.5 V to 5.0 V Accuracy 100 mV + 5 % of pulse amplitude Load 50 Ω Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com