M50FW080 8 Mbit (1M x8, Uniform Block) 3V Supply Firmware Hub Flash Memory FEATURES SUMMARY � SUPPLY VOLTAGE Figure 1. Packages –V = 3V to 3.6V for Program, Erase and CC Read Operations –V = 12V for Fast Program and Fast PP Erase (optional) � TWO INTERFACES – Firmware Hub (FWH) Interface for embedded operation with PC Chipsets – Address/Address Multiplexed (A/A Mux) PLCC32 (K) Interface for programming equipment compatibility � FIRMWARE HUB (FWH) HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Protection – Register Based Read and Write Protection TSOP32 (NB) – 5 Additional General Purpose Inputs for 8 x 14mm platform design flexibility – Synchronized with 33MHz PCI clock � PROGRAMMING TIME – 10µs typical – Quadruple Byte Programming Option � 16 UNIFORM 64 KByte MEMORY BLOCKS � PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block/Chip Erase algorithms TSOP40 (N) – Status Register Bits 10 x 20mm � PROGRAM and ERASE SUSPEND – Read other Blocks during Program/Erase Suspend – Program other Blocks during Erase Suspend � FOR USE in PC BIOS APPLICATIONS � ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 2Dh August 2004 1/47 M50FW080 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Communications (FWH0-FWH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CC V Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PP V Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SS BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/47 M50FW080 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PP Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 21 Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3/47 M50FW080 Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 14. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 16. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 17. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10.A/A Mux Interface AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 19. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 20. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 35 Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 36 Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 37 Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 37 Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 38 Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 38 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 20.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 41 4/47 M50FW080 Figure 21.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 42 Figure 22.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 43 Figure 23.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 24.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 45 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5/47 M50FW080 SUMMARY DESCRIPTION The M50FW080 is an 8 Mbit (1Mbit x8) non-vola- of a program or erase operation can be detected tile memory that can be read, erased and repro- and any error conditions identified. The command grammed. These operations can be performed set required to control the memory is consistent using a single low voltage (3.0 to 3.6V) supply. For with JEDEC standards. fast programming and fast erasing in production Two different bus interfaces are supported by the lines an optional 12V power supply can be used to memory. The primary interface, the Firmware Hub reduce the programming and the erasing times. (or FWH) Interface, uses Intel’s proprietary FWH The memory is divided into blocks that can be protocol. This has been designed to remove the erased independently so it is possible to preserve need for the ISA bus in current PC Chipsets; the valid data while old data is erased. Blocks can be M50FW080 acts as the PC BIOS on the Low Pin protected individually to prevent accidental Pro- Count bus for these PC Chipsets. gram or Erase commands from modifying the The secondary interface, the Address/Address memory. Program and Erase commands are writ- Multiplexed (or A/A Mux) Interface, is designed to ten to the Command Interface of the memory. An be compatible with current Flash Programmers for on-chip Program/Erase Controller simplifies the production line programming prior to fitting to a PC process of programming or erasing the memory by Motherboard. taking care of all of the special operations that are required to update the memory contents. The end 6/47 M50FW080 Figure 2. Logic Diagram (FWH Interface) Table 1. Signal Names (FWH Interface) FWH0-FWH3 Input/Output Communications V V FWH4 Input Communication Frame CC PP ID0-ID3 Identification Inputs 4 4 FGPI0-FGPI4 General Purpose Inputs FWH0- ID0-ID3 IC Interface Configuration FWH3 5 RP Interface Reset FGPI0- WP INIT CPU Reset FGPI4 CLK Clock FWH4 TBL M50FW080 TBL Top Block Lock CLK WP Write Protect IC Reserved for Future Use. Leave RFU disconnected RP V Supply Voltage CC INIT Optional Supply Voltage for Fast V PP Erase Operations V Ground SS V SS AI03979 NC Not Connected Internally Table 2. Signal Names (A/A Mux Interface) Figure 3. Logic Diagram (A/A Mux Interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs V V CC PP G Output Enable W Write Enable 11 8 RC Row/Column Address Select DQ0-DQ7 A0-A10 RB Ready/Busy Output RP Interface Reset RC V Supply Voltage M50FW080 CC IC RB Optional Supply Voltage for Fast V PP G Program and Fast Erase Operations W V Ground SS RP NC Not Connected Internally V SS AI03981 7/47 A/A Mux M50FW080 Figure 4. PLCC Connections A/A Mux A/A Mux 1 32 A7 FGPI1 IC (V ) IC (V ) IL IH A6 FGPI0 NC NC A5 WP NC NC A4 TBL V V SS SS A3 ID3 9 M50FW080 25 V V CC CC A2 ID2 INIT G A1 ID1 FWH4 W A0 ID0 RFU RB DQ0 FWH0 RFU DQ7 17 A/A Mux A/A Mux AI04897 Note: Pins 27 and 28 are not internally connected. Figure 5. TSOP32 Connections NC NC 1 32 INIT G NC NC FWH4/LFRAME W NC NC NC NC NC V RFU DQ7 SS IC (V ) IC RFU DQ6 IH A10 GPI4 RFU DQ5 RC CLK RFU DQ4 V V 8 25 CC CC M50FW080 FWH3/LAD3 DQ3 V V 9 24 V V PP PP SS SS RP RP FWH2/LAD2 DQ2 A9 GPI3 FWH1/LAD1 DQ1 A8 GPI2 FWH0/LAD0 DQ0 A7 GPI1 ID0 A0 A6 GPI0 ID1 A1 A5 WP ID2 A2 A4 TBL 16 17 ID3 A3 AI09757B 8/47 A/A Mux DQ1 FWH1 FGPI2 A8 DQ2 A9 FWH2 FGPI3 V V RP RP SS SS DQ3 FWH3 V V PP PP DQ4 RFU V V CC CC DQ5 RC RFU CLK DQ6 RFU FGPI4 A10 A/A Mux M50FW080 Figure 6. TSOP40 Connections NC NC 1 40 V V SS SS IC (V ) IC (V ) V V IH IL CC CC NC NC FWH4 W NC NC INIT G NC NC RFU RB NC NC RFU DQ7 A10 FGPI4 RFU DQ6 NC NC RFU DQ5 RC CLK RFU DQ4 V V 10 31 V V CC CC CC CC M50FW080 V V 11 30 V V PP PP SS SS RP RP V V SS SS NC NC FWH3 DQ3 NC NC FWH2 DQ2 A9 FGPI3 FWH1 DQ1 A8 FGPI2 FWH0 DQ0 A7 FGPI1 ID0 A0 A6 FGPI0 ID1 A1 A5 WP ID2 A2 TBL 20 21 ID3 A4 A3 AI03980 9/47 A/A Mux M50FW080 SIGNAL DESCRIPTIONS There are two distinct bus interfaces available on the Interface Configuration, IC, should not be this device. The active interface is selected before changed during operation. power-up, or during Reset, using the Interface To select the Firmware Hub (FWH) Interface the Configuration Pin, IC. Interface Configuration pin should be left to float or The signals for each interface are discussed in the driven Low, V ; to select the Address/Address IL Firmware Hub (FWH) Signal Descriptions section Multiplexed (A/A Mux) Interface the pin should be and the Address/Address Multiplexed (A/A Mux) driven High, V . An internal pull-down resistor is IH Signal Descriptions section, respectively, while included with a value of R ; there will be a leakage IL the supply signals are discussed in the Supply Sig- current of I through each pin when pulled to V ; LI2 IH nal Descriptions section. see Table 20.. Firmware Hub (FWH) Signal Descriptions Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface For the Firmware Hub (FWH) Interface see Figure Reset (RP) is set Low, V , the memory is in Reset IL 2. and Table 1.. mode: the outputs are put to high impedance and Input/Output Communications (FWH0-FWH3). the current consumption is minimized. When RP is All Input and Output Communication with the set High, V , the memory is in normal operation. IH memory take place on these pins. Addresses and After exiting Reset mode, the memory enters Data for Bus Read and Bus Write operations are Read mode. encoded on these pins. CPU Reset (INIT). The CPU Reset, INIT, pin is Input Communication Frame (FWH4). The In- used to Reset the memory when the CPU is reset. put Communication Frame (FWH4) signals the It behaves identically to Interface Reset, RP, and start of a bus operation. When Input Communica- the internal Reset line is the logical OR (electrical tion Frame is Low, V , on the rising edge of the IL AND) of RP and INIT. Clock a new bus operation is initiated. If Input Clock (CLK). The Clock, CLK, input is used to Communication Frame is Low, V , during a bus IL clock the signals in and out of the Input/Output operation then the operation is aborted. When In- Communication Pins, FWH0-FWH3. The Clock put Communication Frame is High, V , the cur- IH conforms to the PCI specification. rent bus operation is proceeding or the bus is idle. Top Block Lock (TBL). The Top Block Lock in- Identification Inputs (ID0-ID3).The Identifica- put is used to prevent the Top Block (Block 15) tion Inputs select the address that the memory re- from being changed. When Top Block Lock, TBL, sponds to. Up to 16 memories can be addressed is set Low, V , Program and Block Erase opera- IL on a bus. For an address bit to be ‘0’ the pin can tions in the Top Block have no effect, regardless of be left floating or driven Low, V ; an internal pull- IL the state of the Lock Register. When Top Block down resistor is included with a value of R . For IL Lock, TBL, is set High, V , the protection of the IH an address bit to be ‘1’ the pin must be driven Block is determined by the Lock Register. The High, V ; there will be a leakage current of I IH LI2 state of Top Block Lock, TBL, does not affect the through each pin when pulled to V ; see Table IH protection of the Main Blocks (Blocks 0 to 14). 20.. Top Block Lock, TBL, must be set prior to a Pro- By convention the boot memory must have ad- gram or Block Erase operation is initiated and dress ‘0000’ and all additional memories take se- must not be changed until the operation completes quential addresses starting from ‘0001’. or unpredictable results may occur. Care should General Purpose Inputs (FGPI0-FGPI4). The be taken to avoid unpredictable behavior by General Purpose Inputs can be used as digital in- changing TBL during Program or Erase Suspend. puts for the CPU to read. The General Purpose In- Write Protect (WP). The Write Protect input is put Register holds the values on these pins. The used to prevent the Main Blocks (Blocks 0 to 14) pins must have stable data from before the start of from being changed. When Write Protect, WP, is the cycle that reads the General Purpose Input set Low, V , Program and Block Erase operations IL Register until after the cycle is complete. These in the Main Blocks have no effect, regardless of pins must not be left to float, they should be driven the state of the Lock Register. When Write Protect, Low, V or High, V . IL, IH WP, is set High, V , the protection of the Block IH Interface Configuration (IC). The Interface Con- determined by the Lock Register. The state of figuration input selects whether the Firmware Hub Write Protect, WP, does not affect the protection of (FWH) or the Address/Address Multiplexed (A/A the Top Block (Block 15). Mux) Interface is used. The chosen interface must Write Protect, WP, must be set prior to a Program be selected before power-up or during a Reset or Block Erase operation is initiated and must not and, thereafter, cannot be changed. The state of be changed until the operation completes or un- 10/47 M50FW080 predictable results may occur. Care should be tak- Write Enable (W). The Write Enable, W, controls en to avoid unpredictable behavior by changing the Bus Write operation of the memory’s Com- WP during Program or Erase Suspend. mand Interface. Reserved for Future Use (RFU). These pins do Row/Column Address Select (RC).The Row/ not have assigned functions in this revision of the Column Address Select input selects whether the part. They must be left disconnected. Address Inputs should be latched into the Row Ad- dress bits (A0-A10) or the Column Address bits (A11-A19). The Row Address bits are latched on Table 3. Block Addresses the falling edge of RC whereas the Column Ad- Size Block dress bits are latched on the rising edge. Address Range Block Type (Kbytes) Number Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory’s Program/Erase 64 F0000h-FFFFFh 15 Top Block Controller. When Ready/Busy is Low, V , the OL 64 E0000h-EFFFFh 14 Main Block memory is busy with a Program or Erase operation and it will not accept any additional Program or 64 D0000h-DFFFFh 13 Main Block Erase command except the Program/Erase Sus- 64 C0000h-CFFFFh 12 Main Block pend command. When Ready/Busy is High, V , OH the memory is ready for any Read, Program or 64 B0000h-BFFFFh 11 Main Block Erase operation. 64 A0000h-AFFFFh 10 Main Block Supply Signal Descriptions 64 90000h-9FFFFh 9 Main Block The Supply Signals are the same for both interfac- es. 64 80000h-8FFFFh 8 Main Block V Supply Voltage. The V Supply Voltage CC CC 64 70000h-7FFFFh 7 Main Block supplies the power for all operations (Read, Pro- 64 60000h-6FFFFh 6 Main Block gram, Erase etc.). The Command Interface is disabled when the V CC 64 50000h-5FFFFh 5 Main Block Supply Voltage is less than the Lockout Voltage, 64 40000h-4FFFFh 4 Main Block V . This prevents Bus Write operations from ac- LKO cidentally damaging the data during power up, 64 30000h-3FFFFh 3 Main Block power down and power surges. If the Program/ 64 20000h-2FFFFh 2 Main Block Erase Controller is programming or erasing during this time then the operation aborts and the memo- 64 10000h-1FFFFh 1 Main Block ry contents being altered will be invalid. After V CC 64 00000h-0FFFFh 0 Main Block becomes valid the Command Interface is reset to Read mode. Address/Address Multiplexed (A/A Mux) A 0.1µF capacitor should be connected between Signal Descriptions the V Supply Voltage pins and the V Ground CC SS For the Address/Address Multiplexed (A/A Mux) pin to decouple the current surges from the power Interface see Figure 3. and Table 2.. supply. Both V Supply Voltage pins must be CC Address Inputs (A0-A10). The Address Inputs connected to the power supply. The PCB track are used to set the Row Address bits (A0-A10) and widths must be sufficient to carry the currents re- the Column Address bits (A11-A19). They are quired during program and erase operations. latched during any bus operation by the Row/Col- V Optional Supply Voltage. The V Optional PP PP umn Address Select input, RC. Supply Voltage pin is used to select the Fast Pro- Data Inputs/Outputs (DQ0-DQ7). The Data In- gram (see the Quadruple Byte Program Command puts/Outputs hold the data that is written to or read description) and Fast Erase options of the memory from the memory. They output the data stored at and to protect the memory. When V < V PP PPLK the selected address during a Bus Read opera- Program and Erase operations cannot be per- tion. During Bus Write operations they represent formed and an error is reported in the Status Reg- the commands sent to the Command Interface of ister if an attempt to change the memory contents the internal state machine. The Data Inputs/Out- is made. When V = V Program and Erase op- PP CC puts, DQ0-DQ7, are latched during a Bus Write erations take place as normal. When V = V PP PPH operation. Fast Program (if A/A Mux interface is selected) Output Enable (G). The Output Enable, G, con- and Fast Erase operations are used. Any other trols the Bus Read operation of the memory. voltage input to V will result in undefined behav- PP ior and should not be used. 11/47 M50FW080 V should not be set to V for more than 80 V Ground. V is the reference for all the volt- PP PPH SS SS hours during the life of the memory. age measurements. BUS OPERATIONS The two interfaces have similar bus operations but FWH3. The memory outputs Sync data until the the signals and timings are completely different. wait-states have elapsed. The Firmware Hub (FWH) Interface is the usual in- See Table 5. and Figure 8., for a description of the terface and all of the functionality of the part is Field definitions for each clock cycle of the trans- available through this interface. Only a subset of fer. See Table 22. and Figure 12., for details on the functions are available through the Address/Ad- timings of the signals. dress Multiplexed (A/A Mux) Interface. Bus Abort. The Bus Abort operation can be used See the sections: The Firmware Hub (FWH) Bus to immediately abort the current bus operation. A Operations and Address/Address Multiplexed (A/ Bus Abort occurs when FWH4 is driven Low, V , IL A Mux) Bus Operations, for details of the bus op- during the bus operation; the memory will tri-state erations on each interface. the Input/Output Communication pins, FWH0- Firmware Hub (FWH) Bus Operations FWH3. The Firmware Hub (FWH) Interface consists of Note that, during a Bus Write operation, the Com- four data signals (FWH0-FWH3), one control line mand Interface starts executing the command as (FWH4) and a clock (CLK). In addition protection soon as the data is fully received; a Bus Abort dur- against accidental or malicious data corruption ing the final TAR cycles is not guaranteed to abort can be achieved using two further signals (TBL the command; the bus, however, will be released and WP). Finally two reset signals (RP and INIT) immediately. are available to put the memory into a known Standby. When FWH4 is High, V , the memory IH state. is put into Standby mode where FWH0-FWH3 are The data signals, control signal and clock are de- put into a high-impedance state and the Supply signed to be compatible with PCI electrical specifi- Current is reduced to the Standby level, I . CC1 cations. The interface operates with clock speeds Reset. During Reset mode all internal circuits are up to 33MHz. switched off, the memory is deselected and the The following operations can be performed using outputs are put in high-impedance. The memory is the appropriate bus cycles: Bus Read, Bus Write, in Reset mode when Interface Reset, RP, or CPU Standby, Reset and Block Protection. Reset, INIT, is Low, V . RP or INIT must be held IL Low, V , for t . The memory resets to Read IL PLPH Bus Read. Bus Read operations read from the mode upon return from Reset mode and the Lock memory cells, specific registers in the Command Registers return to their default states regardless Interface or Firmware Hub Registers. A valid Bus of their state before Reset, see Table 14.. If RP or Read operation starts when Input Communication INIT goes Low, V , during a Program or Erase op- IL Frame, FWH4, is Low, V , as Clock rises and the IL eration, the operation is aborted and the memory correct Start cycle is on FWH0-FWH3. On the fol- cells affected no longer contain valid data; the lowing clock cycles the Host will send the Memory memory can take up to t to abort a Program PLRH ID Select, Address and other control bits on or Erase operation. FWH0-FWH3. The memory responds by output- ting Sync data until the wait-states have elapsed Block Protection.Block Protection can be followed by Data0-Data3 and Data4-Data7. forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the See Table 4. and Figure 7., for a description of the Lock Registers. Field definitions for each clock cycle of the trans- fer. See Table 22. and Figure 12., for details on the Address/Address Multiplexed (A/A Mux) Bus timings of the signals. Operations Bus Write. Bus Write operations write to the The Address/Address Multiplexed (A/A Mux) Inter- Command Interface or Firmware Hub Registers. A face has a more traditional style interface. The sig- valid Bus Write operation starts when Input Com- nals consist of a multiplexed address signals (A0- munication Frame, FWH4, is Low, V , as Clock A10), data signals, (DQ0-DQ7) and three control IL rises and the correct Start cycle is on FWH0- signals (RC, G, W). An additional signal, RP, can FWH3. On the following Clock cycles the Host will be used to reset the memory. send the Memory ID Select, Address, other control The Address/Address Multiplexed (A/A Mux) Inter- bits, Data0-Data3 and Data4-Data7 on FWH0- face is included for use by Flash Programming 12/47 M50FW080 equipment for faster factory programming. Only a Bus Write. Bus Write operations write to the subset of the features available to the Firmware Command Interface. A valid Bus Write operation Hub (FWH) Interface are available; these include begins by latching the Row Address and Column all the Commands but exclude the Security fea- Address signals into the memory using the Ad- tures and other registers. dress Inputs, A0-A10, and the Row/Column Ad- dress Select RC. The data should be set up on the The following operations can be performed using Data Inputs/Outputs; Output Enable, G, and Inter- the appropriate bus cycles: Bus Read, Bus Write, face Reset, RP, must be High, V and Write En- IH Output Disable and Reset. able, W, must be Low, V . The Data Inputs/ IL When the Address/Address Multiplexed (A/A Mux) Outputs are latched on the rising edge of Write En- Interface is selected all the blocks are unprotect- able, W. See Figure 15. and Table 25., for details ed. It is not possible to protect any blocks through of the timing requirements. this interface. Output Disable. The data outputs are high-im- Bus Read. Bus Read operations are used to out- pedance when the Output Enable, G, is at V . IH put the contents of the Memory Array, the Elec- Reset. During Reset mode all internal circuits are tronic Signature and the Status Register. A valid switched off, the memory is deselected and the Bus Read operation begins by latching the Row outputs are put in high-impedance. The memory is Address and Column Address signals into the in Reset mode when RP is Low, V . RP must be IL memory using the Address Inputs, A0-A10, and held Low, V for t . If RP is goes Low, V , dur- IL PLPH IL the Row/Column Address Select RC. Then Write ing a Program or Erase operation, the operation is Enable (W) and Interface Reset (RP) must be aborted and the memory cells affected no longer High, V , and Output Enable, G, Low, V , in order IH IL contain valid data; the memory can take up to t PL- to perform a Bus Read operation. The Data Inputs/ to abort a Program or Erase operation. RH Outputs will output the value, see Figure 14. and Table 24., for details of when the output becomes valid. Table 4. FWH Bus Read Field Definitions Clock Clock FWH0- Memory Cycle Cycle Field Description FWH3 I/O Number Count On the rising edge of CLK with FWH4 Low, the contents of 1 1 START 1101b I FWH0-FWH3 indicate the start of a FWH Read cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the 2 1 IDSEL XXXX I FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address phase is transferred starting with the most 3-9 7 ADDR XXXX I significant nibble first. 10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported). The host drives FWH0-FWH3 to 1111b to indicate a 11 1 TAR 1111b I turnaround cycle. 1111b The FWH Flash Memory takes control of FWH0-FWH3 12 1 TAR O (float) during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0101b 13-14 2 WSYNC 0101b O (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. The FWH Flash Memory drives FWH0-FWH3 to 0000b, 15 1 RSYNC 0000b O indicating that data will be available during the next clock cycle. Data transfer is two CLK cycles, starting with the least 16-17 2 DATA XXXX O significant nibble. 13/47 M50FW080 Clock Clock FWH0- Memory Cycle Cycle Field Description FWH3 I/O Number Count The FWH Flash Memory drives FWH0-FWH3 to 1111b to 18 1 TAR 1111b O indicate a turnaround cycle. 1111b The FWH Flash Memory floats its outputs, the host takes 19 1 TAR N/A (float) control of FWH0-FWH3. Figure 7. FWH Bus Read Waveforms CLK FWH4 FWH0-FWH3 START IDSEL ADDR MSIZE TAR SYNC DATA TAR Number of 11712322 clock cycles AI03437 Table 5. FWH Bus Write Field Definitions Clock Clock FWH0- Memory Cycle Cycle Field Description FWH3 I/O Number Count On the rising edge of CLK with FWH4 Low, the contents of 1 1 START 1110b I FWH0-FWH3 indicate the start of a FWH Write Cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the 2 1 IDSEL XXXX I FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address phase is transferred starting with the most 3-9 7 ADDR XXXX I significant nibble first. 10 1 MSIZE 0000b I Always 0000b (single byte transfer). Data transfer is two cycles, starting with the least significant 11-12 2 DATA XXXX I nibble. The host drives FWH0-FWH3 to 1111b to indicate a 13 1 TAR 1111b I turnaround cycle. 1111b The FWH Flash Memory takes control of FWH0-FWH3 14 1 TAR O (float) during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b, 15 1 SYNC 0000b O indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b, 16 1 TAR 1111b O indicating a turnaround cycle. 1111b The FWH Flash Memory floats its outputs and the host takes 17 1 TAR N/A (float) control of FWH0-FWH3. 14/47 M50FW080 Figure 8. FWH Bus Write Waveforms CLK FWH4 FWH0-FWH3 START IDSEL ADDR MSIZE DATA TAR SYNC TAR Number of 11712212 clock cycles AI03441 Table 6. A/A Mux Bus Operations Operation G W RP V DQ7-DQ0 PP Bus Read V V V Don’t Care Data Output IL IH IH Bus Write V V V V or V Data Input IH IL IH CC PPH Output Disable V V V Don’t Care Hi-Z IH IH IH V or V V or V V Reset Don’t Care Hi-Z IL IH IL IH IL Table 7. Manufacturer and Device Codes Operation G W RP A19-A1 A0 DQ7-DQ0 Manufacturer Code V V V V V 20h IL IH IH IL IL V V V V V Device Code 2Dh IL IH IH IL IH 15/47 M50FW080 COMMAND INTERFACE All Bus Write operations to the memory are inter- in the internal state machine and starts the Pro- preted by the Command Interface. Commands gram/Erase Controller. Once the command is is- consist of one or more sequential Bus Write oper- sued subsequent Bus Read operations read the ations. Status Register. See the section on the Status Register for details on the definitions of the Status After power-up or a Reset operation the memory Register bits. enters Read mode. If the address falls in a protected block then the The commands are summarized in Table 9., Com- Program operation will abort, the data in the mem- mands. The following text descriptions should be ory array will not be changed and the Status Reg- read in conjunction with Table 9.. ister will output the error. Read Memory Array Command.The Read During the Program operation the memory will Memory Array command returns the memory to its only accept the Read Status Register command Read mode where it behaves like a ROM or and the Program/Erase Suspend command. All EPROM. One Bus Write cycle is required to issue other commands will be ignored. Typical Program the Read Memory Array command and return the times are given in Table 14.. memory to Read mode. Once the command is is- sued the memory remains in Read mode until an- Note that the Program command cannot change a other command is issued. From Read mode Bus bit set at ‘0’ back to ‘1’ and attempting to do so will Read operations will access the memory array. not cause any modification on its value. One of the Erase commands must be used to set all of the While the Program/Erase Controller is executing a bits in the block to ‘1’. Program or Erase operation the memory will not accept the Read Memory Array command until the See Figure 19., for a suggested flowchart on using operation completes. the Program command. Read Status Register Command.The Read Quadruple Byte Program Command. The Qua- Status Register command is used to read the Sta- druple Byte Program Command can be only used tus Register. One Bus Write cycle is required to is- in A/A Mux mode to program four adjacent bytes sue the Read Status Register command. Once the in the memory array at a time. The four bytes must command is issued subsequent Bus Read opera- differ only for the addresses A0 and A10. Pro- tions read the Status Register until another com- gramming should not be attempted when V is PP mand is issued. See the section on the Status not at V . The operation can also be executed if PPH Register for details on the definitions of the Status V is below V , but result could be uncertain. PP PPH Register bits. Five Bus Write operations are required to issue the command. The second, the third and the fourth Read Electronic Signature Command. The Bus Write cycle latches respectively the address Read Electronic Signature command is used to and data of the first, the second and the third byte read the Manufacturer Code and the Device Code. in the internal state machine. The fifth Bus Write One Bus Write cycle is required to issue the Read cycle latches the address and data of the fourth Electronic Signature command. Once the com- byte in the internal state machine and starts the mand is issued subsequent Bus Read operations Program/Erase Controller. Once the command is read the Manufacturer Code or the Device Code issued subsequent Bus Read operations read the until another command is issued. Status Register. See the section on the Status After the Read Electronic Signature Command is Register for details on the definitions of the Status issued the Manufacturer Code and Device Code Register bits. can be read using Bus Read operations using the During the Quadruple Byte Program operation the addresses in Table 8.. memory will only accept the Read Status register command and the Program/Erase Suspend com- Table 8. Read Electronic Signature mand. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table Code Address Data 8.. Manufacturer Code 00000h 20h Note that the Quadruple Byte Program command Device Code 00001h 2Dh cannot change a bit set to ‘0’ back to ‘1’ and at- tempting to do so will not cause any modification Program Command. The Program command on its value. One of the Erase commands must be can be used to program a value to one address in used to set all of the bits in the block to ‘1’. the memory array at a time. Two Bus Write opera- See Figure 20., Quadruple Byte Program Flow- tions are required to issue the command; the sec- chart and Pseudo Code, for a suggested flowchart ond Bus Write cycle latches the address and data on using the Quadruple Byte Program command. 16/47 M50FW080 Chip Erase Command. The Chip Erase Com- The bits in the Status Register are sticky and do mand can be only used in A/A Mux mode to erase not automatically return to ‘0’ when a new Program the entire chip at a time. Erasing should not be at- or Erase command is issued. If an error occurs tempted when V is not at V . The operation then it is essential to clear any error bits in the Sta- PP PPH can also be executed if V is below V , but re- tus Register by issuing the Clear Status Register PP PPH sult could be uncertain. Two Bus Write operations command before attempting a new Program or are required to issue the command and start the Erase command. Program/Erase Controller. Once the command is Program/Erase Suspend Command. The Pro- issued subsequent Bus Read operations read the gram/Erase Suspend command can be used to Status Register. See the section on the Status pause a Program or Block Erase operation. One Register for details on the definitions of the Status Bus Write cycle is required to issue the Program/ Register bits. During the Chip Erase operation the Erase Suspend command and pause the Pro- memory will only accept the Read Status Register gram/Erase Controller. Once the command is is- command. All other commands will be ignored. sued it is necessary to poll the Program/Erase Typical Chip Erase times are given in Table 14.. Controller Status bit to find out when the Program/ The Chip Erase command sets all of the bits in the Erase Controller has paused; no other commands memory to ‘1’. See Figure 22., for a suggested will be accepted until the Program/Erase Control- flowchart on using the Chip Erase command. ler has paused. After the Program/Erase Control- Block Erase Command. The Block Erase com- ler has paused, the memory will continue to output mand can be used to erase a block. Two Bus Write the Status Register until another command is is- operations are required to issue the command; the sued. second Bus Write cycle latches the block address During the polling period between issuing the Pro- in the internal state machine and starts the Pro- gram/Erase Suspend command and the Program/ gram/Erase Controller. Once the command is is- Erase Controller pausing it is possible for the op- sued subsequent Bus Read operations read the eration to complete. Once Program/Erase Control- Status Register. See the section on the Status ler Status bit indicates that the Program/Erase Register for details on the definitions of the Status Controller is no longer active, the Program Sus- Register bits. pend Status bit or the Erase Suspend Status bit If the block is protected then the Block Erase oper- can be used to determine if the operation has com- ation will abort, the data in the block will not be pleted or is suspended. For timing on the delay be- changed and the Status Register will output the er- tween issuing the Program/Erase Suspend ror. command and the Program/Erase Controller pausing see Table 14.. During the Block Erase operation the memory will only accept the Read Status Register command During Program/Erase Suspend the Read Memo- and the Program/Erase Suspend command. All ry Array, Read Status Register, Read Electronic other commands will be ignored. Typical Block Signature and Program/Erase Resume com- Erase times are given in Table 14.. mands will be accepted by the Command Inter- face. Additionally, if the suspended operation was The Block Erase command sets all of the bits in Block Erase then the Program command will also the block to ‘1’. All previous data in the block is be accepted; only the blocks not being erased may lost. be read or programmed correctly. See Figure 22., for a suggested flowchart on using See Figure 21., and Figure 24., for suggested the Erase command. flowcharts on using the Program/Erase Suspend Clear Status Register Command.The Clear command. Status Register command can be used to reset Program/Erase Resume Command.The Pro- bits 1, 3, 4 and 5 in the Status Register to ‘0’. One gram/Erase Resume command can be used to re- Bus Write is required to issue the Clear Status start the Program/Erase Controller after a Register command. Once the command is issued Program/Erase Suspend has paused it. One Bus the memory returns to its previous mode, subse- Write cycle is required to issue the Program/Erase quent Bus Read operations continue to output the Resume command. Once the command is issued same data. subsequent Bus Read operations read the Status Register. 17/47 M50FW080 Table 9. Commands Bus Write Operations Command 1st 2nd 3rd 4th 5th Addr Data Addr Data Addr Data Addr Data Addr Data Read Memory Array 1 X FFh Read Status Register 1 X 70h 1X 90h Read Electronic Signature 1X 98h 2X 40h PA PD Program 2X 10h PA PD A A A A Quadruple Byte Program 5 X 30h PD PD PD PD 1 2 3 4 Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h 1X 00h 1X 01h Invalid/Reserved 1X 60h 1X 2Fh 1X C0h Note: X Don’t Care, PA Program Address, PD Program Data, A Consecutive Addresses, BA Any address in the Block. 1,2,3,4 Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com- mand is issued. Block Erase, Program. After these commands read the Status Register until the command completes and another command is is- sued. Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A , A , A and A must be consecutive addresses 1 2 3 4 differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another com- mand is issued. Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes and another command is issued. Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved. Do not use Invalid or Reserved commands. 18/47 Cycles M50FW080 STATUS REGISTER The Status Register provides information on the and still failed to verify that the block(s) has erased current or previous Program or Erase operation. correctly. The Erase Status bit should be read Different bits in the Status Register convey differ- once the Program/Erase Controller Status bit is ‘1’ ent information and errors on the operation. (Program/Erase Controller inactive). To read the Status Register the Read Status Reg- When the Erase Status bit is ‘0’ the memory has ister command can be issued. The Status Register successfully verified that the block(s) has erased is automatically read after Program, Erase and correctly; when the Erase Status bit is ‘1’ the Pro- Program/Erase Resume commands are issued. gram/Erase Controller has applied the maximum The Status Register can be read from any ad- number of pulses to the block(s) and still failed to dress. verify that the block(s) has erased correctly. The Status Register bits are summarized in Table Once the Erase Status bit is set to ‘1’ it can only be 10.. The following text descriptions should be read reset to ‘0’ by a Clear Status Register command or in conjunction with Table 10.. a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is is- Program/Erase Controller Status (Bit 7). The sued, otherwise the new command will appear to Program/Erase Controller Status bit indicates fail. whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Sta- Program Status (Bit 4). The Program Status bit tus bit is ‘0’, the Program/Erase Controller is ac- can be used to identify if the memory has applied tive; when the bit is ‘1’, the Program/Erase the maximum number of program pulses to the Controller is inactive. byte and still failed to verify that the byte has pro- grammed correctly. The Program Status bit should The Program/Erase Controller Status is ‘0’ imme- be read once the Program/Erase Controller Status diately after a Program/Erase Suspend command bit is ‘1’ (Program/Erase Controller inactive). is issued until the Program/Erase Controller paus- es. After the Program/Erase Controller pauses the When the Program Status bit is ‘0’ the memory has bit is ‘1’. successfully verified that the byte has pro- grammed correctly; when the Program Status bit is During Program and Erase operation the Pro- ‘1’ the Program/Erase Controller has applied the gram/Erase Controller Status bit can be polled to maximum number of pulses to the byte and still find the end of the operation. The other bits in the failed to verify that the byte has programmed cor- Status Register should not be tested until the Pro- rectly. gram/Erase Controller completes the operation and the bit is ‘1’. Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register com- After the Program/Erase Controller completes its mand or a hardware reset. If it is set to ‘1’ it should operation the Erase Status, Program Status, V PP be reset before a new Program or Erase command Status and Block Protection Status bits should be is issued, otherwise the new command will appear tested for errors. to fail. Erase Suspend Status (Bit 6). The Erase Sus- V Status (Bit 3). The V Status bit can be PP PP pend Status bit indicates that a Block Erase oper- used to identify an invalid voltage on the V pin PP ation has been suspended and is waiting to be during Program and Erase operations. The V PP resumed. The Erase Suspend Status should only pin is only sampled at the beginning of a Program be considered valid when the Program/Erase or Erase operation. Indeterminate results can oc- Controller Status bit is ‘1’ (Program/Erase Control- cur if V becomes invalid during a Program or PP ler inactive); after a Program/Erase Suspend com- Erase operation. mand is issued the memory may still complete the operation rather than entering the Suspend mode. When the V Status bit is ‘0’ the voltage on the PP V pin was sampled at a valid voltage; when the PP When the Erase Suspend Status bit is ‘0’ the Pro- V Status bit is ‘1’ the V pin has a voltage that PP PP gram/Erase Controller is active or has completed is below the V Lockout Voltage, V , the PP PPLK its operation; when the bit is ‘1’ a Program/Erase memory is protected; Program and Erase opera- Suspend command has been issued and the tion cannot be performed. memory is waiting for a Program/Erase Resume command. Once the V Status bit set to ‘1’ it can only be re- PP set to ‘0’ by a Clear Status Register command or a When a Program/Erase Resume command is is- hardware reset. If it is set to ‘1’ it should be reset sued the Erase Suspend Status bit returns to ‘0’. before a new Program or Erase command is is- Erase Status (Bit 5). The Erase Status bit can be sued, otherwise the new command will appear to used to identify if the memory has applied the fail. maximum number of erase pulses to the block(s) 19/47 M50FW080 Program Suspend Status (Bit 2). The Program gram or Block Erase operation has tried to modify Suspend Status bit indicates that a Program oper- the contents of a protected block. When the Block ation has been suspended and is waiting to be re- Protection Status bit is to ‘0’ no Program or Block sumed. The Program Suspend Status should only Erase operations have been attempted to protect- be considered valid when the Program/Erase ed blocks since the last Clear Status Register Controller Status bit is ‘1’ (Program/Erase Control- command or hardware reset; when the Block Pro- ler inactive); after a Program/Erase Suspend com- tection Status bit is ‘1’ a Program or Block Erase mand is issued the memory may still complete the operation has been attempted on a protected operation rather than entering the Suspend mode. block. When the Program Suspend Status bit is ‘0’ the Once it is set to ‘1’ the Block Protection Status bit Program/Erase Controller is active or has complet- can only be reset to ‘0’ by a Clear Status Register ed its operation; when the bit is ‘1’ a Program/ command or a hardware reset. If it is set to ‘1’ it Erase Suspend command has been issued and should be reset before a new Program or Block the memory is waiting for a Program/Erase Re- Erase command is issued, otherwise the new sume command. command will appear to fail. When a Program/Erase Resume command is is- Using the A/A Mux Interface the Block Protection sued the Program Suspend Status bit returns to Status bit is always ‘0’. ‘0’. Reserved (Bit 0). Bit 0 of the Status Register is Block Protection Status (Bit 1). The Block Pro- reserved. Its value should be masked. tection Status bit can be used to identify if the Pro- Table 10. Status Register Bits Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (1) Program active ‘0’ ‘0’‘0’‘0’‘0’‘0’ X (1) Program suspended ‘1 ‘0’‘0’‘0’‘1’‘0’ X (1) Program completed successfully ‘1’ ‘0’‘0’‘0’‘0’‘0’ X (1) Program failure due to V Error ‘1’ ‘0’‘0’‘1’‘0’‘0’ PP X (1) Program failure due to Block Protection (FWH Interface only) ‘1’ ‘0’‘0’‘0’‘0’‘1’ X (1) Program failure due to cell failure ‘1’ ‘0’‘1’‘0’‘0’‘0’ X Erase active ‘0’‘0’‘0’‘0’‘0’‘0’‘0’ Block Erase suspended ‘1’‘1’‘0’‘0’‘0’‘0’‘0’ Erase completed successfully ‘1’‘0’‘0’‘0’‘0’‘0’‘0’ Erase failure due to V Error ‘1’‘0’‘0’‘0’‘1’‘0’‘0’ PP Block Erase failure due to Block Protection (FWH Interface ‘1’‘0’‘0’‘0’‘0’‘0’‘1’ only) Erase failure due to failed cell(s) ‘1’‘0’‘1’‘0’‘0’‘0’‘0’ Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’. 20/47 M50FW080 FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS When the Firmware Hub Interface is selected sev- When V is less than V all blocks are pro- PP PPLK eral additional registers can be accessed. These tected and cannot be modified, regardless of the registers control the protection status of the state of the Write Lock Bit. If Top Block Lock, TBL, Blocks, read the General Purpose Input pins and is Low, V , then the Top Block (Block 15) is write IL identify the memory using the Electronic Signature protected and cannot be modified. Similarly, if codes. See Table 11. for the memory map of the Write Protect, WP, is Low, V , then the Main IL Configuration Registers. Blocks (Blocks 0 to 14) are write protected and cannot be modified. Lock Registers After power-up or reset the Write Lock Bit is al- The Lock Registers control the protection status of ways set to ‘1’ (write protected). the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the Read Lock. The Read Lock bit determines protection of each block, the Write Lock Bit, the whether the contents of the Block can be read Read Lock Bit and the Lock Down Bit. (from Read mode). When the Read Lock Bit is set, ‘1’, the block is read protected; any operation that The Lock Registers can be read and written, attempts to read the contents of the block will read though care should be taken when writing as, once 00h instead. When the Read Lock Bit is reset, ‘0’, the Lock Down Bit is set, ‘1’, further modifications read operations in the Block return the data pro- to the Lock Register cannot be made until cleared, grammed into the block as expected. to ‘0’, by a reset or power-up. After power-up or reset the Read Lock Bit is al- See Table 12. for details on the bit definitions of ways reset to ‘0’ (not read protected). the Lock Registers. Lock Down. The Lock Down Bit provides a Write Lock. The Write Lock Bit determines mechanism for protecting software data from sim- whether the contents of the Block can be modified ple hacking and malicious attack. When the Lock (using the Program or Block Erase Command). Down Bit is set, ‘1’, further modification to the When the Write Lock Bit is set, ‘1’, the block is Write Lock, Read Lock and Lock Down Bits cannot write protected; any operations that attempt to be performed. A reset or power-up is required be- change the data in the block will fail and the Status fore changes to these bits can be made. When the Register will report the error. When the Write Lock Lock Down Bit is reset, ‘0’, the Write Lock, Read Bit is reset, ‘0’, the block is not write protected Lock and Lock Down Bits can be changed. through the Lock Register and may be modified unless write protected through some other means. 21/47 M50FW080 Table 11. Firmware Hub Register Configuration Map Memory Default Mnemonic Register Name Access Address Value T_BLOCK_LK Top Block Lock Register (Block 15) FBF0002h 01h R/W T_MINUS01_LK Top Block [-1] Lock Register (Block 14) FBE0002h 01h R/W T_MINUS02_LK Top Block [-2] Lock Register (Block 13) FBD0002h 01h R/W T_MINUS03_LK Top Block [-3] Lock Register (Block 12) FBC0002h 01h R/W T_MINUS04_LK Top Block [-4] Lock Register (Block 11) FBB0002h 01h R/W T_MINUS05_LK Top Block [-5] Lock Register (Block 10) FBA0002h 01h R/W T_MINUS06_LK Top Block [-6] Lock Register (Block 9) FB90002h 01h R/W T_MINUS07_LK Top Block [-7] Lock Register (Block 8) FB80002h 01h R/W T_MINUS08_LK Top Block [-8] Lock Register (Block 7) FB70002h 01h R/W T_MINUS09_LK Top Block [-9] Lock Register (Block 6) FB60002h 01h R/W T_MINUS10_LK Top Block [-10] Lock Register (Block 5) FB50002h 01h R/W T_MINUS11_LK Top Block [-11] Lock Register (Block 4) FB40002h 01h R/W T_MINUS12_LK Top Block [-12] Lock Register (Block 3) FB30002h 01h R/W T_MINUS13_LK Top Block [-13] Lock Register (Block 2) FB20002h 01h R/W T_MINUS14_LK Top Block [-14] Lock Register (Block 1) FB10002h 01h R/W T_MINUS15_LK Top Block [-15] Lock Register (Block 0) FB00002h 01h R/W FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R MANUF_REG Manufacturer Code Register FBC0000h 20h R DEV_REG Device Code Register FBC0001h 2Dh R 22/47 M50FW080 Firmware Hub (FWH) General Purpose Input throughout the whole Bus Read cycle in order to Register guarantee that the correct data is read. The Firmware Hub (FWH) General Purpose Input Manufacturer Code Register Register holds the state of the Firmware Hub Inter- Reading the Manufacturer Code Register returns face General Purpose Input pins, FGPI0-FGPI4. the manufacturer code for the memory. The man- When this register is read, the state of these pins ufacturer code for STMicroelectronics is 20h. This is returned. This register is read-only and writing to register is read-only and writing to it has no effect. it has no effect. Device Code Register The signals on the Firmware Hub Interface Gener- Reading the Device Code Register returns the de- al Purpose Input pins should remain constant vice code for the memory, 2Dh. This register is read-only and writing to it has no effect. Table 12. Lock Register Bit Definitions Bit Bit Name Value Function 7-3 Reserved ‘1’ Bus Read operations in this Block always return 00h. 2 Read-Lock Bus read operations in this Block return the Memory Array contents. (Default ‘0’ value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ ‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP or INIT) or after power-up. 1 Lock-Down Read-Lock and Write-Lock can be changed by writing new values to them. (Default ‘0’ value). Program and Block Erase operations in this Block will set an error in the Status ‘1’ Register. The memory contents will not be changed. (Default value). 0 Write-Lock Program and Block Erase operations in this Block are executed and will modify the ‘0’ Block contents. Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Reg- ister (T_MINUS15_LK). Table 13. General Purpose Input Register Definition Bit Bit Name Value Function 7-5 Reserved ‘1’ Input Pin FGPI4 is at V IH 4FGPI4 ‘0’ Input Pin FGPI4 is at V IL ‘1’ Input Pin FGPI3 is at V IH 3FGPI3 ‘0’ Input Pin FGPI3 is at V IL Input Pin FGPI2 is at V ‘1’ IH 2FGPI2 ‘0’ Input Pin FGPI2 is at V IL ‘1’ Input Pin FGPI1 is at V IH 1FGPI1 Input Pin FGPI1 is at V ‘0’ IL ‘1’ Input Pin FGPI0 is at V IH 0FGPI0 Input Pin FGPI0 is at V ‘0’ IL Note: Applies to the General Purpose Input Register (FGPI_REG). 23/47 M50FW080 PROGRAM AND ERASE TIMES The Program and Erase times are shown in Table 14.. Table 14. Program and Erase Times (1) Parameter Interface Test Condition Min Max Unit Typ Byte Program 10 200 µs Quadruple Byte Program A/A Mux V = 12V ± 5% 10 200 µs PP Chip Erase A/A Mux V = 12V ± 5% 9sec PP (2) V = 12V ± 5% A/A Mux 5sec PP 0.1 Block Program V = V 0.4 5 sec PP CC V = 12V ± 5% 0.75 8 sec PP Block Erase V = V 110 sec PP CC (3) 5 µs Program/Erase Suspend to Program pause (3) 30 µs Program/Erase Suspend to Block Erase pause Note: 1. T = 25°C, V = 3.3V A CC 2. This time is obtained executing the Quadruple Byte Program Command. 3. Sampled only, not 100% tested. 24/47 M50FW080 MAXIMUM RATING Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con- Absolute Maximum Ratings table may cause per- ditions for extended periods may affect device manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics ratings only and operation of the device at these or SURE Program and other relevant quality docu- any other conditions above those indicated in the ments. Operating sections of this specification is not im- Table 15. Absolute Maximum Ratings Symbol Parameter Min. Max. Unit T Storage Temperature –65 150 °C STG 1 T Lead Temperature during Soldering °C LEAD See note 2 V –0.50 V + 0.6 V CC IO Input or Output range V Supply Voltage –0.50 4 V CC V Program Voltage –0.6 13 V PP 3 V –2000 2000 V ESD Electrostatic Discharge Voltage (Human Body model) ® Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to V + 2V for CC less than 20ns during transitions. 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 25/47 M50FW080 DC AND AC PARAMETERS This section summarizes the operating measure- Conditions summarized in Table 16., Table 17. ment conditions, and the DC and AC characteris- and Table 18.. Designers should check that the tics of the device. The parameters in the DC and operating conditions in their circuit match the oper- AC characteristics Tables that follow, are derived ating conditions when relying on the quoted pa- from tests performed under the Measurement rameters. Table 16. Operating Conditions Symbol Parameter Min. Max. Unit V Supply Voltage 3.0 3.6 V CC Ambient Operating Temperature (Device Grade 5) –20 85 °C T A Ambient Operating Temperature (Device Grade 1) 0 70 °C Table 17. FWH Interface AC Measurement Conditions Parameter Value Unit Load Capacitance (C ) 10 pF L Input Rise and Fall Times ≤ 1.4 ns 0.2 V and 0.6 V Input Pulse Voltages V CC CC Input and Output Timing Ref. Voltages 0.4 V V CC Table 18. A/A Mux Interface AC Measurement Conditions Parameter Value Unit Load Capacitance (C ) 30 pF L Input Rise and Fall Times ≤ 10 ns Input Pulse Voltages 0 to 3 V Input and Output Timing Ref. Voltages 1.5 V 26/47 M50FW080 Figure 9. FWH Interface AC Testing Input Output Waveforms 0.6 V CC 0.4 V CC 0.2 V CC Input and Output AC Testing Waveform I < I I > I I < I O LO O LO O LO Output AC Tri-state Testing Waveform AI03404 Figure 10. A/A Mux Interface AC Testing Input Output Waveform 3V 1.5V 0V AI01417 Table 19. Impedance Symbol Parameter Test Condition Min Max Unit (1) Input Capacitance V = 0V 13 pF C IN IN (1) V = 0V C Clock Capacitance 312 pF CLK IN Recommended Pin (2) 20 nH L PIN Inductance Note: 1. Sampled only, not 100% tested. 2. See PCI Specification. 3. T = 25°C, f = 1MHz. A 27/47 M50FW080 Table 20. DC Characteristics Symbol Parameter Interface Test Condition Min Max Unit FWH 0.5 V V + 0.5 V CC CC V Input High Voltage IH A/A Mux 0.7 V V + 0.3 V CC CC 0.3 V FWH –0.5 CC V V Input Low Voltage IL A/A Mux -0.5 0.8 V V (INIT) INIT Input High Voltage FWH 1.35 V + 0.5 V IH CC V (INIT) 0.2 V IL INIT Input Low Voltage FWH –0.5 CC V (2) Input Leakage Current 0V ≤ V ≤ V ±10 I IN CC µA LI IC, IDx Input Leakage I IC, ID0, ID1, ID2, ID3 = V 200 µA LI2 CC Current IC, IDx Input Pull Low R 20 100 kΩ IL Resistor FWH I = –500µA 0.9 V V CC OH V Output High Voltage OH V – 0.4 A/A Mux I = –100µA V OH CC I = 1.5mA 0.1 V FWH V OL CC V Output Low Voltage OL A/A Mux I = 1.8mA 0.45 V OL I Output Leakage Current 0V ≤ V ≤ V ±10 µA LO OUT CC V V Voltage 33.6 V PP1 PP V Voltage (Fast PP V 11.4 12.6 V PPH Program/Fast Erase) (1) V Lockout Voltage V PP 1.5 V PPLK (1) V Lockout Voltage 1.8 2.3 V V CC LKO FWH4 = 0.9 V , V = V CC PP CC I Supply Current (Standby) FWH All other inputs 0.9 V to 0.1 V 100 µA CC1 CC CC V = 3.6V, f(CLK) = 33MHz CC FWH4 = 0.1 V , V = V CC PP CC I Supply Current (Standby) FWH All other inputs 0.9 V to 0.1 V 10 mA CC2 CC CC V = 3.6V, f(CLK) = 33MHz CC V = V max, V = V Supply Current CC CC PP CC I (Any internal operation FWH f(CLK) = 33MHz 60 mA CC3 active) I = 0mA OUT I G = V , f = 6MHz Supply Current (Read) A/A Mux 20 mA CC4 IH Supply Current (1) A/A Mux Program/Erase Controller Active 20 mA I CC5 (Program/Erase) V Supply Current PP I V > V 400 µA PP PP CC (Read/Standby) V = V 40 mA PP CC V Supply Current PP (1) I PP1 (Program/Erase active) V = 12V ± 5% 15 mA PP Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs. 28/47 M50FW080 Figure 11. FWH Interface Clock Waveform tCYC tHIGH tLOW 0.6 V CC 0.5 V CC 0.4 V , CC p-to-p 0.4 V CC (minimum) 0.3 V CC 0.2 V CC AI03403 Table 21. FWH Interface Clock Characteristics Symbol Parameter Test Condition Value Unit (1) t Min 30 ns CYC CLK Cycle Time t CLK High Time Min 11 ns HIGH t CLK Low Time Min 11 ns LOW Min 1 V/ns CLK Slew Rate peak to peak Max 4 V/ns Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. 29/47 M50FW080 Figure 12. FWH Interface AC Signal Timing Waveforms CLK tCHQV tCHQZ tDVCH tCHQX tCHDX FWH0-FWH3 VALID VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA AI03405 Table 22. FWH Interface AC Signal Timing Characteristics PCI Symbol Parameter Test Condition Value Unit Symbol Min 2 ns t t CLK to Data Out CHQV val Max 11 ns CLK to Active (1) t Min 2 ns t on CHQX (Float to Active Delay) CLK to Inactive t t Max 28 ns CHQZ off (Active to Float Delay) t AVCH (2) t Min 7 ns su Input Set-up Time t DVCH t CHAX (2) t Min 0 ns h Input Hold Time t CHDX Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec- ification. 2. Applies to all inputs except CLK. 30/47 M50FW080 Figure 13. Reset AC Waveforms RP, INIT tPHWL, tPHGL, tPHFL tPLPH W, G, FWH4 tPLRH RB AI03420 Table 23. Reset AC Characteristics Symbol Parameter Test Condition Value Unit t RP or INIT Reset Pulse Width Min 100 ns PLPH Program/Erase Inactive Max 100 ns t RP or INIT Low to Reset PLRH Program/Erase Active Max 30 µs (1) Rising edge only Min 50 mV/ns RP or INIT Slew Rate t RP or INIT High to FWH4 Low FWH Interface only Min 30 µs PHFL t RP High to Write Enable or Output PHWL A/A Mux Interface only Min 50 µs t Enable Low PHGL Note: 1. See Chapter 4 of the PCI Specification. 31/47 M50FW080 Figure 14. A/A Mux Interface Read AC Waveforms tAVAV A0-A10 ROW ADDR VALID COLUMN ADDR VALID NEXT ADDR VALID tAVCL tAVCH tCLAX tCHAX RC tCHQV G tGLQV tGHQZ tGLQX tGHQX DQ0-DQ7 VALID W tPHAV RP AI03406 Table 24. A/A Mux Interface Read AC Characteristics Symbol Parameter Test Condition Value Unit t Read Cycle Time Min 250 ns AVAV t Row Address Valid to RC Low Min 50 ns AVCL t RC Low to Row Address Transition Min 50 ns CLAX t Column Address Valid to RC high Min 50 ns AVCH t RC High to Column Address Transition Min 50 ns CHAX (1) RC High to Output Valid Max 150 ns t CHQV (1) Output Enable Low to Output Valid Max 50 ns t GLQV t RP High to Row Address Valid Min 1 µs PHAV t Output Enable Low to Output Transition Min 0 ns GLQX t Output Enable High to Output Hi-Z Max 50 ns GHQZ t Output Hold from Output Enable High Min 0 ns GHQX Note: 1. G may be delayed up to t – t after the rising edge of RC without impact on t . CHQV GLQV CHQV 32/47 M50FW080 Figure 15. A/A Mux Interface Write AC Waveforms Write erase or Write erase confirm or Automated erase Read Status Ready to write program setup valid address and data or program delay Register Data another command A0-A10 R1 C1 R2 C2 tCLAX tAVCH tAVCL tCHAX RC tWHWL tWLWH tCHWH W tVPHWH tWHGL G tWHRL RB tQVVPL V PP tDVWH tWHDX DQ0-DQ7 D D VALID SRD IN1 IN2 AI04194 33/47 M50FW080 Table 25. A/A Mux Interface Write AC Characteristics Symbol Parameter Test Condition Value Unit t Write Enable Low to Write Enable High Min 100 ns WLWH t Data Valid to Write Enable High Min 50 ns DVWH t WHDX Write Enable High to Data Transition Min 5 ns t Row Address Valid to RC Low Min 50 ns AVCL t RC Low to Row Address Transition Min 50 ns CLAX t Column Address Valid to RC High Min 50 ns AVCH t RC High to Column Address Transition Min 50 ns CHAX t WHWL Write Enable High to Write Enable Low Min 100 ns t RC High to Write Enable High Min 50 ns CHWH (1) V High to Write Enable High Min 100 ns t PP VPHWH t Write Enable High to Output Enable Low Min 30 ns WHGL t Write Enable High to RB Low Min 0 ns WHRL (1,2) Output Valid, RB High to V Low Min 0 ns t PP QVVPL Note: 1. Sampled only, not 100% tested. 2. Applicable if V is seen as a logic input (V < 3.6V). PP PP 34/47 M50FW080 PACKAGE MECHANICAL Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline D A1 D1 A2 1 N B1 E2 e E3 E1 E F B 0.51 (.020) E2 1.14 (.045) D3 A R CP D2 D2 PLCC-A Note: Drawing is not to scale. 35/47 M50FW080 Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A 3.18 3.56 0.125 0.140 A1 1.53 2.41 0.060 0.095 A2 0.38 – 0.015 – B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 CP 0.10 0.004 D 12.32 12.57 0.485 0.495 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 D3 7.62 –– 0.300 –– E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 E3 10.16 –– 0.400 –– e1.27 –– 0.050 –– F 0.00 0.13 0.000 0.005 R0.89 –– 0.035 –– N32 32 36/47 M50FW080 Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline A2 1 N e E B N/2 D1 A D CP DIE C TSOP-a A1 α L Note: Drawing is not to scale. Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A 1.200 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 α 05 05 B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 CP 0.100 0.0039 D 13.800 14.200 0.5433 0.5591 D1 12.300 12.500 0.4843 0.4921 e0.500 –– 0.0197 –– E 7.900 8.100 0.3110 0.3189 L 0.500 0.700 0.0197 0.0276 N32 32 37/47 M50FW080 Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline A2 1 N e E B N/2 D1 A D CP DIE C TSOP-a A1 α L Note: Drawing is not to scale. Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A1.200 0 A1 0.050 0.150 0 0 A2 0.950 1.050 0 0 B 0.170 0.270 0 0 C 0.100 0.210 0 0 CP 0.100 0 D 19.800 20.200 1 1 D1 18.300 18.500 1 1 e0.500 –– 0 –– E 9.900 10.100 0 0 L 0.500 0.700 0 0 α 05 05 N40 40 38/47 M50FW080 PART NUMBERING Table 29. Ordering Information Scheme Example: M50FW080 N 5 T G Device Type M50 = Flash Memory for PC BIOS Architecture F = Firmware Hub Interface Operating Voltage W = V = 3.0 to 3.6V CC Device Function 080 = 8 Mbit (1Mbx8), Uniform Blocks Package K = PLCC32 NB = TSOP32: 8 x 14mm N = TSOP40: 10 x 20mm Device Grade 5 = Temperature range –20 to 85 °C. Device tested with standard test flow 1 = Temperature range 0 to 70 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free 2 3 Devices are shipped from the factory with the For a list of available options (Speed, Package, memory content bits erased to ’1’. etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 39/47 M50FW080 APPENDIX A. FLOWCHARTS AND PSEUDO CODES Figure 19. Program Flowchart and Pseudo Code Start Program command: Write 40h or 10h – Write 40h or 10h – Write Address and Data (memory enters read status state after the Program command) Write Address and Data do: NO – Read Status Register Read Status – If SR7=0 and a Program/Erase Suspend Register command has been executed Suspend YES – SR7 is set to 1 – Enter suspend program loop NO Suspend SR7 = 1 Loop YES NO V Invalid If SR3 = 1, PP SR3 = 0 Error (1, 2) – Enter the "V invalid" error handler PP YES NO Program If SR4 = 1, SR4 = 0 Error (1, 2) – Enter the "Program error" error handler YES FWH/LPC If SR1 = 1, NO Program to Protected Interface SR1 = 0 – Enter the "Program to protected Block Error (1, 2) Only block" error handler YES End AI08425B Note: 1. A Status check of SR1 (Protected Block), SR3 (V invalid) and SR4 (Program Error) can be made after each Program operation PP by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 40/47 M50FW080 Figure 20. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 (3) Quadruple Byte Program command: & Data 1 – write 30h (3) – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) Write Address 2 – write Address 3 & Data 3 (3) (3) & Data 2 – write Address 4 & Data 4 (memory enters read status state after the Quadruple Byte Program command) Write Address 3 (3) & Data 3 Write Address 4 (3) & Data 4 do: NO – Read Status Register Read Status – If SR7=0 and a Program/Erase Suspend Register command has been executed Suspend YES – SR7 is set to 1 – Enter suspend program loop NO Suspend SR7 = 1 Loop YES NO V Invalid If SR3 = 1, V invalid error: PP PP SR3 = 0 Error (1, 2) – error handler YES NO Program If SR4 = 1, Program error: SR4 = 0 Error (1, 2) – error handler YES End AI08437B Note: 1. A Status check of SR3 (V invalid) and SR4 (Program Error) can be made after each Program operation by following the correct PP command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1. 41/47 M50FW080 Figure 21. Program Suspend and Resume Flowchart and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h Write 70h – write 70h do: – read Status Register Read Status Register NO SR7 = 1 while SR7 = 0 YES NO SR2 = 1 Program Complete If SR2 = 0 Program completed YES Write a read Command Read data from another address Program/Erase Resume command: Write D0h Write FFh – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase Read Data Program Continues suspend was not issued). AI08426B Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. 42/47 M50FW080 Figure 22. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Chip Erase command: Write 80h – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) Write 10h do: – read Status Register Read Status Register NO while SR7 = 0 SR7 = 1 YES NO V Invalid If SR3 = 1, V invalid error: PP PP SR3 = 0 Error (1) – error handler YES NO Command If SR4, SR5 = 1, Command sequence error: SR4, SR5 = 0 Sequence Error (1) – error handler YES NO If SR5 = 1, Erase error: SR5 = 0 Erase Error (1) – error handler YES End AI08428B Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 43/47 M50FW080 Figure 23. Block Erase Flowchart and Pseudo Code Start Block Erase command: Write 20h/32h – Write 20h/32h – Write block Address and D0h (memory enters read Status Register after the Block Erase command) Write Block Address and D0h do: – Read Status Register NO Read Status – If SR7=0 and a Program/Erase Suspend Register command has been executed Suspend – SR7 is set to 1 YES – Enter suspend program loop NO Suspend SR7 = 1 Loop YES NO V Invalid If SR3 = 1, PP SR3 = 0 Error (1) – Enter the "V invalid" error handler PP YES NO Command If SR4, SR5 = 1, SR4, SR5 = 0 Sequence Error (1) – Enter the "Command sequence"error handler YES NO If SR5 = 1, SR5 = 0 Erase Error (1) – Enter the "Erase Error" error handler YES FWH/LPC If SR1 = 1, NO Erase to Protected Interface SR1 = 0 – Enter the "Erase to protected block" Block Error (1) Only error handler YES End AI08424B Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 44/47 M50FW080 Figure 24. Erase Suspend and Resume Flowchart and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h Write 70h – write 70h do: Read Status – read Status Register Register NO SR7 = 1 while SR7 = 0 YES NO SR6 = 1 Erase Complete If SR6 = 0, Erase completed YES Read data from another block/sector or Program Program/Erase Resume command: Write D0h Write FFh – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase Read Data Erase Continues suspend was not issued). AI08429B 45/47 M50FW080 REVISION HISTORY Table 30. Document Revision History Date Version Revision Details April 2001 -01 First Issue 18-May-2001 -02 Document type: from Product Preview to Preliminary Data 22-Jun-2001 -03 PLCC32 package added 6-Jul-2001 -04 Note 2 changed (Table 15., Absolute Maximum Ratings) 30-Jan-2002 -05 Document promoted from Preliminary Data to Full Data Sheet 01-Mar-2002 -06 RFU pins must be left disconnected 12-Mar-2002 -07 Specification of PLCC32 package mechanical data revised TSOP32 package added. Part numbering information updated. Flow-chart 19-May-2004 8.0 illustrations, in Appendix, updated. Document reformatted 19-Aug-2004 9.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected 46/47 M50FW080 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 47/47