SMCxxxBF 32-Mbyte, 64-Mbyte, 128-Mbyte, 256-Mbyte, 512-Mbyte, 1-Gbyte, 2-Gbyte and 4-Gbyte 3.3/5 V supply CompactFlash™ card Preliminary Data Features ■ Custom-designed, highly-integrated memory controller TM – Fully compliant with CompactFlash specification 3.0 – Fully compatible with PCMCIA specification – PC Card ATA interface supported – True IDE mode compatible – Up to PIO mode 6 supported TM – Up to 4 multi-word DMA supported CompactFlash – Hardware RS-code ECC (4-byte/528-byte correction) ■ Hot swappable ■ Small form factor ■ High performance – 36.4 mm x 42.8 mm x 3.3 mm – Up to 23.8 Mbyte/s transfer rate ■ Low-power CMOS technology – Sustained write performance (host to card): ■ 3.3 V / 5.0 V power supply 15 Mbyte/s ■ Power saving mode (with automatic wake-up) – Sustained read performance (host to card: ■ High reliability 22.5 Mbyte/s) – MTBF > 3,000,000 hours ■ Available densities (formatted) – Data reliability: < 1 non-recoverable error – 32 Mbytes to 4 Gbytes 14 per 10 bits read ■ Operating system support – Endurance: > 2,000,000 erase/program – Standard software drivers operation cycles – Number of card insertions/removals: >10,000 Table 1. Product list Reference Part number Package form factor Operating voltage range SMC032BF SMC064BF SMC128BF SMC256BF SMCxxxBF CF type I 3.3 V + 5%, 5 V + 10% SMC512BF SMC01GBF SMC02GBF SMC04GBF May 2008 Rev 4 1/90 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.numonyx.com 1 change without notice. Contents SMCxxxBF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Card physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Electrical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 Current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Additional requirements for CompactFlash advanced timing mode . . . . . 22 5 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Attribute memory read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Common memory read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 I/O read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 True IDE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Configuration option register (200h in attribute memory) . . . . . . . . . . . . . 33 6.1.1 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.2 LevlREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.3 Conf5 - Conf0 (configuration index) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Card configuration and status register (202h in attribute memory) . . . . . 34 6.2.1 Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.2 SigChg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.3 IOis8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.4 PwrDwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.5 Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Pin replacement register (204h in attribute memory) . . . . . . . . . . . . . . . . 35 6.3.1 CReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3.2 CWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2/90 SMCxxxBF Contents 6.3.3 RReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3.4 WProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3.5 MReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3.6 MWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 Socket and copy register (206h in attribute memory) . . . . . . . . . . . . . . . . 36 6.4.1 Drive # . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.2 X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 Attribute memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6 I/O transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.7 Common memory transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.8 True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Host configuration requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 Software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 CF-ATA drive register set definition and protocol . . . . . . . . . . . . . . . . . . . 42 8.2 Memory mapped addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 Contiguous I/O mapped addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.4 I/O primary and secondary address configurations . . . . . . . . . . . . . . . . . 45 8.5 True IDE mode addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 CF-ATA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 Error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.1 Bit 7 (BBK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.2 Bit 6 (UNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.3 Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.4 Bit 4 (IDNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.5 Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.6 Bit 2 (abort) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.7 Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.8 Bit 0 (AMNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 Feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.4 Sector count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5 Sector number (LBA 7-0) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3/90 Contents SMCxxxBF 9.6 Cylinder low (LBA 15-8) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.7 Cylinder high (LBA 23-16) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.8 Drive/head (LBA 27-24) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.1 Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.2 Bit 6 (LBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.3 Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.4 Bit 4 (DRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.5 Bit 3 (HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.6 Bit 2 (HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.7 Bit 1 (HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8.8 Bit 0 (HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.9 Status & alternate status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.1 Bit 7 (BUSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.2 Bit 6 (RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.3 Bit 5 (DWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.4 Bit 4 (DSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.5 Bit 3 (DRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.6 Bit 2 (CORR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.7 Bit 1 (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9.8 Bit 0 (ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10 Device control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10.1 Bit 7 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10.2 Bit 2 (SW Rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10.3 Bit 1 (–IEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10.4 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.11 Card (drive) address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.1 Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.2 Bit 6 (–WTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.3 Bit 5 (–HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.4 Bit 4 (–HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.5 Bit 3 (–HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.6 Bit 2 (–HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.7 Bit 1 (–nDS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11.8 Bit 0 (–nDS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 CF-ATA command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4/90 SMCxxxBF Contents 10.1 Check power mode (98h or E5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2 Execute drive diagnostic (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3 Erase sector(s) (C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4 Identify drive (ECh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.1 Word 0: general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.2 Word 1: default number of cylinders . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.3 Word 3: default number of heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.4 Word 6: default number of sectors per track . . . . . . . . . . . . . . . . . . . . . 58 10.4.5 Word 7-8: number of sectors per card . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.6 Word 10-19: memory card serial number . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.7 Word 23-26: firmware revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.8 Word 27-46: model number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.9 Word 47: read/write multiple sector count . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.10 Word 49: capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.11 Word 51: PIO data transfer cycle timing mode . . . . . . . . . . . . . . . . . . . 58 10.4.12 Word 53: translation parameter valid . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.13 Word 54-56: current number of cylinders, heads, sectors/track . . . . . . . 58 10.4.14 Word 57-58: current capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.15 Word 59: multiple sector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.16 Word 60-61: total sectors addressable in LBA mode . . . . . . . . . . . . . . . 59 10.4.17 Word 63: multi-word DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.18 Word 64: advanced PIO transfer modes supported . . . . . . . . . . . . . . . . 59 10.4.19 Word 65: minimum multi-word DMA transfer cycle time . . . . . . . . . . . . 60 10.4.20 Word 66: recommended multi-word DMA transfer cycle time . . . . . . . . 60 10.4.21 Word 67: minimum PIO transfer cycle time without flow control . . . . . . 60 10.4.22 Word 68: minimum PIO transfer cycle time with IORDY . . . . . . . . . . . . 60 10.4.23 Word 163: advanced true IDE timing mode capabilities and settings . . 60 10.4.24 Word 164: advanced PCMCIA I/O and memory timing modes capabilities and settings 61 10.5 Idle command (97h or E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.6 Idle Immediate command (95h or E1h) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.7 Initialize Drive Parameters command (91h) . . . . . . . . . . . . . . . . . . . . . . . 64 10.8 NOP command (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.9 Read Buffer command (E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.10 Read DMA command (C8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.11 Read Multiple command (C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5/90 Contents SMCxxxBF 10.12 Read Sector(s) command (20h or 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.13 Read Verify Sector(s) command (40h or 41h) . . . . . . . . . . . . . . . . . . . . . 68 10.14 Recalibrate command (1Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.15 Request Sense command (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.16 Seek command (7Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.17 Set Features command (EFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.18 Set Multiple Mode command (C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.19 Set Sleep Mode command (99h or E6h) . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.20 Standby command (96h or E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.21 Standby Immediate command (94h or E0h) . . . . . . . . . . . . . . . . . . . . . . . 74 10.22 Translate Sector command (87h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.23 Wear Level command (F5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.24 Write buffer command (E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.25 Write DMA command (CAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.26 Write Multiple command (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.27 Write Multiple without Erase command (CDh) . . . . . . . . . . . . . . . . . . . . . 79 10.28 Write Sector(s) command (30h or 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.29 Write Sector(s) without Erase command (38h) . . . . . . . . . . . . . . . . . . . . 80 10.30 Write Verify command (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 CIS information (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6/90 SMCxxxBF List of tables List of tables Table 1. Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. CF capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. System reliability and maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Pin assignment and pin type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Absolute maximum conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Output drive type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. Output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 16. Attribute memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 17. Configuration register (attribute memory) write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 18. Common memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 19. Common memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 20. I/O read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 21. I/O write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 22. True IDE PIO mode read/write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 23. True IDE multi-word DMA mode read/write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24. CompactFlash memory card registers and memory space decoding. . . . . . . . . . . . . . . . . 32 Table 25. CompactFlash memory card configuration registers decoding. . . . . . . . . . . . . . . . . . . . . . 33 Table 26. Configuration option register (default value: 00h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 27. CompactFlash memory card configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28. Card configuration and status register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29. Pin replacement register (default value: 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 30. Pin replacement changed bit/mask bit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 31. Socket and copy register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 32. Attribute memory function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 33. I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 34. Common memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 35. True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 36. I/O configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 37. Memory mapped decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 38. Contiguous I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 39. Primary and secondary I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 40. True IDE mode I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 41. Data register access (memory and I/O mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 42. Data register access (True IDE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 43. Error register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 44. Drive/head register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 45. Status & alternate status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 46. Device control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 47. Card (drive) address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 48. CF-ATA command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7/90 List of tables SMCxxxBF Table 49. Check power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 50. Execute drive diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 51. Diagnostic codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 52. Erase sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 53. Identify drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 54. Identify drive information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 55. Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 56. Idle Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 57. Initialize Drive Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 58. NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 59. Read Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 60. Read DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 61. Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 62. Read Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 63. Read Verify Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 64. Recalibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 65. Request Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 66. Extended error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 67. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 68. Set Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 69. Features supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 70. Transfer mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 71. Set Multiple Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 72. Set Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 73. Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 74. Standby Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 75. Translate Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 76. Translate Sector information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 77. Wear Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 78. Write Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 79. Write DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 80. Write Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 81. Write Multiple without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 82. Write Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 83. Write Sector(s) without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 84. Write Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 85. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8/90 SMCxxxBF List of figures List of figures Figure 1. CompactFlash memory card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. Attribute memory read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 3. Configuration register (attribute memory) write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 4. Common memory read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5. Common memory write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. I/O read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7. I/O write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 8. True IDE PIO mode read/write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9. True IDE multi-word DMA mode read/write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 10. Type I CompactFlash memory card dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9/90 Description SMCxxxBF 1 Description The CompactFlash is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The card operates in three basic modes: ● PCMCIA I/O mode ● PCMCIA memory mode ● True IDE mode The CompactFlash also supports advanced timing modes. Advanced timing modes are PCMCIA style I/O modes that are 100 ns or faster, PCMCIA memory modes that are 100 ns or faster, true IDE PIO modes 5,6 and multi-word DMA modes 3,4. It conforms to the PC card specification when operating in the PCMCIA I/O mode, and in the PCMCIA memory mode (personal computer memory card international association standard, JEIDA in Japan), and to the ATA specification when operating in true IDE mode. CompactFlash cards can be used with passive adapters in a PC-card type II or type III socket. The card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as hardware RS-code error correction code (ECC), defect handling, diagnostics and clock control. Once the card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The hardware RS-code ECC allows to detect and correct 4 bytes per 528 bytes. The specification has been realized and approved by the CompactFlash association (CFA). This non-proprietary specification enables users to develop CF products that function correctly and are compatible with future CF design. The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7. Related documentation ● PCMCIA PC card standard, 1995 ● PCMCIA PC card ATA specification, 1995 ● AT attachment interface document, american national standards institute, X3.221-1994 ● CF+ and CompactFlash specification revision 3.0. 10/90 SMCxxxBF Description Table 2. System performance System performance Max Unit Sleep to write 0.05 ms Sleep to read 0.15 ms Power-up to ready 480 ms (1) Data transfer rate (burst) 23.8 (162X) Mbyte/s (1) Sustained read 22.5 (150X) Mbyte/s (1) Sustained write 15 (100X) Mbyte/s Read 135 Command to DRQ µs Write 50 1. 162X, 130X and 85X, speed grade markings where 1X = 150 Kbytes/s. All values are measured for an ambient temperature of 25 °C. They refer to the 1-Gbyte CompactFlash card in PIO mode 6, cycle time 80 ns, File size = 20 Mbytes sequential; sector count = 256. (1) Table 3. Current consumption Current consumption (typ) 3.3 V 5 V Unit Read 23 30 mA Write 40 45 mA Standby 1.0 2.0 mA Sleep mode 1.0 2.0 mA 1. All values are typical at 25 °C and nominal supply voltage and refer to 1-Gbyte CompactFlash card, operating in PIO mode. Table 4. Environmental specifications Environmental specifications Operating Non-operating Temperature –40 to 85 °C –50 to 100 °C Humidity (non-condensing) N/A 85% RH, at 85 °C (1) Salt water spray N/A 3% NaCl at 35 °C Vibration (peak -to-peak) N/A 30Gmax. Shock N/A 3,000Gmax. 1. MIL STD METHOD 1009. Table 5. Physical dimensions Physical dimensions Unit Width 42.8 mm Height 36.4 mm Thickness 3.3 mm Weight (typ.) 10 g 11/90 Capacity specification SMCxxxBF 2 Capacity specification This section Table 6 shows the specific capacity for the various CF models and the default number of heads, sector/tracks and cylinders. Table 6. CF capacity specification Total Part Default_ Default_sectors addressable Capacity Default_cylinders Sectors_card number heads _track capacity (byte) SMC032BF 32 Mbytes 490 4 32 62,720 32,112,640 SMC064BF 64 Mbytes 490 8 32 125,440 64,225,280 SMC128BF 128 Mbytes 980 8 32 250,880 128,450,560 SMC256BF 256 Mbytes 980 16 32 501,760 256,901,120 SMC512BF 512 Mbytes 993 16 63 1,000,944 512,483,328 SMC01GBF 1 Gbyte 1,986 16 63 2,001,888 1,024,966,656 SMC02GBF 2 Gbytes 3,970 16 63 4,001,760 2,048,901,120 SMC04GBF 4 Gbytes 7,964 16 63 8,027,712 4,110,188,544 Table 7. System reliability and maintenance MTBF (at 25 °C) > 3,000,000 hours Insertions/removals > 10,000 Preventive maintenance None 14 Data reliability < 1 non-recoverable error per 10 bits read (1) 0 +70 °C > 2,000,000 erase/program cycles Endurance (1) -40 +85 °C > 600,000 erase/program cycles 1. Dependent on final system qualification data. 12/90 SMCxxxBF Card physical 3 Card physical 3.1 Physical description The CompactFlash memory card contains a single chip controller and flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the flash memory module(s). Figure 1 shows the block diagram of the CompactFlash memory card. The card is offered in a type I package with a 50-pin connector consisting of two rows of 25 female contacts on 50 mil (1.27 mm) centers. Figure 10 shows type I card dimensions. Figure 1. CompactFlash memory card block diagram Data In/Out Host Flash Controller interface module(s) Control CompactFlash storage card AI04300 13/90 Electrical interface SMCxxxBF 4 Electrical interface 4.1 Electrical description The CompactFlash memory card operates in three basic modes: ● PC card ATA using I/O mode ● PC card ATA using memory mode ● True IDE mode, which is compatible with most disk drives. The signal/pin assignments are listed in Table 8 Low active signals have a ‘–’ prefix. Pin types are input, output or input/output. The configuration of the card is controlled using the standard PCMCIA configuration registers starting at address 200h in the attribute memory space of the memory card. Table 9 describes the I/O signals. Inputs are signals sourced from the host while outputs are signals sourced from the card. The signals are described for each of the three operating modes. All outputs from the card are totem pole except the data bus signals that are bi-directional tri-state. Refer to the Section 4.2: Electrical specification for definitions of input and output type. Table 8. Pin assignment and pin type PC card memory mode PC card I/O mode True IDE mode Pin Signal Pin In, Out Signal Pin In, Out Signal Pin In, Out Num name type type name type type name type type 1 GND Ground GND Ground GND Ground 2 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3 D03 I/O I1Z,OZ3 3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3 D04 I/O I1Z,OZ3 4 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3 D05 I/O I1Z,OZ3 5 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3 D06 I/O I1Z,OZ3 6 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3 D07 I/O I1Z,OZ3 7 –CE1 I I3U –CE1 I I3U –CS0 I I3Z (2) 8 A10 I I1Z A10 I I1Z A10 II1Z (1) 9 –OE I I3U –OE I I3U –ATASEL I I3U (2) 10 A09 I I1Z A09 I I1Z A09 II1Z (2) 11 A08 I I1Z A08 I I1Z A08 II1Z (2) 12 A07 I I1Z A07 I I1Z A07 II1Z 13 V Power V Power V Power CC CC CC (2) 14 A06 I I1Z A06 I I1Z A06 II1Z (2) 15 A05 I I1Z A05 I I1Z A05 II1Z (2) 16 A04 I I1Z A04 I I1Z A04 II1Z 14/90 SMCxxxBF Electrical interface Table 8. Pin assignment and pin type (continued) PC card memory mode PC card I/O mode True IDE mode Pin Signal Pin In, Out Signal Pin In, Out Signal Pin In, Out Num name type type name type type name type type (2) 17 A03 I I1Z A03 I I1Z A03 II1Z 18 A02 I I1Z A02 I I1Z A02 I I1Z 19 A01 I I1Z A01 I I1Z A01 I I1Z 20 A00 I I1Z A00 I I1Z A00 I I1Z 21 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 22 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 23 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 24 WP O OT3 –IOIS16 O OT3 –IOIS16 O ON3 25 –CD2 O Ground –CD2 O Ground –CD2 O Ground 26 –CD1 O Ground –CD1 O Ground –CD1 O Ground (3) (3) (3) 27 D11 I/O I1Z,OZ3 D11 I/O I1Z,OZ3 D11 I/O I1Z,OZ3 (3) (3) (3) 28 D12 I/O I1Z,OZ3 D12 I/O I1Z,OZ3 D12 I/O I1Z,OZ3 (3) (3) (3) 29 D13 I/O I1Z,OZ3 D13 I/O I1Z,OZ3 D13 I/O I1Z,OZ3 (3) (3) (3) 30 D14 I/O I1Z,OZ3 D14 I/O I1Z,OZ3 D14 I/O I1Z,OZ3 (3) (3) (3) 31 D15 I/O I1Z,OZ3 D15 I/O I1Z,OZ3 D15 I/O I1Z,OZ3 (3) (3) (3) 32 –CE2 II3U –CE2 II3U –CS1 II3Z 33 –VS1 O Ground –VS1 O Ground –VS1 O Ground 34 –IORD I I3U –IORD I I3U –IORD I I3Z 35 –IOWR I I3U –IOWR I I3U –IOWR I I3Z (4) 36 –WE I I3U –WE I I3U –WE II3U 37 READY O OT1 -IREQ O OT1 INTRQ O OZ1 38 V Power V Power V Power CC CC CC (5)(3) (5) (5) 39 –CSEL II2Z –CSEL II2Z –CSEL II2U 40 –VS2 O OPEN –VS2 O OPEN –VS2 O OPEN 41 RESET I I2Z RESET I I2Z -RESET I I2Z 42 –WAIT O OT1 –WAIT O OT1 IORDY O ON1 43 –INPACK O OT1 –INPACK O OT1 DMARQ O OZ1 (6) 44 –REG I I3U –REG I I3U -DMACK II3U 45 BVD2 I/O I1U,OT1 –SPKR I/O I1U,OT1 –DASP I/O I1U,ON1 46 BVD1 I/O I1U,OT1 –STSCHG I/O I1U,OT1 –PDIAG I/O I1U,ON1 (3) (3) (3) 47 D08 I/O I1Z,OZ3 D08 I/O I1Z,OZ3 D08 I/O I1Z,OZ3 (3) (3) (3) 48 D09 I/O I1Z,OZ3 D09 I/O I1Z,OZ3 D09 I/O I1Z,OZ3 15/90 Electrical interface SMCxxxBF Table 8. Pin assignment and pin type (continued) PC card memory mode PC card I/O mode True IDE mode Pin Signal Pin In, Out Signal Pin In, Out Signal Pin In, Out Num name type type name type type name type type (3) (3) (3) 49 D10 I/O I1Z,OZ3 D10 I/O I1Z,OZ3 D10 I/O I1Z,OZ3 50 GND Ground GND Ground GND Ground 1. For True IDE mode, pin 9 is grounded. 2. The signal should be grounded by the host. 3. These signals are required only for 16-bit accesses and not required when installed in 8-bit systems. Devices should allow for 3-state signals not to consume current. 4. The signal should be tied to V by the host. CC 5. The -CSEL signal is ignored by the card in PC card modes. However, because it is not pulled up on the card in these modes it should not be left floating by the host in PC card modes. In these modes, the pin is normally connected by the host to PC card A25 or grounded by the host. 6. When the device does not operate in DMA mode, the signal should be held High or tied to V by the host. To ensure CC proper operation with older hosts when DMA mode is disabled, the card should ignore the –DMACK signal. Table 9. Signal descriptions Signal name Dir. Pin Description Used (with –REG) to select: the I/O port address registers, A10 to A0 the memory mapped port address registers, a byte in the card information structure and its configuration control and (PC card memory mode) 8,10,11,12, status registers. I 14,15,16,17, A10 to A0 Same as PC card memory mode 18,19,20 (PC card I/O mode) A2 to A0 Only A2 to A0 are used to select the one of eight registers in the task file, the remaining lines should be grounded. (True IDE mode) BVD1 The battery voltage status of the card, as no battery is required it is asserted High. (PC card memory mode) Alerts the host to changes in the ready and write protect –STSCHG I/O 46 states. Its use is controlled by the card configuration and (PC card I/O mode) status register. –PDIAG The Pass Diagnostic signal in the master/slave handshake protocol. (True IDE mode) BVD2 The battery voltage status of the card, as no battery is required it is asserted High. (PC card memory mode) –SPKR The Binary Audio output from the card. It is asserted High I/O 45 as audio functions are not supported. (PC card I/O mode) –DASP This input/output is the Disk Active/Slave Present signal in the master/slave handshake protocol. (True IDE mode) 16/90 SMCxxxBF Electrical interface Table 9. Signal descriptions (continued) Signal name Dir. Pin Description Carry the data, commands and status information between D15-D00 the host and the controller. D00 is the LSB of the even byte (PC card memory mode) of the word. D08 is the LSB of the odd byte of the word. 31,30,29,28, 27,49,48,47, D15-D00 I/O Same as PC card memory mode. 6,5,4,3,2, (PC card I/O mode) 23,22,21 D15-D00 All task file operations occur in byte mode on D00 to D07 while all data transfers are 16 bits using D00 to D15. (True IDE mode) GND Ground. (PC card memory mode) GND 1,50 Same for all modes. (PC card I/O mode) GND Same for all modes. (True IDE mode) –INPACK Not used, should not be connected to the host. (PC card memory mode) The input acknowledge is asserted when the card is –INPACK selected and responding to an I/O read cycle at the current address on the bus. It is used by the host to control the (PC card I/O mode) enable of any input data buffers between the card and CPU. The DMARQ input signal is used to request a DMA data transfer between the host and the card. It is asserted to notify that the card is ready to transfer data to or from the O43 host. For multi-word DMA transfers, the direction of data transfer is controlled by -IORD and -IOWR. DMARQ is used in conjunction with –DMACK to perform DMARQ handshaking: the card waits until –DMACK has been (True IDE mode) asserted by the host to de-assert DMARQ, and re-assert it again if there is still data to be transferred (see Section 10.10). DMARQ is not driven when the card is not selected. If the host does not support DMA mode, DMARQ should be left unconnected. –IORD Not used. (PC card memory mode) –IORD I/O read strobe generated by the host. It gates I/O data onto I34 the bus. (PC card I/O mode) –IORD Same as PC card I/O mode. (True IDE mode) 17/90 Electrical interface SMCxxxBF Table 9. Signal descriptions (continued) Signal name Dir. Pin Description These are connected to ground on the card. They are used –CD1, –CD2 by the host to determine that the card is fully inserted into its (PC card memory mode) socket. –CD1, –CD2 O 26,25 Same for all modes. (PC card I/O mode) –CD1, –CD2 Same for all modes. (True IDE mode) Used to select the card and to indicate whether a byte or a word operation is being performed. –CE2 accesses the odd –CE1, –CE2 Byte, –CE1 accesses the even byte or the odd byte depending on A0 and –CE2. A multiplexing scheme based (PC card memory mode) on A0, –CE1, –CE2 allows 8-bit hosts to access all data on D0 to D7. –CE1, –CE2 I7,32 Same as PC card memory mode. (PC card I/O mode) –CS0 is the chip select for the task file registers, while –CS1 selects the alternate status register and the device control –CS0, –CS1 register. (True IDE mode) When –DMACK is asserted, -CS0 and –CS1 must be de- asserted and data width is 16 bits. –CSEL Not used. (PC card memory mode) –CSEL I 39 Not used. (PC card I/O mode) This internally pulled up signal is used to configure the card –CSEL as a master or slave. When grounded it is configured as a (True IDE mode) master, when open it is configured as a slave. –IOWR Not used. (PC card memory mode) The I/O write strobe pulse is used to clock I/O data on the –IOWR I35 bus into the card controller registers. Clocking occurs on the (PC card I/O mode) rising edge. –IOWR Same as PC card I/O mode. (True IDE mode) This is an Output Enable strobe generated by the host –OE interface. It reads data and the CIS and configuration (PC card memory mode) registers. –OE I9 Reads the CIS and configuration registers. (PC card I/O mode) –ATASEL This input signal must be driven Low to enable true IDE mode. (True IDE mode) 18/90 SMCxxxBF Electrical interface Table 9. Signal descriptions (continued) Signal name Dir. Pin Description Indicates whether the card is busy (Low), or ready to accept a new data transfer operation (High). The host socket must provide a pull-up resistor. At power-up and reset, the Ready READY signal is held Low until the commands are completed. No (PC card memory mode) access should be made during this time. The Ready signal is held High whenever the card has been powered up with O37 Reset continuously disconnected or asserted. –IREQ Interrupt request. It is strobed Low to generate a pulse mode interrupt or held Low for a level mode interrupt. (PC card I/O mode) INTRQ Active High interrupt request to the host. (True IDE mode) Used to distinguish between common memory and register –REG (attribute) memory accesses. High for common memory, (PC card memory mode) Low for attribute memory. –REG Must be Low during I/O cycles when the I/O address is on the bus. (PC card I/O mode) The –DMACK input signal is used to acknowledge DMA I44 transfers. It is asserted by the host in response to DMARQ to initiate the transfer. –DMACK When DMA mode is disabled, the card should ignore the -DMACK signal. (True IDE mode) If the host does not support DMA mode, but only True IDE mode, this signal should be driven High or tied to V by the CC host. RESET Resets the card (active High). The card is reset at power-up only if this pin is left High or unconnected. (PC card memory mode) RESET I41 Same as PC card memory mode. (PC card I/O mode) –RESET Hardware reset from the host (active Low). (True IDE mode) V CC +5 V, +3.3 V power. (PC card memory mode) V CC 13,38 Same for all modes. (PC card I/O mode) V CC Same for all modes. (True IDE mode) Voltage sense signals.–VS1 is grounded so that the CIS –VS1, –VS2 can be read at 3.3 volts and –VS2 is reserved by PCMCIA (PC card memory mode) for a secondary voltage. –VS1, –VS2 O 33,40 Same for all modes. (PC card I/O mode) –VS1, –VS2 Same for all modes. (True IDE mode) 19/90 Electrical interface SMCxxxBF Table 9. Signal descriptions (continued) Signal name Dir. Pin Description –WAIT (PC card memory mode) –WAIT O 42 Numonyx CF does not assert the WAIT (IORDY) signal (PC card I/O mode) IORDY (True IDE mode) –WE Driven by the host to strobe memory write data to the registers. (PC card memory mode) –WE I36 Used for writing to the configuration registers. (PC card I/O mode) –WE Not used, should be connected to V by the host. CC (True IDE mode) WP No write protect switch available. It is held Low after the completion of the reset initialization sequence. (PC card memory mode) Used for the 16-bit port (–IOIS16) function. Low indicates –IOIS16 O24 that a 16-bit or odd byte only operation can be performed at (PC card I/O mode) the addressed port. –IOCS16 Asserted Low when the card is expecting a word data transfer cycle. (True IDE mode) 20/90 SMCxxxBF Electrical interface 4.2 Electrical specification Table 10 defines the DC characteristics for the CompactFlash memory card. Unless otherwise stated, conditions are: ● V = 5 V ± 10% CC ● V = 3.3 V ± 5% CC ● -40 °C to 85 °C. Table 11 shows that the card operates correctly in both the voltage ranges and that the current requirements must not exceed the maximum limit shown. Table 10. Absolute maximum conditions Parameter Symbol Conditions Input power V − 0.3 V to 6.5 V CC Voltage on any pin except V with respect to GND V − 0.5 V to V + 0.5 V CC CC Table 11. Input power Voltage Maximum average RMS current Measurement conditions 3.3 V ± 5% 85 − 40 + 85 °C 5V ± 10% 100 − 40 + 85 °C 4.3 Current measurement The current is measured by connecting an amp meter in series with the V supply. The CC meter should be set to the 2A scale range, and have a fast current probe with an RC filter with a time constant of 0.1 ms. Current measurements are taken while looping on a data transfer command with a sector count of 128. Current consumption values for both read and write commands are not to exceed the maximum average RMS current specified in Table 11. Table 12 shows the input leakage current, Table 13 the input characteristics, Table 14 the output drive type and Table 15 the output drive characteristics. (1) Table 12. Input leakage current Type Parameter Symbol Conditions Min Typ Max Units V = V IH CC IxZ Input leakage current IL − 11 µA V = GND IL IxU Pull up resistor RPU1 V = 5.0 V 50 500 kΩ CC IxD Pull down resistor RPD1 V = 5.0 V 50 500 kΩ CC 1. x refers to the characteristics described in Table 13. For example, I1U indicates a pull up resistor with a type 1 input characteristic. 21/90 Electrical interface SMCxxxBF Table 13. Input characteristics MinTyp Max Min TypMax Type Parameter Symbol Units V = 3.3 V V = 5.0 V CC CC V 2.4 3.3 Input voltage IH 1 V CMOS V 0.6 0.8 IL V 1.5 2.0 Input voltage IH 2 V CMOS V 0.6 0.8 IL Input voltage V 1.8 2.8 TH CMOS 3 V V 1.0 2.0 TL Schmitt Trigger (1) Table 14. Output drive type Type Output type Valid conditions OTx Totempole I & I OH OL OZx Tri-state N-P channel I & I OH OL OPx P-channel only I only OH ONx N-channel only I only OL 1. x refers to the characteristics described in Table 15. For example, OT3 refers to totem pole output with a type 3 output drive characteristic. Table 15. Output drive characteristics Type Parameter Symbol Conditions Min Typ Max Units V I = -4 mA V − 0.8 V OH OH CC 1 Output voltage V V I = 4 mA Gnd + 0.4 V OL OL V I = -4 mA V − 0.8 V OH OH CC 2 Output voltage V V I = 4 mA Gnd + 0.4 V OL OL V I = -4 mA V − 0.8 V OH OH CC 3 Output voltage V V I = 4 mA Gnd + 0.4 V OL OL I V = Gnd Tri-state OZ OL X –10 10 µA leakage current V = V OH CC 4.4 Additional requirements for CompactFlash advanced timing mode When operating in a CompactFlash advanced timing mode, the following conditions must be respected: ● Only one CompactFlash card must be connected to the CompactFlash bus ● The load capacitance (cable included) for all signals must be lower than 40 pF ● The cable length must be lower than 0.15 m (6 inches). The cable length is measured from the card connector to the host controller. 0.46 m (18 inches) cables are not supported. 22/90 SMCxxxBF Command interface 5 Command interface There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, direct mapped I/O transfer and memory access. Two types of bus cycles are also available in true IDE interface type: PIO transfer and multi-word DMA transfer. Table 16, Table 17, Table 18, Table 19, Table 20, Table 21 and Table 22 show the read and write timing parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8 show the read and write timing diagrams. In order to set the card mode, the -OE (-ATASEL) signal must be set and kept stable before applying V until the reset phase is completed. To place the card in memory mode or I/O CC mode, -OE(-ATASEL) must be driven High, while it must be driven Low to place the card in true IDE mode. 5.1 Attribute memory read and write Figure 2. Attribute memory read waveforms tc(R) Address Inputs VALID ta(A) tv(A) –REG tsu(A) ta(CE) –CE2/–CE1 tdis(CE) ta(OE) ten(CE) –OE ten(OE) tdis(OE) D0 to D15 (D ) VALID OUT AI10080 1. D signifies data provided by the CompactFlash memory card to the system. The -CE signal or both the -OE signal and OUT the -WE signal must be de-asserted between consecutive cycle operations. 23/90 Command interface SMCxxxBF Table 16. Attribute memory read timing Speed version 300 ns Symbol IEEE symbol Parameter Min Max Unit tc(R) t Read cycle time 300 ns AVAV ta(A) t Address access time 300 ns AVQV ta(CE) t CE access time 300 ns ELQV ta(OE) t OE access time 150 ns GLQV tdis(CE) t Output disable time from CE 100 ns EHQZ tdis(OE) t Output disable time from OE 100 ns GHQZ ten(CE) t Output enable time from CE 5 ns ELQNZ ten(OE) t Output enable time from OE 5 ns GLQNZ tv(A) t Data valid from address change 0 ns AXQX tsu(A) t Address setup time 30 ns AVGL Figure 3. Configuration register (attribute memory) write waveforms tc(W) –REG Address Inputs VALID tsu(A) tw(WE) trec(WE) –WE tsu(D-WEH) th(D) –CE2/–CE1 –OE D0 to D15 (D ) DATA IN VALID IN AI10081 1. D signifies data provided by the system to the CompactFlash card. IN Table 17. Configuration register (attribute memory) write timing Speed version 250 ns Symbol IEEE symbol Parameter Min Max Unit tc(W) t Write cycle time 250 ns AVAV tw(WE) t Write pulse width 150 ns WLWH tsu(A) t Address setup time 30 ns AVWL tsu(D-WEH) t Data setup time from WE 80 ns DVWH th(D) t Data hold time 30 ns WMDX trec(WE) t Write recovery time 30 ns WMAX 24/90 SMCxxxBF Command interface 5.2 Common memory read and write Figure 4. Common memory read waveforms Address Inputs VALID tsu(A) th(A) –REG th(CE) –CE2/–CE1 tsu(CE) ta(OE) –OE tdis(OE) tv(WT) D0 to D15 (D ) VALID OUT AI10083b 1. D means data provided by the CompactFlash memory card to the system. OUT (1) Table 18. Common memory read timing Cycle time mode 250 ns 120 ns 100 ns 80 ns Unit IEEE Symbol Parameter Min Max Min Max Min Max Min Max Symbol ta(OE) t Output enable access time 125 60 50 45 ns GLQV tdis(OE) Output disable time from OE 100 60 50 45 ns tGHQZ tsu(A) t Address setup time 30 15 10 10 ns AVGL th(A) t Address hold time 20 15 15 10 ns GHAX tsu(CE) t CE setup time 0 0 0 0 ns ELGL th(CE) t CE hold time 20 15 15 10 ns GHEH 1. Numonyx CF does not assert the WAIT signal. 25/90 Command interface SMCxxxBF Figure 5. Common memory write waveforms Address Inputs VALID tsu(A) th(A) –REG tsu(CE) trec(WE) –CE2/–CE1 tw(WE) th(CE) –WE tsu(D-WEH) th(D) D0 to D15 (D ) DATA IN VALID IN AI10082b 1. D signifies data provided by the system to the CompactFlash memory card. IN (1) Table 19. Common memory write timing Cycle time mode 250 ns 120 ns 100 ns 80 ns Unit IEEE Symbol Parameter Min Max Min Max Min Max Min Max Symbol tsu(D-WEH) t Data setup time from WE 80 50 40 30 ns DVWH th(D) t Data hold time 30 15 10 10 ns WMDX tw(WE) t WE pulse width 150 70 60 55 ns WLWH tsu(A) t Address setup time 30 15 10 10 ns AVGL tsu(CE) t CE setup time before WE 0 0 0 0 ns ELWL trec(WE) t Write recovery time 30 15 15 15 ns WMAX th(A) t Address hold time 20 15 15 10 ns GHAX th(CE) t CE hold following WE 20 15 15 10 ns GHEH 1. Numonyx CF does not assert the WAIT signal. 26/90 SMCxxxBF Command interface 5.3 I/O read and write Figure 6. I/O read waveforms Address Inputs VALID tsuREG(IORD) thA(IORD) –REG thREG(IORD) tsuCE(IORD) –CE2/–CE1 tsuA(IORD) tw(IORD) thCE(IORD) –IORD td(IORD) tdrINPACK(IORD) –INPACK tdrIOIS16(ADR) tdfIOIS16(ADR) tdfINPACK(IORD) –IOIS16 th(IORD) D0 to D15 VALID AI10084b 1. D signifies data provided by the CompactFlash memory card or to the system. OUT (1) Table 20. I/O read timing Cycle time mode 250 ns 120 ns 100 ns 80 ns Unit IEEE Symbol Parameter Min Max Min Max Min Max Min Max symbol td(IORD) t Data delay after IORD 100 50 50 45 ns IGLQV th(IORD) t Data hold IORD 0 5 5 5 ns IGHQX tw(IORD) t IORD width time 165 70 65 55 ns IGLIGH tsuA(IORD) t Address setup before IORD 70 25 25 15 ns AVIGL thA(IORD) t Address hold following IORD 20 10 10 10 ns IGHAX tsuCE(IORD) t CE setup before IORD 5 5 5 5 ns ELIGL thCE(IORD) t CE hold following IORD 20 10 10 10 ns IGHEH tsuREG(IORD) t REG setup before IORD 5 5 5 5 ns RGLIGL thREG(IORD) t REG hold following IORD 0 0 0 0 ns IGHRGH NA NA NA tdfINPACK(IORD) t INPACK delay falling from IORD 0 45 0 0 0 ns (2) IGLIAL (2) (2) NA NA NA tdrINPACK(IORD) t INPACK delay rising from IORD 45 ns IGHIAH (2) (2) (2) tdfIOIS16(A) t IOIS16 delay falling from address 35 ns ns AVISL tdrIOIS16(A) t IOIS16 delay rising from address 35 ns ns AVISH 1. Numonyx CF does not assert the WAIT signal. 2. -IOIS16 is not supported in this mode. 27/90 Command interface SMCxxxBF Figure 7. I/O write waveforms Address Inputs VALID tsuREG(IOWR) thA(IOWR) thREG(IOWR) –REG tsuCE(IOWR) thCE(IOWR) –CE2/–CE1 tsuA(IOWR) tw(IOWR) –IOWR tdfIOIS16(ADR) tdrIOIS16(ADR) –IOIS16 tsu(IOWR) th(IOWR) D0 to D15 (D ) D VALID IN IN AI10085b 1. D signifies data provided by the system to the CompactFlash memory card. IN 2. -IOIS16 and -INPACK are not supported in this mode. 3. (1) Table 21. I/O write timing Cycle time mode 250 ns 120 ns 100 ns 80 ns Unit IEEE Symbol Parameter Min Max Min Max Min Max Min Max symbol tsu(IOWR) t Data setup before IOWR 60 20 20 15 ns QVIWH th(IOWR) t Data hold following IOWR 30 10 5 5 ns IWHQX tw(IOWR) t IOWR width time 165 70 65 55 ns IWLIWH tsuA(IOWR) t Address setup before IOWR 70 25 25 15 ns AVIWL thA(IOWR) t Address hold following IOWR 20 20 10 10 ns IWHAX tsuCE(IOWR) t CE setup before IOWR 5 5 5 5 ns ELIWL thCE(IOWR) t CE Hold following IOWR 20 20 10 10 ns IWHEH tsuREG(IOWR) t REG Setup before IOWR 5 5 5 5 ns RGLIWL thREG(IOWR) t REG Hold following IOWR 0 0 0 0 ns IWHRGH NA NA IOIS16 Delay Falling from NA tdfIOIS16(A) t 35 AVISL (2) (2) (2) Address NA NA NA IOIS16 Delay Rising from tdrIOIS16(A) t 35 AVISH (2) (2) (2) Address 1. Numonyx CF does not assert the WAIT signal. 2. -IOIS16 is not supported in this mode. 28/90 SMCxxxBF Command interface 5.4 True IDE mode The timing waveforms for true IDE mode and true IDE DMA mode of operation in this section are drawn using the conventions in the ATA-4 specification, which are different than the conventions used in the PCMCIA specification and earlier versions of this specification. Signals are shown with their asserted state as High regardless of whether the signal is actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus. Figure 8. True IDE PIO mode read/write waveforms t0 (1) A0-A2, −CS0, −CS1 ADDRESS VALID t1 t2 t9 t8 −IORD/−IOWR t2i (2) Write Data D0-D15 VALID t3 t4 (2) VALID Read Data D0-D15 t5 t6 t6z t7 (3) −IOCS16 ai10086b 1. The device addresses consists of −CS0, −CS1, and A2-A0. 2. The data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit). 3. −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored. 29/90 Command interface SMCxxxBF (1) Table 22. True IDE PIO mode read/write timing Symbol Parameter Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Unit (2) t Cycle time (min) 600 383 240 180 120 100 80 ns 0 Address Valid to -IORD/-IOWR t 70 50 30 30 25 15 10 ns 1 setup (min) (2) t -IORD/-IOWR (min) 165 125 100 80 70 65 55 ns 2 -IORD/-IOWR (min) register (8 (2) t 290 290 290 80 70 65 55 ns 2 bit) -IORD/-IOWR recovery time (2) t - - - 7025 2520 ns 2i (min) t -IOWR data setup (min) 60 45 30 30 20 20 15 ns 3 t -IOWR data hold (min) 30 20 15 10 10 5 5 ns 4 t -IORD data setup (min) 50 35 20 20 20 15 10 ns 5 t -IORD data hold (min) 5 5 5 5 5 5 5 ns 6 (3) t -IORD data tri-state (max) 30 30 30 30 30 20 20 ns 6Z Address valid to -IOCS16 (4) t 90 50 40 NA NA NA NA ns 7 assertion (max) Address valid to -IOCS16 (4) t 60 45 30 NA NA NA NA ns 8 released (max) -IORD/-IOWR to address valid t 20 15 10 10 10 10 10 ns 9 hold 1. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load. 2. t is the minimum total cycle time, t is the minimum command active time, and t is the minimum command recovery time 0 2 2i or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t , t , and t have to be met. The minimum total cycle time 0 2 2i requirement is greater than the sum of t and t . This means a host implementation can lengthen either or both t or t to 2 2i 2 2i ensure that t is equal to or greater than the value reported in the device's identify drive data. A CompactFlash memory card 0 implementation should support any legal host implementation. 3. This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by the CompactFlash memory card (tri-state). 4. t and t apply only to modes 0, 1 and 2. The -IOCS16 signal is not valid for other modes. 7 8 30/90 SMCxxxBF Command interface Figure 9. True IDE multi-word DMA mode read/write waveforms tM t0 tN −CS0, −CS1 tLW, tLR −∆ΜΑΡΘ tKW tI tD tJ tKR −∆ΜΑΧΚ tE −IORD/−IOWR tZ tF Read Data D0-D15 VALID VALID tG tH VALID VALID Write Data D0-D15 ai13117 Table 23. True IDE multi-word DMA mode read/write timing Symbol Parameter Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit (1) t Cycle time (min) 480 150 120 100 80 ns 0 (1) t -IORD / -IOWR asserted width (min) 215 80 70 65 55 ns D t -IORD data access (max) 150 60 50 50 45 ns E t -IORD data hold (min) 5 5 5 5 5 ns F t -IORD/-IOWR data setup (min) 100 30 20 15 10 ns G t -IOWR data hold (min) 20 15 10 5 5 ns H t DMACK to –IORD/-IOWR setup (min) 0 0 0 0 0 ns I t -IORD / -IOWR to -DMACK hold (min) 20 5 5 5 5 ns J (1) t -IORD Low width (min) 50 50 25 25 20 ns KR (1) t -IOWR Low width (min) 215 50 25 25 20 ns KW t -IORD to DMARQ delay (max) 120 40 35 35 35 ns LR t -IOWR to DMARQ delay (max) 40 40 35 35 35 ns LW t CS(1:0) valid to –IORD / -IOWR 50 30 25 10 5 ns M t CS(1:0) hold 15 10101010 ns N t -DMACK 20 25 25 25 25 ns Z 1. t is the minimum total cycle time. t is the minimum command active time. t and t are the minimum command 0 D KR KW recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the actual command active time and the actual command inactive time. The timing requirements of t , t , t , and t must be 0 D KR KW respected. t is higher than t + t or t + t , for input and output cycles respectively. This means the host can lengthen 0 D KR D KW either t or t /t , or both, to ensure that t0 is equal to or higher than the value reported in the device’s identify device D KR KW data. A CompactFlash storage card implementation shall support any legal host implementation. 31/90 Card configuration SMCxxxBF 6 Card configuration The CompactFlash memory card is identified by information in the card information structure (CIS). The card has four configuration registers (Table 24 and Table 25). ● Configuration option register ● Pin replacement register ● Card configuration and status register ● Socket and copy register They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, in I/O card mode these registers provide a method for accessing status information that would normally appear on dedicated pins in memory card mode. The base address of the card configuration registers is 200h in the attribute memory space. No write operation should be performed to the attribute memory area except for the configuration register addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute memory function. Table 24. CompactFlash memory card registers and memory space decoding –CE2 –CE1 –REG –OE –WE A10 A9 A8-A4 A3 A2 A1 A0 Selected space 1 1 X X X X X XXX X X X X Standby X 0 0 0 1 0 1 XXX X X X 0 Configuration registers read 1 0 1 0 1 X X XXX X X X X Common memory read (D7 to D0) 0 1 1 0 1 X X XXX X X X X Common memory read (D15 to D8) 0 0 1 0 1 X X XXX X X X 0 Common memory read (D15 to D0) X 0 0 1 0 0 1 XXX X X X 0 Configuration registers write 1 0 1 1 0 X X XXX X X X X Common memory write (D7 to D0) 0 1 1 1 0 X X XXX X X X X Common memory write (D15 to D8) 0 0 1 1 0 X X XXX X X X 0 Common memory write (D15 to D0) X 0 0 0 1 0 0 XXX X X X 0 Card information structure read 1 0 0 1 0 0 0 XXX X X X 0 Invalid access (CIS write) 1 0 0 0 1 X X XXX X X X 1 Invalid access (odd attribute read) 1 0 0 1 0 X X XXX X X X 1 Invalid access (odd attribute write) 0 1 0 0 1 X X XXX X X X X Invalid access (odd attribute read) 0 1 0 1 0 X X XXX X X X X Invalid access (odd attribute write) 32/90 SMCxxxBF Card configuration Table 25. CompactFlash memory card configuration registers decoding A8- –CE2 –CE1 –REG –OE –WE A10 A9 A3 A2 A1 A0 Selected register A4 X 0 0 0 1 0 1 00 0 0 0 0 Configuration option register read X 0 0 1 0 0 1 00 0 0 0 0 Configuration option register write X 0 0 0 1 0 1 00 0 0 1 0 Card status register read X 0 0 1 0 0 1 00 0 0 1 0 Card status register write X 0 0 0 1 0 1 00 0 1 0 0 Pin replacement register read X 0 0 1 0 0 1 00 0 1 0 0 Pin replacement register write X 0 0 0 1 0 1 00 0 1 1 0 Socket and copy register read X 0 0 1 0 0 1 00 0 1 1 0 Socket and copy register write 6.1 Configuration option register (200h in attribute memory) The configuration option register is used to configure the card’s interface, address decoding and interrupt to the card (see Table 26). 6.1.1 SRESET Setting the SRESET bit to ‘1’ and returning the bit ‘0’ places the CompactFlash storage card in the reset state. Setting this bit to ‘1’ is equivalent to asserting the Reset signal except that the SRESET bit is not cleared. Returning the SRESET bit to ‘0’ leaves the CompactFlash storage card in the same un-configured reset state as after a power-up and hardware reset. This bit is set to ‘0’ at power-up and taking the card through a hardware reset. 6.1.2 LevlREQ This bit is set to one (1) when level mode interrupt is selected, and zero (0) when pulse mode is selected. Set to zero (0) after power-up. 6.1.3 Conf5 - Conf0 (configuration index) These bits are used to select the operation mode of the card as shown in Table 27. This bit is set to ‘0’ after power-up. Table 26. Configuration option register (default value: 00h) Operation D7 D6 D5 D4D3D2D1 D0 R/W SRESET LevlREQ Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 33/90 Card configuration SMCxxxBF Table 27. CompactFlash memory card configurations Card Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Mapping mode Task file register address mode 0 0 0 0 0 0 Memory Memory 0h - Fh, 400h - 7FFh 0 0 0 0 0 1 Contiguous I/O I/O xx0h - xxFh 0 0 0 0 1 0 Primary I/O I/O 1F0h - 1F7h, 3F6h - 3F7h 0 0 0 0 1 1 Secondary I/O I/O 170h - 177h, 376h - 377h 6.2 Card configuration and status register (202h in attribute memory) The card configuration and status register contains information about the card’s status (see Table 28). 6.2.1 Changed Indicates that one or both of the pin replacement register (CRDY, or CWProt) bits are set to ‘1’. When the changed bit is set, –STSCHG (pin 46) is held Low and if the SigChg bit is ‘1’ the card is configured for the I/O interface. 6.2.2 SigChg This bit is set and reset by the host to enable and disable a state-change signal from the status register (issued on status changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the card is configured for I/O. 6.2.3 IOis8 The host sets this bit to ‘1’ if the card is to be configured in 8 bit I/O mode. The card is always configured for both 8- and 16-bit I/O, so this bit is ignored. 6.2.4 PwrDwn This bit indicates whether the card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’, the card enters power down mode. When set to ‘0’, the card enters active mode. The READY value on pin replacement register becomes BUSY when this bit is changed. READY will not become Ready until the power state requested has been entered. The card automatically powers down when it is idle and powers back up when it receives a command. 6.2.5 Int This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has been configured. It remains valid until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the device control register, this bit is ‘0’. 34/90 SMCxxxBF Card configuration Table 28. Card configuration and status register (default value: 00h) Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Changed SigChg IOIS8 0 0 PwrDwn Int 0 Write 0 SigChg IOIS8 0 0 PwrDwn 0 0 6.3 Pin replacement register (204h in attribute memory) This register contains information on the state of the READY signal when configured in memory mode and the IREQ signal in I/O mode. See Table 29 and Table 30. 6.3.1 CReady This bit is set to ‘1’ when the bit RReady changes state. This bit can also be written by the host. 6.3.2 CWProt This bit is set to '1' when the bit RWProt changes state. This bit can also be written by the host. 6.3.3 RReady This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request. When written, this bit acts as a mask (MReady) for writing the corresponding bit CReady. 6.3.4 WProt This bit is always ‘0’ since the CompactFlash memory card does not have a write protect switch. When written, this bit acts as a mask for writing the corresponding CWProt bit. 6.3.5 MReady This bit acts as a mask for writing the corresponding CReady bit. 6.3.6 MWProt This bit when written acts as a mask for writing the corresponding CWProt bit. Table 29. Pin replacement register (default value: 0Ch) Operation D7D6 D5D4 D3D2D1D0 Read 0 0 CReady CWProt 1 1 RReady WProt Write 0 0 CReady CWProt 0 0 RReady MWProt 35/90 Card configuration SMCxxxBF Table 30. Pin replacement changed bit/mask bit values Written by host Initial value of Final ‘C’ bit Comments ‘C’ status ‘C’ bit ‘M’ bit 0 X 0 0 Unchanged 1 X 0 1 Unchanged X 0 1 0 Cleared by host X 111 Set by host 6.4 Socket and copy register (206h in attribute memory) This register contains additional configuration information which identifies the card from other cards. This register is always written by the system before writing the configuration option register (see Table 31). 6.4.1 Drive # This value can be used to address two different cards in the case of twin card configuration. 6.4.2 X The socket number is ignored by the card. Table 31. Socket and copy register (default value: 00h) Operation D7 D6D5 D4D3 D2D1 D0 Read Reserved 0 0 Drive # 0 0 0 0 Write 0 0 0 Drive # X X X X 36/90 SMCxxxBF Card configuration 6.5 Attribute memory function Attribute memory is a space where identification and configuration information are stored. Only 8-bit wide accesses at even addresses can be performed in this area. The card configuration registers are also located in the attribute memory area, at base address 200h. Attribute memory is not accessible in true IDE mode of operation. For the attribute memory read function, signals –REG and –OE must be active and –WE inactive during the cycle. As in the main memory read functions, the signals –CE1 and –CE2 control the even and odd byte address, but only the even byte data is valid during the attribute memory access. Refer to Table 32 for signal states and bus validity. Table 32. Attribute memory function –CE2 –CE1 –OE –WE Function mode –REG A10 A9 A0 D15 to D8 D7 to D0 (1) (1) (1) (1) Standby X H H X X X X X High-Z High-Z Read byte access CIS L H L L L L L H High-Z Even byte (8 bits) Write byte access CIS L H L L L L H L Don’t care Even byte (8 bits) invalid Read byte access configuration L H L L H L L H High-Z Even byte (8 bits) Write byte access configuration L H L L H L H L Don’t care Even byte (8 bits) Read word access CIS L L L L L X L H Not valid Even byte (16 bits) Write word access CIS L L L L L X H L Don’t care Even byte (16 bits) Invalid Read word access L L L L H X L H Not valid Even byte configuration (16 bits) Write word access L L L L H X H L Don’t care Even byte configuration (16 bits) 1. The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations. 37/90 Card configuration SMCxxxBF 6.6 I/O transfer function The I/O transfer to or from the card can be either 8 or 16 bits. When a 16-bit accessible port is addressed, the –IOIS16 signal is asserted by the card, otherwise it is de-asserted. When a 16-bit transfer is attempted, and the –IOIS16 signal is not asserted, the system must generate a pair of 8-bit references to access the word’s even and odd bytes. The card permits both 8 and 16 bit accesses to all of its I/O addresses, so –IOIS16 is asserted for all addresses (see Table 33). . Table 33. I/O function Function code –REG –CE2 –CE1 A0 –IORD –IOWR D15 to D8 D7 to D0 Standby mode X H H X X X High Z High Z Byte input access L H L L L H High Z Even byte (8 bits) L H L H L H High Z Odd byte Byte output access L H L L H L Don’t care Even byte (8 bits) L H L H H L Don’t care Odd byte Word input access L L L L L H Odd byte Even byte (16 bits) Word output access L L L L H L Odd byte Even byte (16 bits) I/O read inhibit H X X X L H Don’t care Don’t care I/O write inhibit H X X X H L High Z High Z High byte input only L L H X L H Odd byte High Z (8 bits) High byte output only L L H X H L Odd byte Don’t care (8 bits) 38/90 SMCxxxBF Card configuration 6.7 Common memory transfer function The common memory transfer to or from the card permits both 8- or 16-bit access to all of the common memory addresses. (see Table 34). Table 34. Common memory function Function code –REG –CE2 –CE1 A0 –OE –WE D15 to D8 D7 to D0 Standby mode X H H X X X High Z High Z H H L L L H High Z Even byte Byte read access (8 bits) H H L H L H High Z Odd byte H H L L H L Don’t care Even byte Byte write access (8 bits) H H L H H L Don’t care Odd byte Word read access (16 bits) H L L X L H Odd byte Even byte Word write access (16 bits) H L L X H L Odd byte Even byte Odd byte read only (8 bits) H L H X L H Odd byte High Z Odd byte write only (8 bits) H L H X H L Odd byte Don’t care 6.8 True IDE mode I/O function The card can be configured in a true IDE mode of operation. It is configured in this mode only when the –OE signal is grounded by the host during the power off to power on cycle. In this True IDE mode the PCMCIA protocol and configuration are disabled and only I/O operations to the task file and data register are allowed. No memory or attribute registers are accessible to the host. The Set Feature command can be used to put the device in 8-bit mode (see Table 35). Removing and reinserting the card while the host computer’s power is on will reconfigure the card to PC card ATA mode. 39/90 Card configuration SMCxxxBF Table 35. True IDE mode I/O function A2 to Function code –CS1 –CS0 -DMACK –IORD –IOWR D15 to D8 D7 to D0 A0 Undefined Undefined LL X X X X In/Out In/Out L X X L L X Undefined Out Undefined Out Invalid mode L X X L X L Undefined In Undefined In X L X L L X Undefined Out Undefined Out X L X L X L Undefined In Undefined In Standby mode H H X H X X High Z High Z Task file write H L 1h-7h H H L Don’t care Data In Task file read H L 1h-7h H L H High Z Data Out PIO data register write H L 0 H H L Odd-byte In Even-byte In DMA data register H L X L H L Odd-byte In Even-byte In write PIO data register read H L 0 H L H Odd-byte Out Even-byte Out DMA data register H H X L L H Odd-byte Out Even-byte Out read Control register write L H 6h H H L Don’t care Control In Alternate status read L H 6h H L H High Z Status Out Drive address L H 7h H L H High Z Data Out 40/90 SMCxxxBF Host configuration requirements 7 Host configuration requirements The CompactFlash advanced timing modes include PCMCIA-style I/O modes that are faster than the original 250 ns cycle time (see Section 1: Description). Before configuring the card interface for the I/O mode, the host must ensure that all the cards connected to a given electrical interface support I/O transfers faster than 250 ns. These modes must be used in the conditions described in Section 4.4: Additional requirements for CompactFlash advanced timing mode. In particular, the host can be connected to one card only. Consequently, the host must not configure a card to operate in an CompactFlash advanced timing mode if two cards are sharing the same I/O lines in master/slave operation, or if it is connected to the card through a cable which length exceeds 0.15 m. 41/90 Software interface SMCxxxBF 8 Software interface 8.1 CF-ATA drive register set definition and protocol The CompactFlash memory card can be configured as a high performance I/O device through: ● Standard PC-AT disk I/O address spaces – 1F0h-1F7h, 3F6h-3F7h (primary); – 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). ● Any system decoded 16-byte I/O block using any available IRQ ● Memory space. Communication to or from the card is done using the task file registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 36 is a detailed description of these methods: Table 36. I/O configurations Standards configurations Config index I/O or memory Address Description 0 Memory 0h-Fh, 400h-7FFh Memory mapped 1 I/O xx0h-xxFh I/O mapped 16 continuous registers 2 I/O 1F0-1F7h, 3F6h-3F7h Primary I/O mapped 3 I/O 170-177h, 376h-377h Secondary I/O mapped 8.2 Memory mapped addressing When the card registers are accessed via memory references, the registers appear in the common memory space window: 0-2 Kbytes as shown in Table 37. This window accesses the data register FIFO. It does not allow random access to the data buffer within the card. Register 0 is accessed with –CE1 and –CE2 Low, as a word register on the combined odd and even data bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature byte-wide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to address 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer, however repeated byte accesses to register 9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. 42/90 SMCxxxBF Software interface Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1-Kbyte memory window to the data register is provided so that hosts can perform memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory-to-memory block move instruction. Some PCMCIA socket adapters also have an embedded auto incrementing address logic. A word access to address at offset 8 will provide even data on the least significant byte of the data bus, along with odd data at offset 9 on the most significant byte of the data bus. Table 37. Memory mapped decoding A9 to –REG A10 A3 A2 A1 A0 Offset –OE=0 –WE=0 A4 1 0 X 0000 0h Even data register Even data register 1 0 X 0001 1h Error register Feature register 1 0 X 0010 2h Sector count register Sector count register Sector number 1 0 X 0011 3h Sector number register register 1 0 X 0100 4h Cylinder low register Cylinder low register 1 0 X 0101 5h Cylinder high register Cylinder high register Select card/head 1 0 X 0110 6h Select card/head register register 1 0 X 0111 7h Status register Command register Dup. even data 1 0 X 1000 8h Dup. even data register register Dup. odd data 1 0 X 1001 9h Dup. odd data register register 1 0 X 1101 Dh Dup. error register Dup. feature register Alternate status 1 0 X 1110 Eh Device control register register 1 0 X 1111 Fh Drive address register Reserved 1 1 X X X X 0 8h Even data register Even data register 1 1 X X X X 1 9h Odd data register Odd data register 43/90 Software interface SMCxxxBF 8.3 Contiguous I/O mapped addressing When the system decodes a contiguous block of I/O registers to select the card, the registers are accessed in the block of I/O space decoded by the system as shown in Table 38. As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 don’t care) as a word register on the combined odd and even data bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature byte-wide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer, however repeated byte accesses to register 9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Table 38. Contiguous I/O decoding A10 to –REG A3 A2 A1 A0 Offset –IORD=0 –IOWR=0 A4 0 X 0 0 0 0 0h Even data register Even data register 0 X 0 0 0 1 1h Error register Feature register 0 X 0 0 1 0 2h Sector count register Sector count register 0 X 0 0 1 1 3h Sector Number register Sector number register 0 X 0 1 0 0 4h Cylinder low register Cylinder low register 0 X 0 1 0 1 5h Cylinder high register Cylinder high register Select card/head Select card/head 0 X 011 0 6h register register 0 X 0 1 1 1 7h Status register Command register 0 X 1 0 0 0 8h Dup. even data register Dup. even data register 0 X 1 0 0 1 9h Dup. odd data register Dup. odd data register 0 X 1 1 0 1 Dh Dup. error register Dup. feature register 0 X 1 1 1 0 Eh Alternate status register Device control register 0 X 1 1 1 1 Fh Drive address register Reserved 44/90 SMCxxxBF Software interface 8.4 I/O primary and secondary address configurations When the system decodes the primary and secondary address configurations, the registers are accessed in the block of I/O space as shown in Table 39. As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 don’t care) as a word register on the combined odd and even data bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature byte-wide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Table 39. Primary and secondary I/O decoding A9 to –REG A3 A2 A1 A0 –IORD=0 –IOWR=0 A4 0 1F(17)h 0 0 0 0 Even data register Even data register 0 1F(17)h 0 0 0 1 Error register Feature register 0 1F(17)h 0 0 1 0 Sector count register Sector count register 0 1F(17)h 0 0 1 1 Sector number register Sector number register 0 1F(17)h 0 1 0 0 Cylinder low register Cylinder low register 0 1F(17)h 0 1 0 1 Cylinder high register Cylinder high register 0 1F(17)h 0 1 1 0 Select card/head register Select card/head register 0 1F(17)h 0 1 1 1 Status register Command register 0 3F(37)h 0 1 1 0 Alternate status register Device control register 0 3F(37)h 0 1 1 1 Drive address register Reserved 45/90 Software interface SMCxxxBF 8.5 True IDE mode addressing When the card is configured in the true IDE mode, the I/O decoding is as shown in Table 40 Table 40. True IDE mode I/O decoding –CS1 –CS0 A2 A1 A0 -DMACK –IORD=0 –IOWR=0 1 0 0 0 0 1 PIO RD data PIO WR data 1 1 X X X 0 DMA RD data DMA WR data 1 0 0 0 1 1 Error register Features 1 0 0 1 0 1 Sector count Sector count 1 0 0 1 1 1 Sector No. Sector No. 1 0 1 0 0 1 Cylinder low Cylinder low 1 0 1 0 1 1 Cylinder high Cylinder high 1 0 1 1 0 1 Select card/head Select card/head 1 0 1 1 1 1 Status Command 0 1 1 1 0 1 Alt status Alt status 46/90 SMCxxxBF CF-ATA registers 9 CF-ATA registers The following section describes the hardware registers used by the host software to issue commands to the card. These registers are collectively referred to as the ‘task file’. In accordance with the PCMCIA specification, each register that is located at an odd offset address can be accessed in the PC card memory or PC card I/O modes. The register can be addressed in two ways: ● Using the normal register address ● Using the corresponding even address (normal address -1) when -CE1 is High and - CE2 Low, unless -IOIS16 is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data bus lines D15-D8. In true IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit only except for the data register, which is normally 16 bits. However, they can be configured to be accessed in 8-bit mode for non-DMA operations, by using a Set Features command (see Section 10.17). 9.1 Data register The data register is located at address 1F0h [170h], offset 0h, 8h, and 9h. The data register is a 16-bit register used to transfer data blocks between the card data buffer and the host. This register overlaps the error register. Table 41 and Table 42 describes the combinations of data register access and explains the overlapped data and error/feature registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the word data register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed. Table 41. Data register access (memory and I/O mode) (1) Data register –CE2 –CE1 A0 -REG Offset Data bus Word data register 0 0 X - 0h, 8h, 9h D15 to D0 Even data register 1 0 0 - 0h, 8h D7 to D0 Odd data register 1 0 1 - 9h D7 to D0 Odd data register 0 1 X - 8h, 9h D15 to D8 Error/feature register 1 0 1 - 1h, Dh D7 to D0 Error/feature register 0 1 X - 1h D15 to D8 Error/feature register 0 0 X - Dh D15 to D8 1. -REG signal is mode dependent. It must be Low when the card operates in I/O mode and High when it operates in memory mode. 47/90 CF-ATA registers SMCxxxBF Table 42. Data register access (True IDE mode) Data register –CS1 –CS0 A0 -DMACK Offset Data bus PIO word data register 1 0 0 1 0h D15 to D0 DMA word data register 1 1 X 0 X D15 to D0 PIO byte data register (selected using 1 0 0 1 0h D7 to D0 Set Features command) 9.2 Error register The error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh. This read only register contains additional information about the source of an error when an error is indicated in bit 0 of the status register. The bits are defined in Table 43. This register is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and – CE1 High. 9.2.1 Bit 7 (BBK) This bit is set when a bad block is detected. 9.2.2 Bit 6 (UNC) This bit is set when an uncorrectable error is encountered. 9.2.3 Bit 5 This bit is ‘0’. 9.2.4 Bit 4 (IDNF) This bit is set if the requested sector ID is in error or cannot be found. 9.2.5 Bit 3 This bit is ‘0’. 9.2.6 Bit 2 (abort) This bit is set if the command has been aborted because of a card status condition (not ready, write fault, etc.) or when an invalid command has been issued. 9.2.7 Bit 1 This bit is ‘0’. 9.2.8 Bit 0 (AMNF) This bit is set when there is a general error. 48/90 SMCxxxBF CF-ATA registers Table 43. Error register D7 D6 D5 D4 D3 D2 D1 D0 BBK UNC 0 IDNF 0 ABRT 0 AMNF 9.3 Feature register The feature register is a write-only register, located at address 1F1h [171h], offset 1h, Dh. This write-only register provides information on features that the host can utilize. It is accessed on data bits D15 to D8 during a write operation to Offset 0 with –CE2 Low and – CE1 High. 9.4 Sector count register The sector count register is located at address 1F2h [172h], offset 2h. This register contains the number of sectors of data to be transferred on a read or write operation between the host and card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. The default value is 01h. 9.5 Sector number (LBA 7-0) register The sector number register is located at address 1F3h [173h], offset 3h. This register contains the starting sector number or bits 7 to 0 of the logical block address (LBA), for any data access for the subsequent sector transfer command. 9.6 Cylinder low (LBA 15-8) register The cylinder low register is located at address 1F4h [174h], offset 4h. This register contains the least significant 8 bits of the starting cylinder address or bits 15 to 8 of the logical block address. 9.7 Cylinder high (LBA 23-16) register The cylinder high register is located at address 1F5h [175h], offset 5h. This register contains the most significant bits of the starting cylinder address or bits 23 to 16 of the logical block address. 49/90 CF-ATA registers SMCxxxBF 9.8 Drive/head (LBA 27-24) register The driver/head register is located at address 1F6h [176h], offset 6h. The drive/head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined in Table 44 9.8.1 Bit 7 This bit is set to ‘1’. 9.8.2 Bit 6 (LBA) LBA is a flag to select either cylinder/head/sector (CHS) or logical block address mode (LBA). When LBA is set to ‘0’, cylinder/head/sector mode is selected. When LBA is set to’1’, logical block address is selected. In logical block mode, the logical block address is interpreted as follows: ● LBA7-LBA0: sector number register D7 to D0 ● LBA15-LBA8: cylinder low register D7 to D0 ● LBA23-LBA16: cylinder high register D7 to D0 ● LBA27-LBA24: drive/head register bits HS3 to HS0 9.8.3 Bit 5 This bit is set to ‘1’. 9.8.4 Bit 4 (DRV) DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (master). When DRV is ‘1’, drive/card 1 is selected (slave). The card is set to card 0 or 1 using the copy field (drive #) of the PCMCIA socket & copy configuration register. 9.8.5 Bit 3 (HS3) When operating in the cylinder, head, sector mode, this is bit 3 of the head number. It is bit 27 in the logical block address mode. 9.8.6 Bit 2 (HS2) When operating in the cylinder, head, sector mode, this is bit 2 of the head number. It is bit 26 in the logical block address mode. 9.8.7 Bit 1 (HS1) When operating in the cylinder, head, sector mode, this is bit 1 of the head number. It is bit 25 in the logical block address mode. 9.8.8 Bit 0 (HS0) When operating in the cylinder, head, sector mode, this is bit 0 of the head number. It is bit 24 in the logical block address mode. 50/90 SMCxxxBF CF-ATA registers Table 44. Drive/head register D7 D6 D5 D4 D3 D2 D1 D0 1 LBA 1 DRV HS3 HS2 HS1 HS0 9.9 Status & alternate status registers The status & alternate status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively. Offsets are 7h and Eh. These registers return the card status when read by the host. Reading the status register clears a pending interrupt. Reading the auxiliary status register does not clear a pending interrupt. The status register should be accessed in byte mode; in word mode it is recommended that alternate status register is used. The status bits are described as follows. 9.9.1 Bit 7 (BUSY) The busy bit is set when only the card can access the command register and buffer, The host is denied access. No other bits in this register are valid when this bit is set to ‘1’. 9.9.2 Bit 6 (RDY) This bit indicates whether the device is capable of performing CompactFlash memory card operations. This bit is cleared at power up and remains cleared until the card is ready to accept a command. 9.9.3 Bit 5 (DWF) When set this bit indicates a Write Fault has occurred. 9.9.4 Bit 4 (DSC) This bit is set when the card is ready. 9.9.5 Bit 3 (DRQ) The data request is set when the card requires information be transferred either to or from the host through the data register. The bit is cleared by the next command. 9.9.6 Bit 2 (CORR) This bit is set when a correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. 9.9.7 Bit 1 (IDX) This bit is always set to ‘0’. 51/90 CF-ATA registers SMCxxxBF 9.9.8 Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the error register contain additional information describing the error. In case of read or write access commands that end with an error, the address of the first sector with an error is in the command block registers. This bit is cleared by the next command. Table 45. Status & alternate status register D7 D6 D5 D4 D3 D2 D1 D0 BUSY RDY DWF DSC DRQ CORR 0 ERR 9.10 Device control register The device control register is located at address 3F6h [376h], offset Eh. This write-only register is used to control the CompactFlash memory card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows. 9.10.1 Bit 7 to 3 Don’t care. The host should reset this bit to ‘0’. 9.10.2 Bit 2 (SW Rst) This bit is set to ‘1’ to force the CompactFlash storage card to perform an AT disk controller soft reset operation. This clears status register and writes diagnostic code in error register after a write or read sector error. The card remains in reset until this bit is reset to ‘0.’ 9.10.3 Bit 1 (–IEn) When the interrupt enable bit is set to ‘0’, –IREQ interrupts are enabled. When the bit is set to ‘1’, interrupts from the card are disabled. This bit also controls the int bit in the card configuration and status register. It is set to ‘0’ at power-on. 9.10.4 Bit 0 This bit is set to ‘0’. Table 46. Device control register D7 D6 D5 D4 D3 D2 D1 D0 X(0) X(0) X(0) X(0) X(0) SW Rst –IEn 0 52/90 SMCxxxBF CF-ATA registers 9.11 Card (drive) address register The card (drive) address register is located at address 3F7h [377h], offset Fh. This read-only register is provided for compatibility with the AT disk drive interface and can be used for confirming the drive status. It is recommended that this register is not mapped into the host’s I/O space because of potential conflicts on bit 7. The bits are defined as follows. 9.11.1 Bit 7 This bit is don’t care. 9.11.2 Bit 6 (–WTG) This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’. 9.11.3 Bit 5 (–HS3) This bit is the negation of bit 3 in the drive/head register. 9.11.4 Bit 4 (–HS2) This bit is the negation of bit 2 in the drive/head register. 9.11.5 Bit 3 (–HS1) This bit is the negation of bit 1 in the drive/head register. 9.11.6 Bit 2 (–HS0) This bit is the negation of bit 0 in the drive/head register. 9.11.7 Bit 1 (–nDS1) This bit is ‘0’ when drive 1 is active and selected. 9.11.8 Bit 0 (–nDS0) This bit is ‘0’ when the drive 0 is active and selected. Table 47. Card (drive) address register D7 D6 D5 D4 D3 D2 D1 D0 X –WTG –HS3 –HS2 –HS1 –HS0 –nDS1 –nDS0 53/90 CF-ATA command description SMCxxxBF 10 CF-ATA command description This section defines the software requirements and the format of the commands the host sends to the card. Commands are issued to the card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the command register. There are three classes of command acceptance, all dependent on the host not issuing commands unless the card is not busy (BSY is ‘0’). ● Class 1: upon receipt of a Class 1 command, the card sets BSY within 400 ns ● Class 2: upon receipt of a Class 2 command, the card sets BSY within 400 ns, sets up the sector buffer for a write operation, sets DRQ within 700 µs, and clears BSY within 400 ns of setting DRQ ● Class 3: upon receipt of a Class 3 command, the card sets BSY within 400 ns, sets up the sector buffer for a write operation, sets DRQ within 20 ms (assuming no re- assignments), and clears BSY within 400 ns of setting DRQ. For reasons of backward compatibility some commands are implemented as ‘no operation’ NOP. Table 48 summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each. (1) Table 48. CF-ATA command set Class Command Code FR SC SN CY DH LBA 1 Check Power Mode E5h or 98h D 1 Execute Drive Diagnostic 90h YD 1 Erase Sector(s) C0h Y Y Y Y Y 1 Identify Drive ECh D 1 Idle E3h or 97h Y D 1 Idle Immediate E1h or 95h D 1 Initialize drive parameters 91h Y Y 1 NOP 00h D 1 Read Buffer E4h D 1 Read DMA C8 Y Y Y Y Y 1 Read Multiple C4h Y Y Y Y Y 1 Read Sector(s) 20h or 21h Y Y Y Y Y 1 Read Verify Sector(s) 40h or 41h Y Y Y Y Y 1 Recalibrate 1Xh D 1 Request Sense 03h D 1Seek 7Xh YYYY 1 Set Features EFh Y D 1 Set Multiple Mode C6h Y D 1 Set Sleep Mode E6h or 99h D 54/90 SMCxxxBF CF-ATA command description (1) Table 48. CF-ATA command set (continued) Class Command Code FR SC SN CY DH LBA 1 Standby E2h or 96h D 1 Standby Immediate E0h or 94h D 1 Translate Sector 87h Y Y Y Y Y 1 Wear Level F5h Y 2 Write Buffer E8h D 2Write DMA CA Y Y Y Y Y 3 Write Multiple C5h Y Y Y Y Y 3 Write Multiple w/o Erase CDh Y Y Y Y Y 2 Write Sector(s) 30h or 31h Y Y Y Y Y 2 Write Sector(s) w/o Erase 38h Y Y Y Y Y 3 Write Verify 3Ch Y Y Y Y Y 1. FR = features register, SC = sector count register, SN = sector number register, CY = cylinder registers, DH = card/drive/head register, LBA = logical block address mode supported (see command descriptions for use), Y - The register contains a valid parameter for this command. For the drive/head register Y means both the Compact Flash memory card and head parameters are used D - only the Compact Flash memory card parameter is valid and not the head parameter C - the register contains command specific data (see command descriptors for use). 10.1 Check power mode (98h or E5h) This command checks the power mode. Issuing the command while the card is in standby mode, is about to enter standby, or is exiting standby, the command will set BSY, set the sector count register to 00h, clear BSY and generate an interrupt. Issuing the command when the card is in idle mode will set BSY, set the sector count register to FFh, clear BSY and generate an interrupt. Table 49 defines the byte sequence of the Check Power Mode command. Table 49. Check power mode Bit 7 65 432 10 Command (7) 98h or E5h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 55/90 CF-ATA command description SMCxxxBF 10.2 Execute drive diagnostic (90h) This command performs the internal diagnostic tests implemented by the card. In PCMCIA configuration, this command only runs on the card which is addressed by the drive/head register when the command is issued. This is because PCMCIA card interface does not allow for direct inter-drive communication. In true IDE mode, the drive bit is ignored and the diagnostic command is executed by both the master and the slave with the master responding with the status for both devices. Table 50 defines the Execute Drive Diagnostic command byte sequence. The diagnostic codes shown in Table 51 are returned in the error register at the end of the command. Table 50. Execute drive diagnostic Bit 7 6 5432 1 0 Command (7) 90h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X Table 51. Diagnostic codes Code Error type 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC circuitry error 05h Controlling microprocessor error 8Xh Slave error in true IDE mode 56/90 SMCxxxBF CF-ATA command description 10.3 Erase sector(s) (C0h) This command is used to pre-erase and condition data sectors prior to a Write Sector Without Erase command or a Write Multiple Without Erase command. There is no data transfer associated with this command but a write fault error status can occur. Table 52 defines the byte sequence of the Erase Sector command. Table 52. Erase sector(s) Bit 7 654 32 10 Command (7) C0h C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 10.4 Identify drive (ECh) The Identify Drive command enables the host to receive parameter information from the card. This command has the same protocol as the Read Sector(s) command. Table 53 defines the Identify Drive command byte sequence. All reserved bits or words are zero. Table 54 shows the definition of each field in the identify drive information. 10.4.1 Word 0: general configuration This field indicates the general characteristics of the device. The default value for word 0 is set to 848Ah. It is recommended that PCMCIA modes of operation report only the 848Ah value as they are always intended as removable devices. Alternate configuration values for word 0 is 044Ah. Some operating systems require bit 6 of word 0 to be set to ‘1’ (non-removable device) to use the card as the root storage device. The card must be the root storage device when a host completely replaces conventional disk storage with a CompactFlash card in true IDE mode. To support this requirement and provide capability for any future removable media cards, alternate value of word 0 is set in true IDE mode of operation. 10.4.2 Word 1: default number of cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 10.4.3 Word 3: default number of heads This field contains the number of translated heads in the default translation mode. 57/90 CF-ATA command description SMCxxxBF 10.4.4 Word 6: default number of sectors per track This field contains the number of sectors per track in the default translation mode. 10.4.5 Word 7-8: number of sectors per card This field contains the number of sectors per card. This double word value is also the first invalid address in LBA translation mode. 10.4.6 Word 10-19: memory card serial number The contents of this field are right justified and padded with spaces (20h). 10.4.7 Word 23-26: firmware revision This field contains the revision of the firmware for this product. 10.4.8 Word 27-46: model number This field contains the model number for this product and is left justified and padded with spaces (20h). 10.4.9 Word 47: read/write multiple sector count This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands. 10.4.10 Word 49: capabilities ● Bit 13 standby timer: is set to ’0’ to indicate that the standby timer operation is defined by the manufacturer. ● Bit 9 LBA support: CompactFlash memory cards support LBA mode addressing. ● Bit 8 DMA support: Read/Write DMA commands are supported. 10.4.11 Word 51: PIO data transfer cycle timing mode This field defines the mode for PIO data transfer. For backward compatibility with BIOSs written before word 64 was defined for advanced modes, a device reports in word 51, the highest original PIO mode it can support (PIO mode 0, 1 or 2). Bits 15-8: are set to 02H. 10.4.12 Word 53: translation parameter valid ● Bit 1: is set to '1' to indicate that words 64 to 70 are valid ● Bit 0: is set to '1' to indicate that words 54 to 58 are valid. 10.4.13 Word 54-56: current number of cylinders, heads, sectors/track These fields contains the current number of user addressable cylinders, heads, and sectors/track in the current translation mode. 58/90 SMCxxxBF CF-ATA command description 10.4.14 Word 57-58: current capacity This field contains the product of the current cylinders, heads and sectors. 10.4.15 Word 59: multiple sector setting ● Bits 15-9 are reserved and must be set to ‘0’. ● Bit 8 is set to ‘1’, to indicate that the multiple sector setting is valid. ● Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’. 10.4.16 Word 60-61: total sectors addressable in LBA mode This field contains the number of sectors addressable for the card in LBA mode only. 10.4.17 Word 63: multi-word DMA transfer Bits 15 through 8 of word 63 of the identify device parameter information identifies which multi-word DMA mode that has been selected by host.Each bit of Word 0 is significant. Only one of these bits can be set to ‘1’ by the CompactFlash storage card to indicate the multi- word DMA mode which is currently selected: ● Bits 15 to 11 are reserved ● Bit 10: when set to ‘1’, it indicates that multi-word DMA mode 1 has been selected ● Bit 9: when set to ‘1’, it indicates that multi-word DMA mode 1 has been selected ● Bit 8: when set to ‘1’, it indicates that multi-word DMA mode 0 has been selected. Bits 7 to 0 define the multi-word DMA data transfer supported field. Any number of bits may be set to one in this field by the CompactFlash storage card to indicate which multi-word DMA mode is supported: ● Bit 7 to 3 are reserved ● Bit 2: when set to ‘1’, it indicates that the CompactFlash storage card supports multi- word DMA modes 2, 1 and 0 ● Bit 1: when set to ‘1’, it indicates that the CompactFlash storage card supports multi- word DMA modes 1 and 0 ● Bit 0: when set to ‘1’, it indicates that the CompactFlash storage card supports multi- word DMA mode 0. Note: 1 Selection of multi-word DMA modes 3 and above are specific to CompactFlash, and are reported in word 163. 10.4.18 Word 64: advanced PIO transfer modes supported This field is bit significant. Any number of bits may be set to ‘1’ in this field by the CompactFlash memory card to indicate the advanced PIO modes it is capable of supporting. ● Bits 7-2 are reserved for future advanced PIO modes ● Bit 1 is set to ‘1’, indicates that the CompactFlash memory card supports PIO mode 4 ● Bit 0 is set to ‘1’ to indicate that the CompactFlash memory card supports PIO mode 3. Note: Support for PIO modes 5 and above are specific to CompactFlash are reported in word 163 59/90 CF-ATA command description SMCxxxBF 10.4.19 Word 65: minimum multi-word DMA transfer cycle time Word 65 of the parameter information of the Identify Device command is defined as the minimum multi-word DMA transfer cycle time. It corresponds to the minimum cycle time for which the card ensures data integrity during transfers. It is expressed in nanoseconds. The returned value is ‘50h’ (for cycle time values refer to Table 22). 10.4.20 Word 66: recommended multi-word DMA transfer cycle time Word 66 of the parameter information of the Identify Device command is defined as the recommended multi-word DMA transfer cycle time. The returned value is ‘50h’ (for cycle time values refer to Table 22). 10.4.21 Word 67: minimum PIO transfer cycle time without flow control This field gives the minimum cycle time (in ns) that the host should use for the CompactFlash memory card to ensure data integrity during transfers when flow control is not used. The returned value is ‘50h’ (for cycle time values refer to Table 22). 10.4.22 Word 68: minimum PIO transfer cycle time with IORDY This field gives the minimum cycle time (in ns) supported by the CompactFlash memory card to perform data transfers using IORDY flow control. The returned value is ‘50h’ (for cycle time values refer to Table 22). 10.4.23 Word 163: advanced true IDE timing mode capabilities and settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the true IDE interface. There are four sub-fields that describe the advanced PIO and advanced multi-word DMA timing modes supported and selected: ● Bits 2-0: advanced true IDE PIO mode supported. The returned value is ‘2h’ to indicate that PIO mode 6 is the highest PIO mode supported ● Bits 5-3: advanced true IDE multi-word DMA mode supported. The returned value is ‘2h’ to indicate that multi-word DMA mode 4 is the highest multi- word DMA mode supported. ● Bits 8-6: advanced true IDE PIO mode selected. These bits indicate the current true IDE PIO mode selected on the card. ● Bits 11-9: advanced true IDE multi-word DMA mode selected. These bits indicate the current true IDE multi-word DMA mode selected on the card. 60/90 SMCxxxBF CF-ATA command description 10.4.24 Word 164: advanced PCMCIA I/O and memory timing modes capabilities and settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the memory and PCMCIA I/O interface: ● Bits 2-0: maximum advanced PCMCIA I/O mode supported. The returned value is ‘3h’ to indicate that 80 ns is the maximum I/O timing mode supported by the card. ● Bits 5-3: maximum PCMCIA memory timing mode supported. The returned value is ‘3h’ to indicate that 80 ns is the maximum PCMCIA memory timing mode supported by the card. Table 53. Identify drive Bit 7 6 5432 1 0 Command (7) ECh C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 61/90 CF-ATA command description SMCxxxBF Table 54. Identify drive information Word Default Total Data field type information address value bytes General configuration (signature of the CompactFlash 848Ah 2 memory card) 0 044Ah 2 Alternate configuration 1 XXXXh 2 Default number of cylinders 2 0000h 2 Reserved 3 00XXh 2 Default number of heads 4 0000h 2 Obsolete 5 0000h 2 Obsolete 6 XXXXh 2 Default number of sectors per track 7-8 XXXXh 4 Number of sectors per card (Word 7 = MSW, Word 8 = LSW) 9 0000h 2 Obsolete 10-19 aaaa 20 Serial number in ASCII (right justified) 20 0000h 2 Obsolete 21 0000h 2 Obsolete 22 0004h 2 Reserved 23-26 aaaa 8 Firmware revision in ASCII. Big endian byte order in word Model number in ASCII (right justified) big endian byte order 27-46 aaaa 40 in word Maximum number of sectors on Read/Write Multiple 47 0001h 2 command 48 0000h 2 Reserved 49 0200h 2 Capabilities 50 0000h 2 Reserved 51 0200h 2 PIO data transfer cycle timing mode 52 0000h 2 Obsolete 53 0003h 2 Field validity 54 XXXXh 2 Current numbers of cylinders 55 XXXXh 2 Current numbers of heads 56 XXXXh 2 Current sectors per track Current capacity in sectors (LBAs)(word 57 = LSW, word 58 57-58 XXXXh 4 = MSW) 59 0100h 2 Multiple sector setting 60-61 XXXXh 4 Total number of sectors addressable in LBA mode 62 0000h 2 Reserved. Multi-word DMA transfer. In PCMCIA mode, this value is 63 0407h 2 ‘0h’. 62/90 SMCxxxBF CF-ATA command description Table 54. Identify drive information (continued) Word Default Total Data field type information address value bytes 64 0003h 2 Advanced PIO modes supported Minimum multi-word DMA transfer cycle time per word. In 65 0050h 2 PCMCIA mode this value is ‘0h’ Recommended multi-word DMA transfer cycle time. In 66 0050h 2 PCMCIA mode this value is ‘0h’ 67 0050h 2 Minimum PIO transfer cycle time without flow control 68 0050h 2 Minimum PIO transfer cycle time with IORDY flow control 69-128 0000h 120 Reserved 129-159 0000h 62 Manufacturer unique bytes 160-162 0000h 4 Reserved 163 0492h 2 CF advanced true IDE timing mode capability and setting CF advanced PCMCIA I/O and memory timing mode 164 001Bh 2 capability 165-255 0000h 190 Reserved 10.5 Idle command (97h or E3h) This command causes the card to set BSY, enter the idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count (each count is 5 ms) and the automatic power-down mode is enabled. If the sector count is zero, the automatic power-down mode is disabled. Note that this time base (5 ms) is different from the ATA specification. Table 55 defines the byte sequence of the Idle command. Table 55. Idle Bit 76543 210 Command (7) 97h or E3h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) Timer count (5 ms increments) Feature (1) X 10.6 Idle Immediate command (95h or E1h) This command causes the card to set BSY, enter the idle mode, clear BSY and generate an interrupt. Table 56 defines the Idle Immediate command byte sequence. 63/90 CF-ATA command description SMCxxxBF Table 56. Idle Immediate Bit 765 43210 Command (7) 95h or E1h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 10.7 Initialize Drive Parameters command (91h) This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the sector count and the card/drive/head registers are used by this command. Table 57 defines the Initialize Drive Parameters command byte sequence. Table 57. Initialize Drive Parameters Bit 7 6 543 2 1 0 Command (7) 91h C/D/H (6) X 0 X Drive Max Head (no. of heads 1) Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) Number of sectors Feature (1) X 64/90 SMCxxxBF CF-ATA command description 10.8 NOP command (00h) This command always fails with the CompactFlash memory card returning command aborted. Table 58 defines the byte sequence of the NOP command. Table 58. NOP Bit 7 6 543210 Command (7) 00h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 10.9 Read Buffer command (E4h) The Read Buffer command enables the host to read the current contents of the card’s sector buffer. This command has the same protocol as the Read Sector(s) command. Table 59 defines the Read Buffer command byte sequence. Table 59. Read Buffer Bit 7 6 5432 1 0 Command (7) E4h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 65/90 CF-ATA command description SMCxxxBF 10.10 Read DMA command (C8h) This command uses multi-word DMA mode to read from 1 to 256 sectors as specified in the sector count register. If the sector count is set to ‘0’, 256 sectors will be read by issuing a Read DMA command. Data transfer begins at the sector specified in the sector number register. When the Read DMA command is issued, the CompactFlash card asserts BSY, and transfers all or part of the sector data in the buffer. The card can then set DRQ and clear BSY, although it is not required. The card asserts DMARQ when data are available to be transferred. The host then reads the 512*sector-count bytes of data from the card using DMA protocol. When DMARQ is asserted, the host asserts -DMACK to notify it is ready to transfer data, and asserts -IORD once for each 16-bit word to be transferred. Interrupts are not generated for each sector transfer, but when all sectors have been transferred or when an error occurred during the operation. An abort error is returned by the card when a Read DMA command is sent by the host and the 8-bit transfer mode has been enabled by the Set Features command. Table 60 defines the Read DMA command byte sequence. Table 60. Read DMA Bit 7 6 5432 1 0 Command (7) C8h C/D/H (6) LBA Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 66/90 SMCxxxBF CF-ATA command description 10.11 Read Multiple command (C4h) The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the read sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = (sector count) module (block count). If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when read multiple commands are disabled, the read multiple operation is rejected with an aborted command error. Disk errors encountered during read multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) command. This command reads from 1 to 256 sectors as specified in the sector count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the sector number register. If an error occurs, the read terminates at the sector where the error occurred. The command block registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. Table 61 defines the Read Multiple command byte sequence. Table 61. Read Multiple Bit 7 6 5 432 1 0 Command (7) C4h C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 67/90 CF-ATA command description SMCxxxBF 10.12 Read Sector(s) command (20h or 21h) This command reads from 1 to 256 sectors as specified in the sector count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the sector number register. When this command is issued and after each sector of data (except the last one) has been read by the host, the card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 bytes of data from the buffer. If an error occurs, the read terminates at the sector where the error occurred. The command block registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer. Table 62 defines the Read Sector command byte sequence. Table 62. Read Sector(s) Bit 765 4 3 2 1 0 Command 20h or 21h (7) C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High Cylinder High (LBA 23-16) (5) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num Sector number (LBA 7-0) (3) Sect Cnt Sector count (2) Feature (1) X 10.13 Read Verify Sector(s) command (40h or 41h) This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the card sets BSY. When the requested sectors have been verified, the card clears BSY and generates an interrupt. If an error occurs, the verify terminates at the sector where the error occurs. The command block registers contain the cylinder, head and sector number of the sector where the error occurred. The sector count register contains the number of sectors not yet verified. Table 63 defines the Read Verify Sector command byte sequence. 68/90 SMCxxxBF CF-ATA command description Table 63. Read Verify Sector(s) Bit 7 6 5432 1 0 Command (7) 40h or 41h C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 10.14 Recalibrate command (1Xh) This command is effectively a NOP command to the card and is provided for compatibility purposes. Table 64 defines the Recalibrate command byte sequence. Table 64. Recalibrate Bit 7 6 543 2 1 0 Command (7) 1Xh C/D/H (6) 1 LBA 1 Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 69/90 CF-ATA command description SMCxxxBF 10.15 Request Sense command (03h) This command requests extended error information for the previous command. Table 65 defines the Request Sense command byte sequence. Table 66 defines the valid extended error codes. The extended error code is returned to the host in the error register. Table 65. Request Sense Bit 7 6 543 2 1 0 Command (7) 03h C/D/H (6) 1 X 1 Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X Table 66. Extended error codes Extended error code Description 00h No error detected 01h Self test OK (no error) 09h Miscellaneous error 21h Invalid address (requested head or sector invalid) 2Fh Address overflow (address too large) 35h, 36h Supply or generated voltage out of tolerance 11h Uncorrectable ECC error 18h Corrected ECC error 05h, 30-34h, 37h, 3Eh Self test or diagnostic failed 10h, 14h ID not found 3Ah Spare sectors exhausted 1Fh Data transfer error / aborted command 0Ch, 38h, 3Bh, 3Ch, 3Fh Corrupted media format 03h Write / erase failed 70/90 SMCxxxBF CF-ATA command description 10.16 Seek command (7Xh) This command is effectively a NOP command to the card although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. Table 67 shows the Seek command byte sequence. Table 67. Seek Bit 7 6 5 4 3210 Command (7) 7Xh C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) X (LBA 7-0) Sect Cnt (2) X Feature (1) X 10.17 Set Features command (EFh) This command is used by the host to establish or select certain features. Table 68 shows the Set Features command byte sequence. Table 69 defines all features that are supported. ● Features 01h and 81h are used to enable and clear 8 bit data transfer modes in true IDE mode. If the 01h feature command is issued all data transfers will occur on the D7- D0 data lines and the –IOIS16 signal will not be asserted for data register accesses. The host must not enable this feature for DMA transfers. ● Feature 03h allows the host to select the PIO or the multi-word DMA transfer mode. The number of sectors to be transferred must be specified in the sector count register (see Table 70 for values). The upper 5 bits define the type of transfer and the lower 3 bits encode the transfer mode. Only one PIO mode and one multi-word mode can be selected at a time. The host can change the selected mode by issuing the Set Features command. ● Feature code 9Ah allows the host to configure the card to best meet the host system power requirements. The host programs the sector count register to a value that is equal to one-fourth of the desired maximum average current (in mA) that the card should consume. For example, if the sector count register is set to ‘6’, the card must be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the card replies to the host with the range of values that it supports. The minimum value is set in the cylinder low register, and the maximum value is set in the cylinder high register. After power-up, the card defaults to operate at the highest performance and therefore in the highest current mode. Values outside this programmable range are accepted by the card. However, the card will operate either at the lowest power or highest performance as appropriate. 71/90 CF-ATA command description SMCxxxBF M Table 68. Set Features Bit 7 6 5 432 1 0 Command (7) EFh C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) Config Feature (1) Feature Table 69. Features supported Feature Operation 01h Enable 8-bit data transfers 03h Set transfer mode based on value in sector count register 55h Disable read look ahead 69h NOP accepted for backward compatibility 81h Disable 8-bit data transfer 96h NOP accepted for backward compatibility 97h Accepted for backward compatibility. Use of this feature is not recommended Set the host current source capability. Allows trade-off between current drawn and 9Ah read/write speed Table 70. Transfer mode values Mode Bits (7:3) Bits (2:0) PIO default mode 00000b 000b PIO default mode, disable 00000b 001b IORDY PIO flow control transfer (1) 00001b Mode mode Reserved 00010b N/A Multi-word DMA mode 00100b Mode 1. Mode = transfer mode number. 72/90 SMCxxxBF CF-ATA command description 10.18 Set Multiple Mode command (C6h) This command enables the card to perform read and write multiple operations and establishes the block count for these commands. The sector count register is loaded with the number of sectors per block. Upon receipt of the command, the card sets BSY and checks the sector count register. If the sector count register contains a valid value and the block count is supported, the value is loaded for all subsequent read multiple and write multiple commands and execution is enabled. If a block count is not supported, an aborted command error is posted, and Read Multiple and Write Multiple commands are disabled. If the sector count register contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled. At power- on the default mode is Read and Write Multiple disabled, unless it is disabled by a Set Feature command. Table 71 defines the Set Multiple Mode command byte sequence. Table 71. Set Multiple Mode Bit 7 6 543 2 1 0 Command (7) C6h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) Sector Count Feature (1) X 10.19 Set Sleep Mode command (99h or E6h) This command causes the CompactFlash memory card to set BSY, enter the sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command. Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter sleep mode immediately. The default value for the timer is 5 milliseconds. Note that this time base (5 ms) is different from the ATA specification. Table 72 defines the Set Sleep Mode command byte sequence. 73/90 CF-ATA command description SMCxxxBF Table 72. Set Sleep Mode Bit 765 4 3 2 1 0 Command (7) 99h or E6h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 10.20 Standby command (96h or E2) This command causes the card to set BSY, enter the sleep mode (which corresponds to the ATA ‘standby’ mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by issuing another command. Table 73 defines the Standby command byte sequence. Table 73. Standby Bit 7 6 54 32 1 0 Command (7) 96h or E2h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 10.21 Standby Immediate command (94h or E0h) This command causes the card to set BSY, enter the sleep mode (which corresponds to the ATA standby mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by issuing another command. Table 74 defines the Standby Immediate command byte sequence. 74/90 SMCxxxBF CF-ATA command description Table 74. Standby Immediate Bit 7 6 5432 1 0 Command (7) 94h or E0h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 10.22 Translate Sector command (87h) This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512-byte buffer of information containing the desired cylinder, head and sector, including its logical address, and the hot count, if available, for that sector. Table 75 defines the Translate Sector command byte sequence. Table 76 represents the information in the buffer. Table 75. Translate Sector Bit 7 6 5 432 1 0 Command (7) 87h C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) X Feature (1) X Table 76. Translate Sector information Address Information 00h-01h Cylinder MSB (00), cylinder LSB (01) 02h Head 03h Sector 04-06h LBA MSB (04) - LSB (06) 07-12h Reserved 13h Erased flag (FFh) = erased; 00h = not erased 14h-17h Reserved 18h-1Ah Hot count MSB (18) - LSB (1A); 0 = hot count not supported 1Bh-1FFh Reserved 75/90 CF-ATA command description SMCxxxBF 10.23 Wear Level command (F5h) This command is effectively a NOP command and only implemented for backward compatibility. The sector count register will always be returned with a ‘00h’ indicating wear level is not needed. Table 77 defines the Wear Level command byte sequence. Table 77. Wear Level Bit 7 6 5 4 3 2 1 0 Command (7) F5h C/D/H (6) X Drive Flag Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) Completion status Feature (1) X 10.24 Write buffer command (E8h) The Write Buffer command enables the host to overwrite contents of the card’s sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 bytes. Table 78 defines the Write Buffer command byte sequence. Table 78. Write Buffer Bit 7 6 5 432 1 0 Command (7) E8h C/D/H (6) X Drive X Cyl High (5) X Cyl Low (4) X Sect Num (3) X Sect Cnt (2) X Feature (1) X 76/90 SMCxxxBF CF-ATA command description 10.25 Write DMA command (CAh) This command uses DMA mode to write from 1 to 256 sectors as specified in the sector count register. If the sector count is set to ‘0’, 256 sectors will be read by issuing a Read DMA command. The transfer begins at the sector specified in the sector number register. When the Write DAM command is issued, the CompactFlash storage card asserts BSY and transfers all or part of the sector data in the buffer. The card can then set DRQ and clear BSY, although it is not required. The card asserts DMARQ when data are available to be transferred. The host then writes the 512*sector-count bytes of data to the card using the DMA protocol. When DMARQ is asserted by the card, the host asserts -DMACK to notify that it is ready to transfer data, and asserts -IOWR once for each 16-bit word to be transferred. Interrupts are not generated for each sector transfer, but when all sectors have been transferred or when an error occurred during the operation. An abort error is returned by the card when a Write DMA command is sent by the host and the 8-bit transfer mode has been enabled by the Set Features command. Table 79 defines the Write DMA command byte sequence. Table 79. Write DMA Bit 7 6 5 432 1 0 Command (7) CAh C/D/H (6) LBA Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 77/90 CF-ATA command description SMCxxxBF 10.26 Write Multiple command (C5h) This command is similar to the Write Sectors command. The card sets BSY within 400 ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the write sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = (sector count) module (block count). If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when write multiple commands are disabled, the write multiple operation will be rejected with an aborted command error. Errors encountered during write multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The command block registers contain the cylinder, head and sector number of the sector where the error occurred and the sector count register contains the residual number of sectors that need to be transferred for successful completion of the command. For example, each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The sector count register contains 6 and the address is that of the third sector. Note: The current revision of the CompactFlash memory card only supports a block count of 1 as indicated in the Identify Drive command information. The Write Multiple command is provided for compatibility with future products which may support a larger block count. Table 80 defines the Write Multiple command byte sequence. Table 80. Write Multiple Bit 765 4 3 2 1 0 Command (7) C5h C/D/H (6) 1 LBA 1 Drive Head Cyl High (5) Cylinder High Cyl Low (4) Cylinder Low Sect Num (3) Sector number Sect Cnt (2) Sector count Feature (1) X 78/90 SMCxxxBF CF-ATA command description 10.27 Write Multiple without Erase command (CDh) This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. Table 81 defines the Write Multiple without Erase command byte sequence. Table 81. Write Multiple without Erase Bit 7 6 5 432 1 0 Command (7) CDh Driv C/D/H (6) X LBA 1 Head e Cyl High (5) Cylinder High Cyl Low (4) Cylinder Low Sect Num (3) Sector number Sect Cnt (2) Sector count Feature (1) X 10.28 Write Sector(s) command (30h or 31h) This command writes from 1 to 256 sectors as specified in the sector count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the sector number register. When this command is accepted, the card sets BSY, sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurred. The command block registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. Table 82 defines the Write Sector(s) command byte sequence. 79/90 CF-ATA command description SMCxxxBF Table 82. Write Sector(s) Bit 7 6 543 2 1 0 Command (7) 30h or 31h C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 10.29 Write Sector(s) without Erase command (38h) This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. This command has the same protocol as the Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. If the sector is not pre-erased a normal write sector operation will occur. Table 83 defines the Write Sector(s) without Erase command byte sequence. Table 83. Write Sector(s) without Erase Bit 7 65432 1 0 Command (7) 38h LB C/D/H (6) 1 1 Drive Head (LBA 27-24) A Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 80/90 SMCxxxBF CF-ATA command description 10.30 Write Verify command (3Ch) This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write Sector(s) command. Table 84 defines the Write Verify command byte sequence. Table 84. Write Verify Bit 7 6 5432 1 0 Command (7) 3Ch C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sect Num (3) Sector number (LBA 7-0) Sect Cnt (2) Sector count Feature (1) X 81/90 CIS information (typical) SMCxxxBF 11 CIS information (typical) -------- 0000: Code 01, link 04 DF 79 01 FF -------- – Tuple CISTPL_DEVICE (01), length 4 (04) – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80ns – Write protect switch is not in control – Device size is 2K bytes -------- 000C: Code 1C, link 05 02 DF 79 01 FF -------- – Tuple CISTPL_DEVICE_OC (1C), length 5 (05) – Device conditions: V = 3.3V CC – Device type is FUNCSPEC – Extended speed byte used – Device speed is 80ns – Write protect switch is not in control – Device size is 2K bytes -------- 001A: Code 18, link 02 DF 01 -------- – Tuple CISTPL_JEDEC_C (18), length 2 (02) – Device 0 JEDEC id: Manufacturer DF, ID 01 -------- 0022: Code 20, link 04 0A 00 00 00 -------- – Tuple CISTPL_MANFID (20), length 4 (04) – Manufacturer # 0x000A hardware rev 0.00 -------- 002E: Code 15, link 12 04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00 00 FF 82/90 SMCxxxBF CIS information (typical) -------- – Tuple CISTPL_VERS_1 (15), length 18 (12) – Major version 4, minor version 1 – Product Information: Manufacturer: ‘Numonyx’, – Product name: ‘Numonyx-xxxxB’ -------- 0056: Code 21, link 02 04 01 -------- – Tuple CISTPL_FUNCID (21), length 2 (02) – Function code 04 (Fixed Disk), system init 01 -------- 005E: Code 22, link 02 01 01 -------- – Tuple CISTPL_FUNCE (22), length 2 (02) – This is a PC Card ATA Disk -------- 0066: Code 22, link 03 02 0C 0F -------- – Tuple CISTPL_FUNCE (22), length 3 (03) –V is not required PP – This is a silicon device – Identify Drive Model/Serial Number is guaranteed unique – Low-Power Modes supported: Sleep Standby Idle – Drive automatically minimizes power – All modes include 3F7 or 377 – Index bit is not supported – -IOIS16 is unspecified in Twin configurations -------- 0070: Code 1A, link 05 01 03 00 02 0F -------- – Tuple CISTPL_CONFIG (1A), length 5 (05) – Last valid configuration index is 3 – Configuration Register Base Address is 200 – Configuration Registers Present: Configuration Option Register at 200 – Card Configuration and Status Register at 202 – Pin Replacement Register at 204 – Socket and Copy Register at 206 83/90 CIS information (typical) SMCxxxBF -------- 007E: Code 1B, link 08 C0 C0 A1 01 55 08 00 20 -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08) – Configuration Table Index is 00 (default) – Interface type is Memory – BVDs not active, WP not active, RdyBsy active – Wait signal support required –V Power Description: Nom V = 5.0 V CC – map 2048 bytes of memory to Card address 0 – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown -------- 0092: Code 1B, link 06 00 01 21 B5 1E 4D -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 00 –V Power Description: Nom V = 3.30 V, Peak I = 45.0 mA CC -------- 00A2: Code 1B, link 0A C1 41 99 01 55 64 F0 FF FF 20 -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 10 (0A) – Configuration Table Index is 01 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required –V Power Description: Nom V = 5.0 V CC – Decode 4 I/O lines, bus size 8 or 16 – IRQ may be shared, pulse and level mode interrupts are supported – Interrupts in mask FFFF are supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown -------- 00BA: Code 1B, link 06 01 01 21 B5 1E 4D -------- Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 01 V Power Description: Nom V = 3.30 V, CC 84/90 SMCxxxBF CIS information (typical) Peak I = 45.0 mA -------- 00CA: Code 1B, link 0F C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20 -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) – Configuration Table Index is 02 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required –V Power Description: CC – Nom V = 5.0 V – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 01F0, length 8 – I/O block at 03F6, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown -------- 00EC: Code 1B, link 06 02 01 21 B5 1E 4D -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 02 –V Power Description: Nom V = 3.30 V, Peak I = 45.0 mA CC -------- 00FC: Code 1B, link 0F C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20 -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) – Configuration Table Index is 03 (default) – Interface type is I/O – BVDs not active, WP not active, RdyBsy active – Wait signal support not required –V Power Description: Nom V = 5.0 V CC – Decode 10 I/O lines, bus size 8 or 16 – I/O block at 0170, length 8 – I/O block at 0376, length 2 – IRQ may be shared, pulse and level mode interrupts are supported – Only IRQ14 is supported – Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 85/90 CIS information (typical) SMCxxxBF -------- 011E: Code 1B, link 06 03 01 21 B5 1E 4D -------- – Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) – Configuration Table Index is 03 –V Power Description: Nom V = 3.30 V, Peak I = 45.0 mA CC -------- 012E: Code 14, link 00 -------- – Tuple CISTPL_NO_LINK (14), length 0 (00) -------- 0134: Code FF -------- – Tuple CISTPL_END (FF) 86/90 SMCxxxBF Package mechanical 12 Package mechanical Figure 10. Type I CompactFlash memory card dimensions 1.60mm ± 0.5 (0.063in ± 0.002) 26 50 0.99mm± 0.05 (0.039in ± 0.002) 125 3.30mm ± 0.10 1.01mm ± 0.07 1.01mm ± 0.07 (0.130in ± 0.004) (0.039in ± 0.003) (0.039in ± 0.003) 2.44mm ± 0.07 (0.096in ± 0.003) Optional Configuration (see note) 2.15mm ± 0.07 (0.085in ± 0.003) 0.76mm ± 0.07 (0.030in ± 0.003) 1.65mm 41.66mm ± 0.13 (0.130in) (1.640in ± 0.005) 0.63mm ± 0.07 42.80mm ± 0.10 4X R 0.5mm ± 0.1 (0.025in ± 0.003) (1.685in ± 0.004) (4X R 0.020in ± 0.004) AI04301b 87/90 TOP 2X 12.00mm ± 0.1 (2X 0.472in ± 0.004) 2X 25.78mm ± 0.07 (2X 1.015in ± 0.003) 36.40mm ± 0.15 (1.433in ± 0.006) 2X 3.00mm ± 0.07 (2X 0.118in ± 0.003) Ordering information SMCxxxBF 13 Ordering information Table 85. Ordering information scheme Example: SMC 01G B F Y 6 E Memory card standard SMC = storage medium, CompactFlash Density 032 = 32 Mbytes 064 = 64 Mbytes 128 = 128 Mbytes 256 = 256 Mbytes 512 = 512 Mbytes 01G = 1 Gbyte 02G = 2 Gbytes 04G = 4 Gbytes Options of the standard B = CF type SM222 Memory type F = flash memory Card version Y= version depending on device technology Temperature range 6 = -40 to 85 °C Packing Blank = standard packing (tray) E = lead-free package, standard packing (tray) Note: Other digits may be added to the ordering code for pre-programmed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’.For further information on any aspect of the device, please contact your nearest Numonyx sales office. 88/90 SMCxxxBF Revision history 14 Revision history Table 86. Document revision history Date Revision Changes 22-Sep-2006 1 Initial release. Sustained write and read performances changed to 12.5 Mbyte/s and 19 Mbyte/s, respectively. Table 2: System performance and Table 3: Current consumption updated. Sectors_card and total addressable capacity updated for SMC04GBF in Table 6: CF capacity specification. Table 11: Input power 27-Oct-2006 2 updated. Note 1 updated below Figure 7: I/O write waveforms. Read byte access configuration CF+ (8 bits) mode removed from Table 32: Attribute memory function. 10-Dec-2007 3 Applied Numonyx branding. Sustained write and read performances changed to 15 Mbyte/s and 12-May-2008 4 22.5 Mbyte/s, respectively. Updated: Table 2: System performance and Table 3: Current consumption. Minor text changes. 89/90 SMCxxxBF Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 90/90