ST486DX/DX2 5 Volt CPUs PRELIMINARY DATA ON-CHIP 8-KBYTE WRITE-BACK CACHE - Up to 15% higher performance than write-through IMPROVED 486DX/DX2 PERFORMANCE (PC Bench 8.0, 80MHZ) - Clock doubled core speeds up to 80 MHz - Industry-wide write-back chipset suppor - Integrated FPU 10% faster than 80486DX - Burst-mode write capability - Up to 50 MHz bus speeds for fast local bus systems - Configurable as write-back or write-through INDUSTRY STANDARD 486 COMPATIBILITY ADVANCED POWER MANAGEMENT - 486DX socket and instruction set compatible - Fast SMI interrupt with separate memory space - Runs DOS, Windows, OS/2, UNIX - Fully static design permits dynamic clock control - Standard 168-pin PGA - Software or hardware initiated low power suspend - Automatic FPU power-down mode The SGS-THOMSON ST486DX/DX2 5 volt CPUs areadvanced These processors are designed to meet the power management 486DX/DX2 compatible processors. These CPUs incorporate an requirements in the newest generation of low-power desktops and on-chip 8KByte write-back cache and an integrated math coproc- notebooks. Power is saved by taking advantage of advanced power essor. management features such as static circuitry, SMM, and automatic FPU power-down. Fast entry and exit of SMM allowsfrequent use of The on-chipwrite-back cacheallowsup to 15% higher performance the SMM feature without noticeable performance degradation. by eliminating unnecessary external write cycles. On traditional write-through CPUs, these external write cycles can create bus This CPU family maintains compatibility with the installed base of bottlenecks affecting system wide performance. x86 software and provides essential socket compatibility with the 486DX/DX2 The integratedfloating point unit, improves performance up to 10% over the 80486DX as measured using Power Meter Whetstone test. 16-byte Decoder Instruction SUSP# Core Queue SMM, SUSPA# Clock Suspend Control Immediate Mode CLK Prefetch 32 and Data Bus ROM SMI# Address Clock Bus Sequencer Microcode ROM Clock Control SMADS# Control Immediate 8 Write Branch Control Memory Execution Unit Data Buffers Byte D31-D0 3-Input Bus Muxes Data Limit Multiplier Shift Register Adder & I/O Buffers Unit Unit File 32 Execution Pipeline Unit Regs Unit Linear Address Bus Control Bus Memory FPU Cacheand Memory 8 KByte Control Prefetch Management Instr/Data Management Unit Cache Unit Control A31-A2 BE3#-BE0# Address Instruction Address Bus Buffers Data AddressBus 486DX Compatible Bus Interface 1738600 1 ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW A list of ST486DX/DX2 5-volt parts, including 1.0 PRODUCT OVERVIEW their operating frequency, and package types The SGS THOMSON ST486DX 5-volt mi- are listed on page 12 of this document. croprocessors are advanced 486DX/DX2 mi- croprocessors. The ST486DX CPU operates at 1.1 Clock-Doubled CPU Core the same speed as the external bus and the The clock-doubled ST486DX2 CPU core oper- ST486DX2 CPU operates at twice the external ates at twice the frequency of the external bus speed. The ”ST486DX/DX2” designation clock input, while continuing to operate the bus refers to either the ST486DX or ST486DX2 mi- interface at the external clock frequency. This croprocessor. A more complete product de- configuration provides high frequency CPU scription can be found in the SGS-Thomson performance without requiring a high speed in- ST486DX/DX2 data book. (see ordering in- terface to external memory. structions). The ST486DX2 provides up to 1.8 times the The CPUs in the ST486DX/DX2 family are performance of a 486DX at the same external high speed 5-volt CPUs attaining clock-dou- clock frequency. This level of performance is bled core speeds of up to 80 MHz. achieved by doubling the frequency of the in- The ST486DX/DX2 8-KByte cache can be con- put clock and using the resulting signal to drive figured to run in traditional write-through the CPU core. To further enhance this architec- mode or in the higher performance write-back ture, the ST486DX2 reduces the performance mode. Write-back mode eliminates unneces- penalty of slow external memory accesses sary external memory write cycles offering up through use of an on-chip write-back cache and to 15% higher overall performance (80 MHz, eight write buffers. PC Bench 8.0) than write-through mode. The CPU core consists of a five-stage pipeline The ST486DX/DX2 supports 8, 16 and 32-bit optimized for minimal instruction cycle times data types and operates in real, virtual 8086 and includes all necessary hardware interlocks and protected modes. The CPU can access up to permit successive instruction execution over- to 4 GBytes of physical memory using a 32-bit lap. The execution stage of the pipeline exe- burst mode bus. Floating point instructions are cutes simple but frequently used instructions in parallel processed using an on-chip math co- a single clock cycle and the hardware multi- processor. plier executes 16-bit integer multiplies in only three clocks. The ST486DX/DX2 CPUs are ideal design so- lutions for low-powered ”Green PC” desktops 1.2 On-Chip Write-Back Cache as well as portable computers. These micro- processors typically draw only 450 μA, while The ST486DX/DX2 on-chip cache can be con- the input clock is stopped in suspend mode, figured to run in traditional write-through mode or in a higher performance write-back due to their static design. System Management mode. The write-back cache mode was specifi- Mode (SMM) allows the implementation of cally designed to optimize performance of the transparent system power management or the software emulation of I/O peripheral devices. CPU core by eliminating bus bottlenecks caused by unnecessary external write cycles. This write-back architecture is especially effec- 2 ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW tive in improving performance of the clock- 1.4 System Management Mode doubled ST486DX2 CPU. System Management Mode (SMM) provides Traditional write-through cache architectures an additional interrupt and a separate address require that all writes to the cache also update space that can be used for system power man- external memory simultaneously. These unnec- agement or software transparent emulation of essary write cycles create bottlenecks which re- I/O peripherals. SMM is entered using the Sys- sult in CPU stalls and adversely impact tem Management Interrupt (SMI#) or SMINT performance. In contrast, a write-back archi- instruction. While running in isolated SMM tecture allows data to be written to the cache address space, the SMI interrupt routine can without updating external memory. With a execute without interfering with the operating write-back cache, external write cycles are system or application programs. only required when a cache miss occurs, a After entering SMM, portions of the CPU state modified line is replaced in the cache, or when are automatically saved. Program execution an external bus master requires access to data. begins at the base of SMM address space. The The ST486DX/DX2 cache is an 8-KByte uni- location and size of the SMM memory are pro- fied instruction and data cache implemented us- grammable within the ST486DX/DX2. Eight ing a four-way set associative architecture and SMM instructions have been added to the 486 a least recently used (LRU) replacement algo- instruction set that permit software entry into rithm. The cache is designed for optimum per- SMM, as well as saving and restoring the total formance in write-back mode, however, the CPU state when in SMM mode. cache can be operated in write-through mode. The cache line size is 16 bytes and new lines 1.5 Power Management are only allocated during memory read cycles. The ST486DX/DX2 power management fea- Valid status is maintained on a 16-byte cache tures allow for a dramatic improvement in bat- line basis, but modified or ”dirty” status for tery life over systems designed with non-static write-back mode is maintained on a 4-byte 486 processors. During suspend mode the typi- (double-word) basis. Therefore, only the dou- cal current consumption is less than 1 percent ble-words that have been modified are written of the full operation current. back to external memory when a line is re- placed in the cache. The CPU core can access Suspend mode is entered by either a hardware the cache in a single internal clock cycle for or a software initiated action. Using the hard- both reads and writes. ware method to initiate suspend mode involves a two-pin handshake between the SUSP# and 1.3 FPU Operations SUSPA# signals. The software can initiate sus- pend mode through the execution of the HALT Since the FPU is resident within the CPU, the instruction. Once in suspend mode, the overhead associated with external math coproc- ST486DX/DX2 power consumption is further essor cycles is eliminated. If the FPU is not in reduced by stopping the external clock input. use, the FPU is automatically powered down. The resulting current draw is typically less This feature reduces overall power consump- than 500 μA. Since the ST486DX/DX2 is tion. The integrated FPU results in the addi- static, no internal data is lost when the clock is tion of two new pins FERR# (replaces stopped. ERROR#) and IGNNE#. 3 ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW 1.6 Signal Summary The ST486DX/DX2 signal set includes five cache interface signals, two coprocessor interface sig- nals, two power management signals, and two system management mode signals. A31-A2 ADS# A20M# BE3#-BE0# 1 AHOLD BLAST# BOFF# BREQ BRDY# BS16#, BS8# D31-D0 ST486DX/DX2 CLK CPU D/C# EADS# 1 FLUSH# 1 DP3-DP0 IGNNE# 2 2 FERR# INTR 1 HITM# INVAL 1 HLDA HOLD LOCK# KEN# 1 M/IO# NMI 1 PCD RDY# PCHK# RESET PLOCK# SMI# 4 1 PWT SUSP# 3 RPLSET(1-0) 1 UP# 1 RPLVAL# WM_RST 5 4 SMADS# 3 SUSPA# W/R# 1 - Cache Interface 4 - System Management Mode 2 - Coprocessor Interface 5 - Reset Input 3 - Power Management 1738000 Figure 1 - 1. 4 ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS not require connection to external pull-up or 2.0 ELECTRICAL pull-down resistors. The SUSP# pin is unique SPECIFICATIONS in that it is connected to a pull-up resistor only Electrical specifications in this chapter are when SUSP# is not asserted. valid for both the ST486DX and the clock-dou- bled ST486DX2. The ST486DX2 differs from Table 2 - 1. Pins Connected to Inter- the ST486DX in that the ST486DX2 internal nal Pull-Up and Pull-Down Resistors CPU core operates at twice the frequency of SIGNAL RESISTOR the bus interface. A20M# 20-kΩ pull-up AHOLD 20-kΩ pull-down 2.1 Electrical Connections BOFF# 20-kΩ pull-up BS16# 20-kΩ pull-up BS8# 20-kΩ pull-up 2.1.1 Power and Ground BRDY# 20-kΩ pull-up Connections and EADS# 20-kΩ pull-up Decoupling FLUSH# 20-kΩ pull-up IGNNE# 20-kΩ pull-up Due to the high frequency of operation of the INVAL 20-kΩ pull-up ST486DX/DX2, it is necessary to install and KEN# 20-kΩ pull-up test this device using standard high frequency RDY# 20-kΩ pull-up UP# 20-kΩ pull-up techniques. The high clock frequencies used SUSP# 20-kΩ pull-up in the ST486DX/DX2 and its output buffer cir- WM_RST 20-kΩ pull-down cuits can cause transient power surges when several output buffers switch output levels si- multaneously. These effects can be minimized by filtering the DC power leads with low-in- It is recommended that the ADS#, LOCK# ductance decoupling capacitors, using low im- and SMI# output pins be connected to pull-up pedance wiring, and by utilizing all of the resistors, as indicated in Table 2-2. The exter- VCC and GND pins. nal pull-ups guarantee that the signals remain negated during hold acknowledge states. 2.1.2 Pull-Up/Pull-Down Resistors Table 2 - 2. Pins Requiring External Pull-Up Resistors Table 2-1 lists the input pins which are inter- SIGNAL EXTERNAL RESISTOR nally connected to pull-up and pull-down resis- ADS# 20-kΩ pull-up tors. The pull-up resistors are connected to LOCK# 20-kΩ pull-up VCC and the pull-down resistors are con- SMI# 20-kΩ pull-up nected to VSS. When unused, these inputs do 5 ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS 2.1.3 Unused Input Pins 2.2 Absolute Maximum Ratings All inputs not used by the system designer and The following table lists absolute maximum not listed in Table 2-1 (Page 5) should be con- ratings for the ST486DX/DX2 microproces- nected either to ground or to VCC. Connect sors. Stresses beyond those listed under Table active-high inputs to ground through a 2-3 limits may cause permanent damage to the device. These are stress ratings only and do 20 kΩ (±10%) pull-down resistor and active- not imply that operation under any conditions low inputs to VCC through a 20 kΩ (±10%) other than those listed under ”Recommended pull-up resistor to prevent possible spurious op- Operating Conditions” Table 2-4 (Page 6) is eration. possible. Exposure to conditions beyond Ta- 2.1.4 NC Designated Pins ble 2-3 may (1) reduce device reliability and (2) result in premature failure even when there Pins designated NC should be left discon- is no immediately apparent sign of failure. nected. Connecting an NC pin to a pull-up re- Prolonged exposure to conditions at or near sistor, pull-down resistor, or an active signal the absolute maximum ratings (Table 2-3) may could cause unexpected results and possible also result in reduced useful life and reliability. circuit malfunctions. Table 2 - 3. Absolute Maximum Ratings ST486DX/DX2 PARAMETER UNITS NOTES MIN MAX Case Temperature -65° +110° C Power Applied Storage Temperature -65° +150° C No Bias Supply Voltage, VCC -0.5 6.5 V With Respect to V SS Voltage On Any Pin -0.5 V + 0.5 V With Respect to V CC SS Input Clamp Current, IIK 10 mA Power Applied Output Clamp Current, IOK 25 mA Power Applied 2.3 Recommended Operating Conditions Table 2-4 presents the recommended operating conditions for the ST486DX/DX2 device. Table 2 - 4. Recommended Operating Conditions ST486DX/DX2 PARAMETER UNITS NOTES MIN MAX TC Case Temperature 0° +85° C Power Applied V Supply Voltage 4.75 5.25 V With Respect to Vss CC V High Level Input 2 V +0.3 V IH CC V Low Level Input -0.3 0.8 V IL IOH Output Current (High) -1 mA VOH=VOH(MIN) I Output Current (Low) 5 mA V =V OL OL OL(MAX) 6 ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS 2.4 DC Characteristics Table 2 - 5. DC Characteristics (at Recommended Operating Conditions) ST486DX/DX2 PARAMETER UNITS NOTES MIN MAX V Output Low Voltage 0.45 V OL I =5 mA OL V Output High Voltage 2.4 V OH I =-1mA OH ILI Input Leakage Current ±15 μA 0