128MB to 16GB ATA PC Card www.stec-inc.com SLATAxxx(M/G)M1U(I) Solid-State Memory Card General Description and Key Features (No Moving Parts) STEC’s flash storage adheres to the latest industry compliance and regulatory standards including UL, FCC, RoHS, and various compliance associations. Each Capacity: 128MB - 16GB device incorporates a proprietary state-of-the-art flash memory controller that provides the greatest flexibility to customer-specific applications while supporting key flash management features resulting in the industry’s highest reliability and endurance. Key ATA-5 Compatible features include:  Built-in ECC engine detects up to 5-byte and corrects up to 4-byte errors ATA Transfer modes:  Sophisticated block management and wear leveling algorithms guarantees 2,000,000 write/erase cycles  PIO 0-6, MWDMA 0-4  Power-down data protection ensures data integrity and errors in case of power loss  Lifecycle management feature allows users to monitor the device’s block  PIO 0-6 only (for applications management that require MWDMA access to STEC’s ATA PC Card is the product of choice in applications requiring high reliability be disabled) and high tolerance to shock, vibration, humidity, altitude, ESD, and temperature. The rugged industrial design combined with industrial temperature (-40°C to 85°C) testing Supports TrueIDE and PC Card and adherence to rigid JEDEC JESD22 standards ensures flawless execution in the harshest environments. Memory and I/O Modes In addition to custom hardware and firmware designs, STEC also offers value-added services including: Form Factors:  Custom labeling and packaging  Custom software imaging and ID strings  PC Card Type II  Full BOM control and product change notification  Total supply-chain management to ensure continuity of supply Endurance Guarantee of 2,000,000  In-field application engineering to help customers through product design-ins Write/Erase Cycles Ordering Information: ATA PC Card Card Information Structure (CIS) Part Number PC Card Form Factor Capacity Programmed into 256 Bytes of Internal Memory SLATA128MM1U(I) Type II 128 Mbytes SLATA256MM1U(I) Type II 256 Mbytes PC Card and Socket Services SLATA512MM1U(I) Type II 512 Mbytes Release 2.1 or later compatible SLATA1GM1U(I) Type II 1 GByte SLATA2GM1U(I) Type II 2 GBytes 5V or 3.3V Power Supply SLATA4GM1U(I) Type II 4 GBytes SLATA8GM1U(I) Type II 8 GBytes Commercial and Industrial SLATA16GM1U(I) Type II 16 GBytes Operating Temperature Range Legend: 5-Byte Detection, 4-Byte Correction  SLATA = STEC standard ATA PC Card part number prefix. ECC Engine  (M/G) = proceeding capacity (xxx) is in Megabytes (M) or Gigabytes (G).  M1 = STEC Mach 1 controller. 10 Year Data Retention  U = RoHS-6 compliant lead-free. RoHS-6 Compliant  Part numbers without (I) = Commercial temperature range (0ºC to 70ºC).  I = Industrial temperature range (-40ºC to +85 ºC).  F = media set to fixed storage for non-removable IDE applications. Use with operating systems, such as Windows XP, that require storage media to be identified as a fixed drive before it can be used as a bootable drive. Example: SLATAxxx(M/G)M1U(I)-F.  P = firmware programmed for PIO Modes 0-6 only for applications requiring MWDMA access to be disabled. Example: SLATAxxx(M/G)M1U(I)-P SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Table of Contents General Description and Key Features ................................................................................... 1 Ordering Information: ATA PC Card ....................................................................................... 1 1.0 Product Specifications ..................................................................................................... 3 1.1 Labeling ........................................................................................................................................ 3 1.2 Package Dimensions and Pin Locations ...................................................................................... 4 1.3 Pin Assignment ............................................................................................................................. 5 1.4 Signal Descriptions ....................................................................................................................... 6 1.6 CHS Parameters .......................................................................................................................... 9 1.7 Standards Compliance ............................................................................................................... 10 1.7.1 CE and FCC Class B & D ....................................................................................................... 10 1.7.2 RoHS ....................................................................................................................................... 10 2.0 Environmental Specifications .........................................................................................11 2.1 Recommended Operating Conditions ........................................................................................ 11 2.2 Reliability .................................................................................................................................... 11 2.3 Shock, Vibration, and Humidity .................................................................................................. 11 3.0 Electrical Specifications .................................................................................................12 3.1 Absolute Maximum Ratings ........................................................................................................ 12 3.2 DC Characteristics...................................................................................................................... 12 3.3 AC Characteristics ...................................................................................................................... 13 3.3.1 PC Card Memory Mode Attribute Memory Read .................................................................... 13 3.3.2 PC Card Memory Mode Attribute Memory Write .................................................................... 14 3.3.3 PC Card Memory Mode Common Memory Read ................................................................... 15 3.3.4 PC Card Memory Mode Common Memory Write ................................................................... 16 3.3.5 PC Card I/O Mode Read AC Characteristics .......................................................................... 17 3.3.6 PC Card I/O Mode Write AC Characteristics .......................................................................... 18 3.3.7 True IDE Mode Register Access ............................................................................................. 19 3.3.8 True IDE Mode PIO Access .................................................................................................... 20 3.3.9 True IDE Mode Multiword DMA (not used for part numbers with P) ....................................... 22 3.4 PC Card Memory and I/O Modes Power Up to READY and RESET to READY ........................ 23 4.0 Host Access Specification ..............................................................................................24 4.1 Task File Register and Byte/Word/Odd-Byte Mode Mappings ................................................... 24 4.2 Host Access Interface Modes ..................................................................................................... 24 4.3 Card Information Structure (CIS) ................................................................................................ 25 4.4 Identify Drive Parameter Information .......................................................................................... 29 5.0 Registers ..........................................................................................................................30 5.1 Configuration Registers .............................................................................................................. 30 5.2 Task File Registers ..................................................................................................................... 31 6.0 Supported ATA Commands ............................................................................................32 7.0 Revision History ..............................................................................................................34 61000-04497-117, April 2008 2 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 1.0 Product Specifications 1.1 Labeling STEC ATA Cards can be manufactured with standard labeling, or customer-specific, custom labeling. Standard labeling is shown in Figure 1. Figure 1: Standard Labeling 61000-04497-117, April 2008 3 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 1.2 Package Dimensions and Pin Locations Table 1 and Figure 2 show the mechanical dimensions of the PC Card Type II. Table 1: Mechanical dimensions PC Card Type II Parameter Value Length 85.60 ± 0.20 mm (3.370 ±. 0.008 in) Width 54.00 ± 0.10 mm (2.126 ± 0.004 in) Height (including label area) 5.00 mm (0.196 in) max Figure 2: Mechanical dimensions PC Card Type II 61000-04497-117, April 2008 4 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 1.3 Pin Assignment Table 2: ATA PC Card Pin Assignment Pin Pin Signal Name Pin Type Signal Name Pin Type Number Number 1 GND Ground 35 GND Ground 2 D03 I/O 36 -CD1 O 3 D04 I/O 37 D11 I/O 4 D05 I/O 38 D12 I/O 5 D06 I/O 39 D13 I/O 6 D07 I/O 40 D14 I/O 7 -CE1, -CS0 I 41 D15 I/O 8 A10 I 42 -CE2, -CS1 I 9 -OE, -ATASEL I 43 -VS1 O 10 N/C 44 -IORD I 11 A09 I 45 -IOWR I 12 A08 I 46 N/C 13 N/C 47 N/C 14 N/C 48 N/C 15 -WE I 49 N/C 16 RDY/-BSY, -IREQ, INTRQ O 50 N/C 17 VCC Power 51 VCC Power 18 N/C 52 N/C 19 N/C 53 N/C 20 N/C 54 N/C 21 N/C 55 N/C 22 A07 I 56 -CSEL I 23 A06 I 57 -VS2 O 24 A05 I 58 RESET, -RESET I 25 A04 I 59 -WAIT, IORDY O -INPACK, 26 A03 I 60 DMARQ (not used for part O numbers with P) -REG, 27 A02 I 61 -DMACK (not used for part I numbers with P) 28 A01 I 62 BVD2, -SPKR, -DASP I/O 29 A00 I 63 BVD1, -STSCHG, -PDIAG I/O 30 D00 I/O 64 D08 I/O 31 D01 I/O 65 D09 I/O 32 D02 I/O 66 D10 I/O 33 WP, -IOIS16 O 67 -CD2 O 34 GND Ground 68 GND Ground Legend: ―-― = Low active 61000-04497-117, April 2008 5 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 1.4 Signal Descriptions Table 3: ATA PC Card Signal Descriptions Pin Signal Name Type Description Number BVD2 I/O 62 This output line is always driven to a high state in Memory (PC Card Memory Mode) Mode since a battery is not required for this product. -SPKR This output line is always driven to a high state in I/O Mode (PC Card I/O Mode) since this product produces no audio. -DASP In the True IDE Mode, this input/output is the Disk (True IDE Mode) Active/Slave Present signal in the Master/Slave handshake protocol. -CD1, -CD2 I/O 36, 67 These Card Detect pins are connected to ground on the card. (PC Card Memory Mode) They are used by the host to determine that the card is fully inserted into the socket. -CD1, -CD2 This signal is the same as Memory Mode. (PC Card I/O Mode) -CD1, -CD2 These signals are not used in IDE Mode. (True IDE Mode) D15-D00 I/O 37, 38, These lines carry the data, commands, and host and the (PC Card Memory Mode) 39, 40, controller. D00 is the LSB of the LSB of the Odd Byte of the 41, 66, Word. 65, 64, 6, 5, 4, 3, 2, 32, 31, 30 D15-D00 This signal is the same as the PC Card Memory Mode signal. PC Card I/O Mode D15-D00 In True IDE Mode, all Task File operations occur in byte (True IDE Mode) mode on the low order bus D00-D07 while all data transfers are 16 bit using D00-D15. -IOWR I 45 This signal is not used in this mode. (PC Card Memory Mode) -IOWR The I/O Write strobe pulse is used to clock I/O data onto the (PC Card I/O Mode) data bus and into the controller registers. The clocking occurs on the negative to positive edge of the signal (trailing edge). -IOWR In True IDE Mode, this signal has the same function as in PC (True IDE Mode) Card I/O Mode. -IORD I 44 This signal is not used in this mode. (PC Card Memory Mode) -IORD This is an I/O Read strobe generated by the host. This signal (PC Card I/O Mode) gates I/O data onto the bus from the ATA PC Card. -IORD In True IDE Mode, this signal has the same function as in PC (True IDE Mode) Card I/O Mode. -WE I 15 This is a signal driven by the host and used for strobing (PC Card Memory Mode) memory write data into the registers. It is also used for writing the configuration registers. -WE In PC Card I/O Mode, this signal is used for writing the (PC Card I/O Mode) configuration registers. -WE In True IDE Mode, this input signal is not used and should be (True IDE Mode) connected to VCC. -OE I 9 This is an Output Enable strobe generated by the host interface. (PC Card Memory Mode) It is used to read data from the ATA PC Card in PC Card Memory Mode and to read the CIS and configuration registers. 61000-04497-117, April 2008 6 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Pin Signal Name Type Description Number -OE In PC Card I/O Mode, this signal is used to read the CIS and (PC Card I/O Mode) configuration registers. -ATASEL To enable True IDE Mode, this input should be grounded by (True IDE Mode) the host. RDY/-BSY O 16 In Memory Mode, this signal is set high when the ATA PC (PC Card Memory Mode) Card is ready to accept a new data transfer operation and held low when the ATA PC Card is busy. The host must provide a pull-up resistor. At power up and at reset, the RDY/-BSY signal is held low (busy) until the ATA PC Card completes its power up or reset function. No access of any type should be made to the ATA PC Card during this time. The RDY/-BSY signal is held high (disabled from being busy) when the ATA PC Card is powered up with RESET continuously disconnected or asserted high. -IREQ After the ATA PC Card has been configured for I/O operation, (PC Card I/O Mode) this signal is used as the active low interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. INTRQ In True IDE Mode, this signal is the active high interrupt (True IDE Mode) request to the host. A10-A0 I 8, 11, 12, These address lines along with the -REG signal are used to (PC Card Memory Mode) 22, 23, select the following: the I/O port address registers within the 24, 25, ATA PC Card, the memory mapped port address registers 26, 27, within the ATA PC Card, a byte in the CIS and the 28, 29 Configuration Control and Status Registers. A10-A0 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) A2-A0 27, 28, 29 In True IDE Mode only, A2:A0 are used to select the one of (True IDE Mode) eight registers in the Task File. The remaining address lines should be grounded. -CE1, -CE2 I 7, 42 These input signals are used both to select the ATA PC Card (PC Card Memory Mode and to indicate to the ATA PC Card whether a byte or a word Card Enable operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, -CE2 allows 8-bit hosts to access all data on D0-D7. -CE1, -CE2 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) Card Enable -CS0, -CS1 In the True IDE Mode, -CS0 is the chip select for the task file (True IDE Mode) registers while -CS1 is used to select the Alternate Status Register and the ATA PC Card Control Register. -CSEL I 56 This signal is not used for this mode. (PC Card Memory Mode) -CSEL This signal is not used for this mode. (PC Card I/O Mode) -CSEL This internally pulled up signal is used to configure the card (True IDE Mode) as a Master or Slave. When the pin is grounded, the card is configured as a Master. When the pin is open, the card is configured as a Slave. -REG I 61 This signal distinguishes between accesses to Common (PC Card Memory Mode) Memory (high) and Register Attribute Memory (low). Attribute Memory Select 61000-04497-117, April 2008 7 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Pin Signal Name Type Description Number -REG The signal must also be active (low) during I/O Cycles when (PC Card I/O Mode) the I/O address is on the bus. -DMACK (not used for part In True IDE Mode this input signal is used by host in numbers with P) response to DMARQ to initiate DMA transfers. (True IDE Mode) WP O 33 The ATA PC Card does not have a write protect switch; (PC Card Memory Mode) therefore, this signal is held low after the completion of the Write Protect reset initialization sequence. -IOIS16 A low signal indicates that a 16 bit or odd byte only operation (PC Card I/O Mode) can be performed at the addressed port. -IOCS16 Not defined in IDE Mode. (True IDE Mode) -INPACK O 60 This signal is not used in this mode. (PC Card Memory Mode) -INPACK The Input Acknowledge signal is asserted by the ATA PC (PC Card I/O Mode) Card when it is selected and responding to an I/O read cycle Input Acknowledge at the address that is on the bus. The host uses this signal to control the enable of any input data buffers between the ATA PC Card and the host’s CPU. DMARQ (Not used for part In True IDE Mode this signal is asserted by the ATA PC Card numbers with P) when it is ready to transfer data to/from the host. Data (True IDE Mode) direction is controlled by -IORD and -IOWR. This signal is used in a handshake manner with -DMACK. BVD1 I/O 63 This signal is asserted high as since a battery is not used (PC Card Memory Mode) with this product. -STSCHG This signal is asserted low to alert the host to changes in the (PC Card I/O Mode) RDY/-BSY and Write Protect states. Its use is controlled by Status Changed the Configuration and Status Register. -PDIAG In True IDE Mode, this input/output signal is the Pass (True IDE Mode) Diagnostic signal in the Master/Slave handshake protocol. -WAIT O 59 This signal is not used by the ATA PC Card, and is pulled up (PC Card Memory Mode) to VCC through a 4.7K ohm resistor. -WAIT This signal is not used by the ATA PC Card, and is pulled up (PC Card I/O Mode) to VCC through a 4.7K ohm resistor. IORDY This signal is not used by the ATA PC Card, and is pulled up (True IDE Mode) to VCC through a 4.7K ohm resistor. GND GND 1, 34, 35, Ground (PC Card Memory Mode) 68 GND Ground (PC Card I/O Mode) GND Ground (True IDE Mode) VCC VCC 17, 51 +5 V or 3.3V power (PC Card Memory Mode) VCC +5 V or 3.3V power (PC Card I/O Mode) VCC +5 V or 3.3V power (True IDE Mode) RESET I 58 When RESET is high, this signal resets the ATA PC Card. The (PC Card Memory Mode) ATA PC Card is reset only at power up if this signal is left high or open from power-up. The ATA PC Card can also be reset when the soft reset bit in the Configuration Option Register is set. 61000-04497-117, April 2008 8 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Pin Signal Name Type Description Number RESET This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) -RESET In the True IDE Mode this input pin is the active low hardware (True IDE Mode) reset from the host. -VS1 O 43, 57 -VS1 is grounded so that the card CIS can be read at 3.3 -VS2 volts. -VS2 is reserved for a secondary voltage and is not (PC Card Memory Mode) connected.. -VS1 This signal is the same for all models. -VS2 (PC Card I/O Mode) -VS1 This signal is not used in IDE Mode. -VS2 (True IDE Mode) 1.5 Performance Table 4: ATA PC Card Read/Write Performance Parameter Value Data transfer rate to/from host 16.7 MBytes/s (burst) Sustained read up to 10 MBytes/s Sustained write up to 7 MBytes/s 1.6 CHS Parameters Table 5: CHS Parameters per capacity Capacity Cylinder (C) Head (H) Sectors/Track (S) 128MB 980 8 32 256MB 980 16 32 512MB 993 16 63 1GB 1,986 16 63 2GB 3,970 16 63 4GB 7,964 16 63 8GB 16,062 16 63 16GB 31,760 16 63 61000-04497-117, April 2008 9 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 1.7 Standards Compliance STEC products specified in this document are certified for compliance with the following industry standards:  PCMCIA v7.0  UL 950  CE, and FCC Class B & D  RoHS 1.7.1 CE and FCC Class B & D The STEC products specified in this document meet the following requirements and limits of the European Standards:  Class B requirements of the following European Standard: EN 55022: 1998 – ―Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement‖  Class D limits of the following European Standards: EN 61000-3-2 ―Electromagnetic compatibility (EMC) Part 3-2: Limits – Limits for harmonic current emissions (equipment input current up to and including 16 A per phase)‖ EN 61000-3-3: 1995 – ―Part 3: Limits – Section 3: Limitation of voltage fluctuations and flicker in low-voltage supply systems for equipment with rated current <= 16A‖ EN 55024 – ―Information technology equipment – Immunity characteristics – Limits and methods of measurement‖ 1.7.2 RoHS STEC certifies that its products do not contain any of the restricted substances as stated below and are in compliance with RoHS EU directive 2002/95/EC, specifically:  Mercury (Hg)  Cadmium Cd)  Chromium VI (Cr +6)  Polybrominated biphenyl (PBB)  Polybrominated biphenyl ether (PBDE)  Lead (Pb) Materials used in the STEC’s products are limited to the following:  Steel, Nylon 6/6, PCB laminate  Copper, Gold, Nickel  Silicon on ICs and Components  Polyester on Labels 61000-04497-117, April 2008 10 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 2.0 Environmental Specifications 2.1 Recommended Operating Conditions Table 6: ATA PC Card Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Commercial Operating Temperature Ta 0 25 70 C Industrial Operating Temperature Ta -40 - 85 C VCC voltage 5.0 VCC5 4.75 5.0 5.25 V VCC voltage 3.3 VCC3.3 3.18 3.3 3.465 V 2.2 Reliability Table 7: ATA PC Card Endurance & Data Reliability Parameter Value Endurance 2,000,000 Write/Erase Cycles 14 Data reliability 1 in 10 bits, read Data retention 10 years 2.3 Shock, Vibration, and Humidity Table 8: ATA PC Card Shock, Vibration & Humidity Parameter Value 1.5K G peak, 0.5ms pulse duration, five (5) pulses per each of six (6) directions Shock (per JEDEC JESD22 standard, method B110) 20 G peak, 20Hz-2000Hz, 4 cycles per direction Vibration (per JEDEC JESD22 standard, method B103) Humidity 85°C 85% RH, 500 hrs 61000-04497-117, April 2008 11 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.0 Electrical Specifications 3.1 Absolute Maximum Ratings Table 9: ATA PC Card Absolute Maximum Ratings Parameter Symbol Value Unit Voltage Vin, Vout -0.5 to VCC +0.5 V Storage temperature range Tstg -65 to +150 C 3.2 DC Characteristics Measurements at Recommended Operating Conditions unless otherwise specified. Table 10: ATA PC Card DC Characteristics Symbol Parameter Min Max Unit Notes VIL Input LOW Voltage -0.3 +0.8 V VCC=3.3V or 5.0V VIH Input HIGH Voltage 2.0 VCC +0.3 V VCC=3.3V or 5.0V VOL3.3 Output LOW Voltage 3.3 0.45 V VCC=3.3V VOL5 Output LOW Voltage 5 0.8 VCC=5.0V VOH Output HIGH Voltage 2.4 V VCC=3.3V or 5.0V ICCSB Standby Mode 2 mA ICC at VCC=3.3V or 5.0V ICC at VCC=3.3V or 5.0V; ICC Operating Current 75 mA Operating current measured with 2-way interleaving. ILI Input Leakage Current 10 µA VCC=3.3V or 5.0V ILO3.3 Output Leakage Current 3.3 1 µA VCC=3.3V ILO5 Output Leakage Current 5 2 µA VCC= 5.0V CI/O Input/output Capacitance 25 pF VCC=3.3V or 5.0V 61000-04497-117, April 2008 12 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3 AC Characteristics Measurements at Recommended Operating Conditions, unless otherwise specified. 3.3.1 PC Card Memory Mode Attribute Memory Read Table 11: PC Card Memory Mode Attribute Memory Read AC Characteristics Parameter Symbol IEEE Symbol Min (ns) Max (ns) Read Cycle Time tc(R) tAVAV 250 Address Access Time ta(A) tAVQV 250 Card Enable Access Time ta(CE) tELQV 250 Output Enable Access Time ta(OE) tGLQV 125 Output Disable Time from -CE tdis(CE) tEHQZ 100 Output Disable Time from -OE tdis(OE) tGHQZ 100 Address Setup Time tsu(A) tAVGL 30 Output Enable Time from -CE ten(CE) tELQNZ 5 Output Enable Time from -OE ten(OE) tGLQNZ 5 Data Valid from Address Change tv(A) tAXQX 0 Address Hold Time th(A) — 20 -CE Setup Time tsu(CE) — 0 -CE Hold Time th(CE) — 20 Figure 3: PC Card Memory Mode Attribute Memory Read Timing Diagram 61000-04497-117, April 2008 13 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.2 PC Card Memory Mode Attribute Memory Write Table 12: PC Card Memory Mode Attribute Memory Write AC Characteristics Parameter Symbol IEEE Symbol Min (ns) Max (ns) Write Cycle Time tc(W) tAVAV 250 Write Pulse Width tw(WE) tWLWH 150 Address Setup Time tsu(A) tAVWL 30 Address Setup Time (-WE) tsu(A-WEH) — 180 -CE Setup Time (-WE) tsu(CE-WEH) — 180 Data Setup Time (-WE) tsu(D-WEH) tDVWH 80 Data Hold Time th(D) tWMDX 30 Write Recovery Time trec(WE) tWMAX 30 Output Disable Time (-WE) tdis(WE) — 100 Output Disable Time (-OE) tdis(OE) — 100 Output Enable Time (-WE) ten(WE) — 5 Output Enable Time (-OE) ten(OE) — 5 Output Enable Setup Time (-WE) tsu(OE-WE) — 10 Output Enable Hold Time (-WE) th(OE-WE) — 10 -CE Setup Time tsu(CE) — 0 -CE Hold Time th(CE) — 20 Figure 4: PC Card Memory Mode Attribute Memory Write Timing Diagram 61000-04497-117, April 2008 14 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.3 PC Card Memory Mode Common Memory Read Table 13: PC Card Memory Mode Common Memory Read AC Characteristics IEEE 250 ns Cycle 120 ns Cycle 100 ns Cycle 80 ns Cycle Parameter Symbol Symbol Time Mode Time Mode Time Mode Time Mode Output Enable Access Time ta(OE) tGLQV 125 60 50 45 (max) Output Disable Time from OE tdis(OE) tGHQZ 100 60 50 45 (max) Address Setup tsu(A) tAVGL 30 15 10 10 Time (min) Address Hold th(A) tGHAX 20 15 15 10 Time (min) CE Setup tsu(CE) tELGL 0 0 0 0 before OE (min) CE Hold following OE th(CE) tGHEH 20 15 15 10 (min) Wait Delay Falling from OE tv(WT-OE) tGLWTV 35 35 35 N/A (max) Data Setup for Wait Release tv(WT) tQVWTH 0 0 0 N/A (max) Wait Width tw(WT) tWTLWTH 350 350 350 N/A Time (max) Figure 5: PC Card Memory Mode Common Memory Read Timing Diagram 61000-04497-117, April 2008 15 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.4 PC Card Memory Mode Common Memory Write Table 14: PC Card Memory Mode Common Memory Write AC Characteristics 250 ns 120 ns 100 ns IEEE 80ns Cycle Parameter Symbol Cycle Time Cycle Time Cycle Time Symbol Time Mode Mode Mode Mode Data Setup before tsu tDVWH 80 50 40 30 WE (min) (D-WEH) Data Hold following th(D) tWMDX 30 15 10 10 WE (min) WE Pulse Width (min) tw(WE) tWLWH 150 70 60 55 Address Setup Time tsu(A) tAVWL 30 15 10 10 (min) CE Setup before WE tsu(CE) tELWL 0 0 0 0 (min) Write Recovery Time trec(WE) tWMAX 30 15 15 15 (min) Address Hold Time th(A) tGHAX 20 15 15 15 (min) CE Hold following WE th(CE) tGHEH 20 15 15 10 (min) Wait Delay Falling tv(WT- tWLWTV 35 35 35 N/A from WE (max) WE) WE High from Wait tv(WT) tWTHWH 0 0 0 N/A Release (min) Wait Width Time tw(WT) wWTLWTH 350 350 350 N/A (max) Figure 6: PC Card Memory Mode Common Memory Write Timing Diagram 61000-04497-117, April 2008 16 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.5 PC Card I/O Mode Read AC Characteristics Table 15: PC Card I/O Mode Read AC Characteristics IEEE 250 ns Cycle 120 ns Cycle 100 ns Cycle 80 ns Cycle Parameter Symbol Symbol Time Mode Time Mode Time Mode Time Mode Data Delay after td(IORD) tIGLQV 100 50 50 45 -IORD (max) Data Hold following -IORD th(IORD) tIGHQX 0 5 5 5 (min) -IORD Width tw(IORD) tIGLIGH 165 70 65 55 Time (min) Address Setup before -IORD tsuA(IORD) tAVIGL 70 25 25 15 (min) Address Hold following -IORD thA(IORD) tIGHAX 20 10 10 10 (min) -CE Setup before -IORD tsuCE(IORD) tELIGL 5 5 5 5 (min) -CE Hold thCE(IORD) tIGHEH 20 10 10 10 following -IORD -REG Setup before -IORD tsuREG(IORD) tRGLIGL 5 5 5 5 (min) -REG Hold following – thREG(IORD) tIGHRGH 0 0 0 0 IORD (min) Figure 7: PC Card I/O Mode Read Timing Diagram 61000-04497-117, April 2008 17 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.6 PC Card I/O Mode Write AC Characteristics Table 16: PC Card I/O Mode Write AC Characteristics 250 ns 120 ns 100 ns IEEE 80 ns Cycle Parameter Symbol Cycle Time Cycle Time Cycle Time Symbol Time Mode Mode Mode Mode Data Setup before -IOWR tsu(IOWR) tDVIWH 60 20 20 15 (min) Data Hold following -IOWR th(IOWR) tIWHDX 30 10 5 5 (min) -IOWR Width tw(IOWR) tIWLIWH 165 70 65 55 Time (min) Address Setup before -IOWR tsuA(IOWR) tAVIWL 70 25 25 15 (min) Address Hold following –IOWR thA(IOWR) tIWHAX 20 20 10 10 (min) -CE Setup before tsuCE(IOWR) tELIWL 5 5 5 5 -IOWR (min) -CE Hold following -IOWR thCE(IOWR) tIWHEH 20 20 10 10 (min) -REG Setup before -IOWR tsuREG(IOWR) tRGLIWL 5 5 5 5 (min) -REG Hold following -IOWR thREG(IOWR) tIWHRGH 0 0 0 0 (min) Figure 8: PC Card I/O Mode Read Timing Diagram 61000-04497-117, April 2008 18 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.7 True IDE Mode Register Access Table 17: True IDE Mode Register Access AC Characteristics Parameter Symbol Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Unit Cycle time (min) t0 600 383 330 180 120 100 80 ns Address valid to -IORD/-IOWR t1 70 50 30 30 25 15 10 ns (min) setup -IORD/-IOWR pulse width 8bit t2 290 290 290 80 70 65 55 ns (min) -IORD/-IOWR recovery time t2i — — — 70 25 25 20 ns (min) -IOWR data t3 60 45 30 30 20 20 15 ns setup (min) -IOWR data t4 30 20 15 10 10 5 5 ns hold (min) -IORD data t5 50 35 20 20 20 15 10 ns setup (min) -IORD data hold t6 5 5 5 5 5 5 5 ns (min) -IORD data t6z 30 30 30 30 30 20 20 ns tristate (max) Addresses valid to -IOCS16 t7 90 50 40 N/A N/A N/A N/A ns assert. (max) Address valid to -IOCS16 t8 60 45 30 N/A N/A N/A N/A ns release (max) -IORD/-IOWR to address valid t9 20 15 10 10 10 10 10 ns hold 61000-04497-117, April 2008 19 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.8 True IDE Mode PIO Access Table 18: True IDE Mode PIO Access AC Characteristics Parameter Symbol Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Unit Cycle time (min) t0 600 383 330 180 120 100 80 ns Address valid to -IORD/-IOWR t1 70 50 30 30 25 15 10 ns (min) setup -IORD/-IOWR pulse width 8bit t2 290 290 290 80 70 65 55 ns (min) -IORD/-IOWR recovery time t2i — — — 70 25 25 20 ns (min) -IOWR data t3 60 45 30 30 20 20 15 ns setup (min) -IOWR data t4 30 20 15 10 10 5 5 ns hold (min) -IORD data t5 50 35 20 20 20 15 10 ns setup (min) -IORD data hold t6 5 5 5 5 5 5 5 ns (min) -IORD data t6z 30 30 30 30 30 20 20 ns tristate (max) Addresses valid to -IOCS16 t7 90 50 40 N/A N/A N/A N/A ns assert. (max) Address valid to t8 60 45 30 N/A N/A N/A N/A ns -IOCS16 release -IORD/-IOWR to address valid t9 20 15 10 10 10 10 10 ns hold 61000-04497-117, April 2008 20 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Figure 9: True IDE Mode PIO Access Timing Diagram 61000-04497-117, April 2008 21 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.3.9 True IDE Mode Multiword DMA (not used for part numbers with P) Table 19: True IDE Mode Multiword DMA AC Characteristics Parameter Symbol Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit Cycle time (min) t 480 150 120 100 80 ns 0 -IORD/-IOWR Asserted Pulse t 215 80 70 65 55 ns D (min) -IORD data access (max) t 150 60 50 50 45 ns E -IORD data hold (min) t 5 5 5 5 5 ns F -IORD/-IOWR data setup t 100 30 20 15 10 ns G (min) -IOWR data hold (min) t 20 15 10 5 5 ns H DMACK to t 0 0 0 0 0 ns I -IORD/-IOWR setup (min) -IORD/-IOWR to DMACK hold t 20 5 5 5 5 ns J (min) -IORD negated pulse width tKR 50 50 25 25 20 ns (max) -IOWR negated pulse width t 215 50 25 25 20 ns KW (min) -IORD to DMARQ delay (max) t 120 40 35 35 35 ns LR -IOWR to DMARQ delay t 40 40 35 35 35 ns LW (max) Figure 10: True IDE Mode Multiword DMA Timing Diagram 61000-04497-117, April 2008 22 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 3.4 PC Card Memory and I/O Modes Power Up to READY and RESET to READY Table 20: Power Up to READY and RESET to READY AC Characteristics Parameter Symbol Capacity Min Typ Max Unit 128MB 0.069 70 71 ms 256MB 0.073 73.8 74.1 ms Power up to READY t rdy 512MB 0.0702 70.3 70.3 ms 1GB 0.069 69.2 69.5 ms 128MB 0.048 48 48 ms 256MB 0.0521 52.1 52.2 ms RESET to READY t rdy 512MB 0.0483 48.3 48.5 ms 1GB 0.0469 47.1 47.3 ms Minimum Rec. Reset Width T (reset) - 0.200 - - ms w Figure 11: Power Up to RDY Timing Figure 12: RESET to RDY Timing 61000-04497-117, April 2008 23 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 4.0 Host Access Specification 4.1 Task File Register and Byte/Word/Odd-Byte Mode Mappings Please refer to the ATA PC Card standards for complete details on:  Task File Register mapping for the interface modes  Byte/Word/Odd-byte mode mapping within each of the interface modes 4.2 Host Access Interface Modes The host can access the ATA PC Card by using the following interface modes with the Task Registers:  PC Card Memory Mode, Attribute Memory The Card Information Structure (CIS) in Attribute Memory can be accessed by Byte/Word/Odd-byte modes in PC Card Memory Mode. The -REG signal must be asserted when accessing Attribute Memory. The ATA PC Card is mapped to PC Card Memory Mode by the Index bits in the Configuration Option Register. An example of a CIS is listed in 4.3, Card Information Structure (CIS).  PC Card Memory Mode, Common Memory Common Memory can be accessed in the Byte/Word/Odd Byte modes in PC Card Memory Mode. The -REG signal must be de-asserted when accessing the Common Memory. The ATA PC Card is mapped to PC Card Memory Mode by the Index bits in the Configuration Option Register  PC Card I/O Mode The ATA PC Card can be accessed by Byte/Word/Odd Byte modes in PC Card I/O Mode. The ATA PC Card is mapped to PC Card I/O Mode by the Index bits in the Configuration Option Register. The Index bits also select Contiguous I/O, Primary I/O, or Secondary I/O mapping when using the PC Card I/O Mode.  True-IDE mode The ATA PC Card is configured in a True IDE Mode of operation when the -ATASEL input signal is asserted GND by the host at power up. In the True IDE Mode, Attribute Registers are not accessible from the host. The Data Register is accessed in word (16-bit) mode at power up. The ATA PC Card permits 8-bit accesses if the host issues a Set Feature Command to put the ATA PC Card in 8-bit mode. Parameter information that the ATA PC Card uses in True IDE mode is returned when the Identify Drive command (ECh) is invoked. Refer to 4.4 Identify Drive Parameter Information for an example. 61000-04497-117, April 2008 24 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 4.3 Card Information Structure (CIS) The ATA PC Card uses a Card Information Structure (CIS) as summarized below: 1. 0000: Code 01, link 03 D9 01 FF Tuple CISTPL_DEVICE (01), length 3 (03) at offset 0  Device type is FUNCSPEC  Device speed is 250ns  Write protect switch is not in control  Device size is 2K bytes 2. 0005: Code 1C, link 04 03 D9 01 FF Tuple CISTPL_DEVICE_OC (1C), length 4 (04) at offset 5  Device conditions: minimum cycle with WAIT at Vcc = 3.3V  Device type is FUNCSPEC  Device speed is 250ns  Write protect switch is not in control  Device size is 2K bytes 3. 000B: Code 18, link 02 DF 01 Tuple CISTPL_JEDEC_C (18), length 2 (02) at offset B  Device 0 JEDEC id: Manufacturer DF, ID 01 4. 000F: Code 20, link 04 4D 01 00 01 Tuple CISTPL_MANFID (20), length 4 (04) at offset F  Manufacturer # 0x014D hardware rev 1.00 5. 0015: Code 15, link 13 04 01 53 54 49 00 46 6C 61 73 68 20 37 2E 30 2E 30 00 FF Tuple CISTPL_VERS_1 (15), length 19 (13) at offset 15  Major version 4, minor version 1  Product Information: "STI" (Manufacuturer) "Flash X.Y.Z" (Product Name) 6. 002A: Code 21, link 02 04 /xx 01 Tuple CISTPL_FUNCID (21), length 2 (02) at offset 2A  Function code 04 (Fixed), or xx (Removable), system init 01 7. 002E: Code 22, link 02 01 01 Tuple CISTPL_FUNCE (22), length 2 (02) at offset 2E  This is an PC Card ATA Disk 61000-04497-117, April 2008 25 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 8. 0032: Code 22, link 03 02 0C 0F Tuple CISTPL_FUNCE (22), length 3 (03) at offset 32  Vpp is not required  This is a silicon device  Identify Drive Model/Serial Number is guaranteed unique  Low-Power Modes supported: Sleep Standby Idle  Drive automatically minimizes power  All modes include 3F7 or 377  Index bit is not supported  -IOIS16 is unspecified in Twin configurations 9. 0037: Code 1A, link 05 01 03 00 02 0F Tuple CISTPL_CONFIG (1A), length 5 (05) at offset 37  Last valid configuration index is 3  Configuration Register Base Address is 200  Configuration Registers Present:  Configuration Option Register at 200  Card Configuration and Status Register at 202  Pin Replacement Register at 204  Socket and Copy Register at 206 10. 003E: Code 1B, link 08 C0 C0 A1 01 55 08 00 20 Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08) at offset 3E  Configuration Table Index is 00 (default)  Interface type is Memory  BVDs not active, WP not active, RdyBsy active  Wait signal support required  Vcc Power Description: Nom V = 5.0 V  Map 2048 bytes of memory to CF Card address 0  Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 11. 0048: Code 1B, link 06 00 01 21 B5 1E 4D Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) at offset 48  Configuration Table Index is 00  Vcc Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 61000-04497-117, April 2008 26 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 12. 0050: Code 1B, link 0A C1 41 99 01 55 64 F0 FF FF 20 Tuple CISTPL_CFTABLE_ENTRY (1B), length10 (0A) at offset 50 10 (0A) at offset 50  Configuration Table Index is 01 (default)  Interface type is I/O  BVDs not active, WP not active, RdyBsy active  Wait signal support not required  Vcc Power Description: Nom V = 5.0 V  Decode 4 I/O lines, bus size 8 or 16  IRQ may be shared, pulse and level mode interrupts are supported  Interrupts in mask FFFF are supported  Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 13. 005C: Code 1B, link 06 01 01 21 B5 1E 4D Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) at offset 5C  Configuration Table Index is 01  Vcc Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 14. 0064: Code 1B, link 0F C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20 Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) at offset 64  Configuration Table Index is 02 (default)  Interface type is I/O  BVDs not active, WP not active, RdyBsy active  Wait signal support not required  Vcc Power Description: Nom V = 5.0 V  Decode 10 I/O lines, bus size 8 or 16  I/O block at 01F0, length 8  I/O block at 03F6, length 2  IRQ may be shared, pulse and level mode interrupts are supported  Only IRQ14 is supported  Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 15. 0075: Code 1B, link 06 02 01 21 B5 1E 4D Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) at offset 75  Configuration Table Index is 02  Vcc Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 61000-04497-117, April 2008 27 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 16. 007D: Code 1B, link 0F C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20 Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) at offset 7D  Configuration Table Index is 03 (default)  Interface type is I/O  BVDs not active, WP not active, RdyBsy active  Wait signal support not required  Vcc Power Description: Nom V = 5.0 V  Decode 10 I/O lines, bus size 8 or 16  I/O block at 0170, length 8  I/O block at 0376, length 2  IRQ may be shared, pulse and level mode interrupts are supported  Only IRQ14 is supported  Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 17. 008E: Code 1B, link 06 03 01 21 B5 1E 4D Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) at offset 8E  Configuration Table Index is 03  Vcc Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 18. 0096: Code 14, link 00 Tuple CISTPL_NO_LINK (14), length 0 (00) at offset 96 19. 0098: Code FF Tuple CISTPL_END (FF) at offset 98 61000-04497-117, April 2008 28 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 4.4 Identify Drive Parameter Information An example of the parameter information received from the ATA PC Card when invoking the Identify Drive command (ECh) is listed in Table 21. Table 21: Identify Drive Parameter Information Word Total Data Description Address Bytes 0 848AH 2 Value fixed by CFA (value=044AH for part numbers with F suffix) 1 XXXXH 2 Default number of cylinders 2 0000H 2 Reserved 3 00XXH 2 Default number of heads Do not use this word. Before retirement, was number of unformatted bytes per 4 XXXXH 2 track Do not use this word. Before retirement, was number of unformatted bytes per 5 XXXXH 2 sector 6 XXXXH 2 Default number of sectors per track 7 - 8 XXXXH 4 Number of sectors per ATA PC Card (word 7 = MSW, word 8 = LSW) 9 0000H 2 Reserved 10 - 19 Unique per card 20 Serial Number in ASCII (20 characters): STEC proprietary 20 XXXXH 2 Do not use this word. Before retirement, was buffer type 21 XXXXH 2 Do not use this word. Before retirement, was buffer size in 512 byte increments 22 0004H 2 # of ECC bytes passed on Read/Write Long commands Firmware revision in ASCII (8 characters): Rev8.0.0 23 - 26 See description 8 52 65 76 38 2E 30 2E 30 hex Model Number in ASCII (40 characters): STI Flash 8.0.0 27 - 46 See description 40 53 54 49 20 46 6C 61 73 68 20 38 2E 30 2E 30 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 hex 47 0001H 2 Maximum of 1 sector on Read/Write Multiple command 48 0000H 2 Double Word not supported DMA supported, LBA supported 49 0300H 2 (0200H DMA not supported, LBA supported for part numbers with P) 50 0000H 2 Reserved 51 0200H 2 PIO data transfer cycle timing mode 52 0000H 2 Single word DMA data transfer cycle timing mode (not supported) 53 0003h 2 Words 54 - 58 and 64 - 70 are valid 54 XXXXH 2 Number of Current Cylinders 55 XXXXH 2 Number of Current Heads 56 XXXXH 2 Number of Current Sectors Per Track 57 XXXXH 2 LSW of the Current Capacity in Sectors 58 XXXXH 2 MSW of the Current Capacity in Sectors 59 010XH 2 Current Setting for Block Count=1 for R/W Multiple commands 60 - 61 XXXXH 4 Total number of sectors addressable in LBA Mode 62 0000H 2 Single word DMA transfer not supported Multiword DMA modes supported 63 0407H 2 (0000H Multiword DMA modes not supported for part numbers with P) 64 0003H 2 Advanced PIO modes supported (modes 3 and 4) Minimum multiword DMA transfer cycle time per word (ns) 65 0078H 2 (0000H for part numbers with P) Recommended multiword DMA transfer cycle time per word (ns) 66 0078H 2 (0000H for part numbers with P) 67 0078H 2 Minimum PIO transfer without flow control 68 0078H 2 Minimum PIO transfer with IORDY flow control 69 - 255 0000H 374 Reserved XXXXH = These values depend on the specific ATA PC Card. 61000-04497-117, April 2008 29 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 5.0 Registers This chapter lists the registers of the ATA PC Card. Refer to ATA PC Card standards for further details. 5.1 Configuration Registers In PC Card Mode, four configuration registers, as listed in Table 22, are used. Note: In True IDE Mode, these registers cannot be used. Table 22: Configuration Registers Configuration Register Description This register is used to configure and observe the status of the ATA PC Card, and to issue soft resets to it. Also, the Index bits of this register are Configuration Option Register used to select the PC Card mapping mode that the ATA PC Card uses: 1) PC Card Memory, 2) PC Card Contiguous I/O, 3).PC Card Primary I/O, and 4) PC Card Secondary I/O Configuration and Status Register This register is used for observing the ATA PC Card state. This register is used for providing the signal state of -IREQ when the ATA Pin Replacement Register PC Card is configured in the PC Card I/O Mode. This read/write register is used to identify the ATA PC Card from other Socket and Copy Register. devices. This register should be set by the host before this Configuration Option register is set. 61000-04497-117, April 2008 30 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 5.2 Task File Registers Table 23: ATA PC Card Task File Registers Task File Register Description The Data Register is a 16-bit read/write register used for transferring data Data Register between the ATA PC Card and the host. This register can be accessed in word mode and byte mode. The Error Register is a read-only register that is used for analyzing an error. This register is valid when the BSY bit in the Status register and Alternate Status register are set to ―0‖ (Ready). Diagnostic Codes are returned in the Error Error Register Register after a Execute Drive Diagnostic command (code 90h). Extended Error Codes returned in the Error Register after a Request Sense command (code 03h). This register contains the numbers of sectors of data requested to be transferred Sector Count Register on a read or write operation between the host and the ATA PC Card. If the value in the register is 0, a count of 256 sectors is indicated. When the LBA bit in the Drive/Head register is 0, this register contains the Sector Number Register starting sector number for any media access. When the LBA bit is set to 1, this register contains bits 7:0 of the LBA for any media access. In CHS mode (LBA=0), this register contains the low-order bits of the starting Cylinder Low Register cylinder address. In LBA mode, it contains bits 15:8 of the LBA. In CHS mode (LBA=0), this register contains the high-order bits of the starting Cylinder High Register cylinder address. In LBA mode, it contains bits 23:16 of the LBA. This register selects the ATA PC Card address translation (CHS or LBA) and Drive/Head Register provides head address (CHS) or high-order address bits 27:24 for LBA. This read-only register indicates status of a command execution. When the BSY Status Register bit is ―0‖, the other bits are valid; when the BSY bit is ―1‖, the other bits are not valid. When the register is read, the interrupt pin, is cleared. This register is the same as the Status register, except that is not negated when Alternate Status Register the register is read. This write-only register is used for controlling the interrupt request and issuing an Device Control Register ATA soft reset to the ATA PC Card. This read-only register is used for confirming the ATA PC Card’s status. This register is provided for compatibility with the AT disk drive interface and it is not Drive Address Register recommended that this register be mapped into the host’s I/O space because of potential conflicts on bit 7. This write-only register is used for writing the command that executes the ATA Command Register PC Card’s operation. The command code is written in the command register after its parameters are written in the Task File during the ATA PC Card ready state. 61000-04497-117, April 2008 31 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 6.0 Supported ATA Commands The ATA commands used by the ATA PC Card are listed in Table 24. Refer to ATA PC Card standards for details. Table 24: ATA PC Card Supported ATA Commands Command Set Code Description Check Power Mode E5h or 98h This command checks the power mode. This command performs the internal diagnostic tests Execute Drive Diagnostic 90h implemented by the ATA PC Card. The Diagnostic Code is returned in the Error Register. Erase Sector(s) C0h Command is used to pre-erase/condition data sectors in advance. Command writes the desired head/cylinder of the selected drive with a vender unique data pattern (typically 00h or FFh). This Format Track 50h ATA PC Card accepts a sector buffer of data from the host to follow the command with the same protocol as the Write Sector Command although the information in the buffer is not used. Command lets the host receive parameter information from the Identify Drive ECh ATA PC Card in the same protocol as Read Sector(s) command. Command causes the ATA PC Card to set BSY, enter the Idle mode, clear BSY, and generate an interrupt. If sector count is Idle E3h or 97h non-zero, automatic power down mode is enabled. If sector count is zero, the automatic power down mode is disabled. This command causes the ATA PC Card to set BSY, enter the Idle Immediate E1h or 95h Idle mode, clear BSY, and generate an interrupt. This command enables the host to set the number of sectors Initialize Drive Parameters 91h per track and the number of heads per cylinder. NOP 00h No Operation. This command enables the host to read the current contents of Read Buffer E4h the ATA PC Card’s sector buffer. Read DMA (Not used for Command is sector read command used for Multiword DMA C8h part numbers with P) transfer. Command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on transfer of a Read Multiple C4h block which contains the number of sectors defined by a Set Multiple command. Command performs similarly to the Read Sector(s) command Read Long Sector 22h or 23h except that it returns 516 bytes of data instead of 512 bytes. Command reads from 1 to 256 sectors as specified in the Sector 20h (w/ retry) Read Sector(s) Count register. Sector count of 0 requests 256 sectors. Transfer 21h (w/o retry) begins at the sector specified in the Sector Number register. This command verifies one or more sectors on the ATA PC Card by transferring data from the flash media to the data buffer in the 40h (w/ retry) Read Verify Sector(s) ATA PC Card and verifying that the ECC is correct. This 41h (w/o retry command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. The ATA PC Card performs only the interface timing and register operations. When this command is issued, the ATA PC Recalibrate 1Xh Card sets BSY and waits for an appropriate length of time, after which it clears BSY and issues an interrupt. When this command ends normally, the ATA PC Card is initialized. Request Sense Command requests extended error code after command ends 03h (Extended Error) with error. Extended error code is returned in the Error Register 61000-04497-117, April 2008 32 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet Command Set Code Description This command is effectively a NOP command to the ATA PC Seek 7Xh Card although it does perform a range check. This command is used by the host to establish or select certain Set Features EFh features. This command enables the ATA PC Card to perform multiple Set Multiple Mode C6h read and write operations and establishes the block count for these commands. This is the only command that allows the host to set the ATA PC Card into Sleep mode. When the ATA PC Card is set to sleep mode, the ATA PC Card clears the BSY line and issues an Set Sleep Mode E6h or 99h interrupt. The ATA PC Card enters sleep mode and the only method to make the ATA PC Card active again (back to normal operation) is by performing a hardware reset or a software reset. This command sets the ATA PC Card in Standby mode. If the Sector Count Register is a value other than 0H, an Auto Power Stand By E2h or 96h Down is enabled and when the ATA PC Card returns to the idle mode, the timer starts a countdown. The time is set in the Sector Count Register. This command causes the ATA PC Card to set BSY, enter the Stand By Immediate E0h or 94h Standby mode, clear BSY and return the interrupt immediately. This command allows the host a method of determining the Translate Sector 87h exact number of times a user sector has been erased and programmed. This command is not supported. Command is effectively NOP and only implemented for Wear Level F5h backward compatibility. The Sector Count Register will always be returned with a 00h indicating Wear Level is not needed. This command enables the host to overwrite the contents of the Write Buffer E8h ATA PC Card’s sector buffer with any data pattern desired. Write DMA (Not used for This command is the sector write command used for Multiword CAh part numbers with P) DMA transfer. This command is provided for compatibility purposes and is Write Long Sector 32h or 33h similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer Write Multiple C5h of a block which contains the number of sectors defined by Set Multiple command. This command is similar to the Write Multiple command, except that an implied erase before the write operation is not performed. Write Multiple w/o Erase CDh Note: Before using this command, it is required to erase the respective sectors using the Erase Sectors command This command writes from 1 to 256 sectors as specified in the 30h (w/ retry) Sector Count register. A sector count of zero requests 256 Write Sector(s) 31h (w/o retry) sectors. The transfer begins at the sector specified in the Sector Number register. This command is similar to the Write Sector(s) command, except that an implied erase before the write operation is not performed. Write Sector(s) w/o Erase 38h Note: Before using this command, it is required to erase the respective sectors using the Erase Sectors command. This command is similar to the Write Sector(s) command except Write Verify 3Ch each sector is verified immediately after being written. 61000-04497-117, April 2008 33 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet 7.0 Revision History Revision Date Description -101 11/17/06 Product release. -102 12/11/06. P option added to Ordering Information Legend. Where MWDMA is documented, it is noted that N/A to part numbers with P. -103 12/14/06 ID file Serial Number, Firmware Revision, and Model Number corrected in table. -104 1/16/07 Logo updated. Disclaimer updated. Contact Information added. -105 2/23/07 Logo left from last update replaced with new logo. Paragraph added to General Description on gold plated connector. In between capacities removed from Ordering Information and CHS parameters. Serial number revision (paper correction only). -106 2/28/07 CSEL signal description corrected. 16GB CHS parameters added. DC Characteristics corrected. -107 4/10/07 Shock updated from 1K to 1.5K. Vibration updated from 18 to 20. -108 5/2/07 Heading in Ordering Information table corrected to PC Card Form Factor. -109 5/9/07 Power up/RESET to RDY timing added. -110 5/21/07 Labeling section added. -111 6/11/07 Connector location added to Labeling section. Label added to dimension illustration. -112 8/06/07 Warranty bullet removed from features column on page 1. -113 9/19/07 General Description text updated. -114 11/2/07 Pasting error corrected in CIS (paper error only). -115 11/7/07 Layout updated for consistency and easier editing. Disclaimer notice reformatted with headings. -116 3/7/08 Contact information on last page updated. -117 4/2/08 STEC China address on last page updated. 61000-04497-117, April 2008 34 SLATAxxx(M/G)M1U(I) ATA PC Card Datasheet DISCLAIMER OF LIABILITY STEC™ Inc. reserves the right to make changes to specifications and product descriptions such as but not limited to numbers, parameters and other technical information contained herein without notice. Please contact the STEC™ Inc. sales office to obtain the latest specifications. STEC™ Inc. grants no warranty with respect to this datasheet, neither explicit or implied, and is not liable for direct or indirect damages. Some states do not grant the exclusion of incidental damages and as such this statement may not be valid in such states. The provisions of the datasheet do not convey to the purchaser of the device any license under any patent rights or other intellectual property rights of STEC Inc. or others. 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Information contained in this document, including but not limited to any instructions, descriptions and product specifications, is considered proprietary and confidential to STEC™, Inc. and shall not be modified, used, copied, reproduced or disclosed in whole or in part, in any form or by any means, electronic or mechanical, for any purpose, without the written consent of STEC™ Inc Worldwide Headquarters STEC Europe STEC Japan STEC Malaysia STEC China STEC, Inc. Donau-City-Strasse 1 Arents Daikanyama 114 STEC Techology Sdn Bhd RM1805, 18F Bund Centre 3001 Daimler Street 1220 Vienna, Austria 11-1 Hachiyama-cho Plot 107 Bayan Lepas Industrial Park 222 Yan An Rd East Santa Ana, California 92705 USA Tel: +43 1 263 38 08 Shibuya-ku, Tokyo Phase 4, 11900 Penang, Malaysia HuangPu District Tel: (949) 476-1180 Fax: +43 1 263 37 65 150-0035 Japan Tel: +60 (4)-6198888 Shanghai, 200002. Fax: (949) 476-1209 www.stec-inc.com/ Tel: +81(0) 3-5428-2231 www.stec-inc.com/ P R. China www.stec-inc.com/ Tel: +81(0) 3-5489-0230 Tel: +86 21 6132 3892 * 629 www.stec-inc.jp/ Fax: +86 21 6335 1336 www.stecchina.cn/ 61000-04497-117, April 2008 35