DATA SHEET SILICONDRIVE™ CF SSD-CXXX(I)-3500 OVERVIEW FEATURES Pb SiliconDrive™ CF is an optimal time-to- • RoHS 6 of 6 compliant market replacement for hard drives and • Integrated PowerArmor™ and flash cards or in host systems that require SiSMART™ technology low power and scalable storage solutions. • Capacity range: 32MB to 8GB SiliconDrive technology is engineered • Supports both 8-bit and 16-bit data exclusively for the high performance, high register transfers reliability and multiyear product lifecycle requirements of the Enterprise System • Supports dual-voltage 3.3V or 5V OEM market. Typical end-market interface applications include broadband data and 14 • Data reliability < 1 error in 10 bits read voice networks, military systems, flight • MTBF > 4,000,000 hours system avionics, medical equipment, industrial control systems, video • ATA-3 compliant surveillance, storage networking, VoIP, • Industry standard Type I CF form factor wireless infrastructure, and interactive • Supports PIO modes 0-4 and DMA kiosks. modes 0-2 Every SiliconDrive is integrated with SiliconSystems patented PowerArmor™ and patent-pending SiSMART™ technology to virtually eliminate storage systems failures. 8GB SSD-C08G(I)-3500 PowerArmor technology prevents data corruption and loss from power disturbances by integrating proprietary voltage detection circuitry and logic into every SiliconDrive. SiSMART acts as an early warning system to eliminate unscheduled downtime by constantly monitoring and reporting the exact amount of remaining storage system useful life. Numerous SiliconSystems patented and patent-pending application-specific technology can be integrated into SiliconDrive to safeguard application data and software IP. Application notes detailing these performance-enhancing options are available under NDA. Click here Click here SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 26940 ALISO VIEJO PARKWAY, ALISO VIEJO, CA 92656 • PHONE: 949.900.9400 • FAX: 949.900.9500 • http://www.siliconsystems.com DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 SSD-CXXX(I)-3500 DATA SHEET REVISION HISTORY REVISION HISTORY Document No. Release Date Changes SSDS02-3500C-R February 7, 2007 Updated: •V symbol from 2.0 to 2.5 in the "DC IH Characteristics" table. • "Common Memory Description and Operation" tables. SSDS01-3500C-R December 29, 2006 Updated: • -CS0, -CS1 signals in the "Signal Description" table. SSDS00-3500C-R July 6, 2006 Minor formatting changes. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE II FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R TABLE OF CONTENTS SSD-CXXX(I)-3500 DATA SHEET TABLE OF CONTENTS Overview.......................................................................................................................... i Physical Specifications................................................................................................. 1 Physical Dimensions .................................................................................................... 1 Product Specifications.................................................................................................. 2 System Performance.................................................................................................... 2 System Power Requirements....................................................................................... 2 System Reliability......................................................................................................... 2 Product Capacity Specifications................................................................................... 3 Environmental Specifications ....................................................................................... 3 Electrical Specification.................................................................................................. 4 Pin Assignments........................................................................................................... 4 Signal Descriptions....................................................................................................... 5 Absolute Maximum Ratings........................................................................................ 15 Vcc = 3.3 ± 10% ................................................................................................... 15 Vcc = 5.0 ± 10% ................................................................................................... 15 Capacitance ............................................................................................................... 15 DC Characteristics ..................................................................................................... 16 AC Characteristics...................................................................................................... 17 Attribute and Common Memory Read Timing...................................................... 17 Attribute and Common Memory Write Timing ...................................................... 18 I/O Access Read Timing....................................................................................... 20 I/O Access Write Timing....................................................................................... 22 True IDE Read/Write Access Timing.................................................................... 23 True IDE Multiword DMA Read/Write Access Timing .......................................... 25 Attribute Memory Description and Operation........................................................... 26 Attribute Memory Read Operations............................................................................ 26 Attribute Memory Write Operations............................................................................ 27 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE III SSD-CXXX(I)-3500 DATA SHEET TABLE OF CONTENTS Attribute Memory Map................................................................................................ 28 Card Information Structure......................................................................................... 29 Configuration Option Register (200h)......................................................................... 40 Configuration and Status Register (202h).................................................................. 41 Pin Placement Register (204h) .................................................................................. 42 Socket and Copy Register (206h) .............................................................................. 43 Common Memory Description and Operation .......................................................... 44 Common Memory Read Operations........................................................................... 44 Common Memory Write Operations........................................................................... 44 I/O Space Description and Operation ........................................................................ 45 I/O Space Read Operations ....................................................................................... 45 I/O Space Write Operations ....................................................................................... 45 ATA and True IDE Register Decoding ........................................................................ 46 Memory-Mapped Register Decoding.......................................................................... 46 Independent I/O Mode Register Decoding................................................................. 47 Primary and Secondary I/O Mapped Register Decoding ........................................... 48 Task File Register Specification................................................................................. 49 ATA Registers............................................................................................................... 50 Data Register ............................................................................................................. 50 Error Register............................................................................................................. 50 Feature Register......................................................................................................... 51 Sector Count Register................................................................................................ 52 Sector Number Register............................................................................................. 53 Cylinder Low Register ................................................................................................ 54 Cylinder High Register ............................................................................................... 55 Drive/Head Register................................................................................................... 56 Status Register........................................................................................................... 57 Command Register .................................................................................................... 58 Alternate Status Register ........................................................................................... 59 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE IV FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R TABLE OF CONTENTS SSD-CXXX(I)-3500 DATA SHEET Device Control Register ............................................................................................. 60 Device Address Register............................................................................................ 61 ATA Command Block and Set Description................................................................ 62 ATA Command Set .................................................................................................... 62 Check Power Mode — 98h, E5h.......................................................................... 64 Executive Drive Diagnostic — 90h....................................................................... 65 Format Track — 50h ............................................................................................ 66 Identify Drive — ECh............................................................................................ 67 Identify Drive — Drive Attribute Data ............................................................. 68 Idle — 97h, E3h.................................................................................................... 71 Idle Immediate — 95h, E1h.................................................................................. 72 Initialize Drive Parameters — 91h........................................................................ 73 Recalibrate — 1Xh ............................................................................................... 74 Read Buffer — E4h .............................................................................................. 75 Read DMA — C8h................................................................................................ 76 Read Multiple — C4h ........................................................................................... 77 Read Sector — 20h, 21h...................................................................................... 78 Read Long Sector(s) — 22h, 23h......................................................................... 79 Read Verify Sector(s) — 40h, 41h ....................................................................... 80 Seek — 7Xh ......................................................................................................... 81 Set Features — EFh............................................................................................. 82 Set Multiple Mode — C6h .................................................................................... 83 Set Sleep Mode — 99h, E6h................................................................................ 84 Standby — 96h, E2h ............................................................................................ 85 Standby Immediate — 94h, E0h .......................................................................... 86 Write Buffer — E8h .............................................................................................. 87 Write DMA — CAh ............................................................................................... 88 Write Multiple — C5h ........................................................................................... 89 Write Sector(s) — 30h, 31h.................................................................................. 90 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE V SSD-CXXX(I)-3500 DATA SHEET TABLE OF CONTENTS Write Long Sector(s) — 32h, 33h......................................................................... 91 Erase Sector(s) — C0h ........................................................................................ 92 Request Sense — 03h ......................................................................................... 93 Translate Sector — 87h ....................................................................................... 94 Wear-Level — F5h ............................................................................................... 95 Write Multiple w/o Erase — CDh.......................................................................... 96 Write Sector(s) w/o Erase — 38h......................................................................... 97 Write Verify — 3Ch............................................................................................... 98 Sales and Support ....................................................................................................... 99 Part Numbering............................................................................................................ 99 Nomenclature............................................................................................................. 99 Part Numbers ............................................................................................................. 99 RoHS 6 of 6 Product Labeling — Pb-Free Identification Label ................................ 100 Sample Label ........................................................................................................... 100 Related Documentation............................................................................................. 101 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE VI FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R LIST OF FIGURES SSD-CXXX(I)-3500 DATA SHEET LIST OF FIGURES Figure 1: Physical Dimensions......................................................................................... 1 Figure 2: Attribute and Common Memory Read Timing Diagram.................................. 17 Figure 3: Attribute and Common Memory Write Timing Diagram.................................. 18 Figure 4: I/O Access Read Timing Diagram .................................................................. 20 Figure 5: I/O Access Write Timing Diagram................................................................... 22 Figure 6: True IDE Read/Write Access Timing Diagram ............................................... 23 Figure 7: True IDE Multiword DMA Read/Write Access Timing..................................... 25 Figure 8: Sample Label................................................................................................ 100 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE VII SSD-CXXX(I)-3500 DATA SHEET LIST OF FIGURES SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE VIII FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R LIST OF TABLES SSD-CXXX(I)-3500 DATA SHEET LIST OF TABLES Table 1: System Performance ......................................................................................... 2 Table 2: System Power Requirements ............................................................................ 2 Table 3: System Reliability............................................................................................... 2 Table 4: Product Capacity Specifications ........................................................................ 3 Table 5: Environmental Specifications............................................................................. 3 Table 6: Pin Assignments ................................................................................................ 4 Table 7: Signal Descriptions ............................................................................................ 5 Table 8: Absolute Maximum Rating — Vcc = 3.3 ± 10% ............................................... 15 Table 9: Absolute Maximum Rating — Vcc = 5.0 ± 10% ............................................... 15 Table 10: Capacitance................................................................................................... 15 Table 11: DC Characteristics......................................................................................... 16 Table 12: Attribute and Common Memory Read Timing................................................ 17 Table 13: Attribute and Common Memory Write Timing................................................ 18 Table 14: I/O Access Read Timing ................................................................................ 20 Table 15: I/O Access Write Timing ................................................................................ 22 Table 16: True IDE Read/Write Access Timing ............................................................. 24 Table 17: True IDE Multiword DMA Read/Write Access Timing.................................... 25 Table 18: Attribute Memory Read Operations ............................................................... 26 Table 19: Attribute Memory Write Operations................................................................ 27 Table 20: Attribute Memory Map.................................................................................... 28 Table 21: Card Information Structure............................................................................. 29 Table 22: Configuration Option Register (200h) ............................................................ 40 Table 23: Configuration and Status Register (202h)...................................................... 41 Table 24: Pin Placement Register (204h)...................................................................... 42 Table 25: Socket and Copy Register (206h).................................................................. 43 Table 26: Common Memory Read Operations .............................................................. 44 Table 27: Common Memory Write Operations .............................................................. 44 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE IX SSD-CXXX(I)-3500 DATA SHEET LIST OF TABLES Table 28: I/O Space Read Operations........................................................................... 45 Table 29: I/O Space Write Operations........................................................................... 45 Table 30: Memory-Mapped Register Decoding ............................................................. 46 Table 31: Independent I/O Mode Register Decoding..................................................... 47 Table 32: Primary and Secondary I/O Mapped Register Decoding............................... 48 Table 33: Task File Register Specification..................................................................... 49 Table 34: Error Register................................................................................................. 50 Table 35: Feature Register ............................................................................................ 51 Table 36: Sector Count Register.................................................................................... 52 Table 37: Sector Number Register ................................................................................ 53 Table 38: Cylinder Low Register.................................................................................... 54 Table 39: Cylinder High Register................................................................................... 55 Table 40: Drive/Head Register....................................................................................... 56 Table 41: Status Register .............................................................................................. 57 Table 42: Command Register........................................................................................ 58 Table 43: Alternate Status Register............................................................................... 59 Table 44: Device Control Register................................................................................. 60 Table 45: Device Address Register ............................................................................... 61 Table 46: ATA Command Block and Set Description .................................................... 62 Table 47: ATA Command Set........................................................................................ 62 Table 48: Check Power Mode — 98h, E5h.................................................................... 64 Table 49: Executive Drive Diagnostic — 90h................................................................. 65 Table 50: Format Track — 50h...................................................................................... 66 Table 51: Identify Drive — ECh ..................................................................................... 67 Table 52: Identify Drive — Drive Attribute Data............................................................. 68 Table 53: Idle — 97h, E3h ............................................................................................. 71 Table 54: Idle Immediate — 95h, E1h ........................................................................... 72 Table 55: Initialize Drive Parameters — 91h ................................................................. 73 Table 56: Recalibrate — 1Xh......................................................................................... 74 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE X FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R LIST OF TABLES SSD-CXXX(I)-3500 DATA SHEET Table 57: Read Buffer — E4h........................................................................................ 75 Table 58: Read DMA — C8h ......................................................................................... 76 Table 59: Read Multiple — C4h..................................................................................... 77 Table 60: Read Sector — 20h, 21h ............................................................................... 78 Table 61: Read Long Sector(s) — 22h, 23h .................................................................. 79 Table 62: Read Verify Sector(s) — 40h, 41h................................................................. 80 Table 63: Seek — 7Xh................................................................................................... 81 Table 64: Set Features — EFh ...................................................................................... 82 Table 65: Set Features’ Attributes ................................................................................. 82 Table 66: Set Multiple Mode — C6h.............................................................................. 83 Table 67: Set Sleep Mode — 99h, E6h ......................................................................... 84 Table 68: Standby — 96h, E2h...................................................................................... 85 Table 69: Standby Immediate — 94h, E0h.................................................................... 86 Table 70: Write Buffer — E8h........................................................................................ 87 Table 71: Write DMA — CAh......................................................................................... 88 Table 72: Write Multiple — C5h..................................................................................... 89 Table 73: Write Sector(s) — 30h, 31h ........................................................................... 90 Table 74: Write Long Sector(s) — 32h, 33h .................................................................. 91 Table 75: Erase Sector(s) — C0h.................................................................................. 92 Table 76: Request Sense — 03h................................................................................... 93 Table 77: Extended Error Codes ................................................................................... 93 Table 78: Translate Sector — 87h................................................................................. 94 Table 79: Wear-Level — F5h......................................................................................... 95 Table 80: Write Multiple w/o Erase — CDh ................................................................... 96 Table 81: Write Sector(s) w/o Erase — 38h .................................................................. 97 Table 82: Write Verify — 3Ch ........................................................................................ 98 Table 83: Part Numbering Nomenclature ...................................................................... 99 Table 84: Part Numbers................................................................................................. 99 Table 85: Related Documentation ............................................................................... 101 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE XI SSD-CXXX(I)-3500 DATA SHEET LIST OF TABLES SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE XII FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R PHYSICAL SPECIFICATIONS SSD-CXXX(I)-3500 DATA SHEET PHYSICAL SPECIFICATIONS The SiliconDrive CF products are offered in an industry standard Type I form factor. See "Part Numbering" on page 99 for details regarding CF capacities. PHYSICAL DIMENSIONS This section provides diagrams that describe the physical dimensions for the CF. Figure 1: Physical Dimensions SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 1 SSD-CXXX(I)-3500 DATA SHEET PRODUCT SPECIFICATIONS PRODUCT SPECIFICATIONS Note: All SiliconDrive CF values quoted are typical at 25°C and nominal supply voltage. SYSTEM PERFORMANCE Table 1: System Performance Reset to Ready Startup Time (Typical/Max) 200ms/400ms Read Transfer Rate (Typical) 8MBps Write Transfer Rate (Typical) 6MBps Burst Transfer Rate 16.7MBps Controller Overhead (Command to DRQ) 2ms (max) SYSTEM POWER REQUIREMENTS Table 2: System Power Requirements DC Input Voltage 3.3 ± 10% 5.0 ± 10% Sleep (Standby Current) <0.5mA <1.0mA Read (Typical/Peak) 20mA/75mA 30mA/100mA Write (Typical/Peak) 30mA/75mA 40mA/100mA SYSTEM RELIABILITY Table 3: System Reliability MTBF (@ 25ºC) > 4,000,000 hours 14 Data Reliability < 1 non-recoverable error in 10 bits read Endurance >2,000,000 write/erase cycles Data Retention 10 years SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 2FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R PRODUCT SPECIFICATIONS SSD-CXXX(I)-3500 DATA SHEET PRODUCT CAPACITY SPECIFICATIONS Table 4: Product Capacity Specifications Formatted Number of Product Number of Number of Number Capacity Sectors/ Capacity Sectors Cylinders of Heads (Bytes) Track 32MB 32,702,464 63,872 499 4 32 64MB 65,601,536 128,128 1001 4 32 128MB 130,154,496 254,208 993 8 32 256MB 260,571,136 508,928 994 16 32 512MB 521,773,056 1,019,088 1011 16 63 1GB 1,047,674,880 2,046,240 2030 16 63 2GB 2,098,446,336 4,098,528 4066 16 63 4GB 4,224,761,856 8,251,488 8186 16 63 8GB 8,455,200,76816,514,064 16,383* 16 63 * = All IDE drives 8GB and larger use 16383 cylinders, 16 heads, and 63 sectors/track due to interface restrictions. ENVIRONMENTAL SPECIFICATIONS Table 5: Environmental Specifications Temperature 0ºC to 70ºC (Commercial) -40ºC to 85ºC (Industrial) Humidity 8% to 95% non-condensing Vibration 16.3gRMS, MIL-STD-810F, Method 514.5, Procedure I, Category 24 Shock 1000G, Half-sine, 0.5ms Duration 50g Pk, MIL-STD-810F, Method 516.5, Procedure I Altitude 80,000ft, MIL-STD-810F, Method 500.4, Procedure II SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 3 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION ELECTRICAL SPECIFICATION PIN ASSIGNMENTS The following table describes the SiliconDrive CF 50-pin IDE connector signals. Table 6: Pin Assignments PC Card PC Card PC Card IDE-ATA PC Card IDE-ATA Memory Memory Pin I/O Mode Mode Pin I/O Mode Mode Mode Mode 26 CD1# CD1# CD1# 1 GND GND GND 1 1 1 27 2D3D3D3 D11 D11 D11 3D4D4D4 1 1 1 28 D12 D12 D12 4D5D5D5 1 1 1 29 D13 D13 D13 5D6D6D6 1 1 1 30 D14 D14 D14 6D7D7D7 1 1 1 31 D15 D15 D15 7 CE1# CE1# CE1# 32 CE2# CE2# CE2# 8A10 A10 A10 33 VS1# VS1# VS1# 9 OE# OE# OE# 34 IORD# IORD# IORD# 2 10A9 A9 A9 35 IOWR# IOWR# IOWR# 2 11A8 A8 A8 36 WE# WE# WE# 2 12A7 A7 A7 37 RDY/BSY IREQ RDY/BSY 13 VCC VCC VCC 38 VCC VCC VCC 2 14 A6 A6 A6 39 CSEL# CSEL# CSEL# 2 15 A5 A5 40 VS2# VS2# VS2# A5 41 RESET# RESET# RESET# 2 16 A4 A4 A4 42 WAIT# WAIT# WAIT# 2 17 A3 A3 A3 43 INPACK# INPACK# DMARQ 18 A2 A2 A2 44 REG# REG# DMACK# 19 A1 A1 A1 45 BVD2 SPKR# DASP# 20 A0 A0 A0 46BVD1 STSCHG# PDIAG# 21 D0 D0 D0 1 1 1 47 D8 D8 D8 22 D1 D1 D1 1 1 1 48 D9 D9 D9 23 D2 D2 D2 1 1 1 49 24 WP -IOIS16 -IOIS16 D10 D10 D10 25 CD2# CD2# CD2# 50GND GND GND Notes: 1 = These signals are required only for 16-bit access, and not required when installed in 8-bit systems. 2 = Should be grounded by the host. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 4FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET SIGNAL DESCRIPTIONS Table 7: Signal Descriptions Signal Name Pin Type Description A10-A0 8, 10, 11, I These address lines along with the - 12, 14, 15, REG signal are used to select the 16, 17, 18, following: 19, 20 • The I/O port address registers within the SiliconDrive CF • The memory-mapped port address registers within the SiliconDrive CF • A byte in the card's information structure and its configuration control and status registers A10-A0 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O mode) A2-A0 18, 19, 20 I In true IDE mode, only A[2:0] are used to select the one of eight registers in (True IDE mode) the Task File. The remaining address lines should be grounded by the host. BVD1 46 I/O This signal is asserted high, because BVD1 is not supported. (PC Card memory mode) -STSCHG This signal is asserted low to alert the host to changes in the RDY/-BSY and (PC Card I/O Write Protect states while the I/O mode) interface is configured. This signal’s use is controlled by the Card Configuration and Status register. -PDIAG In the true IDE mode, this input/ output is the Pass Diagnostic signal in (True IDE mode) the Master/Slave handshake protocol. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 5 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description BVD2 45 I/O This signal is asserted high, as BVD2 is not supported. (PC Card memory mode) -SPKR This line is the Binary Audio output from the card. If the Card does not (PC Card I/O support the Binary Audio function, this mode) line should be held negated. -DASP In the true IDE mode, this input/output is the Disk Active/Slave Present (True IDE mode) signal in the Master/Slave handshake protocol. -CD1, -CD2 26, 25 O These Card Detect pins are connected to ground on the (PC Card memory SiliconDrive CF, and are used by the mode) host to determine that the SiliconDrive CF is fully inserted into its socket. -CD1, -CD2 This signal is the same for all modes. (PC Card I/O Mode) -CD1, -CD2 This signal is the same for all modes. (True IDE mode) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 6FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -CE1, -CE2 7, 32 I These input signals are used both to select the card and to indicate to the (PC Card memory card whether a byte or a word mode) operation is being performed. Card Enable • -CE2 always accesses the odd byte of the word. • -CE1 accesses the even byte or the odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, and -CE2 allows 8-bit hosts to access all data on D0-D7. See "Attribute Memory Read Operations" on page 26, "Attribute Memory Write Operations" on page 27, "Common Memory Read Operations" on page 44, and "Common Memory Write Operations" on page 44. -CE1, -CE2 This signal is the same as the PC Card Memory Mode signal. See "I/O (PC Card I/O Space Read Operations" on page 45 mode) and "I/O Space Write Operations" on Card Enable page 45. -CS0, -CS1 In the true IDE mode, -CS0 is the chip select for the task file registers while - (True IDE mode) CS1 is used to select the Alternate Status register and the Device Control register. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 7 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -CSEL 39 I This signal is not used for this mode. (PC Card memory mode) -CSEL This signal is not used for this mode. (PC Card I/O mode) -CSEL This internally pulled-up signal is used to configure this device as a master or (True IDE mode) slave when configured in the true IDE mode. When this pin is: • Grounded, this device is configured as a master. • Open, this device is configured as a slave. -INPACK 43 O This signal is not used in this mode. (PC Card memory mode) -INPACK This signal is asserted by the SiliconDrive CF when the card is (PC Card I/O selected and responding to an I/O mode) read cycle at the address that is on Input Acknowledge the address bus. This signal is used by the host to control the enabling of any input data buffers between the SiliconDrive CF and the CPU. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 8FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description DMARQ 43 O In true IDE mode, this signal is used for DMA transfers between the host (True IDE mode) and device. DMARQ is asserted by the device when the device is ready to transfer data to/from the host. The direction of data transfer is controlled by -IORD and -IOWR. This signal is used in a handshake manner with -DMACK (i.e., the device waits until the host asserts -DMACK before negating DMARQ, and reasserts DMARQ if there is more data to transfer). The DMARQ/-DMACK handshake is used to provide flow control during the transfer. D15-D00 31, 30, 29, I/O These lines carry the data, 28, 27, 49, commands, and status information (PC Card memory 48, 47, 6, between the host and the controller. mode) 5, 4, 3, 2, • D00 is the LSB of the word’s even 23, 22, 21 byte. • D08 is the LSB of the word’s odd byte. D15-D00 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O mode) D15-D00 In true IDE mode, all Task File operations occur in byte mode on the (True IDE mode) low-order bus D00-D07, while all data transfers are 16 bits using D00-D15. GND 1, 50 - Ground. (PC Card memory mode) GND This signal is the same for all modes. (PC Card I/O mode) GND This signal is the same for all modes. (True IDE mode) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 9 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -IORD 34 I This signal is not used in this mode. (PC Card memory mode) -IORD This is an I/O read strobe generated by the host. This signal gates I/O data (PC Card I/O onto the bus from the SiliconDrive CF mode) when the card is configured to use the I/O interface. -IORD In true IDE mode, this signal has the same function as the PC Card I/O (True IDE mode) mode. -IOWR 35 I This signal is not used in this mode. (PC Card memory mode) -IOWR The I/O write strobe pulse is used to clock I/O data on the Card data bus (PC Card I/O into the SiliconDrive CF controller mode) registers when the SiliconDrive CF is configured to use the I/O interface. The clocking occurs on the negative- to-positive edge of the signal (the trailing edge). -IOWR In true IDE mode, this signal has the same function as the PC Card I/O (True IDE mode) mode. -OE 9 I This is an output enable strobe generated by the host interface, which (PC Card memory is used to read: mode) • Data from the SiliconDrive CF in memory mode. • The CIS and configuration registers. -OE In PC Card I/O mode, this signal is used to read the CIS and (PC Card I/O configuration registers. mode) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 10 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -ATA SEL To enable true IDE mode, this input should be grounded by the host. (True IDE mode) -RDY/-BSY 37 O In memory mode, this signal is: (PC Card memory • Set high when the SiliconDrive CF mode) is ready to accept a new data transfer operation. • Held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power-up and reset, the RDY/-BSY signal is held low (busy) until the SiliconDrive CF has completed its power-up or reset function. No access of any type should be made to the SiliconDrive CF during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the SiliconDrive CF has been powered up with +RESET continuously disconnected or asserted. -IREQ I/O Operation. After the SiliconDrive CF has been configured for I/O (PC Card I/O operation, this signal is used as mode) -Interrupt Request. This line is strobed Input Acknowledge low to generate a pulse mode interrupt or held low for a level mode interrupt. -IREQ In true IDE mode, this signal is the active high Interrupt Request to the (True IDE mode) host. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 11 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -REG 44 I This signal is used during memory cycles to distinguish between (PC Card memory common memory and register mode) (attribute) memory accesses. This Attribute Memory signal is set: Select • High for common memory. • Low for attribute memory. -REG The signal must also be active (low) during I/O cycles when the I/O (PC Card I/O address is on the bus. mode) -DMACK In true IDE mode, this signal is used by the host in response to DMARQ to (True IDE mode) initiate DMA transfers. The DMARQ/ -DMACK handshake is used to provide flow control during the transfer. When -DMACK is asserted, -CS0 and -CS1 are not asserted and transfers are 16-bits wide. -RESET 41 I When the pin is high, this signal resets the SiliconDrive CF. The (PC Card memory SiliconDrive CF is reset only at power- mode) up if this pin is left high or open from power-up. The SiliconDrive CF is also reset when the Soft Reset bit in the Card Configuration Option register is set. -RESET This signal is the same as the PC Card Memory Mode signal. (PC Card I/O mode) -RESET In the true IDE mode, this input pin is the active low hardware reset from the (True IDE mode) host. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 12 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description VCC 13, 38 - +5V, +3.3V power. (PC Card memory mode) VCC This signal is the same for all modes. (PC Card I/O mode) VCC This signal is the same for all modes. (True IDE mode) -VS1, -VS2 33, 40 O Voltage Sense Signals. • -VS1 is grounded so that the SiliconDrive CF CIS can be read at 3.3V. • -VS2 is reserved by PC Card for a secondary voltage. -VS1, -VS2 This signal is the same for all modes. (PC Card I/O mode) -VS1, -VS2 This signal is the same for all modes. (True IDE mode) -WAIT 42 O The -WAIT signal is driven low by the SiliconDrive CF to signal the host to (PC Card memory delay completion of a memory or I/O mode) cycle that is in progress. -WAIT This signal is the same as the PC Card Memory Mode signal. (PC Card I/O mode) -IORDY In true IDE mode, this output signal may be used as IORDY. (True IDE mode) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 13 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 7: Signal Descriptions (Continued) Signal Name Pin Type Description -WE 36 I This is a signal driven by the host and used for strobing memory write data (PC Card memory to the registers of the SiliconDrive CF mode) when the card is configured in the memory interface mode. This signal is also used for writing the configuration registers. -WE In PC Card I/O mode, this signal is used for writing the configuration (PC Card I/O registers. mode) -WE In true IDE mode, this input signal is not used and should be connected to (True IDE mode) VCC by the host. WP 24 O Write Protect Memory Mode. The SiliconDrive CF does not have a write (PC Card memory protect switch. This signal is held low mode) after the completion of the reset initialization sequence. -IOIS16 I/O Operation. When the SiliconDrive CF is configured for I/O operation, pin (PC Card I/O 24 is used for the -I/O Selected, which mode) is a 16-bit port (-IOIS16) function. A low signal indicates that a 16-bit or odd byte only operation can be performed at the addressed port. -IOIS16 In true IDE mode, this output signal is asserted low when this device is (True IDE mode) expecting a word data transfer cycle. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 14 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET ABSOLUTE MAXIMUM RATINGS Vcc = 3.3 ± 10% Table 8: Absolute Maximum Rating — Vcc = 3.3 ± 10% Symbol Parameter Minimum Maximum Units Ts Storage Temperature -55 125 °C T Operating Temperature -40 85 °C A Vcc Vcc with Respect to GND -0.3 6.7 V Vin Input Voltage -0.5 3.8 V Vout Output Voltage -0.3 3.6 V Vcc = 5.0 ± 10% Table 9: Absolute Maximum Rating — Vcc = 5.0 ± 10% Symbol Parameter Minimum Maximum Units Ts Storage Temperature -55 125 °C T Operating Temperature -40 85 °C A Vcc Vcc with Respect to GND -0.3 6.7 V Vin Input Voltage -0.5 6.0 V Vout Output Voltage -0.3 5.8 V CAPACITANCE Table 10: Capacitance Symbol Parameter Maximum Units Cin Input Capacitance 35 pF Cout Output Capacitance 35 pF CI/O Bidirectional Capacitance 35 pF SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 15 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION DC CHARACTERISTICS Table 11: DC Characteristics 3.3 V ±10% 5V ±10% Symbol Parameter Units Minimum Maximum Minimum Maximum Vcc Power Supply 3.03.6 4.55.5 V Voltage I Input Leakage -5 -5 µA LI *(1) Current I Output -5 -5 µA LO Leakage *(1) Current V Vcc Read -50 - 80 mA CCR Current V Vcc Write -50 - 80 mA CCW Current V Vcc Standby -.3 - .5 mA CCS Current V Input Low -0.3 .3 x Vcc -0.3 .3 x Vcc V IL Voltage V Input High 2.5 Vcc + .3 2.5 Vcc + .3 V IH Voltage V Output Low -.4 - .4 V OL Voltage V Output High 2.4 - 2.4 - V OH Voltage Note: *(1) Except the pulled-up/pulled-down pin. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 16 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET AC CHARACTERISTICS Attribute and Common Memory Read Timing tRC tGHAX tA(A) ____ A[10::0],REG tA(CE) tAXQX tELWL __ CE tAVWL __ tA(OE) tGHEH OE tDIS(OE) tEN(OE) D[15::0] Figure 2: Attribute and Common Memory Read Timing Diagram Table 12: Attribute and Common Memory Read Timing Symbol Parameter Minimum Maximum Units t Read Cycle Time 100 - ns RC t (A) Address Access Time - 100 ns A t (CE) Card Enable Access Time - 100 ns A t (OE) Output Enable Access Time - 50 ns A t (OE) Output Disable Time from OE - 50 ns DIS t (OE) Output Enable Time from OE 5 - ns EN t Data Valid from Address Change 0 - ns AXQX t Address Setup Time 10 - ns AVWL t Address Hold Time 15 - ns AXQX t Card Enable Setup Time before OE 0 - ns ELWL t Card Enable Hold Time following OE 15 - ns GHEH SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 17 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Attribute and Common Memory Write Timing tWR ____ A[10::0],REG tELWH tELWL __ CE tGHEH tAVWH __ OE tAVWL tWLWH tWHAX ___ WE tWHOL tWLOL tDVWH tWHDX D[15:0](Dout) tWLQZ tOHDX tOLWH tWHOX D[15:0](Dout) Figure 3: Attribute and Common Memory Write Timing Diagram Table 13: Attribute and Common Memory Write Timing Symbol Parameter Minimum Maximum Units t Write Cycle Time 100 - ns WR t Write Pulse Width 60 - ns WLWH t Address Setup Time 10 - ns AVWL t Address Setup Time for WE 70 - ns AVWH t Card Enable Setup Time for WE 70 - ns ELWH t Data Hold Time 10 - ns WHDX t Write Recover Time 15 - ns WHAX t Output Disable Time from WE - 75 ns WLQZ t Output Disable Time from OE - 100 ns OLWH t Output Enable Time from WE 5 - ns WHOX SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 18 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 13: Attribute and Common Memory Write Timing (Continued) Symbol Parameter Minimum Maximum Units t Output Enable Time from OE 5 - ns OHDX t Output Enable Setup for WE 10 - ns WLOL t Output Enable Hold from WE 10 - ns WHOL t Card Enable Setup Time before WE 0 - ns ELWL t Card Enable Hold Time from WE 15 - ns GHEH t Data Setup Time 40 - ns DVWH SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 19 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION I/O Access Read Timing A[10::0] tGHAX tRLIGL ____ tRHIGH REG tCLIGL tCHIGH __ CE tIGLIGH ___ IORD tIGHINH tAVIGL ______ INPACK tIGLINL tAXISH ______ IOIS16 tAVISL tIGHQX tDVRL D[15::0] Figure 4: I/O Access Read Timing Diagram Table 14: I/O Access Read Timing Symbol Parameter Minimum Maximum Units t Data Delay after IORD - 50 ns DVRL t Data Hold following IORD 5 - ns IGHQX t IORD Pulse Width 65 - ns IGLIGH t Address Setup before IORD 25 - ns AVIGL t Address Hold following IORD 10 - ns GHAX t CE Setup before IORD 5 - ns CLIGL SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 20 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 14: I/O Access Read Timing (Continued) Symbol Parameter Minimum Maximum Units t CE Hold following IORD 10 - ns CHIGH t REG Setup before IORD 5 - ns RLIGL t REG Hold following IORD 0 - ns RHIGH t INPACK Delay falling from IORD - (1) ns IGLINL t INPACK Delay Rising from IORD - (1) ns IGHINH t IOIS16 Delay Falling from Address - (1) ns AVISL t IOIS16 Delay Rising from Address - (1) ns AXISH Note: (1) IOIS16 and INPACK are not supported. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 21 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION I/O Access Write Timing A[10::0] tAXIGH tRLIGL ____ tRHIGH REG tCHIGH tCLIGL __ CE tIGLIGH _____ IOWR tAVIGL tAXISH ______ tAVISL IOIS16 tIGHQX tIGHDX D[15::0] Figure 5: I/O Access Write Timing Diagram Table 15: I/O Access Write Timing Symbol Parameter Minimum Maximum Units t Data Hold following IOWR 5 - ns IGHDX t Data Setup before IOWR 20 - ns IGHQX t IOWR Pulse Width 65 - ns IGLIGH t Address Setup before IOWR 25 - ns AVIGL t Address Hold following IOWR 10 - ns AXIGH t CE Setup before IOWR 5 - ns CLIGL t CE Hold following IOWR 10 - ns CHIGH SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 22 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET Table 15: I/O Access Write Timing (Continued) Symbol Parameter Minimum Maximum Units t REG Setup before IOWR 5 - ns RLIGL t REG Hold following IOWR 0 - ns RHIGH t IOIS16 Delay Falling from Address - (1) ns AVISL t IOIS16 Delay Rising from Address - (1) ns AXISH Note: (1) IOIS16 and INPACK are not supported. True IDE Read/Write Access Timing tICL ADDRESS Valid CS0, CS1, DA[2::0] tAX16H tAVRW L tAXRW H tRW PW ____ _____ DIOR,DIOW tDVW L WRITE DD[15::00] tDXW H READ DD[15::00] tDVRL tDXRH tIOST tIOPW IORDY ______ IOIS16 tAV16L Figure 6: True IDE Read/Write Access Timing Diagram SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 23 SSD-CXXX(I)-3500 DATA SHEET ELECTRICAL SPECIFICATION Table 16: True IDE Read/Write Access Timing Symbol Parameter Minimum Maximum Units t Cycle Time 100 - ns ICL t Address Valid to DIOR,DIOW Setup 15 - ns AVRWL Time t DIOR, DIOW Pulse Width 65 - ns RWPW t DIOW Data Setup Time 20 - ns DVWL t DIOW Data Hold Time 5 - ns DXWH t DIOR Data Setup Time 15 - ns DVRL t DIOR Data Hold Time 5 - ns DXRH t Address Valid to IOCS16 Assertion - (1) ns AV16L t Address Valid to IOCS16 Negation - (1) ns AX16H t DIOW,DIOR to Address Valid Hold Time 10 - ns AXRWH t IORDY Setup Time - (1) ns IOST t IORDY Pulse Width - (1) ns IOPW Note: (1) IOIS16 and INPACK are not supported. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 24 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ELECTRICAL SPECIFICATION SSD-CXXX(I)-3500 DATA SHEET True IDE Multiword DMA Read/Write Access Timing This function does not apply to SiliconDrives that have DMA disabled. Figure 7: True IDE Multiword DMA Read/Write Access Timing Table 17: True IDE Multiword DMA Read/Write Access Timing Symbol Parameter Minimum Maximum Units t Cycle Time (mode 2) 100 - ns RWC t DIOR/DIOW Pulse Width 65 - ns RWPW t DIOR Data Access - 50 ns RDA t DIOR/DIOW Data Setup Time 15 - ns RWSU t DIOW Data Hold Time 5 - ns WH t DIOR Data Hold Time 5 - ns RH t DMACK to DIOR/DIOW Setup Time 0 - ns DMRW t DIOR/DIOW to DMACK Hold Time 5 - ns RWDH t DIOR/DIOW negated Pulse Width 25 - ns RWN t DIOR/DIOW to DMARQ Delay - 25 ns RWD t CS(1:0) valid to DIOR/DIOW 10 - ns CSRW t CS(1:0) Hold Time 10 - ns CSH SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 25 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION ATTRIBUTE MEMORY DESCRIPTION AND OPERATION The attribute memory plane can be read or written to by asserting the REG# signal, qualified by the appropriate combination of CE1#, OE#, and WE#. An attribute memory map describing the type and location of the information maintained in the attribute memory plane is provided in "Attribute Memory Map" on page 28. With respect to SiliconDrive CF, attribute memory consists of two sections: • Card Information Structure (CIS), which contains a description of the Card’s capabilities and specifications. • Function Configuration Registers (FCRs), which consists of four registers, that can be read or written to by a host to configure the Card for specific purposes. ATTRIBUTE MEMORY READ OPERATIONS Attribute memory read operations are enabled by asserting REG#, OE#, and CE1# low. Odd byte read operations from the attribute memory plane are not valid. Table 18: Attribute Memory Read Operations Function REG# CE1# CE2# A0 OE# WE# D[15:8] D[7:0] Mode Standby L H H X X X High-Z High-Z Byte Access L L H L L H High-Z Even L H L H L H High-Z Not Valid Word Access L L L X L H Not Valid Even Odd Byte L L HX HHNot Valid High-Z Only Access SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 26 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY WRITE OPERATIONS Attribute memory write operations are enabled by asserting REG#, WE#, and CE1# low. Odd byte write operations from the attribute memory plane are not valid. Table 19: Attribute Memory Write Operations Function REG# CE1# CE2# A0 OE# WE# D[15:8] D[7:0] Mode Standby L H H X X X High-Z High-Z Byte Access L L H L H L High-Z Even L H L H H L High-Z Not Valid Word Access L L L X H L Not Valid Even Odd Byte L L HX HHNot Valid High-Z Only Access SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 27 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION ATTRIBUTE MEMORY MAP As stated earlier, the Attribute Memory plane is comprised of two components, the CIS and the FCRs. The following tables detail the type, location, and read/ write requirements for each of the four FCRs maintained in the attribute memory plane. Table 20: Attribute Memory Map Register Operation Addr CE1# REG# WE# OE# Card Information Structure Read X 0 0 1 0 Write X 0001 Configuration Option Read 200h 0 0 1 0 Write 200h 0 0 0 1 Card Configuration and Read 202h 0 0 1 0 Status Write 202h 0 0 0 1 Pin Replacement Read 204h 0 0 1 0 Write 204h 0 0 0 1 Socket and Copy Read 206h 0 0 1 0 Write 206h 0 0 0 1 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 28 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET CARD INFORMATION STRUCTURE The CIS is data that describes the SiliconDrive CF, and is described by the CFA standard. This information can be used by the host system to determine a number of things about the Card that has been inserted. For information regarding the exact nature of this data and how to design the host software to interpret it, refer to the PC Card Standard Metaformat Specification. Table 21: Card Information Structure Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 00h 01h CISTPL_DEVICE Device information tuple Tuple code 02h 03h - Link length is 3 bytes Link to next tuple 04h D9h Device Type W Device • I/O device • Device ID Code Speed •No WP •WPS Dh = I/O 1 • Speed = 100ns • Device speed 1 06h 01h 1X 2K 2KB of address space Device size 08h FFh List End Marker End of device END marker 0Ah 1Ch CISTPL_DEVICE_OC Other conditions device in tuple code Tuple code 0Ch 04h TPL_LINK Link length is 4 bytes Link to next tuple 0Eh 02h EXT Reserved VCC 3V, wait is Not Used Other conditions MWAIT information field 10h D9h Device Type W Device • Device type = DH: I/O - P Speed • Device WPS = 1: No WP S • Device speed = 1: 250ns 12h 01h 1x 2K units 2KB of address space Device size 14h FFh List End Marker End of device End marker 16h 18h CISTPL_JEDEC_C JEDEC ID common memory Tuple code 18h 02h TPL_LINK Link length is 2 bytes Link to next tuple 1Ah DFh PCMCIA Manufacturer’s JEDEC Manufacturer’s ID code - - JEDEC ID 1Ch 01h PCMCIA JEDEC Device Code Second byte of JEDEC ID - 1Eh 20h CISTPL_MANFID Manufacturer’s ID code Tuple code 20h 04h TPL_LINK - - 22h 00h Low Byte of PCMCIA Manufacturer’s JEDEC manufacturer’s ID Low byte of Code manufacturer’s code 24h 00h High Byte of PCMCIA Code of 0, because the other byte is the High byte of the Manufacturer’s Code JEDEC 1 byte manufacturer’s ID manufacturer’s code 26h 00h Low Byte of Product Code Manufacturer’s code for SiliconDrive CF Low byte of the product code 28h 00h High Byte of Product Code Manufacturer’s code for SiliconDrive CF High byte of the product code 2Ah 21h CISTPL_FUNCID Function ID tuple Tuple code 2Ch 02h TPL_LINK Link length is 2 bytes Link to next tuple SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 29 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 2Eh 04h TPLFID_FUNCTION = 04H Disk function, which may be silicon or PC Card function removable code 30h 01h Reserved R P • R = 0: No BIOS ROM System initialization • P = 1: Configure card at power-on byte 32h 22h CISTPL_FUNCE Function extension tuple Tuple code 34h 02h TPL_LINK Link length is 2 bytes Link to next tuple 36h 01h Disk Function Extension Tuple Type Disk interface type Extension tuple type for disk 38h 01h Disk Interface Type PC Card interface type Interface type 3Ah 22h CISTPL_FUNCE Function extension tuple Tuple code 3Ch 03h TPL_LINK Link length is 3 bytes Link to next tuple 3Eh 02h Disk Function Extension Tuple Type Basic PCMCIA-ATA extension tuple Extension tuple type for disk 40h 04h Reserved D U S V No Vpp, silicon, single drive Basic ATA option parameters byte 1 • V = 0: No Vpp required • S = 0: Silicon • U = 1: Unique serial number • D = 0: Single drive on Card 42h 07h R I E N P3 P2 P1 P0 • P0: Sleep mode supported Basic ATA option • P1: Standby mode supported parameters byte 2 • P2: Idle mode supported • P3: Drive auto power control • N: Some configuration excludes 3X7 • E: Index bit is emulated • I: Twin IOIS16# data register only •R: Reserved 44h 1Ah CISTPL_CONFIG Configuration tuple Tuple code 46h 05h TPL_LINK Link length is 5 bytes Link to next tuple 48h 01h RAS RMS RAS - • RFS: Reserved Size of fields byte • RMS: TPCC RMSK size -1 = 0 TPCC_SZ • RAS: TPCC_RADR size -1 = 1 • 1-byte register mask • 2-byte configuration base address 4Ah 07h TPCC_LAST Entry with configuration index of 7 is final Last entry of entry in table configuration registers 4Ch 00h TPCC_RADR (LSB) Configuration registers are located at Location of 200H in REG space configuration registers 4Eh 02h TPCC_RADR (MSB) - - 50h 0Fh Reserved S P C I - • I: Configuration index Configuration • C: Configuration and status registers present • P: Pin replacement mask • S: Socket and copy TPCC_RMSK 52h 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code 54h 0Bh TPL_LINK Link length is 11 bytes Link to next tuple SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE 30 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 56h C0h I D Configuration index Memory-mapped I/O configuration Configuration table index byte • I = 1: Interface byte follows TPCE_INDX • D = 1: Default entry • Configuration index = 0 58h C0h W R P B Interface Type • W = 0: Wait not used Interface description • R = 1: Ready active field TPCE_IF • P = 0: WP used • B = 0: BVD1 and BVD2 not used • IF type = 0: Memory interface 5Ah A1h M MS IR IO T P • M = 1: Miscellaneous information Feature selection present byte TPCE_FS • MS = 01: Memory space information single 2-byte length • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information 5Ch 27h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information 5Eh 55h X Mantissa Exponent Nominal voltage = 5V VCC nominal value 60h 4Dh X Mantissa Exponent VCC nominal 4.5V VCC minimum value 62h 5Dh X Mantissa Exponent VCC nominal 5.5V VCC maximum value 64h 75h X Mantissa Exponent Maximum average current over 10ms is Maximum average 80mA current 66h 08h Length in 256 bytes pages (LSB) Length of memory space is 2KB Memory space description structures (TPCE_MS) 68h 00h Length in 256 bytes pages (MSB) Length of memory space is 2KB Memory space description structures (TPCE_MS) 6Ah 21h X R P RO AT - • X = 0: No more miscellaneous fields Miscellaneous •R: Reserved features field • P = 1: Powerdown supported TPCE_MI • RO = 0: Not read only mode • A = 0: Audio not supported • T = 0: Single drive 6Ch 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 31 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 6Eh 06h TPL_LINK Link length is 6 bytes Link to next tuple 70h 00h I D IR IQ T P - Memory-mapped I/O configuration Configuration table index byte • I = 0: No interface byte TPCE_INDX • D = 0: No default entry • Configuration index = 0 72h 01h M MS IR IO T P - • M = 0: No miscellaneous information Feature selection • MS = 00: No memory space byte information TPCE_FS • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information 74h 21h R DI PI AI SI HV/LV/NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information 76h B5h X Mantissa Exponent Nominal voltage = 3.0 V VCC nominal value 78h 1Eh Extension +0.3 V Extension byte 7Ah 4Dh X Mantissa Exponent Maximum average current over 10ms is Maximum average 45 mA current 7Ch 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code 7Eh 0Dh TPL_LINK Link length is 10 bytes Link to next tuple 80h C1h I D Configuration INDEX Contiguous I/O mapped ATA registers Configuration table configuration index byte TPCE_INDX • I = 1: Interface byte follows • D = 1: Default entry • Configuration index = 1 82h 41h W R P B Interface Type • W = 0: Wait not used Interface description • R = 1: Ready active field TPCE_IF • P = 0: WP not used • B = 0: BVS1 and BVD2 not used • IF type = 1: I/O interface 84h 99h M MS IR IO T P - • M = 1: Miscellaneous information Feature selection present byte TPCE_FS • MS = 00: No memory space information • IR = 1: Interrupt information present • IO = 1: I/O port information present • T = 0: No timing information present • P = 1: VCC only information SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE 32 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 86h 27h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information 88h 55h X Mantissa Exponent Nominal voltage = 5V VCC nominal value 8Ah 4Dh X Mantissa Exponent VCC nominal 4.5V VCC minimum value 8Ch 5Dh X Mantissa Exponent VCC nominal 5.5V VCC maximum value 8Eh 75h X Mantissa Exponent Maximum average current over 10ms is Maximum average 80mA current 90h 64h R S E I O AddrLine • S = 1: 16-bit hosts supported I/O space • E = 1: 8-bit hosts supported description field • IO AddrLine: 4 lines decoded TPCE_IO 92h F0h S P L M V B I N • S = 1: Share logic active Interrupt request • P = 1: Pulse mode IRQ supported description structure • L = 1: Level mode IRQ supported TPCE_IR • M = 1: Bit mask of IRQs present • V = 0: No vender unique IRQ • B = 0: No bus error IRQ • I = 0: No IO check IRQ • N = 0: No NMI 94h FFh IR IR IR IR IR IR IR IR SiliconSystems recommends the IRQ Mask extension level to be routed 0 to 15 byte 1 TPCE_IR Q QQQ QQQ Q 76 54 321 0 96h FFh IR IR IR IR IR IR IR IR SiliconSystems recommends routing to Mask extension any normal, maskable IRQ. byte 2 TPCE_IR Q QQQ QQQ Q 15 14 13 12 11 10 9 8 98h 21h X R P R O A T - • X = 0: No more miscellaneous fields Miscellaneous •R: Reserved features field • P = 1: Powerdown supported TPCE_MI • RO = 0: Not read only mode • A = 0: Audio not supported • T = 0: Single drive 9Ah 1Bh CISTPL__TABLE_ENTRY Configuration table entry tuple Tuple code 9Ch 06h TPL_LINK Link length is 6 bytes Link to next tuple 9Eh 01h I D Configuration Index Contiguous I/O mapped ATA registers Configuration table configuration index Byte TPCE_INDX • I = 0: No Interface byte • D = 0: No Default entry • Configuration index = 1 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 33 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset A0h 01h M MS IR IO T P - • M = 0: No miscellaneous information Feature selection • MS = 00: No memory space byte TPCE_FS information • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information A2h 21h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information A4h B5h X Mantissa Exponent Nominal voltage = 3.0V VCC nominal value A6h 1Eh X Mantissa Exponent +0.3V Extension byte A8h 4Dh X Mantissa Exponent Maximum average current over 10ms is Maximum average 45mA current AAh 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Extension byte ACh 12h TPL_LINK Link length is 18 bytes Link to next tuple AEh C2h I D Configuration Index ATA primary I/O mapped configuration Configuration table index byte • I = 1: Interface byte follows TPCE_INDX • D = 1: default entry follows • Configuration index = 2 B0h 41h W R P B Interface Type • W = 0: Wait not used Interface description • R = 1: Ready active field TPCE_IF • P = 0: WP not used • B = 0: BVS1 and BVD2 not used • IF type = 1: I/O interface B2h 99h M MS IR IO T P - • M = 1: Miscellaneous information Feature selection present byte TPCE_FS • MS = 00: No memory space information • IR = 1: Interrupt information present • IO = 1: I/O port information present • T = 0: No timing information present • P = 1: VCC only information B4h 27h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE 34 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset B6h 55h X Mantissa Exponent Nominal voltage = 5V VCC nominal value B8h 4Dh X Mantissa Exponent VCC nominal 4.5V VCC minimum value BAh 5Dh X Mantissa Exponent VCC nominal 5.5V VCC maximum value BCh 75h X Mantissa Exponent Maximum average current over 10ms is Maximum average 80mA current BEh EAh R S E I O AddrLine • R = 1: Range follows I/O space • S = 1: 16-bit hosts supported description field • E = 1: 8-bit hosts supported TPCE_IO IO AddrLines: 10 lines decoded C0h 61h LS AS N Range • LS = 1: Size of lengths is 1 byte I/O range format • AS = 2: Size of address is 2 bytes description • N Range = 1: Address Range-1 C2h F0h First I/0 Base Address First I/O base address (LSB) First I/O range address C4h 01h First I/0 Base Address First I/O base address (MSB) - C6h 07h First I/0 Base Address First I/O length -1 First I/O range length C8h F6h Second I/O Base Address Second I/O base address (LSB) Second I/O range address CAh 03h Second I/O Base Address Second I/O base address (MSB) CCh 01h Second I/O Range Length Second I/O length -1 Second I/O range length CEh EEh S P L M IRQ Level • S = 1: Share logic active Interrupt request • P = 1: Pulse mode IRQ supported description structure • L = 1: Level mode IRQ supported TPCE_IR • M = 0: Bit mask of IRQs present — IRQ level is IRQ14 D0h 21h X R P R O A T - • X = 0: No more miscellaneous fields Miscellaneous •R: Reserved features field • P = 1: Powerdown supported TPCE_MI • RO = 0: Not read only mode • A = 0: Audio not supported • T = 0: Single drive D2h 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code D4h 06h TPL_LINK Link length is 6 bytes Link to next tuple D6h 02h I D Configuration Index ATA primary I/O mapped configuration Configuration table index byte • I = 0: No Interface byte TPCE_INDX • D = 0: No Default entry • Configuration index = 2 D8h 01h I D Configuration Index Contiguous I/O mapped ATA registers Configuration table configuration index byte TPCE_INDX • I = 0: No interface byte • D = 0: No default entry • Configuration index = 1 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 35 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset DAh 21h M MS IR IO T P - • M = 0: No miscellaneous information Feature selection • MS = 00: No memory space byte TPCE_FS information • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information DCh B5h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information DEh 1Eh X Mantissa Exponent Nominal voltage = 3.0V VCC nominal value E0h 4Dh Extension +0.3V Extension byte E2h 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code E4h 12h TPL_LINK Link length is 18 bytes Link to next tuple E6h C3h M MS IR IO T P - • M = 0: No miscellaneous information Feature selection • MS = 00: No memory space byte TPCE_FS information • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information E8h 41h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information EAh 99h M MS IR IO T P - • M = 1: No miscellaneous information Feature selection • MS = 00: No Memory space byte TPCE_FS information • IR = 1: No interrupt information present • IO = 1: No I/O port information present • T = 0: No timing information present • P = 01: VCC only information SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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PAGE 36 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset ECh 27h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information EEh 55h X Mantissa Exponent Nominal voltage = 5V VCC nominal value F0h 4Dh X Mantissa Exponent VCC nominal 4.5V VCC minimum value F2h 5Dh X Mantissa Exponent VCC nominal 5.5V VCC maximum value F4h 75h X Mantissa Exponent Maximum average current over 10ms is Maximum average 80mA current F6h EAh R S E I O AddrLine • R = 1: Range follows I/O space • S = 1: 16-bit hosts supported description field • E = 1: 8-bit hosts supported TPCE_IO • IO AddrLines: 10 lines decoded F8h 61h LS AS N Range • LS = 1: Size of lengths is 1 byte I/O range format • AS = 2: Size of address is 2 bytes description • N Range = 1: Address range -1 FAh 70h - First I/O base address (LSB) First I/O range address FCh 01h - First I/O base address (MSB) - FEh 07h - First I/O length -1 First I/O range length 100h 76h - Second I/O base address (LSB) Second I/O range address 102h 03h - Second I/O base address (MSB) - 104h 01h - Second I/O length Second I/O range length 106h EEh S P L M IRQ Level • S = 1: Share logic active Interrupt request • P = 1: Pulse mode IRQ supported description structure • L = 1: Level mode IRQ supported TPCE_IR • M = 0: Bit mask of IRQs present — miscellaneous IRQ level is IRQ14 features field TPCE_MI 108h 21h X R P R O A T - • X = 0: No more miscellaneous fields - •R: Reserved • P = 1: Powerdown supported • RO = 0: Not read only mode • A = 0: Audio not supported • T = 0: Single drive 10Ah 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code 10Ch 06h TPL_LINK Link length is 6 bytes Link to next tuple SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. 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DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 37 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 10Eh 03h I D Configuration Index ATA primary I/O mapped configuration Configuration table index byte • I = 0: No interface byte TPCE_INDX • D = 0: No default entry • Configuration index = 2 110h 01h M MS IR IO T P - • M = 0: No miscellaneous information Feature selection • MS = 00: No memory space byte TPCE_FS information • IR = 0: No interrupt information present • IO = 0: No I/O port information present • T = 0: No timing information present • P = 1: VCC only information 112h 21h R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for VCC •R: Reserved • DI: Powerdown current information • PI: Peak current information • AI: Average current information • SI: Static current information • HV: Maximum voltage information • LV: Minimum voltage information • NV: Nominal voltage information 114h B5h X Mantissa Exponent Nominal voltage = 3.0V VCC nominal value 116h 1Eh Extension +0.3V Extension byte 118h 4Dh X Mantissa Exponent Maximum average current over 10ms is Maximum average 45mA current 11Ah 1Bh CISTPL_MANFID Manufacturer’s ID code Tuple code 11Ch 04h TPL_LINK Link length is 4 bytes Link to next tuple 11Eh 07h I D Configuration Index AT fixed disk secondary I/O 3.3V TPCE_INDX configuration 120h 00h M MS IR IO T P - P: Power information type TPCL_FS 122h 28h - Manufacturer code for SiliconDrive CF Reserved 124h D3h - Manufacturer code for SiliconDrive CF Reserved 126h 14h CISTPL_NO_LINK No link control tuple Tuple code 128h 00h - Link is 0 bytes Link to next tuple 12Ah 15h CISTPL_VERS_1 Level 1 version Tuple code 12Ch 1Ah TPL_LINK Link length is 26h bytes Link to next tuple 12Eh 04h TPPLV1_MAJOR PC Card 2.0/JEIDA4.1 END marker 130h 01h TPPLV1_MINOR PC Card 2.0/JEIDA4.1 Tuple code 132h 53h - S Information string 134h 49h - I - 136h 4Ch - L - 138h 49h - I - 13Ah 43h - C - SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 38 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function Offset 13Ch 4Fh - O - 13Eh 4Eh - N - 140h 53h - S - 142h 59h - Y - 144h 53h - S - 146h 54h - T - 148h 45h - E - 14Ah 4Dh - M - 14Ch 53h - S - 14Eh 00h - Space - 150h 56h - V - 152h 45h - E - 154h 52h - R - 156h 32h - 2 - 158h 2Eh - - - 15Ah 30h - 0 - 15Ch 30h - 0 - 15Eh 00h - - - 160h FFh - - - SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 39 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION CONFIGURATION OPTION REGISTER (200H) The Configuration Option register is used to configure the SiliconDrive CF, define the address decoding, and initiate the software RESET sequence. Table 22: Configuration Option Register (200h) D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/ SRESET LevIREQ Configuration Index Write Default 0 0 000000 Value Bit(s) Description SRESET When set, this bit initiates a software-reset sequence, which is equivalent to a power-on reset or hardware reset. LevlREQ IREQ# interrupt signal level mode select: • Logic 0 = Pulse mode • Logic 1 = Level mode Configuration • Memory-mapped mode 000000B Index • Independent I/O mode 000001B • Primary mode 000010B • Secondary mode 000011B SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 40 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET CONFIGURATION AND STATUS REGISTER (202H) The Configuration and Status Register (CSR) informs the host of any status changes with regard to power-down. Table 23: Configuration and Status Register (202h) D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read Changed SigChg IOis8 0 0 PwrDn Int 0 Write Changed SigChg IOis8 0 0 PwrDn Int 0 Default 00 0 0 0 0 0 0 Value Bit(s) Description Changed Indicates that either CREADY (D5) or CWPort (D4) of the Pin Replacement register is set. Additionally, this bit changes state as the Powerdown (D2) bit changes. SigChg Outputs the inverse state of the Changed bit to the hardware interface signal STSCHG# at the card interface. Iois8 Informs the host of the valid data bus width for the operations in progress: • 0 = 16-bit data transfer • 1 = 8-bit data transfer PwrDwn Indicates the state of the Card, which is either operating -0 or powerdown mode 1. During powerdown mode, no commands are accepted. Additionally, the host may not initiate a powerdown request when the card is busy via the Status register or the Hardware RDY/BSY pin. Int Indicates the inverse of the IREQ# status signal. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 41 SSD-CXXX(I)-3500 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION PIN PLACEMENT REGISTER (204H) Table 24: Pin Placement Register (204h) D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/ CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt Write Default 00 0 0 11 0 0 Value Bit(s) Description CRDY Indicates a bit change in the RRDY (D1) bit. CWProt Indicates a bit change in the RWProt (D0) bit. RRDY When set: • High 1 informs the host that the card is ready • Low 0 state indicates the card is busy RWProt Indicates Write Protect is enabled when set to 1, and disabled when 0. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 42 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET SOCKET AND COPY REGISTER (206H) Table 25: Socket and Copy Register (206h) D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/Write RFU Copy Number Socket Number Default Value 0 000000 0 Bit(s) Description RFU Reserved for future use. Copy Indicates the card number. Allows the host to differentiate Number between identical cards by writing to the bit of the card that is being accessed. This value is compared to the DRV bit in the ATA Drive/Head register. • Card 0: 000B = (D6, D5, D4) (default) • Card 1: 001B = (D6, D5, D4) (alternate) Socket The host writes the socket number that identifies the inserted Number card. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 43 SSD-CXXX(I)-3500 DATA SHEET COMMON MEMORY DESCRIPTION AND OPERATION COMMON MEMORY DESCRIPTION AND OPERATION Common memory space can be accessed when the SiliconDrive is configured in memory-mapped mode. COMMON MEMORY READ OPERATIONS Common memory read operations are issued by asserting CE1#, CE2#, or both, and OE# low, REG#, and WE# must be inactive. Table 26: Common Memory Read Operations Function Mode REG# CE1# CE2# A0 OE# WE# D[15:8] D[7:0] Standby X H H X X X High-Z High-Z Byte Access H L H L L H High-Z Even H L H H L H High-Z Odd Word Access H L L X L H Odd Even Odd Byte Only H H L X L H Odd High-Z Access COMMON MEMORY WRITE OPERATIONS Common memory write operations are issued by asserting CE1#, CE2#, or both, and WE# low, REG#, and OE# must be inactive. Table 27: Common Memory Write Operations Function Mode REG# CE1# CE2# A0 OE# WE# D[15:8] D[7:0] Standby X H H X X X High-Z High-Z Byte Access H L H L H L High-Z Even H L H H H L High-Z Odd Word Access H L L X H L Odd Even Odd Byte Only HH L X H L Odd High-Z Access SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 44 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R I/O SPACE DESCRIPTION AND OPERATION SSD-CXXX(I)-3500 DATA SHEET I/O SPACE DESCRIPTION AND OPERATION I/O SPACE READ OPERATIONS Table 28: I/O Space Read Operations Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0] Standby X H H X X X High-Z High-Z Byte Access L L H L L H High-Z Even L L H H L H High-Z Odd Word Access L L L L L H Odd Even I/O Inhibit H X X X L H High-Z High-Z Odd Byte Only L H L X L H Odd High-Z Access I/O SPACE WRITE OPERATIONS Table 29: I/O Space Write Operations Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0] Standby X H H X X X X X Byte Access L L H L H L X Even LL H HH L X Odd Word Access L L L L H L Odd Even I/O Inhibit H X X X H L X X Odd Byte Only LH L XH L Odd X Access SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 45 SSD-CXXX(I)-3500 DATA SHEET ATA AND TRUE IDE REGISTER DECODING ATA AND TRUE IDE REGISTER DECODING SiliconDrive can be configured as either memory-mapped or I/O devices. As noted earlier, communication to and from the drive is accomplished using the ATA Command Block. MEMORY-MAPPED REGISTER DECODING In memory-mapped mode, the SiliconDrive registers are accessed via standard memory references (i.e., OE# and WE#). The ATA registers are mapped to common memory space in a 2KB window starting at address 0. Table 30: Memory-Mapped Register Decoding Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L WE# = L 1 0 0 X 0000Even Data Even Data Read Write 1 1 0 X 0001Error Feature 1 2 0 X 0010Sector Count Sector Count 1 3 0 X 0011Sector Sector Number Number 1 4 0 X 0100Cylinder Low Cylinder Low 1 5 0 X 0101Cylinder High Cylinder High 1 6 0 X 0110Drive/Head Drive/Head 1 7 0 X 0111Status Command 1 8 0 X 1000Duplicate Duplicate Even Data Even Data Read Write 1 9 0 X 1001Duplicate Odd Duplicate Odd Data Read Data Write 1 D 0 X 1101Duplicate Duplicate Error Feature 1 E 0 X 1110Alternate Device Control Status 1 F 0 X 1111Drive Address Reserved 1 X 1 X XXX0 Even Data Even Data Read Write 1 X 1 X XXX1 Odd Data Odd Data Read Write SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 46 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA AND TRUE IDE REGISTER DECODING SSD-CXXX(I)-3500 DATA SHEET INDEPENDENT I/O MODE REGISTER DECODING Independent I/O mode or contiguous I/O mode requires the host to decode a continuous block of 16 I/O registers to select the SiliconDrive. Table 31: Independent I/O Mode Register Decoding Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L WE# = L 0 0 X X 0000Even Data Even Data Read Write 0 1 X X 0001Error Feature 0 2 X X 0 0 1 0 Sector Count Sector Count 0 3 X X 0011Sector Sector Number Number 0 4 X X 0 1 0 0 Cylinder Low Cylinder Low 0 5 X X 0 1 0 1 Cylinder High Cylinder High 0 6 X X 0110Drive/Head Drive/Head 0 7 X X 0111Status Command 0 8 X X 1 0 0 0 Duplicate Duplicate Even Data Even Data Read Write 0 9 X X 1 0 0 1 Duplicate Odd Duplicate Odd Data Read Data Write 0 D X X 1 1 0 1 Duplicate Error Duplicate Feature 0 E X X 1 1 1 0 Alternate Device Control Status 0 F X X 1 1 1 1 Drive Address Reserved SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 47 SSD-CXXX(I)-3500 DATA SHEET ATA AND TRUE IDE REGISTER DECODING PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING Table 32: Primary and Secondary I/O Mapped Register Decoding A9:A4 A9:A4 Reg# A10 A3 A2 A1 A0 IORD# = L IOWR# = L Primary Secondary 0 X 1Fxh 17xh 0 0 0 0 Even Data Even Data Read Write 0 X 1Fxh 17xh 0 0 0 1 Error Feature 0 X 1Fxh 17xh 0 0 1 0 Sector Sector Count Count 0 X 1Fxh 17xh 0 0 1 1 Sector Sector Number Number 0 X 1Fxh 17xh 0 1 0 0 Cylinder Cylinder Low Low 0 X 1Fxh 17xh 0 1 0 1 Cylinder Cylinder High High 0 X 1Fxh 17xh 0 1 1 0 Drive/Head Drive/Head 0 X 1Fxh 17xh 0 1 1 1 Status Command 0 X 3Fxh 37xh 0 1 1 0 Alternate Device Status Control 0 X 3Fxh 37xh 0 1 1 1 Drive Reserved Address SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 48 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA AND TRUE IDE REGISTER DECODING SSD-CXXX(I)-3500 DATA SHEET TASK FILE REGISTER SPECIFICATION The Task File registers are used for reading and writing the storage data in the SiliconDrive. The decoded addresses are as shown in the following table. Table 33: Task File Register Specification CS0# CS1# DA02 DA01 DA00 DIOR# = L DIOW# = L 01000Data Data 0 1 0 0 1 Error Feature 0 1 0 1 0 Sector Count Sector Count 0 1 0 1 1 Sector Number Sector Number 0 1 0 1 1 Cylinder Low Cylinder Low 0 1 1 0 1 Cylinder High Cylinder High 01110Drive/Head Drive/Head 01111Status Command 0 0 X X X Invalid Invalid 1 1 XXXHigh-Z Not Used 1 0 0 X X High-Z Not Used 1 0 1 0 X High-Z Not Used 1 0 1 1 0 Alternate Status Device Control 1 0 1 1 1 Device Address Not Used SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 49 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS ATA REGISTERS DATA REGISTER The Data register is a 16-bit register used to transfer data blocks between the host and drive buffers. The register may set to 8-bit mode by using the Set Features Command defined in "Seek — 7Xh" on page 81. ERROR REGISTER The Error register contains the error status, if any, generated from the last executed ATA command. The contents are qualified by the ERR bit being set in "Status Register" on page 57. Table 34: Error Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read BBK UNC MC IDNF MCR ABRT TKNOF AMNF Default 000000 0 0 Value Bit(s) Description 7 Bad Block Detected (BBK). Set when a bad block is detected. 6 Uncorrectable Data Error (UNC). Set when an uncorrectable error is encountered. 5 Media Changed (MC). Set to 0. 4 ID Not Found (IDNF). Set when the sector ID is not found. 3 MCR (Media Change Request). Set to 0. 2 Aborted Command (ABRT). Set when a command is aborted due to a drive error. 1 Track 0 Not Found (TKONF). Set when the executive drive diagnostic command is executed. 0 Address Mark Not Found (AMNF). Set in the case of a general error. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 50 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET FEATURE REGISTER The Feature register is command-specific and used to enable and disable interface features. This register supports only either odd or even byte data transfers. Table 35: Feature Register Operation D D D D D D D D 7 6 5 4 3 2 1 0 Read/Write Feature Byte SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 51 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS SECTOR COUNT REGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made. Table 36: Sector Count Register D D D D D D D Operation D 7 6 5 4 3 2 1 0 Read/Write Sector Count Default Value 0 000000 1 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 52 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET SECTOR NUMBER REGISTER The Sector Number register is set by the host to specify the starting sector number associated with the next ATA command to be executed. Following a qualified ATA command sequence, the device sets the register value to the last sector read or written as a result of the previous AT command. When Logical Block Addressing (LBA) mode is implemented and the host issues a command, the contents of the register describe the Logical Block Number bits A[7:0]. Following an ATA command, the device loads the register with the LBA block number resulting from the last ATA command. Table 37: Sector Number Register D D D D D D D Operation D 7 6 5 4 3 2 1 0 Read/Write Sector Number (CHS Addressing) Logical Block Number bits A07-A00 (LBA Addressing) Default Value 0000000 1 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 53 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS CYLINDER LOW REGISTER The Cylinder Low register is set by the host to specify the cylinder number low byte. Following an ATA command, the content of the register is written by the device, identifying the cylinder number low byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A15:A08. Table 38: Cylinder Low Register D D D D D D D Operation D 7 6 5 4 3 2 1 0 Read/Write Cylinder Number Low Byte (CHS Addressing) Logical Block Number bits A15-A08 (LBA Addressing) Default Value 0000000 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 54 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET CYLINDER HIGH REGISTER The Cylinder High register is set by the host to specify the cylinder number high byte. Following an ATA command, the content of the register is set internally by the device, identifying the cylinder number high byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A23:A16. Table 39: Cylinder High Register D D D D D D D Operation D 7 6 5 4 3 2 1 0 Read/Write Cylinder Number Low Byte (CHS Addressing) Logical Block Number bits A23-A16 (LBA Addressing) Default Value 0 000000 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 55 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS DRIVE/HEAD REGISTER The Drive/Head register is used by the host and the device to select the type of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head number in CHS mode or logical block number bits 27-24 in LBA mode. Table 40: Drive/Head Register Operation D D D D D D D D 7 6 5 4 3 2 1 0 Read/Write 1 LBA 1 DRV HS3 HS2 HS1 HS0 LBA24 LBA27 LBA26 LBA25 Default 10100000 Value The Drive/Head register is used by the host to specify one of a pair of ATA drives present in the platform. Bit(s) Description 6 LBA. Selects between CHS (0) and LBA (1) addressing mode. 4 Drive Address (DRV). Indicates the drive number selected by the host, either 0 or 1. 3-0 HS3 to 0. Indicates bits 3-0 of the head number in CHS addressing mode or LBA bits 27-24 in LBA mode. • CHS to LBA conversion: LBA = (C x HpC + H) x SpH + S -1 • LBA to CHS conversion: ¶ C = LBA/(HpC x SpH) ¶ H = (LBA/SpH) mod (HpC) ¶ S = (LBA mod(SpH)) + 1 ...where: ¶ C is the cylinder number ¶ H is the head number ¶ S is the sector count ¶ HpC is the head count per cylinder count ¶ SpH is the sector count per head count (track) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 56 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET STATUS REGISTER The Status register provides the device’s current status to the host. The status register is an 8-bit read-only register. When the contents of the register are read by the host, the IREQ# bit is cleared. Table 41: Status Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 0 0 0 0 Bit(s) Description 7 Busy (BSY). Set when the drive is busy and unable to process any new ATA commands. 6 Data Ready (DRDY). Set when the device is ready to accept ATA commands from the host. 5 Drive Write Fault (DWF). Always set to 0. 4 Drive Seek Complete (DSC). Set when the drive heads have been positioned over a specific track. 3 Data Request (DRQ). Set when a device is ready to transfer a word or byte of data to or from the host and the device. 2 Corrected Data (CORR). Always set to 0. 1 Index (IDX). Always set to 0. 0 Error (ERR). Set when an error occurs during the previous ATA command. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 57 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS COMMAND REGISTER The Command register specifies the ATA command code being issued to the drive by the host. Execution of the command begins immediately following the issuance of the command register code by the host. Table 42: Command Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/Write ATA Command Code See "ATA Command Block and Set Description" on page 62 for a listing of the supported ATA commands. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 58 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET ALTERNATE STATUS REGISTER The Alternate Status register is a read-only register indicating the status of the device, following the previous ATA command. See "Status Register" on page 57 for specific details. Table 43: Alternate Status Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 0 0 0 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 59 SSD-CXXX(I)-3500 DATA SHEET ATA REGISTERS DEVICE CONTROL REGISTER The Device Control register is used to control the interrupt request and issue ATA software resets. Table 44: Device Control Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Write ---- 1 SRSTnIEN 0 Bit(s) Description 7-4 Reserved bits. 3 Always set to 1. 2 Software Reset (SRST). When set, resets the ATA software. 1 Interrupt Enable (nIEN). When set, device interrupts are disabled. There is no function in the memory-mapped mode. 0 Always set to 0. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 60 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA REGISTERS SSD-CXXX(I)-3500 DATA SHEET DEVICE ADDRESS REGISTER The Device Address register is used to maintain compatibility with ATA disk drive interfaces. Table 45: Device Address Register D D D D D D D D Operation 7 6 5 4 3 2 1 0 Read/Write - nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0 Default Value 0 0 1 11110 Bit(s) Description 7 Reserved bit. 6 Write Gate (nWTG). Low when a write to the device is in process. 5-2 nHS3 to nHS0. The negated binary address of the currently selected head. 1 nDS1. Low when drive 1 is selected and active. 0 nDS0. Low when drive 0 is selected and active. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 61 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION ATA COMMAND BLOCK AND SET DESCRIPTION In accordance with the ANSI ATA Specification, the device implements seven registers that are used to transfer instructions to the device by the host. These commands follow the ANSI standard ATA protocol. A description of the ATA command block is provided in the following table. Table 46: ATA Command Block and Set Description D D D D D D D D Operation 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1LBA 1 Drive X Command X ATA COMMAND SET Table 47: ATA Command Set Registers Used Command Class Command Name Code FR SC SN CY DH LBA 1 Check Power Mode 98h, E5h - - - - D - 1 Execute Drive 90h ----D - Diagnostics 1 Erase Sector C0h - YYYYY 2 Format Track 50h - Y - Y Y Y 1 Identify Drive ECh ----D - 1 Idle 97h, E3h - Y - - D - 1 Idle Immediate 95h, E1h - - - D - 1 Initialize Drive 91h - Y - - Y - Parameters 1 Read Buffer E4h - - - - D - 1 Read DMA* C8h - YYYYY 1 Read Multiple C4h - Y Y Y Y Y SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 62 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Table 47: ATA Command Set (Continued) Registers Used Command Class Command Name Code FR SC SN CY DH LBA 1 Read Long Sector 22h, 23h - - YYYY 1 Read Sector(s) 20h, 21h - - YYYY 1 Read Verify Sector(s) 40h, 41h - YYYYY 1 Recalibrate 1Xh ----Y - 1 Request Sense 03h ----D - 1 Seek 7Xh - - YYYY 1 Set Features EFh Y - - D - 1 Set Multiple Mode C6h - Y - - D - 1 Set Sleep Mode 99h, E6h ----D - 1 Standby 96h, E2h ----D - 1 Standby Immediate 94h, E0h ----D - 1 Translate Sector 87h - YYYYY 1 Wear Level F5h ----Y - 2 Write Buffer E8h ----D - 1 Write DMA* CAh - YYYYY 2 Write Long Sector 32h, 33h - YYYY 3 Write Multiple C5h - YYYYY 3 Write Multiple w/o CDh - YYYYY Erase 2 Write Sector(s) 30h, 31h - YYYYY 2 Write Sector(s) w/o 38h - YYYYY Erase 3 Write Verify 3Ch - YYYYY - NOP FFh ------ * = This function does not apply to SiliconDrives that have DMA disabled. Notes: • CY = Cylinder • SC = Sector Count • DH = Drive/Head • SN = Sector Number • FR = Feature LBA — LBA bit of the Drive/Head register (D denotes that only the drive bit is used) SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 63 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Check Power Mode — 98h, E5h The Check Power Mode command verifies the device’s current power mode. When the device is configured for standby mode or is entering or exiting standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY bit is cleared. In idle mode, BSY is set and the Sector Count register is set to FFh. The BSY bit is then cleared and an interrupt is issued. Table 48: Check Power Mode — 98h, E5h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive Command 98h or E5h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 64 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Executive Drive Diagnostic — 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using (AA55h and 55AAh). If an error is detected in the read/write buffer, the Error register reports the appropriate diagnostic code. Table 49: Executive Drive Diagnostic — 90h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive Command 90h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 65 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Format Track — 50h The Format Track command formats the common solid-state memory array. Table 50: Format Track — 50h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 50h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 66 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Identify Drive — ECh Issued by the host, the Identify Drive command provides 256 bytes of drive attribute data (i.e., sector size, count, and so on) The identify drive data structure is detailed in the following table. Table 51: Identify Drive — ECh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command ECh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 67 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Identify Drive — Drive Attribute Data Table 52: Identify Drive — Drive Attribute Data Word Data Default Bytes Data Description Address 0 044Ah (fixed 2 General configuration bit information ID bit) in IDE • 15: Non-magnetic disk mode • 14: Formatting speed latency 848A permissible gap needed (removable ID • 13: Track Offset option supported bit) in PCMCIA • 12: Data Strobe Offset option supported memory and I/ • 11: Over 0.5% rotational speed O modes difference • 10: Disk transfer rate > 10Mbps • 9: 10Mbps >= disk transfer rate > 5Mbps • 8: 5Mbps >= disk transfer rate • 7: Removable cartridge drive • 6: Fixed drive • 5: Spindle Motor Control option executed • 4: Over 15µs changing head time • 3: Non-MFM encoding • 2: Soft sector allocation • 1: Hard sector allocation •0: Reserved 1 XXXXh 2 Number of cylinders 2 0000h 2 Reserved 3 00XXh 2 Number of heads 4 0000h 2 Number of unformatted bytes per track 5 XXXXh 2 Number of unformatted bytes per sector 6 XXXXh 2 Number of sectors per track 7-8 XXXXh 4 Number of sectors per device 9 0000h 2 Reserved 10-19 XXXXh 20 Serial number SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 68 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Bytes Data Description Address 20 0002h 2 Buffer type • 0000h: Not specified • 0001h: A single-ported, single-sector buffer • 0002h: A dual-ported multisector buffer • 0003h: A dual-ported multisector buffer with a read caching 21 0002h 2 Buffer size in 512-byte increments 22 0004h 2 Number of ECC bytes passed on read/ write long commands 23-26 XXXXh 8 Firmware revision (eight ASCII characters) 27-46 XXXXh 40 Model number (40 ASCII characters) 47 0001h 2 7-0: Maximum number of sectors that can be transferred with a Read/Write Multiple command per interrupt 48 0000h 2 Double word (32 bit) not supported 49 0002h 2 • 11: IORDY supported • 9: LBA supported • 8: DMA supported 50 0000h 2 Reserved 51 0100h 2 15-8: PIO data transfer cycle timing 52 0000h 2 15-8: DMA data transfer cycle timing 53 0000h 2 • 1: Words 64-70 are valid • 0: Words 54-58 are valid 54 XXXXh 2 Current number of cylinders 55 XXXXh 2 Current number of heads 56 XXXXh 2 Current sectors per track 57-58 XXXXh 4 Current capacity in sectors 59 010Xh 2 7-0: Current sectors can be transferred with a Read/Write Multiple command per interrupt 60-61 XXXXh 4 Total number of sectors addressable in LBA mode 62 0000h 2 Single-word DMA modes supported SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 69 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Bytes Data Description Address 63 0407h 2 Multiword DMA modes supported 64 0003h 2 PIO modes supported 65 0078h 2 Minimum DMA transfer cycle time per word (ns) 66 0078h 2 Manufacturer’s recommended DMA transfer cycle time (ns) 67 0078h 2 Minimum PIO transfer cycle time without flow control (ns) 68 0078h 2 Minimum PIO transfer cycle time with IORDY flow controls (ns) 69-127 0000h 118 Reserved 128-159 0000h 64 Vendor-unique 160-255 0000h 192 Reserved SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 70 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Idle — 97h, E3h When issued by the host, the device’s internal controller sets the BSY bit, enters the Idle mode, clears the BSY bit, and generates an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5ms, and the automatic power-down mode is enabled. If the sector count is zero, the automatic power-down mode is disabled. Table 53: Idle — 97h, E3h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Timer Count (5ms increments) Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 97h or E3h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 71 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Idle Immediate — 95h, E1h When issued by the host, the device’s internal controller sets the BSY bit, enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is issued whether or not the Idle mode is fully entered. Table 54: Idle Immediate — 95h, E1h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 95h or E1h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 72 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Initialize Drive Parameters — 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed. Upon issuance of the command, the device sets the BSY bit and associated parameters, clears the BSY bit, and issues an interrupt. Table 55: Initialize Drive Parameters — 91h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count (Number of Sectors) Sector Number X Cylinder Low X Cylinder High X Drive Head X 0 X Drive Head Number (Number of Heads — 1) Command 91h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 73 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Recalibrate — 1Xh The Recalibrate command sets the cylinder low and high, head number to 0h, and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector number is set to 0h. Table 56: Recalibrate — 1Xh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 LBA 1 Drive X Command 1Xh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 74 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Read Buffer — E4h The Read Buffer command allows the host to read the contents of the sector buffer. When issued, the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation. When the data is ready, the DRQ bit is set and the BSY bit in the Status register are set and cleared, respectively. Table 57: Read Buffer — E4h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command E4h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 75 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Read DMA — C8h The Read DMA command allows the host to read data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled. Table 58: Read DMA — C8h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command C8h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 76 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Read Multiple — C4h The Read Multiple command executes similarly to the Read Sector command, with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred. Table 59: Read Multiple — C4h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command C4h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 77 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Read Sector — 20h, 21h The Read Sector command allows the host to read sectors 1 to 256 as specified in the Sector Count register. If the sector count is set to 0h, all 256 sectors of data are made available. When the command code is issued and the first sector of data has been transferred to the buffer, the DRQ bit is set. The Read Sector command is terminated by writing the cylinder, head, and sector number of the last sector read in the task file. On error, the read operation is aborted in the errant sector. Table 60: Read Sector — 20h, 21h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 20h or 21h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 78 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Read Long Sector(s) — 22h, 23h The Read Long Sector(s) command operates similarly to the Read Sector(s) command, with the exception that it transfers requested data sectors and ECC data. The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes. Table 61: Read Long Sector(s) — 22h, 23h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 22h or 23h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 79 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Read Verify Sector(s) — 40h, 41h The Read Verify Sector(s) command operates similarly to the Read Sector(s) command, with the exception that is does not set the DRQ bit and does not transfer data to the host. When the requested sectors are verified, the onboard controller clears the BSY bit and issues an interrupt. Table 62: Read Verify Sector(s) — 40h, 41h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 40h or 41h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 80 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Seek — 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file. When the command is issued, the solid-state memory chips do not need to be formatted. After an appropriate amount of time, the DSC bit is set. Table 63: Seek — 7Xh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 7Xh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 81 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Set Features — EFh The Set Features command allows the host to configure the feature set of the device according to the attributes listed in Table 65. Table 64: Set Features — EFh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature Feature Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command EFh Table 65: Set Features’ Attributes Feature Operation 01h Enable 8-bit data transfer 66h Disable reverting to power on defaults 81h Disable 8-bit data transfer BBh 4 bytes of data apply on Read/Write Long commands CCh Enable revert to power on defaults On power-up or following a hardware reset, the device is set to the default mode 81h. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 82 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Set Multiple Mode — C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands. Additionally, the command sets the block count (i.e., the number of sectors within the block) for the Read/Write Multiple command. The sector count per block is set in the Sector Count register. Table 66: Set Multiple Mode — C6h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command C6h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 83 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Set Sleep Mode — 99h, E6h The Set Sleep Mode command allows the host to set the device in sleep mode. When the onboard controller transitions to sleep mode, it clears the BSY bit and issues an interrupt. The device interface then becomes inactive. Sleep mode can be exited by issuing either a hardware or software reset. Table 67: Set Sleep Mode — 99h, E6h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 99h or E6h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 84 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Standby — 96h, E2h When the Standby command is issued by the host, it transitions the device into standby mode. If the Sector Count register is set to a value other than 0h, the Auto Powerdown function is enabled and the device returns to Idle mode. Table 68: Standby — 96h, E2h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Timer Count (5ms x Timer Count) Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 96h or E2h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 85 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Standby Immediate — 94h, E0h When the Standby Immediate command is issued by the host, it transitions the device into standby mode. Table 69: Standby Immediate — 94h, E0h D D D D D D D D Register 7 6 5 4 3 2 1 7 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 94h or E0h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 86 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Write Buffer — E8h The Write Buffer command allows the host to rewrite the contents of the 512- byte data buffer with the wanted data. Table 70: Write Buffer — E8h D D D D D D D D Register 7 6 5 4 3 2 1 7 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command E8h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 87 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Write DMA — CAh The Write DMA command allows the host to write data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled. Table 71: Write DMA — CAh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low(LBA15-8) Cylinder High Cylinder High(LBA23-16) Drive Head X LBA X Drive Head Number(LBA27-24) Command CAh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 88 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Write Multiple — C5h The Write Multiple command operates in the same manner as the Write Sector command. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer. Table 72: Write Multiple — C5h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low(LBA15-8) Cylinder High Cylinder High(LBA23-16) Drive Head X LBA X Drive Head Number(LBA27-24) Command C5h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 89 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Write Sector(s) — 30h, 31h The Write Sector(s) command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer. Table 73: Write Sector(s) — 30h, 31h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command 30h or 31h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 90 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Write Long Sector(s) — 32h, 33h The Write Long Sector(s) command operates in the same manner as the Write Sector command — when issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer. Table 74: Write Long Sector(s) — 32h, 33h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command 32h or 33h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 91 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Erase Sector(s) — C0h The Erase Sector(s) command is issued prior to the issuance of a Write Sector(s) or Write Multiple w/o Erase command. Table 75: Erase Sector(s) — C0h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command C0h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 92 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Request Sense — 03h The Request Sense command identifies the extended error codes generated by the preceding ATA command. The Request Sense command must be issued immediately following the detection of an error via the Error register. Table 76: Request Sense — 03h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 X 1 Drive X Command 03h The extended error codes are defined in the following table. Table 77: Extended Error Codes Extended Error Codes Description 00h No error detected 01h Self test is OK (no error) 09h Miscellaneous error 20h Invalid command 21h Invalid address (requested head or sector invalid) 2Fh Address overflow (address too large) 35h, 36h Supply or generated voltage out of tolerance 11h Uncorrectable ECC error 18h Corrected ECC error 05h, 30h-32h, 37h,3Eh Self test of diagnostic failed 10h, 14h ID not found 3Ah Spare sectors exhausted 1Fh Data transfer error/aborted command 0Ch, 38h, 3Bh, 3Ch, 3Fh Computed media format 03h Write/erase failed SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 93 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Translate Sector — 87h The Translate Sector command is not currently supported by the SiliconSystems’ SiliconDrive. If the host issues this command, the device responds with 0x00h in the data register. Table 78: Translate Sector — 87h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head 1 LBA 1 Drive Head Number (LBA27-24) Command 87h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 94 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Wear-Level — F5h The Wear-Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard. This command sets the Sector Count register to 0x00h. Table 79: Wear-Level — F5h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Completion Status Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive Flag Command F5h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 95 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Write Multiple w/o Erase — CDh The Write Multiple w/o Erase command functions identically to the Write Multiple command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 80: Write Multiple w/o Erase — CDh D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command CDh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 96 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R ATA COMMAND BLOCK AND SET DESCRIPTION SSD-CXXX(I)-3500 DATA SHEET Write Sector(s) w/o Erase — 38h The Write Sector(s) w/o Erase command functions similar to the Write Sector command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 81: Write Sector(s) w/o Erase — 38h D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command 38h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 97 SSD-CXXX(I)-3500 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION Write Verify — 3Ch The Write Verify command verifies each sector immediately after it is written. This command performs identically to the Write Sector(s) command, with the added feature of verifying each sector written. Table 82: Write Verify — 3Ch D D D D D D D D Register 7 6 5 4 3 2 1 0 Feature X Sector Count Sector Count Sector Number Sector Number (LBA7-0) Cylinder Low Cylinder Low (LBA15-8) Cylinder High Cylinder High (LBA23-16) Drive Head X LBA X Drive Head Number (LBA27-24) Command 3Ch SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 98 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R SALES AND SUPPORT SSD-CXXX(I)-3500 DATA SHEET SALES AND SUPPORT To order or obtain information on pricing and delivery, contact your SiliconSystems Sales Representative. PART NUMBERING NOMENCLATURE The following table defines the SiliconDrive CF part numbering scheme. Table 83: Part Numbering Nomenclature SSD- C YYY T -3500 Part number suffix — contact your SiliconSystems Sales Representative Temperature Range: • Blank = Commercial • I = Industrial Capacity: 32M = 32MB to 08G = 8GB Form Factor: •C = CF •D = 2.5" Drive •M = Module •P = PC Card SiliconSystems SiliconDrive PART NUMBERS The following table lists the SiliconDrive’s part numbers. Table 84: Part Numbers Part Number Capacity SSD-C08G(I)-3500 8GB SSD-C04G(I)-3500 4GB SSD-C02G(I)-3500 2GB SSD-C01G(I)-3500 1GB SSD-C51M(I)-3500 512MB SSD-C25M(I)-3500 256MB SSD-C12M(I)-3500 128MB SSD-C64M(I)-3500 64MB SSD-C32M(I)-3500 32MB SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 99 SSD-CXXX(I)-3500 DATA SHEET PART NUMBERING ROHS 6 OF 6 PRODUCT LABELING — PB-FREE IDENTIFICATION LABEL Pb The Pb-free identification label indicates that the enclosed components/ devices and/or assemblies do not contain any lead (i.e., they are lead-free, as defined in RoHS directive 2002/95/ED). The above Pb symbol is on all RoHS 6 of 6 compliant product labels, as seen in Figure 8. SAMPLE LABEL Standard Back Label with Front Label Lot Code Information 8GB 8GB SSD-C08G(I)-3500 0841/3500 Figure 8: Sample Label SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 100 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R RELATED DOCUMENTATION SSD-CXXX(I)-3500 DATA SHEET RELATED DOCUMENTATION For more information, visit www.siliconsystems.com or contact your SiliconSystems Sales Representative. Table 85: Related Documentation SiliconDrive Application-Specific Description Document Number Technology PowerArmor™ Eliminates drive corruption SSWPxx-PowerArmor-R SiSMART™ Calculates remaining useful SSWPxx-SiSMART-R life SiProtect™ Software write protection SSANxx-SilDrvSec-R for Read-only access SiSecure™ Password required for read/ SSANxx-SilDrvSec-R write access SiSweep™ Ultra-fast data erasure SSANxx-SilDrvSec-R SiPurge™ Non-recoverable data SSANxx-SilDrvSec-R erasure * NDA required SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. DOCUMENT: SSDS02-3500C-R FEBRUARY 7, 2007 PAGE 101 SSD-CXXX(I)-3500 DATA SHEET RELATED DOCUMENTATION Click here Click here SiliconSystems' performance tests, ratings and product specifications are measured using specific computer systems and/or components and reflect the approximate performance of SiliconSystems’ products as measured by those tests. Any difference in system hardware or software design or configuration, as well as system use, may affect actual test results, ratings and product specifications. SiliconSystems welcomes user comments and reserves the right to revise this document and/or make updates to product specifications, products, or programs described without notice at any time. SiliconSystems makes no representations or warranties regarding this document. The names of actual companies and products mentioned herein are the trademarks of their respective owners. SiliconSystems™, SiliconDrive™, PowerArmor™, and the SiliconSystems logo are trademarks or registered trademarks of SiliconSystems and may be used publicly only with permission from SiliconSystems and require proper acknowledgement. Other listed names and brands are trademarks or registered trademarks of their respective owners. © Copyright 2006 by SiliconSystems, Inc. All rights reserved. No part of this publication may be reproduced without the prior written consent of SiliconSystems. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. PAGE 102 FEBRUARY 7, 2007 DOCUMENT: SSDS02-3500C-R