SI-C671xDSP-cPCI C671x DSP Board for CompactPCI/PXI Bus Key Features • 1800 MFLOPS peak performance with C6713, 32 bit floating/fixed point precision. • Up to 256MB SDRAM, using conventional PC133 SDRAM SO-DIMM format. • Full 32 bit bi-directional PCI initiated bus mastering, with 132MB/sec peak transfer rate. • Memory mapped host communications port. • Software development tools from Sheldon Instruments includes QuVIEW, QuBASE and the SI-DDKs; as well compatibility with separately purchased TI and third party tools. • Win98/2000/XP and Linux drivers and sample application support. • Expansion connectors for prototyping, analog & digital I/O daughtercards. • Small 3U form factor. • JTAG port for in system development and debugging. Introduction The SI-C6xDSP-cPCI from Sheldon Instruments is a powerful Digital Signal Processor (DSP) card for your system equipped with a cPCI/PXI bus. It is based on Texas Instruments' 225-300Mhz TMS320C6713, 32 bit DSP, and can transform your cPCI/PXI chassis into an ultra high performance development system and DSP accelerator. A full line of software development tools are available from Sheldon Instruments and TI, which include compilers, assemblers, linkers, and debuggers. Host cPCI/PXI bus to DSP Link The hardware interface betwen the host cPCI/PXI bus and the DSP is implemented with PLX's PCI9054 device. Onboard control logic arbitrates the appropriate timing between the C6x's EMIF bus, the boot SRAM/Flash, and the PCI9054's local bus. A combination of hardware and software handshaking takes place in order to support a myriad of data transfer schemes, where the host side can be selected to operate in one mode and the DSP in another. From the host cPCI/PXI side, three (3) modes are available: 1) target/slave mode, 2) PCI initiated bus mastered transfer mode with the PCI9054 acting as the bus master, and 3) bus mastering with the DSP acting as the PCI bus master. From the DSP side, ©Copyright 2007 Sheldon Instruments Incorporated. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. three (3) modes are available: 1) standard programmed I/O, 2) asynchronous DMA, and 3) synchronous DMA. Host target/slave mode accesses are performed when the DSP is either disabled (reset asserted) or enabled (reset deasserted). While the DSP is disabled, the host uses target/slave mode transfers to load an initialization COFF file to the card's boot SRAM/Flash memory, as well as to access expansion daughter modules. After DSP activation, any combination of data transfer modes can be used on either side. For most applications, the most efficient method of large data block transfer is to use cPCI/PXI bus mastering, as it requires minimal host intervention. The first bus master method involves using the PCI9054's DMA engine, in conjunction with the DSP using programmed I/O or its own DMA engine. The second bus master transfer method allows the DSP to act as the PCI bus master, where it actually has direct access to the host computer's main memory! Memory Options The SI-C6xDSP-cPCI is configured with conventional 144 pin SO-DIMM socket to accommodate standard, 3.3V non-buffered PC133 SDRAM modules used in laptops. The SI-C6xDSP-cPCI supports *half* of the capacity on 64MB, 128MB, 256MB, and 512MB module sizes, making it a very cost effective solution for the most demanding and memory intensive applications. Hardware Support The SI-C6xDSP-cPCI includes expansion connectors allowing for custom designs, or for attaching 'off the shelf' multifunction I/O modules from Sheldon Instruments. Sheldon Instruments offers several daughter modules for multichannel analog and digital I/O, including 4 to 64 channels of 16 bit ADCs and DACs. Expandability Diagram ©Copyright 2007 Sheldon Instruments Incorporated. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. Software Support The SI-C6xDSP-cPCI is available with extensive development tools from Sheldon Instruments and TI. For quick turnkey development, Sheldon Instruments offers QuVIEW and QuBASE, which are a set of DSP-resident libraries for real time performance that greatly accelerate data acquisition, signal processing, and control applications. QuVIEW is a real time accelerator for LabVIEW, and QuBASE a real time accelerator for Visual Basic. A full range of examples and tutors are provided to demonstrate their ease of use and breadth of functionality and capabilities. QuBASE runs under Win98/2000/XP, while QuVIEW also runs under Linux. When purchased as a DSP evaluation board, Sheldon Instruments also includes free sample DSP and Win98/2000/XP or Linux device driver source code to accompany TI's development environment. The DSP source code illustrates full communication modes, and the Win98/2000/XP or Linux device driver source code includes the complete SI-DDK, along with COFF file loader utilities. ©Copyright 2007 Sheldon Instruments Incorporated. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. Technical Specifications Processor for SI-C671xDSP-cPCI: Interface to Host: • 225-300Mhz TMS320C6713. • cPCI/PXI initiated bus master transfer speeds: • 16 DSP DMA channels, 2 cPCI/PXI DMA channels. o Up to 132Mbyte/sec bursts with block Memory: sizes of eight (8) 32 bit words. o Up to 25Mbyte/sec sustained transfers • SDRAM program and data memory: of any block size, using DMA. o Standard 3.3V, non-buffered PC133 • Eight 32 bit, bi-directional communications SDRAM in SODIMM format. modes between TMS320C6x and the PCI9054: o Sizes: 64MB, 128MB, 256MB and 512MB, with x16 organizations. Only half of o Host target/slave access mode, capacity is used. combined with DSP I/O or DSP's DMA o PC133 SDRAM module clocked from E engine. Clock running at 75Mhz, maximum delay o Block Mode DMA Bus Master mode, using of memory ICs mounted on module not the PCI9054 as the cPCI/PXI bus master, to exceed 7.5 nsec. combined with DSP I/O or DSP's DMA o Single bank SO-DIMMs: supports *half* of engine. memory ICs mounted on single bank o cPCI/PXI Initiated/Local Master with the modules, with all capacity only mapped DSP as the cPCI/PXI bus master, with on CE2 (DSP memory region starting at DSP I/O or DSP's DMA engine. 0xA0000000). The DSP's CE3 region is left empty (DSP memory region starting • The PCI9054's internal registers are tied onto at 0xB000000). the C6x's EMIF bus, mapped on CE0 (DSP o Dual bank SO-DIMMs: supports *half* of memory region starting at 0x80000000). memory ICs mounted on dual bank • Four C6x routable interrupts: modules, with quarter of module capacity mapped on CE2 (DSP memory o Up to three C6x interrupts can be region starting at 0xA0000000), and the second quarter mapped on CE3 (DSP routed for basic communication and DMA synchronization. memory region starting at 0xB000000). o Host accessible while DSP is active, with o Up to two C6x interrupts can be routed to expansion connectors. multiple communication options. • Boot memory: o 512kx8 SRAM or 2Mx8 Flash memory. o Configured as Dual Access memory: Accessible by host (only while DSP is inactive/reset) for downloading COFF files. Accessed by DSP during its boot loading process. o Mapped on CE1 (DSP memory region starting at 0x90000000). ©Copyright 2007 Sheldon Instruments Incorporated. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. Peripheral Expansion: Software: • Two 2mm socket connectors, and one external 100 pin half pitch DSUB connector: • Win98/2000/XP and Linux driver support. • Extensive QuVIEW DSP-resident libraries for o DSP Expansion: First external 2mm pitch, LabVIEW, including examples for real time 5x30 (150 contacts) socket connector for acquisition, signal processing, and control. interfacing the expansion board to the DSP's • Extensive QuBASE DSP-resident libraries for bus, or linking to all of the DSP's peripheral Visual Basic, including examples for real time ports (McBSP, McASP, HPI/GPIO, Timers). acquisition, control and analysis. o User I/O: Second external 2mm pitch, 4x30 • Sample code for COFF loaders, PC <-> DSP (120 contacts) socket connector for communications source code and SI-DDK. interfacing external user defined signals to custom daughter board. Linked only to • Compatible with separately purchased TI externally accessible 100 pin half pitch debuggers, C/C++ compilers, assemblers and DSUB connector. linkers. o External 100 pin, half pitch (0.050"), Series III DSUB connector for interfacing external Physical Dimensions & Electrical user defined signals to the 2mm User I/O Requirements: connector. AMP part 787169-9, 787170-9, or 787362-9. • 3U size cPCI/PXI bus card measuring 160mm(L) x 100mm(H). • DSP Expansion 2mm connector decodes 64Kx32 words, mapped into the DSP's EMIF bus, which • 0.31lbs or 140 grams. contains the following signals: • Supply Voltages: 3.3V for all circuitry, and 5V o Address: A15-A0 (DWord Boundary). for expansion bus buffers; 3V expansion buffers o Data: D31-D0. may be placed on special request. +/-12V supplies passed on to expansion connector. o Control: X_R/Wn, X_CSn, X_INT[1:0] (software routable to DSP's • 4.5 watts (3.3V @ 1.5A) typical with 128MB EXTINT[7:4]), X_RDY, X_CLK[1:0]. SDRAM. o Peripheral Port: McBSP[1:0], HPI/GPIO, TINP[1:0], TOUT[1:0]. Ordering Information: o Host +3.3Vdc, +5Vdc, +/-12Vdc, +1.8Vdc & GND. • SI-C6713DSP-cPCI: • Two 2mm pitch, 2x5 (10 contacts) headers: o SI-C6713DSP-cPCI-64. McBSP0 and McBSP1. o SI-C6713DSP-cPCI-128. o SI-C6713DSP-cPCI-256. • One 14 pin header for JTAG port. Contact Information Sheldon Instruments 10393 San Diego Mission Rd. - Suite 202 San Diego, CA 92108-2176 USA Tel (619) 282-6700 Fax (619) 282-6710 Email info@sheldoninst.com Web www.sheldoninst.com ©Copyright 2007 Sheldon Instruments Incorporated. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies.