SEMTECH SC561

SC561 Dual Output Low Noise LDO Linear Regulator POWER MANAGEMENT Features Description The SC561 is a dual output, ultra-low dropout linear „ Input voltage range — 2.5V to 5.5V voltage regulator designed for use in battery powered „ Output voltage — V = 3.1V; V = 2.85V LDOA LDOB applications. The SC561 provides fi xed output voltages of „ Maximum output current — 300mA (each LDO) V = 3.1V and V = 2.85V, and up to 300mA of load „ Dropout at 200mA load — 200mV max. LDOA LDOB current per channel. „ Quiescent supply current — 40μA (both LDOs enabled) In applications where maximum battery life is essential, „ Shutdown current — 100nA (typ) the SC561 can operate in an extremely low power state by „ Output noise < 50μV RMS setting the dynamic bias control. At very light loads, the „ PSRR >65dB at 1kHz LOAD pin can be pulled low so that the device consumes „ Over-temperature protection only 40μA of quiescent current. „ Short-circuit protection „ Under-voltage lockout The SC561 provides superior low-noise performance by „ Power good monitor for output A using an external bypass capacitor to fi lter the bandgap „ MLPQ-UT8, 1.5mm x 1.5mm x 0.6mm package reference. The device also has a PGOOD output to hold a processor in reset when the voltage on OUTA is not in Applications regulation. „ PDAs and cellular phones The device provides protection circuitry such as short- „ GPS devices circuit protection, under-voltage lockout, and thermal „ Palmtop computers and handheld instruments protection to prevent device failures. Stability is main- „ TFT/LCD applications tained by using 1μF capacitors on the output pins. The „ Wireless handsets MLPQ-UT8 package and small ceramic bypass capacitors „ Digital cordless phones and PCS phones minimize the required PCB area. „ Personal communicators „ Wireless LAN Typical Application Circuit SC561 PGOOD VIN IN PGOOD OUTA EN OUTA EN OUTB LOAD OUTB LOAD C IN C C C BYP OUTA OUTB BYP GND 2.2μF 1μF 22nF 1μF November 21, 2007 1 SC561 Pin Confi guration Ordering Information Device Package (1)(2) SC561ULTRT MLPQ-UT8 1.5×1.5 PGOOD SC561EVB Evaluation Board 8 Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. OUTB 1 BYP 7 (2) Lead-free package only. Device is WEEE and RoHS compliant. TOP VIEW IN 2 6 EN 3 OUTA GND 5 4 LOAD MLPQ-UT-8; 1.5x1.5, 8 LEAD θ = 157°C/W JA Voltage Options Marking Information Output Voltage Part Options Device Number Code V V LDOA LDOB SC561 3.1 2.85 0V nn yw nn = Part No. Code — See the Voltage Options Table for details yw = Datecode — See package marking design guidelines document #ALOW-693AQX 2 SC561 Absolute Maximum Ratings Recommended Operating Conditions IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 Ambient Temperature Range (°C) . . . . . . . . . -40 < T < +85 A EN, LOAD(V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V + 0.3) V (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 to 5.5 IN IN PGOOD (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V + 0.3) IN Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (V + 0.3) IN OUTA, OUTB, Short Circuit Duration . . . . . . . . Continuous (1) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal Information (2) Thermal Resistance, Junction to Ambient (°C/W) . . . 157 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260 Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted V = 3.6V, C = 2.2μF, C = C = 1μF, V = V = V , T = -40 to +85°C. Typical values are at T = 25°C. All specifi ca- IN IN OUTA OUTB EN LOAD IN A A tions apply to both LDOs unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Input Supply Voltage Range V 2.5 5.5 V IN V 3.1 OUTA Output Voltage V V 2.85 OUTB V = 2.5V to 5.5V, I = 0 to 300mA, IN OUTx Output Voltage Accuracy ΔV -3 3 % OUTx V ≥ V + 0.3 IN OUTx Maximum Output Current I Each LDO 300 mA MAX I = 250mA, V = 2.5V to 3.3V 150 250 mV OUTx OUTx (1) Dropout Voltage V D I = 50mA, V = 2.5V to 3.3V 50 100 mV OUTx OUTx Shutdown Current I T = 25°C 0.1 1 μA SD A I = I = 0mA, LOAD = V 55 85 μA OUTA OUTB IN Quiescent Current I Q I = I = 1mA, LOAD = 0V 40 60 μA OUTA OUTB Load Regulation ΔV I = 1mA to I 20 mV LOAD OUTx MAX Line Regulation ΔV I = 1mA -6 6 mV LINE OUTx 3 SC561 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Current Limit I 350 850 mA LIMx I = 50mA , OUTx (2) Noise e 50 100 μV N RMS 10Hz < f < 100kHz, C = 22nF BYP Power Supply Rejection I = 50mA, f = 1kHz, OUTx (2) PSRR 50 65 dB Ratio C = 22nF BYP PGOOD Delay t 160 200 240 ms DELAY Percentage of nominal output, PGOOD Threshold V 82 87 92 % TH-PGOOD V falling OUTA PGOOD Threshold Hysteresis V 3% PGOOD-HYS From OFF to 87% V , I = 50mA, OUTx OUTx Start-Up Time t 1ms SU C = 22nF BYP Under Voltage Lockout V V Rising 2.20 2.30 2.40 V UVLO IN UVLO Hysteresis V 100 mV UVLO-HYS Over Temperature Protection T Temperature Rising 160 °C (3) OT Threshold Over Temperature Threshold V 20 °C OT-HYS Hysteresis Digital Inputs Logic Input High Threshold V V = 5.5V 1.25 V IH IN Logic Input Low Threshold V V = 2.5V 0.4 V IL IN Logic Input High Current I V = 5.5V 1 μA IH IN Logic Input Low Current I V = 5.5V 1 μA IL IN Digital Outputs PGOOD Output voltage Low V I = 500μA,V =3.7V 7 20 mV OL SINK IN Notes: (1) Dropout voltage is defi ned as V - V , when V is 100mV below the value of V at V = V + 0.5V. IN OUTx OUTx OUTx IN OUTx (2) Guaranteed by design (3) Thermal shutdown latches both LDOs off . Cycle EN or VIN pin to reset. 4 SC561 Typical Characteristics Load Regulation (LDOA) Load Regulation (LDOB) V = 3.1V, V = 3.6V V = 2.85V, V = 3.6V OUTA IN OUTB IN 8 8 7 7 6 6 5 5 T =85°C A 4 4 T =25°C T =25°C A A TA=85°C 3 3 2 2 1 T =-40°C 1 A T =-40°C A 0 0 0 50 100 150 200 250 300 0 50 100 150 200 250 300 Output Current (mA) Output Current (mA) Line Regulation (LDOA) Line Regulation (LDOB) V = 2.85V, I = 1mA V = 3.1V, I = 1mA OUTB OUTB OUTA OUTA 3 3 2.5 2.5 2 2 1.5 1.5 1 1 T =85°C A T =25°C A TA=85°C T =25°C A 0.5 0.5 0 T =-40°C A 0 T =-40°C A -0.5 -0.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Input Voltage (V) Input Voltage (V) Dropout Voltage (LDOA) Dropout Voltage (LDOB) V = 2.85V, I = 250mA V = 3.1V, I = 250mA OUTB OUTB OUTA OUTA 350 350 300 300 250 250 T =85°C A T =85°C A 200 200 T =25°C A 150 150 T =-40°C A T =25°C T =-40°C A A 100 100 50 50 0 0 2.8 2.85 2.9 2.95 3 3.05 3.1 3.1 3.15 3.2 3.25 3.3 3.35 3.4 Input Voltage (V) Input Voltage (V) 5 VIN - VOUT (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) VIN - VOUT (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) SC561 Typical Characteristics (continued) Dropout Voltage (LDOA) Dropout Voltage (LDOB) V = 2.85V, I = 50mA V = 3.1V, I = 50mA OUTB OUTB OUTA OUTA 350 300 300 250 250 200 200 150 T =-40°C A 150 T =85°C A 100 TA=85°C TA=-40°C 100 T =25°C A 50 50 T =25°C A 0 0 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.1 2.8 2.85 2.9 2.95 33.05 Input Voltage (V) Input Voltage (V) PSRR vs. Frequency (LDOA) PSRR vs. Frequency (LDOB) V = 3.1V, I = 50mA, C = 22nF OUTA OUTA BYP V = 2.85V, I = 50mA, C = 22nF OUTB OUTB BYP 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 10 100 1000 10000 10 100 1000 10000 Frequency (Hz) Frequency (Hz) Output Noise vs. Load Current (LDOA) Output Noise vs. Load Current (LDOB) V = 3.1V, V = 3.6V, C = 22nF OUTA IN BYP VOUTB = 2.85V, VIN = 3.6V, CBYP = 22nF 70 70 60 T =85°C A 60 T =25°C A 50 50 T =85°C A T =-40°C A 40 40 T =25°C A 30 30 T =-40°C A 20 20 10 10 0 0 1 10 100 1000 1 10 100 1000 Output Current (mA) Output Current (mA) 6 VIN - VOUT (mV) Output Voltage Noise (μV) PSRR (dB) VIN - VOUT (mV) Output Voltage Noise (uV) PSRR (dB) SC561 Typical Characteristics (continued) Load Transient Response Rising Edge (Both LDOs) Load Transient Response Falling Edge (Both LDOs) V = 3.6V, V = 3.1V, LOAD = H V = 3.6V, V = 3.1V, LOAD = H IN OUT IN OUT I =1mA to OUT 100mA I =1mA to (50mA/div) OUT 100mA (50mA/div) V V OUT OUT (20mV/div) (20mV/div) Time (50μs/div) Time (50μs/div) Load Transient Response Rising Edge (Both LDOs) Load Transient Response Falling Edge (Both LDOs) V = 3.6V, V = 3.1V, LOAD = H V = 3.6V, V = 3.1V, LOAD = H IN OUT IN OUT I =1mA to OUT I =1mA to OUT 3mA 3mA (50mA/div) (50mA/div) V OUT V OUT (10mV/div) (10mV/div) Time (50μs/div) Time (50μs/div) Load Transient Response Falling Edge (Both LDOs) Load Transient Response Rising Edge (Both LDOs) V = 3.6V, V = 3.1V, LOAD = L IN OUT V = 3.6V, V = 3.1V, LOAD = L IN OUT I =1mA to I =1mA to OUT OUT 3mA 3mA (50mA/div) (50mA/div) V V OUT OUT (10mV/div) (10mV/div) Time (50μs/div) Time (50μs/div) 7 SC561 Pin Confi gurations and Descriptions SC561 Pin Name Pin Function 1 OUTB Output for LDOB 2 VIN Input supply voltage terminal 3 OUTA Output for LDOA Dynamic bias control — pull this pin high for normal operation at all load currents. Pull this pin low for lowest 4LOAD I at loads less than 2mA. This pin is a logic input and cannot be left unconnected. Q 5 GND Analog and digital ground 6 EN Logic input — active HIGH enables both LDOs 7 BYP LDO bypass output — bypass with a 22nF capacitor Power Good open-drain output — monitors the level of LDOA, switches low when the output drops out of 8 PGOOD regulation. Tie to VIN or OUTA via a 100k Ω resistor. Leave fl oating when function is not required. 8 SC561 Block Diagram SC561 7 BYP V IN 8 PGOOD VIN 2 VREF PGOOD UVLO Logic V IN 5 GND OUTA O/T LDOA 3 V IN Power- ON 6 EN Logic LDOB 1 OUTB 4 LOAD 9 SC561 Applications Information General Description Dynamic Bias Control The SC561 is a dual output linear regulator device The LOAD pin provides dynamic bias control which allows intended for applications where low dropout voltage, low the device to be operated in a low quiescent current supply current, and low output noise are critical. The mode at light loads. At loads less than 2mA, the LOAD device provides a simple, low cost solution for two pin should be pulled low in order to force the device into separate regulated outputs. Minimal PCB area is required an ultra-low quiescent current mode. When the load is due to the miniature package size and the need for only increased above 2mA, the LOAD pin should be pulled four external capacitors. high to ensure normal operation. This pin is a logic input, therefore it must never be left unconnected. Figure 2 The linear regulators LDOA and LDOB are powered from shows the quiescent current versus load current with a single input supply rail, and each provides up to 300mA both LDOs enabled. of output current. The SC561 provides output voltages in 1.4 the range 1.2V to 3.3V. Available voltage values are shown in the Voltage Options table on page 2. 1.2 1 Power On Control The SC561 device has a single enable pin (EN) that controls 0.8 both LDO outputs. Pulling this pin low causes the device 0.6 to enter a low power shutdown mode where it typically draws 100nA from the input supply. 0.4 The outputs of both LDOA and LDOB are enabled when 0.2 LOAD = H EN transitions high. When the output voltage of LDOA 0 reaches 87% of its regulation point, the delay timer starts 0.01 0.1 1 10 1000 100 Io (mA) and the PGOOD signal transitions high after a delay of 200ms. The power up/down sequence is shown in the Figure 2a - Quiescent Current versus Output Current timing diagram in Figure 1. 0.2 0.18 0.16 EN 0.14 t SU 87% 87% 0.12 OUTA 200ms 0.1 0.08 PGOOD 0.06 LOAD = L 0.04 0.02 OUTB 0 Figure 1 — Timing Diagram 0.01 0.1 1 10 100 1000 Io (mA) As PGOOD is an open-drain output, it can be left uncon- Figure 2b - Quiescent Current versus Output Current nected when it is not in use without affecting the performance of the device. 10 Iq (mA) Iq (mA) SC561 Applications Information (continued) Protection Features Short-Circuit Protection The SC561 provides protection features to ensure that no Each output has short-circuit protection. If the output damage is incurred in the event of a fault condition. These current exceeds the current limit, the output voltage will functions include: drop and the output current will be limited until the load current returns to a specifi ed level. • Under-Voltage Lockout • Over-Temperature Protection Component Selection • Short-Circuit Protection A minimum capacitance of 1μF on each output is required to ensure stability. This must be considered when Under-Voltage Lockout choosing very small size capacitors as the dc bias must The Under-Voltage Lockout (UVLO) circuit protects the be included in their derating to ensure this required value. device from operating in an unknown state if the input For example, a 1μF 0402 size capacitor may work at low voltage supply is too low. output voltages, but the capacitance may be too low at higher output voltages. Although there is no maximum When the V drops below the UVLO threshold, as defi ned IN value of output capacitor specifi ed, very large values may in the Electrical Characteristics section, the LDOs are increase the rise time of the output voltages without disabled and PGOOD is held low. The LDOs are re-enabled aff ecting stability. It is recommended that the value of into their previous states when VIN is increased above the output capacitance be restricted to a maximum of 10μF. hysteresis level. When powering up with V below the IN Ceramic capacitors of type X5R or X7R should be used UVLO threshold, the LDOs remain disabled and PGOOD is because of their low ESR and stable temperature held low. coefficients. It is also recommended that the input be bypassed with a 2.2μF, low ESR X5R or X7R capacitor to Over-Temperature Protection minimize noise and improve transient response. Note: An internal Over-Temperature (OT) protection circuit is Tantalum and Y5V capacitors are not recommended. provided that monitors the internal junction temperature. When the temperature exceeds the OT threshold as The BYP pin on the SC561 must have a minimum of 22nF defi ned in the Electrical Characteristics section, the OT connected to ground to meet all noise-sensitive require- protection disables both LDO outputs and holds the ments. This value can be increased to a maximum of 1μF PGOOD signal low. The LDOs can only be re-enabled by to improve noise and PSRR. However, larger values of cycling the EN pin. bypass capacitor will increase the start-up time of the SC561. 11 Maximum Recommended Input Voltage SC561 Applications Information (continued) Thermal Considerations known operating conditions using the following Although each of the two LDOs in the SC561 can provide equation: 300mA of output current, the maximum power dissipation T = T +(P x θ ) in the device is restricted by the miniature package size. J A D JA The graphs in Figures 3 and 4 can be used as a guideline where to determine whether the input voltage, output voltages, output currents, and ambient temperature of the system T = Junction Temperature (°C) J result in power dissipation within the operating limits are met or if further thermal relief is required. T = Ambient Temperature (°C) A 0.7 P = Power Dissipation (W) D 0.6 θ = Thermal Resistance Junction to Ambient (°C/W) JA 0.5 Example 0.4 A SC561 is used to provide outputs of 3.1V, 150mA from LDOA and 2.85V, 250mA from LDOB. The input voltage is 0.3 4.2V, and the ambient temperature of the system is 40°C. 0.2 P = 0.15(4.2 – 3.1) + 0.25(4.2 – 2.85) D 0.1 ______ T =+25°C, P = 0.8W A D(MAX) - - - - T =+85°C, P = 0.41W A D(MAX) 0 = 0.503W 33.5 4 4.5 5 5.5 6 Input Voltage (V) and Figure 3 — Safe Operating Limit T = 40 + (0.503 x 157) = 118.9°C J 1.6 1.4 Figure 4 shows that the junction temperature would be within the maximum specifi cation of 150°C for this power 1.2 dissipation. This means that operation of the SC561 under 1 these conditions is within the specified limits and the TJ(Max)=150°C 0.8 device would not require further thermal relief measures. 0.6 T (Max)=125°C J 0.4 0.2 0 -40 -20 0 20 40 60 80 100 o Ambient Temperature ( C) Figure 4 — Maximum P vs. T D A The following procedure can be followed to determine if the thermal design of the system is adequate. The junc- tion temperature of the SC561 can be determined in 12 Maximum Power Dissipation (W) Maximum Total Output Current (A) SC561 Applications Information (continued) Layout Considerations • Place the input, output, and bypass capacitors While layout for linear devices is generally not as critical close to the device for optimal transient as for a switching application, careful attention to detail response and device behavior. will ensure reliable operation. The diagram below illus- • Connect all ground connections directly to the trates proper layout of a circuit. ground plane whenever possible to minimize ground potential diff erences on the PCB. • Attach the part to a large copper footprint, to enable better heat transfer from the device on PCBs where there are internal power and ground planes. C OUTB SC561 C IN C BYP C OUTA Scale = 20:1 (20mm = 1mm) Layer 1 Layer 2 Via between Layer 1 and Layer 2 13 SC561 Outline Drawing — MLPQ-UT8 D A B DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .020 .024 0.50 0.60 - - A1 .000 .002 0.00 0.05 A2 (.006) (0.1524) PIN 1 E b .006 .008 .010 0.15 0.20 0.25 INDICATOR D .059 BSC 1.50 BSC (LASER MARK) E .059 BSC 1.50 BSC e .016 BSC 0.40 BSC L 0.12 .014 0.16 0.30 0.35 0.40 N 8 8 aaa .004 0.10 bbb .004 0.10 A2 A SEATING aaa C PLANE C A1 LxN e 2 0.20 1 0.25 N bxN bbb C A B 0.17 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 14 SC561 Land Pattern — MLPQ-UT8 Z DIMENSIONS G DIM INCHES MILLIMETERS C (.057) (1.45) G 0.70 .028 P .016 0.40 P (Z) (G) 2X (C) R .004 0.10 X .008 0.20 Y .030 0.75 Z .087 2.20 X R Y NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 15