SEMTECH SC508

SC508/SC508A ® EcoSpeed DC-DC Buck Controller with Integrated LDO POWER MANAGEMENT Features Description  Power system ® The SC508/SC508A is a synchronous EcoSpeed buck reg- • Input voltage — 4.5V to 46V ulator which incorporates Semtech’s advanced, patented • Integrated bootstrap switch adaptive `on-time control architecture to provide excel- • Fixed 5V LDO output — 200mA lent light-load efficiency and fast transient response. It • 1% reference tolerance -40 to +85 °C features an integrated bootstrap switch and a fixed 5V • Selectable internal/external bias power supply LDO in a 3 x 3(mm) package. The device is highly efficient ® • EcoSpeed architecture with pseudo-fixed fre- and uses minimal PCB area. The SC508A is available for quency adaptive on-time control automotive applications and is qualified to AEC-Q100.  Logic input and output control • Independent control EN for LDO and switcher The SC508 supports using standard capacitor types such as • Programmable soft-start time electrolytic or special polymer, in addition to ceramic, at switch- • Programmable V UVLO threshold IN ing frequencies up to 1MHz. The programmable frequency, • Power Good output • Selectable power-save mode synchronous operation, and programmable power-save • Programmable ultrasonic power-save mode provide high efficiency operation over a wide load range.  Protections Additional features include cycle-by-cycle current limit, • Automatic restart on fault shutdown • Over-voltage and under-voltage programmable soft-start, under and over-voltage protec- • TC compensated R sensed current limit tion, programmable over-current protection, start-up into DS(ON) • Thermal shutdown pre-biased output, automatic fault recovery (hiccup restart), • Smart power-save soft-shutdown, selectable power-save modes, and pro- • Pre-bias start-up grammable ultrasonic power-save. The device also provides  Capacitor types: SP, POSCAP, OSCON, and ceramic separate enable inputs for the PWM controller and LDO as  Package — 3 x 3(mm), 20-pin MLPQ well as a power good output for the PWM controller. Output  Lead-free and halogen-free voltage range is 0.6 to 5V, with output voltages greater than  RoHS and WEEE compliant 5V supported using additional components.  AEC-Q100 Qualified available in SC508A The input voltage can range from 5V to 46V. The wide Applications input voltage range, programmable frequency, and inte- grated 5V LDO make the device extremely flexible and  Office automation and computing easy to use in a broad range of applications. Support is  Networking and telecommunication equipment provided for multi-cell battery systems in addition to tra-  Point-of-load power supplies and module replacement ditional DC power supply applications.  Automotive applications Typical Application Circuit VEXT or VLDO VIN VIN PGOOD PGOOD SC508 CIN ENABLE EN DH SC508A ENL ENABLE LDO LX RTON VOUT L1 TON 3.3O + COUT BST VDDA ILIM VEXT or VLDO VDDP RLIM 0.1µF 1µF DL VLDO VOUT VLDO SS 1µF 10nF FB PSV AGND PGND PSV © 2011 Semtech Corporation Revision 4.1 1 SC508/SC508A Pin Configuration Ordering Information Device Package (1)(2) SC508ULTRT MLPQ-UT20 (1)(2)(3) SC508AULTRT MLPQ-UT20 20 19 18 17 16 SC508EVB Evaluation Board Top View FB 1 15 PGOOD SC508AEVB Evaluation Board 14 PSV VOUT 2 Notes: AGND PAD 1) Available in tape and reel only. A reel contains 3000 devices. VDDA 3 13 VDDP 2) Lead-free packaging only. Device is WEEE and RoHS compliant VLDO 4 12 DL and halogen-free. 3) AEC-Q100 Qualified. 11 PGND VIN 5 6 7 8 9 10 MLPQ-UT20 Marking Information 508 508A yyww yyww xxxx xxxx yyww = Date Code yyww = Date Code xxxx = Semtech Lot Number xxxx = Semtech Lot Number 2 SS ENL TON NC BST AGND DH EN LX ILIM SC508/SC508A (1) Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +50 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 46 LX to PGND (V) (transient — 100ns) . . . . . . . . . -2 to +50 VDDA to AGND, VDDP to PGND (V) . . . . . . . . . . . 4.5 to 5.5 (2) DH, BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +55 VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5 Supports output voltages greater than 5.5V using DH, BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 external components DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 Thermal Information VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +50 EN, FB, ILIM, PGOOD to AGND (V) . . . -0.3 to +(VDDA + 0.3) Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150 PSV, SS, TON to AGND (V) . . . . . . . . . . -0.3 to +(VDDA + 0.3) Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150 VLDO, VOUT to AGND (V) . . . . . . . . . . -0.3 to +(VDDA + 0.3) Operating Junction Temperature (°C) . . . . . . . . -40 to +125 TON to AGND (V). . . . . . . . . . . . . . . . . . . -0.3 to +(VDDA -1.5) (3) Thermal resistance, junction to ambient (°C/W) . . . . . . 50 ENL to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260 VDDP to PGND, VDDA to AGND (V) . . . . . . . . . . 0.3 to +6 VDDA to VDDP (V) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +0.3 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +0.3 (1) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) VOUT pin must not exceed (VDDA pin + 0.3V). (3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specified: V =12V, VDDA = VDDP = 5V, T = +25°C for Typ, -40 to +85 °C for Min and Max, T < 125°C, Typical Application Circuit IN A J Parameter Conditions Min Typ Max Units Input Supplies Input Supply Voltage (V ) VDDA = 5V 4.5 46 V IN Sensed at ENL pin, rising edge 1.50 1.56 1.70 (1) V UVLO Threshold V IN Sensed at ENL pin, falling edge 1.45 1.52 1.65 V UVLO Hysteresis Sensed at ENL pin; EN = 5V 0.04 V IN Measured at VDDA pin, rising edge 3.7 3.9 4.1 VDDA UVLO Threshold V Measured at VDDA pin, falling edge 3.5 3.7 3.9 VDDA UVLO Hysteresis 0.2 V Shutdown mode; ENL, EN = 0V, V = 46V 20 35 IN V Supply Current μA IN Standby mode; VDDA, VDDP, ENL = 5V, EN = 0V 130 3 SC508/SC508A Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) ENL , EN = 0V 3 7 μA Power-save operation 0.4 EN = 5V, PSV = open (float), V > 600mV FB (2) VDDA + VDDP Supply Current Ultrasonic Power-save operation 2.4 mA EN = 5V, R = 115kΩ, V > 600mV PSV FB Forced Continuous Mode operation 13 Operating f = 220kHz, PSV = VDDA, no load SW Static V and load, 0 to +85 °C 0.5952 0.600 0.6048 V IN FB Comparator Threshold Static V and load, -40 to +85 °C 0.594 0.606 V IN Frequency Range Continuous mode operation 1000 kHz Timing Forced Continuous Mode operation 1530 1700 1870 ns V = 30V, V = 3 V, R = 600kΩ, VDDA = 5V IN OUT TON On-Time On-time Accuracy; Forced Continuous Mode ±15 % V = 4.5 to 10V, V = 3 V, R = 600kΩ, VDDA = 5V IN OUT TON Minimum On-Time 80 ns Minimum Off-Time 250 ns Ultrasonic Frequency Minimum switching frequency, R = 115kΩ 25 kHz PSV Soft-Start Soft-Start Charge Current 3.0 μA Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero Cross Detector Threshold LX with respect to PGND -3 0 +3 mV Power Good Upper limit, V > internal 600mV reference +20 FB Power Good Threshold % Lower limit, V < internal 600mV reference -10 FB Startup Delay Time EN rising edge to PGOOD rising edge, CSS = 10nF 11 ms Fault (noise immunity) Delay Time 5 µs Leakage PGOOD = high impedance (open) 1 µA Power Good On-Resistance PGOOD = pulled low to AGND 10 Ω 4 SC508/SC508A Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Fault Protection I Source Current 9 10 11 μA LIM I Source Current Temperature Coefficient 0.41 %/°C LIM I Comparator Offset With respect to AGND -8 0 +8 mV LIM V with respect to internal 600mV reference, FB Output Under-Voltage Threshold -25 % 8 consecutive cycles Smart Power-Save Protection Threshold V with respect to internal 600mV reference +10 % FB Over-Voltage Protection Threshold V with respect to internal 600mV reference +20 % FB Over-Voltage Fault Delay 5 μs Over-Temperature Shutdown 10°C hysteresis 165 °C Logic Inputs/Outputs Logic Input High Voltage — EN 1.4 V Forced Continuous Mode operation; Logic Input High Voltage — PSV -0.4 V PSV pin with respect to VDDA (3) Logic Input Low Voltage — EN, ENL With respect to AGND 0.4 V EN Input Bias Current EN = VDDA or AGND -10 +10 μA ENL Input Bias Current V = 46V +11 μA IN FB Input Bias Current FB = VDDA or AGND -1 +1 μA PSV = VDDA 5 16 μA PSV Input Bias Current PSV < 1.5V 1 μA Linear Regulator VLDO Accuracy VLDO load = 10mA 4.875 5.0 5.125 V VLDO < 1V start-up 13 Current Limit 1V < VLDO < 4.5V (typ) 90 mA Operating, VLDO > 4.5V (typ) 200 (4) VLDO to VOUT Switch-over Threshold -130 +130 mV (4) VLDO to VOUT Non-switch-over Threshold -500 +500 mV VLDO to VOUT Switch-over Resistance VLDO = VOUT = 5V 2.0 Ω VLDO Drop Out Voltage V to VLDO, LDO load = 50mA 1.2 V IN 5 SC508/SC508A Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units High-Side Driver (DH, BST, LX) Peak Current VDDP = 5V, DH pin sourcing or sinking 2 A R LX < 0.5V, VDDP = 5V 3.0 6.0 Ω DH_PULL-UP, On Resistance R LX > 0.5V, VDDP = 5V 1.0 2.0 Ω DH_PULL-UP, R VDDP = 5V 0.6 1.2 Ω DH_PULL-DOWN, Rise Time C = 3nF, VDDP = 5V 22 ns DH-LX Fall Time C = 3nF, VDDP = 5V 12 ns DH-LX Propagation Delay From FB Input to DH 45 ns Shoot-thru Protection Delay 45 ns Bootstrap Switch Resistance 16 Ω Low-Side Driver (DL, VDDP, PGND) VDDP = 5V, DL sourcing 2 A Peak Current VDDP = 5V, DL sinking 4 R VDDP = 5V 1.0 2.1 Ω DL_PULL-UP, On Resistance R VDDP = 5V 0.50 0.86 Ω DL_PULL-DOWN, Rise Time C = 3nF, VDDP = 5V 7 ns DL Fall Time C = 3nF, VDDP = 5V 3.5 ns DL Notes: (1) V UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. IN (2) For UPSV and FCM operation, the VDDA and VDDA supply current includes the DH/DL current required to drive the external MOSFETS. (3) The ENL pin will enable the LDO with 0.8V typical. The ENL pin V ULVO function will disable the switcher unless the ENL pin exceeds the V IN IN UVLO Threshold which is typically 1.56V. (4) The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. 6 SC508/SC508A Typical Characteristics (continued) Efficiency vs Load — PSAVE Mode Efficiency vs Load — 5V output V 5V, Internal 5V bias, Power-save, 250kHz Frequency V 1.8V, External 5V bias, 220kHz Frequency OUT OUT 100 100 42V 90 90 42V 15V 28V 80 80 15V 28V 70 70 60 60 50 50 40 40 Inductor: Cyntec PCMB104E-4R7MS 30 30 High side MOSFET: Alpha Omega AO4440 Low side MOSFET: Fairchild FMDS5352 20 20 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 I (ADC) OUT I (ADC) OUT Efficiency vs Load — 12V output Efficiency vs Load — Ultrasonic PSAVE Mode V 12V, External 5V bias, Power-save, 400kHz Frequency V 1.8V, External 5V bias, 220kHz Frequency OUT OUT 100 100 28V 90 90 42V 42V 80 80 15V 28V 70 70 60 60 50 50 40 40 Inductor: Cyntec PCMB104E-4R7MS 30 High side MOSFET: Fairchild FMDS5352 30 Low side MOSFET: Fairchild FMDS5352 20 20 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 I (ADC) I (ADC) OUT OUT Efficiency vs Load — Forced Continuous Mode Load Regulation V 1.8V, External 5V bias, 220kHz Frequency V 1.8V, External 5V bias, 220kHz Frequency OUT OUT 1.85 100 42 V IN 1.84 PSAVE 90 42V 1.83 80 28V 15V 1.82 28 V 15 VIN IN 70 1.81 UPSAVE FCM 60 1.80 1.79 50 1.78 40 1.77 30 1.76 20 1.75 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 IOUT (ADC) IOUT (ADC) 7 Efficiency (%) Efficiency (%) Efficiency (%) V (V) OUT Efficiency (%) Efficiency (%) SC508/SC508A Typical Characteristics (continued) Start-up — EN Input Pre-Bias Start- up — EN Input V = 42V, V = 1.8V, I = 0A, PSAVE V = 42V, V = 1.8V, I = 0A, PSAVE IN OUT OUT IN OUT OUT EN (5V/div) EN (5V/div) V (1V/div) OUT V (1V/div) OUT PGOOD (5V/div) PGOOD (5V/div) LX (50V/div) LX (50V/div) Time (1m��� ��� ��iii�� �� �� Time (1m��� ��� ��iii�� �� �� Start-up — SS ramp-up Shutdown — EN Input V = 42V, V = 1.8V, I = 0A, PSAVE, startup using EN input V = 5V, V = 1.8V, I = 1A, PSAVE IN OUT OUT IN OUT OUT ENL (5V/div) SS (5V/div) V (1V/div) OUT V (1V/div) PGOOD (5V/div) OUT PGOOD (5V/div) LX (50V/div) LX (50V/div) Time (1m��� ��� ��iii�� �� �� Time (1m��� ��� ��iii�� �� �� Start-up, Shutdown — ENL Input (V UVLO) Over-current — Automatic Restart IN V = 42V, V = 1.8V, I = 1A, PSAVE V = 42V, V = 1.8V, External load = 15A IN OUT OUT IN OUT SS (5V/div) ENL (5V/div) V (1V/div) OUT V (1V/div) OUT I (10A/div) OUT PGOOD (5V/div) LX (50V/div) LX (50V/div) Time (20m��� ��� ��iii�� �� �� Time (4m��� ��� ��iii�� �� �� 8 SC508/SC508A Typical Characteristics (continued) Switching — PSAVE Transient Response — PSAVE V = 42V, V = 1.8V, I = 0A V = 42V, V = 1.8V, I = 0A to 8A to 0A IN OUT OUT IN OUT OUT V (50mV/div) OUT V (50mV/div) OUT DL (5V/div) I (5AV/div) OUT LX (50V/div) LX (50V/div) Time (10m��� ��� ��iii�� �� �� Time (100µ��� ��� ��iii�� �� �� Switching — UPSAVE Transient Response — UPSAVE V = 42V, V = 1.8V, I = 0A V = 42V, V = 1.8V, I = 0A to 8A to 0A IN OUT OUT IN OUT OUT V (50mV/div) V (50mV/div) OUT OUT DL (5V/div) I (5A/div) OUT LX (50V/div) LX (50V/div) Time (20μ��� ��ii�� �� Time (100μ��� ��ii�� �� Switching — FCM Transient Response — FCM V = 42V, V = 1.8V, I = 0A V = 42V, V = 1.8V, I = 0A to 8A to 0A IN OUT OUT IN OUT OUT V (50mV/div) OUT V (50mV/div) OUT DL (5V/div) I (5A/div) OUT LX (50V/div) LX (50V/div) Time (100μ��� ��ii�� �� Time (4μ��� ��ii�� �� 9 SC508/SC508A Detailed Application Circuit ENABLE LDO EN PGOOD RTON 154kW 5V 20 19 18 17 16 PAD 1µF 1 15 FB PGOOD 2 14 VOUT PSV 5V (1) (1) 3 13 VDDA SC508 VDDP RLIM 6.81kW VIN 4 12 VLDO DL (2) 1µF 100nF RPSV 5 VLDO 11 VIN PGND 6 7 8 9 10 Q1 VIN RBST CIN2 CIN1 3.3W CSS 100nF 3.9nF CBST Q2 100nF L1 36V to 1.8V @ 8A VOUT CTOP* RTOP COUT 1µF + 20kW np RBOT 10kW Key Component� Component Value Manufacturer Part Number Web CIN1, CIN2 10µF/50V Murata GRM32ER71H106KA12L www.murata.com 2TPF330M6 COUT 330µF/6mW Sanyo www.panasonic.com L1 1.8µH IHLP4040EZER1R8M01 www.vishay.com Vishay Q1 AO4440 Alpha Omega AO4440 www.aosmd.com FDMS5352 Fairchild FDMS5352 www.fairchildsemi.com Q2 Notes: (1) 5V: Connect VDDA and VDDP to external 5V supply for external bias. Connect VDDA and VDDP to VLDO for self -biased operation. (2) RPSV: Use 115kW for Ultrasonic operation. Remove RPSV for Power-Save operation. Connect PSV pin to VDDA for Forced Continuous Mode operation. 10 SS ENL N/C TON BST AGND DH EN LX ILIM SC508/SC508A Pin Descriptions Pin # Pin Name Pin Function Feedback input for switching regulator — connect to an external resistor divider from output — used to pro- 1 FB gram the output voltage. Switcher output voltage sense pin — also the input to the internal switch-over MOSFET between VOUT and VLDO. The voltage at this pin must not exceed the VDDA pin. For output voltages up to 5V connect this pin 2 VOUT directly to the switcher output. For output voltages exceeding 5V connect this pin to the switcher output through a resistor divider. Supply input for internal analog circuits — connect to external 5V supply or connect to VLDO — also the 3 VDDA sense input for VDDA Under Voltage Lockout (VDDA UVLO). 4 VLDO Output of the 5V LDO — The voltage at this pin must not exceed the voltage at the VDDA pin. Input supply voltage — connect to the same supply used for the high-side MOSFET. Connect a 100nF capaci- 5 VIN tor from this pin to AGND to filter high frequency noise. 6 SS Soft-Start — connect tan external capacitor to AGND to program the soft start and automatic recovery time. 7 NC No Connection Bootstrap pin — connect a 100nF minimum capacitor and series resistor from BST to LX to develop the float- 8 BST ing voltage for the high-side gate drive. A 3.3 ohm resistor is recommended. 9 DH High-side gate drive output 10 LX Switching (phase) node 11 PGND Power ground for the DL and DH drivers and the low-side external MOSFET. 12 DL Low-side gate drive output 13 VDDP 5V supply input for the DH and DL gate drives — connect to the same 5V supply used for VDDA. Power-save programming input — connect a resistor to AGND to set a minimum (ultrasonic) power-save fre- 14 PSV quency — float pin to select power-save with no minimum frequency — pull up to VDDA to disable power- save and select forced continuous mode. Open-drain Power Good indicator — high impedance indicates the switching regulator output is good. An 15 PGOOD external pull-up resistor is required. 16 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX. Enable input for switching regulator — logic low disables the switching regulator — logic high enables the 17 EN switching regulator. 18 AGND Analog ground 19 TON ON time programming input — set the on-time by connecting through a resistor to AGND. Enable input for the LDO and VIN UVLO input for the switching regulator — connect ENL to AGND to disable 20 ENL the LDO — drive to logic high (>1.7V) to enable the LDO and inhibit V UVLO — connect to resistor divider IN from VIN to AGND to program the V UVLO threshold. IN PAD AGND Analog ground 11 SC508/SC508A Block Diagram VIN VDDA PGOOD PSV EN VDDP 3 15 14 17 5 13 VDDA VIN VDDP AGND A VDDA UVLO Control & Status Bootstrap Switch 8 BST VDDA Reference DL VIN ULVO 9 DH Soft Start/ SS 6 Automatic Restart 10 LX Gate Drive On-time 1 Control DL FB Generator VDDP FB Comparator 12 DL TON 19 11 PGND Zero Cross Detector 2 VOUT VLDO Switchover Comparator 16 ILIM Current Limit A VIN VLDO 4 Y 5V B LDO VLDO Switchover MUX VIN ULVO To Control & Status detect 20 ENL A = connected to pins 18 and PAD 12 SC508/SC508A Applications Information The adaptive on-time is determined by an internal one- Synchronous Buck Converter shot timer. When the one-shot is triggered by the output The SC508 is a step down synchronous DC-DC buck con- ripple, the device sends a single on-time pulse to the high- troller with an internal 5V LDO. It provides efficient opera- side MOSFET. The pulse period is determined by V and tion in a space saving 3x3 (mm) 20-pin package. The OUT V . The period is proportional to output voltage and programmable operating frequency range up to 1MHz IN inversely proportional to input voltage. With this adaptive enables optimizing the configuration for PCB area and on-time configuration, the device automatically antici- efficiency. For automotive applications, the SC508A is pates the on-time needed to regulate V for the present qualified to AEC-Q100. OUT V condition and at the selected frequency. IN The controller uses a pseudo-fixed frequency adaptive The advantages of adaptive on-time control are: on-time control. This allows fast transient response which permits the use of smaller output capacitors. • Predictable operating frequency compared to other variable frequency methods. Input Voltage Requirements • Reduced component count by eliminating the The SC508 requires two input supplies for normal opera- error amplifier and compensation components. tion: V and VDDA/VDDP. V operates over the wide IN IN • Reduced component count by removing the range of 5V to 46V. VDDA and VDDP require a 5V supply need to sense and control inductor current. which can be from an external source or from the internal • Fast transient response — the response time is LDO. VDDA and VDDP are derived from the same source controlled by a fast comparator instead of a typi- voltage. cally slow error amplifier. • Reduced output capacitance due to fast tran- Psuedo-fixed Frequency Adaptive On-time Control sient response. The PWM control method used by the SC508 is pseudo- fixed frequency, adaptive on-time, as shown in Figure 1. One-Shot Timer and Operating Frequency The ripple voltage generated at the output capacitor ESR One-shot timer operation is shown in Figure 2. The FB is used as a PWM ramp signal. This ripple is used to trigger comparator output goes high when V is less than the FB the on-time of the controller. internal 600mV reference. This feeds into the DH gate drive and turns on the high-side MOSFET, and also starts TON V IN the one-shot timer. The one-shot timer uses an internal V LX comparator and a capacitor. One comparator input is con- nected to V , the other input is connected to the capaci- OUT C IN tor. When the on-time begins, the capacitor charges from Q1 V FB FB Threshold zero volts through a current which is proportional to V . IN V LX When the capacitor voltage reaches V , the on-time is OUT V OUT completed and the high-side MOSFET turns off. L ESR Gate Q2 Drives V IN FB Comparator FB FB - + + Q1 C OUT REF DH V L OUT V LX V OUT ESR FB One-Shot Q2 V IN + DL C OUT Timer Figure 1 — PWM Control Method, V Ripple OUT R TON On-time = K x R x (V /V ) TON OUT IN Figure 2 — On-Time Generation 13 SC508/SC508A Applications Information (continued) V To FB pin OUT This method automatically produces an on-time that is R 1 proportional to V and inversely proportional to V . R OUT IN 2 Under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. V Figure 3 — Output Voltage Selection OUT f SW T uV ON IN Note that this control method regulates the valley of the The SC508 uses an external resistor to set the on-time which output ripple voltage, not the DC value. The DC value of indirectly sets the frequency. The on-time can be pro- V is offset by the output ripple according to the follow- OUT grammed to provide an operating frequency of up to 1MHz ing equation. using a resistor between the TON pin and ground. The resis- tor value is selected by the following equation. § · R § V · 1 RIPPLE V 0.6u¨1 ¸ ¨ ¸ OUT ¨ ¸ R 2 2 © ¹ © ¹ § · 9 287 ¨ QV¸u9 ,1 ¨ ¸ 9 uI 7 QVu9 In some applications a small capacitor CTOP is placed in 21 ,1 © ,1 6: ¹ 5 721 S)u9 S)u9 parallel with R1 to provide a larger ripple signal from VOUT 287 287 to the FB pin. In these applications, the output voltage VOUT is calculated according to the following equation in The maximum recommended R value is shown by the TON which w represents the switching frequency. following equation. 9 ,1B0,1 5  721B0$; § · 5 9 5Ȧ&  § · uȝ$  5,33/(  723 9 u¨ ¸ u ¨ ¸ 287  ¨ ¸ 5  © ¹ © ¹ § · 5 u5   Immediately after the on-time, the DL output drives high ¨ ¸  Ȧ& 723 ¨ ¸ 5 5 ©   ¹ to energize the low-side MOSFET. DL has a minimum high time of ~250ns, after which DL continues to stay high until one of the following occurs: Configuring V Greater Than 5V OUT The switcher output voltage can be programmed higher • The FB input falls below the 600mV reference than 5V with careful attention to the VOUT and RTON pins. • The Zero Cross Detector trips if power-save is In these applications the VOUT pin cannot connect directly active to the switcher output due to its maximum voltage rating. An additional resistor divider network is required to Note that the on-time variation increases to typically 15% connect from the switcher output to the VOUT pin as at input voltages from 4.5 to 10V. In most applications this shown in Figure 4. does not significantly affect overall performance. V Voltage Selection LX L VOUT > 5V OUT R V1 The switcher output voltage is regulated by comparing COUT To VOUT pin V as seen through a resistor divider at the FB pin to the OUT internal 600mV reference voltage (see Figure 3). R V2 Figure 4 — Resistor Divider For V Exceeding 5V OUT 14 SC508/SC508A Applications Information (continued) If the internal LDO is used for bias power, the LDO switch- the maximum recommended resistance between the over function must be inhibited by selecting the resistor VDDA supply and the PSV pin is 40kW. divider so that the voltage at the VOUT pin does not exceed 4V; this will inhibit the VLDO switch-over func- FB Ripple tion. If the SC508 bias power is from an external 5V supply FB threshold Voltage (V ) FB and the LDO is disabled by grounding the ENL pin, the voltage at the VOUT pin is not limited to 4V and can be as high as the VDDA supply voltage. DC Load Current Inductor Current Note that the VOUT pin has an internal 500kW resistor connected to AGND. To minimize the effect of this resistor on the resistor divider ratio, the maximum recommend On-time DH on-time is triggered when value for resistor R in Figure 4 is 10kW. V reaches the FB Threshold. V2 (T ) FB ON In addition to the resistor divider, the RTON resistor value DH must be adjusted. The on-time is calculated according to the voltage at the VOUT pin. In order to select the desired DL on-time and operating frequency, the RTON resistor should be adjusted to a higher value to compensate for DL drives high when on-time is completed. the reduced voltage at the VOUT pin. For output voltages DL remains high until V falls to the FB threshold. FB exceeding 5V, the required RTON value can be determined by the following equation. Figure 5 — Forced Continuous Mode Operation § · 9 287 ¨ ¸ QV u9 ,1 ¨ ¸ 9 uI § 5 · © ,1 6: ¹ 9 ¨ ¸ 5 u  721 ¨ ¸ Programmable Ultrasonic Power-Save Operation S)u9 5 287 © 9¹ The device provides programmable ultrasonic power-save operation at light loads; the minimum operating fre- For applications where V exceeds 5V, FCM operation is OUT quency is programmed by connecting a resistor from PSV recommended. to AGND. The SC508 uses the PSV resistor to set an inter- nal timer that monitors the time between consecutive Forced Continuous Mode Operation high-side gate pulses. If the time exceeds the programmed The SC508 operates the switcher in Forced Continuous timer, DL drives high to turn the low-side MOSFET on. This Mode (FCM) by connecting the PSV pin to VDDA. The PSV draws current from V through the inductor, forcing both pin should never exceed the VDDA supply. See Figure 5 OUT V and V to fall. When V drops to the 600mV thresh- for FCM waveforms. In this mode one of the power OUT FB FB old, the next DH on-time is triggered. After the on-time is MOSFETs is always on, with no intentional dead time other completed the high-side MOSFET is turned off and the than to avoid cross-conduction. This results in more low-side MOSFET turns on, and the internal timer is uniform frequency across the full load range with the restarted. The low-side MOSFET remains on until the trade-off being reduced efficiency at light loads due to inductor current ramps down to zero, at which point the the high-frequency switching of the MOSFETs. low-side MOSFET is turned off. This ends the cycle until V FB again falls below the 600mV threshold, or the internal The PSV pin contains a 5μA current sink to prevent stray timer forces another DL turn-on. leakage current from pulling the PSV pin up to the VDDA supply when the PSV pin is floated to select Power-Save operation. To select Forced Continuous Mode operation, 15 SC508/SC508A Applications Information (continued) Because the period between on-times is limited to a ately exits power-save and returns to forced continuous maximum value, a minimum operating frequency is main- mode. Figure 7 shows power-save operation at light tained. Figure 6 shows ultrasonic power-save operation. loads. Dead time varies minimum frequency according to load FB Ripple FB Ripple Voltage Voltage (V ) FB FB threshold (V ) FB FB threshold Inductor (0A) Inductor Zero (0A) Current Current DH On-time is triggered when On-time On-time (T ) ON V reaches the FB Threshold FB (T ) ON DH DH On-time is triggered when V reaches the FB Threshold. FB DH programmable time-out DL DL After the programmable time-out, DL drives high if V has not reached the FB threshold. FB DL drives high when on-time is completed. DL remains high until inductor current reaches zero. Figure 6 — Ultrasonic Power-Save Operation Figure 7 — Power-Save Operation The equation for determining the R resistor value is PSV Smart Power-Save Protection shown next. The desired minimum frequency is f . SWMIN Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with 1 R PSV power-save enabled, this can force V to slowly rise and 350pFuf OUT SWMIN reach the over-voltage threshold, resulting in an over- voltage shutdown. Smart power-save prevents this condi- Power-Save Mode Operation tion. When the FB voltage exceeds 10% above nominal The device provides power-save operation at light loads (exceeds 660mV), the device immediately disables power- with no minimum operating frequency, selected by float- save and DL drives high to turn on the low-side MOSFET. ing the PSV pin (no connection). In this mode of opera- This draws current from V through the inductor and OUT tion, the zero cross comparator monitors inductor current causes V to fall. When V drops back to the 600mV trip OUT FB via the voltage across the low-side MOSFET during the point, a normal T switching cycle begins. This method ON off-time. If the inductor current falls to zero for 8 consecu- prevents over-voltage shutdown by cycling energy from tive switching cycles, the controller enters power-save V back to V . It also minimizes operating power under OUT IN operation. It will then turn off the low-side MOSFET on light load conditions by avoiding forced continuous mode each subsequent cycle, provided that the current falls to operation. zero. After the low-side MOSFET is off, both high-side and low-sides MOSFETs remain off until V drops to the 600mV Figure 8 shows typical waveforms for the Smart Power- FB threshold. While the MOSFETs are off the load is supplied save feature. by the output capacitor. If the inductor current does not reach zero on any switching cycle, the controller immedi- 16 SC508/SC508A Applications Information (continued) Note that the LDO enable pin (ENL) can also disable the V drifts up to due to leakage OUT current flowing into C V discharges via inductor OUT OUT switching regulator through the V UVLO function. Refer IN and low-side MOSFET Smart Power Save Threshold to the ENL Pin and V UVLO section. IN Normal V ripple OUT FB threshold Current Limit Protection DH and DL off The SC508 features programmable current limiting, which High-side is accomplished using the RDS of the lower MOSFET for (ON) Drive (DH) current sensing. The current limit is set by R resistor LIM Single DH on-time pulse which connects from the ILIM pin to the drain of the low- after DL turn-off side MOSFET. When the low-side MOSFET is on, an internal Low-side 10μA current flows from the ILIM pin and through the R LIM Drive (DL) resistor, creating a voltage drop across the resistor. While DL turns on when Smart Normal DL pulse after DH the low-side MOSFET is on, the inductor current flows PSAVE threshold is reached on-time pulse DL turns off when FB through it and creates a voltage across the RDS . The (ON) threshold is reached voltage across the MOSFET is negative with respect to PGND. If this MOSFET voltage drop exceeds the voltage Figure 8 — Smart Power-Save across R , the voltage at the ILIM pin will be negative and LIM TM current limit will activate. The current limit then keeps the SmartDrive low-side MOSFET on and prevents another high-side on- For each DH pulse, the DH driver initially turns on the time, until the current in the low-side MOSFET reduces high-side MOSFET at a slower speed, allowing a softer, enough to bring the ILIM pin voltage up to zero. This smooth turn-off of the low-side diode. Once the diode is method regulates the inductor valley current at the level off and the LX voltage has risen 0.8V above PGND, the shown by I in Figure 9. SmartDrive circuit automatically drives the high-side LIM MOSFET on at a rapid rate. This technique reduces switch- ing noise while maintaining high efficiency, reducing the I PEAK need for snubbers. I LOAD I Enable Input for Switching Regulator LIM The EN input is a logic level input. When EN is low (grounded), the switching regulator is off and in its lowest power state. When EN is low and VDDA is above the VDDA Time UVLO threshold, the output of the switching regulator soft-discharges into the VOUT pin through an internal Figure 9 — Valley Current Limit 2kΩ resistor. When EN is a logic high (>1V) the switching regulator is enabled. The EN input has internal resistors — 2MΩ pullup to VDDA, and a 1MΩ pulldown to AGND. These resistors will normally cause the EN voltage to be near the logic high trip point as VDDA reaches the VDDA UVLO threshold. To prevent undesired toggling of EN and erratic start-up performance, the EN pin should not be allowed to float as open-circuit. 17 In�uctor Current SC508/SC508A Applications Information (continued) The current limit schematic with the R resistor is shown the soft-start time (t ). The calculation for the soft-start LIM SS in Figure 10. time is shown by the following equation. C u1.5V V IN SS t SS 3PA + CIN BST Q1 After the SS capacitor voltage reaches 1.5V, the SS capaci- C BST V L OUT DH tor continues to charge until the SS voltage is equal to LX 67% of VDDA. At this time the Power Good monitor com- ILIM R LIM pares the FB pin and sets the PGOOD output high (open DL C OUT drain) if VOUT is in regulation. The time between VOUT PGND + D2 Q2 reaching the regulation point and the PGOOD output going high is shown by the following equation. & u9''$ § · 66 W u 9 ¨ ¸ 3*22' Figure 10 — Valley Current Limit ȝ$  © ¹ Setting the valley current limit to 10A results in a peak The time from the rising edge of the EN pin to the PGOOD inductor current of 10A plus peak ripple current. In this output going high is shown by the following equation. situation the average current through the inductor is 10A plus one-half the peak-to-peak ripple current. & u9''$ § · 66 W u ¨ ¸ (1B*22' ȝ$  © ¹ The R value is calculated by the next equation. LIM After the Power Good Start-up Delay Time is completed, 5'6 u, 21 /,0 5 the SS pin is internally pulled up to the VDDA supply. /,0 ȝ$ The soft-start cycle and Power Good timing can be seen in The internal 10μA current source is temperature compen- the Figure 11. sated at 4100ppm in order to provide tracking with the RDS . ON EN V = 3.35V SS Soft-Start of PWM Regulator V = 1.5V SS The SC508 has a programmable soft-start time that is con- CSS charging trolled by an external capacitor at the SS pin. During the current 3uA soft-start time, the controller sources 3μA from the SS pin to charge the capacitor. During the start-up process SS (Figure 11), 40% of the voltage ramp at the SS pin is used as the reference for the FB comparator. The PWM compara- tor issues an on-time pulse when the FB voltage is less VOUT in regulation than 40% of the SS voltage, which forces the output voltage to follow the SS ramp. The output voltage reaches FB regulation when the SS pin voltage exceeds 1.5V and the t t SS PGOOD FB reaches the 600mV threshold. The time between the PGOOD first LX pulse and VOUT reaching the regulation point is Figure 11 — Soft-start Cycle and Power Good timing 18 SC508/SC508A Applications Information (continued) Pre-Bias Start-up Output Under-Voltage Protection SC508 can support soft-start with an output pre-bias. The When V falls 25% below its nominal voltage (falls to FB SS ramp time is the same as a normal start-up when the 450mV) for eight consecutive clock cycles, the switcher is output voltage starts from zero. Under a pre-bias start-up, shut off and the DH and DL drives are pulled low to tri- the DH and DL drivers inhibit switching until 40% of the state the MOSFETs. The controller stays off while the ramp at the SS pin equals the pre-bias FB voltage level. device goes through the automatic fault recovery cycle. Pre-bias start-up is achieved by turning off the lower MOSFET when the inductor current reaches zero during Automatic Fault Recovery the soft-start cycle. This method prevents the output The SC508 includes an automatic recovery feature (hiccup voltage from decreasing. mode upon fault). If the switcher output is shut down due to a fault condition, the device uses the SS capacitor as a Power Good Output timer. Upon fault detection the SS pin is pulled low and The PGOOD (power good) output is an open-drain output then begins charging through the internal 3μA current which requires a pull-up resistor. During start-up, PGOOD source. When the SS capacitor reaches 67% of VDDA, the is held low and is not allowed to transition high until the SS pin is again pulled low, after which the SS capacitor output voltage is in regulation and the SS pin has reached begins another charging cycle. The SS capacitor will be 67% of VDDA. The time from EN going high to PGOOD used for 15 cycles of charging from 0 to 67% of VDDA. going high is typically 11ms for CSS = 10nF. During these cycles the switcher is off and there is no MOSFET switching. When the voltage at the FB pin is 10% below the nominal voltage, PGOOD is pulled low. Once PGOOD pulls low During the 16th SS charging cycle, the normal soft-start there is typically 2% hysteresis to prevent chatter on the routine is implemented and the MOSFETs begin switch- PGOOD output. ing. Switching continues until the Power Good Start-up Delay Time is reached. If the switcher output is still in a PGOOD will transition low if the FB voltage exceeds +20% fault condition, the switcher will again shut down and of nominal (720mV), which is also the over-voltage shut- force 15 cycles of SS charging before attempting another down threshold. PGOOD also pulls low if the EN pin is low soft-start. The long delay between soft-start cycles and VDDA is present. reduces the average power loss in the power components. Output Over-Voltage Protection Over-voltage protection (OVP) becomes active as soon as The automatic recovery timing is shown in Figure 12. the device is enabled. The OVP threshold is set at 600mV 1 soft-start cycle 1 soft-start cycle + 20% (720mV). There is a 5μs delay built into the OVP t t EN_PGOOD EN_PGOOD 15 cycles 15 cycles detector to prevent false transitions. When V exceeds the fault t = 15 x t t = 15 x t HICCUP EN_PGOOD HICCUP EN_PGOOD FB applied OVP threshold, DL is driven high and the low-side MOSFET t EN_PGOOD 67% x VDDA is turned on. DL remains high and the controller remains off while the device goes through the automatic fault SS recovery cycle. When the automatic recovery cycle is completed, the device will attempt a new soft-start cycle. Figure 12 — Automatic Recovery Timing At the start of the soft-start cycle, the DL output will go low for typically 30usec while the controller initializes the If the fault was due to an over-voltage condition, the DL soft-start sequence. PGOOD is also low after an OVP output will remain high during the 15 SS charging cycles. event. For all other faults, the DL output will remain low. In all cases, during the 16th SS charging cycle, DL will drive low for typically 30usec as the controller initializes a soft-start cycle. 19 SC508/SC508A Applications Information (continued) Figure 13 shows the ENL voltage thresholds and their VDDA UVLO and POR effect on LDO and Switcher operation. The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib- its switching and tri-states the DH/DL drivers until VDDA rises above 3.9V. When VDDA exceeds 3.9V, an internal ENL voltage POR (Power-On Reset) resets the fault latch and the soft- LDO on start circuitry and then the SC508 is ready to begin a soft- Switcher on if EN = high start cycle. The switcher will shut off if VDDA falls below 1.56V 3.6V. VDDP does not have UVLO protection. V UVLO hysteresis IN 1.52V LDO Regulator LDO on Switcher off by V UVLO When the LDO is providing bias power to the device, a IN ENL low minimum 0.1μF capacitor referenced to AGND is required, threshold along with a minimum 1μF capacitor referenced to PGND (min 0.4V) LDO off Switcher on if EN = high to filter the gate drive pulses. Refer to the PCB Layout AGND Guidelines section. ENL Pin and V UVLO IN The ENL pin is also used for the V under-voltage lockout IN Figure 13 — ENL Thresholds (V UVLO) for the switcher. The V UVLO voltage is pro- IN IN grammable via a resistor divider at the V , ENL and AGND IN pins. The V UVLO function has a typical threshold of 1.56V ENL Logic Control of PWM Operation IN on the V rising edge. The falling edge threshold is 1.52V. When the ENL input exceeds the V UVLO threshold of IN IN 1.56V, internal logic checks the PGOOD signal. If PGOOD Timing is important when driving ENL with logic and not is high, the switcher is already running and the LDO will using the V UVLO capability. The ENL pin must transition IN start without affecting the switcher. If PGOOD is low, the from high to low within 2 switching cycles to avoid the device disables PWM switching until the LDO output has PWM output turning off. If ENL goes below the V UVLO IN reached 90% of its final value. This delay prevents the threshold and stays above 1V, then the switcher will turn additional current needed by the DH and DL gate drives off but the LDO will remain on. from overloading the LDO at start-up. Note that it is possible to operate the switcher with the LDO Start-up LDO disabled, but the ENL pin must be below the logic Before LDO start-up, the device checks the status of the low threshold (0.4V maximum), otherwise the V UVLO IN following signals to ensure proper operation can be function will disable the switcher. maintained. The next table summarizes the function of the ENL and EN 1. ENL pin pins, with respect to the rising edge of ENL. 2. VLDO output 3. V input voltage IN ENL LDO status Switcher status EN When the ENL pin is high and V voltage is available, the low low, < 0.4V off off IN LDO will begin start-up. During the initial phase when high low, < 0.4V off on V is below 1V, the LDO initiates a current-limited start- LDO low high, < 1.52V on off up (typically 20mA). This protects the LDO from thermal high high, < 1.52V on off damage if the VLDO pin is shorted to ground. As V LDO low high, > 1.56V on off exceeds 1V, the start-up current gradually increases to high high, > 1.56V on on 20 SC508/SC508A Applications Information (continued) 80mA. When V reaches 4.5V, the LDO current limit and if within ±300mV the switch-over occurs and the LDO LDO increases to 200mA and the LDO output rises quickly to is turned off. 5.0V. The LDO start-up profile is shown in Figure 14. Switch-over MOSFET Parasitic Diodes VLDO The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in Figure 15. 5V voltage regulating with Switchover Switchover 4.5V 200mA current limit control MOSFET VLDO VOUT increasing current 1.0V 20mA constant current Parasitic diode Parasitic diode Figure 14 — LDO Start-Up VDDA LDO Switch-Over Operation Figure 15— Switch-over MOSFET Parasitic Diodes The SC508 includes a switch-over function for the LDO. The switch-over function is designed to increase efficiency It is important to prevent forward bias of these diodes. by using the more efficient DC-DC converter to power the The following two conditions must be satisfied in order for IC, avoiding the less efficient LDO regulator when possible. the parasitic diodes to stay off. The switch-over function connects the VLDO pin directly to the VOUT pin through an internal switch. When the • VDDA > V LDO switch-over is complete the LDO is turned off, which • VDDA > V OUT reduces operating power loss. If the LDO output is used to If either V or V is higher than VDDA, the respective bias the SC508, then after switch-over the device is self- LDO OUT diode will turn on and the SC508 operating current will powered from the switching regulator with the LDO then flow through this diode. This has the potential of turned off. damaging the device. After the switcher completes soft-start and the PGOOD delay, the switch-over logic waits for 32 switching cycles Using the Internal LDO to Bias the SC508 before it starts the switch-over. There are two methods of The following steps must be followed when using the completing the switch-over of V to V . internal LDO to bias the device. LDO OUT • Connect VDDA and VDDP to VLDO before In the first method, the LDO is already in regulation when enabling the LDO. the DC-DC converter is enabled. As soon as the PGOOD • During the initial start-up the LDO, when the output goes high, the 32 cycle count is started. The volt- LDO output is less than 1V, the external load ages at the VLDO and VOUT pins are then compared; if the should not exceed 10mA. Above 1V, any exter- two voltages are within ±300mV of each other, the VLDO nal load on VLDO should not exceed 40mA until pin connects to the VOUT pin using an internal switch, the LDO voltage has reached 4.5V. and the LDO is turned off. When the switch-over feature is used and the VDDA/VDDP In the second method, the DC-DC converter is already power comes from the VOUT pin, the EN and ENL inputs running and the LDO is enabled. In this case the 32 cycle must be used carefully. Do not connect the EN pin directly count is started as soon as the LDO reaches 90% of its final to VDDA or another supply voltage. If this is done, driving value. At this time, the VLDO and VOUT pins are compared, 21 SC508/SC508A Applications Information (continued) the ENL pin low (to AGND) will turn off the LDO and the The following parameters define the design. LDO switch-over MOSFET, but the switcher will continue • Nominal output voltage (V ) OUT operating. V will feed into the LDO output and the OUT • Static or DC output tolerance VDDA/VDDP supplies through the internal parasitic diode. • Transient response This can potentially damage the device, and also prevents • Maximum load current (I ) OUT the switcher from shutting off until the VDDA supply drops below the VDDA UVLO threshold. For these applications a There are two values of load current to evaluate — con- dedicated logic signal is required to drive EN low and tinuous load current and peak load current. Continuous disable the switcher. This signal can be combined with load current relates to thermal stresses which drive the the ENL signal if needed, as long as the EN pin does not selection of the inductor and input capacitors. Peak load exceed Absolute Maximum Ratings. current determines instantaneous component stresses and filtering requirements such as inductor saturation, output LDO Usage at Low Input Voltage capacitors, and design of the current limit circuit. Applications requiring steady-state or transient operation at low input voltages (V below 6.5V) may use the internal The following values are used in this design. IN LDO to bias the VDDA/VDDP pins within limitations. There • V = 28V + 10% IN are limitations to both startup and normal operation as • V = 1.8V + 4% OUT explained below. • f = 220kHz SW • Load = 8A maximum When starting up using the internal LDO, switcher opera- tion is inhibited until the LDO output reaches 4.5V. During Frequency Selection this time, the LDO start-up is implemented using a current Selection of the switching frequency requires making a source. At low V it is important to not apply an external IN trade-off between the size and cost of the external filter load to the LDO, in order to allow the LDO output to reach components (inductor and output capacitor) and the the 4.5V threshold and allow switching to begin. power conversion efficiency. Once switching begins, LDO operation transitions from The desired switching frequency is 220kHz. current-source operation to voltage regulation. The minimum operating V is then limited by the RDS of the IN ON A resistor, R is used to program the on-time (indirectly TON internal LDO MOSFET. The current required to power the setting the frequency) using the following equation. SC508 and external MOSFET gates causes a voltage drop from the V pin to the VLDO pin. The VLDO pin must stay IN (T 10ns)uV ON IN R above 4.5V, otherwise the LDO control will revert back to TON 28pFuV OUT current-source operation, causing more voltage drop at To select R , use the maximum value for V , and for T the LDO output. The RDS of the LDO mosfet at low V is TON IN ON ON IN use the value associated with maximum V . typically 24 ohms at 25°C. IN V OUT Design Procedure T ON V uf INMAX SW When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor T = 266 ns at 30.8V , 1.8V , 220kHz ON IN OUT ripple current must be specified. Substituting for R results in the following solution. TON The maximum input voltage (V ) is the highest specified INMAX input voltage. The minimum input voltage ( V ) is deter- R = 156kΩ, use R = 154kΩ INMIN TON TON mined by the lowest input voltage including the voltage drops due to connectors, fuses, switches, and PCB traces. 22 SC508/SC508A Applications Information (continued) Inductor Selection The ripple current under minimum V conditions is also IN In order to determine the inductance, the ripple current checked using the following equations. must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce S)u5 u9 721 287 7 QV QV 21B9,10,1 efficiency. Higher inductor values will reduce the ripple 9 ,10,1 current/voltage and for a given DC resistance are more (V V )uT IN OUT ON efficient. However, larger inductance translates directly I RIPPLE L into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. uQV , $ 5,33/(B9,10,1 ȝ+ The ripple current will also set the boundary for power- save operation. The switching will typically enter power- Capacitor Selection save mode when the load current decreases to 1/2 of the The output capacitors are chosen based on required ESR ripple current. For example, if ripple current is 4A then and capacitance. The maximum ESR requirement is con- Power-save operation will typically start for loads less than trolled by the output ripple requirement and the DC toler- 2A. If ripple current is set at 40% of maximum load current, ance. The output voltage has a DC value that is equal to then power-save will start for loads less than 20% of the valley of the output ripple plus 1/2 of the peak-to-peak maximum current. ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The inductor value is typically selected to provide a ripple current that is between 25% to 60% of the maximum load The design goal is for the output voltage regulation to be current. This provides an optimal trade-off between cost, ±4% under static conditions. The internal 600mV refer- efficiency, and transient performance. ence tolerance is 1%. Allowing 1% tolerance from the FB resistor divider, this allows 2% tolerance due to V ripple. OUT During the DH on-time, voltage across the inductor is Since this 2% error comes from 1/2 of the ripple voltage, (V - V ). The following equation for determining induc- the allowable ripple is 4%, or 72mV for a 1.8V output. IN OUT tance is shown. The maximum ripple current of 4.3A creates a ripple (V V )uT voltage across the ESR. The maximum ESR value allowed IN OUT ON L I is shown by the following equations. RIPPLE In this example the inductor ripple current is set approxi- 9 P9 5,33/( (65 mately equal to 50% of the maximum load current. Thus 0$; , $ 5,33/(0$; ripple current target will be 50% x 8A or 4A. ESR = 16.7 mΩ MAX To find the minimum inductance needed, use the V and IN T values that correspond to V . The output capacitance is chosen to meet transient ON INMAX requirements. A worst-case load release, from maximum uQV load to no load at the exact moment when inductor / ȝ+ $ current is at the peak, determines the required capaci- tance. If the load release is instantaneous (load changes A slightly smaller value of 1.8µH is selected. This will from maximum to zero in < 1µs), the output capacitor increase the maximum I to 4.3A. RIPPLE must absorb all the inductor’s stored energy. This will Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. 23 SC508/SC508A Applications Information (continued) cause a peak voltage on the capacitor according to the Example following equation. dl 2.5A LOAD 2 1 § · dt Ps L¨I  uI ¸ OUT RIPPLEMAX 2 © ¹ COUT MIN 2 2 This would cause the output current to move from 10A to V  V  PEAK OUT zero in 4µs as shown by the following equation. Assuming a peak voltage V of 1.98 (180mV rise upon PEAK load release), and a 8A load release, the required capaci- 10.2 8 1.8PHu  u1Ps tance is shown by the next equation. 1.8 2.5 C 10.2u OUT 2 2u1.981.8 § 1 · 1.8PH 8 u 4.3 ¨ ¸ 2 © ¹ COUT MIN 2 2 C = 198µF OUT 1.98 1.80 Note that C is much smaller in this example, 198µF COUT = 272µF OUT MIN compared to 272µF based on a worst-case load release. To meet the two design criteria of minimum 272µF and If the load release is relatively slow, the output capacitance maximum 16.7mΩ ESR, select a capacitor rated at 330µF can be reduced. At heavy loads during normal switching, and 6mΩ ESR. when the FB pin is above the 600mV reference, the DL output is high and the low-side MOSFET is on. During this It is recommended that an additional small capacitor with time, the voltage across the inductor is approximately a value of 1 to 10µF be placed in parallel with C in order -V . This causes a down-slope or falling di/dt in the OUT OUT to filter high frequency switching noise. inductor. If the load di/dt is not faster than the -di/dt in the inductor, then the inductor current will tend to track Stability Considerations the falling load current. This will reduce the excess induc- Unstable operation is possible with adaptive on-time con- tive energy that must be absorbed by the output capaci- trollers, and usually takes the form of double-pulsing or tor, therefore a smaller capacitance can be used. ESR loop instability. The following can be used to calculate the needed capaci- Double-pulsing occurs due to switching noise seen at the tance for a given dI /dt. Peak inductor current is shown LOAD FB input or because the FB ripple voltage is too low. This by the next equation. causes the FB comparator to trigger prematurely after the 250ns minimum off-time has expired. In extreme cases I = I + 1/2 x I LPK MAX RIPPLEMAX the noise can cause three or more successive on-times. I = 8 + 1/2 x 4.3 = 10.2A Double-pulsing will result in higher ripple voltage at the LPK output, but in most applications it will not affect opera- tion. This form of instability can usually be avoided by dl LOAD RateofchangeofLoadCurrent providing the FB pin with a smooth, clean ripple signal dt that is at least 10mVp-p, which may dictate the need to I = maximum load release = 10A increase the ESR of the output capacitors. It is also impera- MAX tive to provide a proper PCB layout as discussed in the I I Layout Guidelines section. LPK MAX Lu  u dt V dl OUT LOAD C I u OUT LPK Another way to eliminate doubling-pulsing is to add a 2V  V  PK OUT small capacitor across the upper feedback resistor, as shown in Figure 16. This capacitor should be left unpopu- lated unless it can be confirmed that double-pulsing 24 SC508/SC508A Applications Information (continued) quency. The formula for minimum ESR is shown by the exists. Adding the C capacitor will couple more ripple TOP following equation. into FB to help eliminate the problem. An optional con- nection on the PCB should be available for this capacitor. 3 ESR MIN 2uSuC uf OUT sw C TOP Using Ceramic Output Capacitors When using high ESR value capacitors, the feedback voltage ripple lags the phase node voltage by 90 degrees To FB pin V R1 OUT and the converter is easily stabilized. When using ceramic R2 output capacitors, the ESR value is normally too small to meet the above ESR criteria. As a result, the feedback voltage ripple is 180 degrees from the phase node leading to unstable operation. In this application it is necessary to Figure 16 — Capacitor Coupling to FB Pin add a small virtual ESR network that is composed of two capacitors and one resistor, as shown by R , C , and C in NOTE: The C capacitor can moderately affect the DC output volt- L L C TOP age, refer to the section on V voltage selection. Figure 17. OUT ESR loop instability is caused by insufficient ESR. The DCR L details of this stability issue are discussed in the ESR C R L L V L Requirements section. The best method for checking sta- R bility is to apply a zero-to-full load transient and observe 1 C OUT C C the output voltage ripple envelope for overshoot and + D x V IN - ringing. Ringing for more than one cycle after the initial R 2 step is an indication that the ESR should be increased. FB pin One simple way to solve this problem is to add trace resis- tance in the high current output path. A side effect of adding trace resistance is decreased load regulation. Figure 17 — Virtual ESR Ramp Circuit The ripple voltage at FB is a superposition of two voltage ESR Requirements sources: the voltage across C and the output ripple A minimum ESR is required for two reasons. One reason is L voltage. They are defined in the following equations. to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid ,/u'&5Vu/'&5 double-pulsing. 9F / 6u5&  / / The second reason is to prevent instability due to insuffi- ', / cient ESR. The on-time control regulates the valley of the '9 287 &uI 6: output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis- charging during the switching cycle. For most applica- tions the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre- 25 SC508/SC508A Applications Information (continued) Figure 18 shows the equivalent circuit for calculating the switching node similar to the case of using standard high magnitude of the ripple contribution at the FB pin due to C . ESR capacitors. This is illustrated in Figure 20. L FB contribution by V OUT LX output voltage ripple FB R L L C pin C V L FB contribution D x V IN + by C L - C R R DCR L 1 2 Combined FB I L Figure 18 — FB Voltage by CL Voltage Figure 20 — FB voltage in Phaser Diagram The magnitude of the FB ripple contribution due to C is L The magnitude of the feedback ripple voltage, which is shown by the following equation. dominated by the contribution from C , is controlled by L the value of R , R and C . If the corner frequency of (R // 1 2 C 1   R1//R2 uSuC C VFBc Vc u R ) x C is too high, the ripple magnitude at the FB pin will L L 2 C R1//R2uSuC 1 C be smaller, which can lead to double-pulsing. Conversely, if the corner frequency of (R // R ) x C is too low, the ripple 1 2 C Figure 19 shows the equivalent circuit for calculating the magnitude at FB pin will be higher. Since the SC508 regu- magnitude of the ripple contribution due to the output lates to the valley of the ripple voltage at the FB pin, a high voltage ripple. ripple magnitude is undesirable as it significantly impacts the output voltage regulation. As a result, it is desirable to L DCR select a corner frequency for (R // R ) x C to achieve V V 1 2 C OUT OUT enough, but not excessive, ripple magnitude and phase R L V L margin. The component values for R , R , and C should 1 2 C C C L R C R 1 1 be calculated using the following procedure. C C C OUT C OUT Select C (typical 10nF) and R to match with L and DCR L L R R 2 2 time constant using the following equation. FB FB pin pin / 5 / '&5u& / Figure 19 — FB Voltage by Output Voltage Select C by using the following equation. The magnitude of the FB ripple contribution due to output C voltage ripple is shown by the following equation.   & | u & 55 uSuIVZ   5  9)%'9 '9 u 287 287  5 5  The resistor values (R and R ) in the voltage divider circuit 6u& 1 2 & set the V for the switcher. The typical value for C is OUT C from 10pF to 1nF. The purpose of this network is to couple the inductor current ripple information into the feedback voltage such that the feedback voltage has 90 degrees phase lag to the 26 SC508/SC508A Applications Information (continued) Dropout Performance The use of 1% feedback resistors contributes up to 1% The output voltage adjust range for continuous-conduc- error. If tighter DC accuracy is required, 0.1% resistors tion operation is limited by the fixed 250ns (typical) should be used. minimum off-time of the one-shot. When working with The output inductor value may change with current. This low input voltages, the duty-factor limit must be calcu- will change the output ripple and therefore will have a lated using worst-case values for on and off times. minor effect on the DC output voltage. The output ESR The duty-factor limitation is shown by the following also affects the output ripple and thus has a minor effect equation. on the DC output voltage. T ON(MIN) Switching Frequency Variations DUTY T T The switching frequency will vary depending on line and ON(MIN) OFF(MAX) load conditions. The line variations are a result of fixed The inductor resistance and MOSFET on-state voltage propagation delays in the on-time one-shot, as well as drops must be included when performing worst-case unavoidable delays in the external MOSFET switching. As dropout duty-factor calculations. V increases, these factors make the actual DH on-time IN slightly longer than the ideal on-time. The net effect is System DC Accuracy (V Controller) that frequency tends to falls slightly with increasing input OUT Three factors affect V accuracy: the trip point of the FB voltage. OUT error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error The switching frequency also varies with load current as a comparator offset is trimmed so that under static condi- result of the power losses in the MOSFETs and the induc- tions it trips when the feedback pin is 600mV, + 1%. tor. For a conventional PWM constant-frequency con- verter, as load increases the duty cycle also increases The on-time pulse from the SC508 in the design example slightly to compensate for IR and switching losses in the is calculated to give a pseudo-fixed frequency of 220kHz. MOSFETs and inductor. A adaptive on-time converter Some frequency variation with line and load is expected. must also compensate for the same losses by increasing This variation changes the output ripple voltage. Because the effective duty cycle (more time is spent drawing adaptive on-time converters regulate to the valley of the energy from V as losses increase). Because the on-time is IN output ripple, ½ of the output ripple appears as a DC regu- essentially constant for a given V /V combination, to OUT IN lation error. For example, if the output ripple is 50mV with offset the losses the off-time will reduce slightly as load V = 6 volts, then the measured DC output will be 25mV increases. The net effect is that switching frequency IN above the comparator trip point. If the ripple increases to increases slightly with increasing load. 80mV with V = 25V, then the measured DC output will be IN 40mV above the comparator trip. The best way to mini- mize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. 27 SC508/SC508A Applications Information (continued) • Avoid overlapping of the DL trace with LX/DH/ PCB Layout Guidelines BST. This helps reduce transient peaks on the A switch-mode converter requires good PCB layout which gate of the low-side MOSFET during the turn-on is essential to achieving high performance. The following of the high-side MOSFET. guidelines will provide an optimum PCB layout. Low-noise Analog Circuits The device layout recommendations consist of four parts. Low-noise analog circuits are sensitive circuits that are • Grounding for PGND and AGND referenced to AGND. Due to their high impedance and • Power components sensitivity to noise, it is important that these circuits be • Low-noise analog circuits located as far as possible from the switching signals. • Bypass capacitors • Use a plane or solid area for AGND. Place all Grounding for PGND and AGND components connected to AGND above this • A ground plane layer for PGND is recommended area. to minimize the effects of switching noise, resis-  Use short direct traces for the AGND con- nections to all components. tive losses, and to maximize heat removal from  Place vias to the AGND plane directly near the power components. the component pins. • A separate ground plane or island should be used • Proper routing of the V sense trace is essential for AGND and all associated components. The OUT since it feeds into the FB resistor divider. Noise AGND island should avoid overlapping switching on the FB waveform will cause instability and signals on other layers (DH/DL/BST/LX). multiple pulsing. • Connect PGND and AGND together with a zero  Connect the V sense trace directly to ohm resistor or copper trace. Make the connec- OUT the output capacitor or a ceramic bypass tion near the AGND and PGND pins of the IC. capacitor.  Route this trace over to the VOUT pin, care- Power Components fully avoiding all switching signals and • Use short, wide traces between the following power components. power components.  Route this trace in a quiet layer if possible.  Input capacitors and high-side MOSFETs  Route this trace away from the switch-  High-side and Low-side MOSFETs and in- ing traces and components, even if the ductor (LX connection). Use wide copper trace is longer. Avoid shorter trace routing traces to provide high current carrying ca- through the power switching area. pacity and for heat dissipation.  If a bypass capacitor is used at the IC side  Inductor and output capacitors. of the V sense trace, it should be placed OUT  All PGND connections — the input capaci- near the FB resistor divider. tors, low-side MOSFETs, output capacitors, • All components connected to the FB pin must and the PGND pin of the SC508. be located near the pin. The FB traces should be • An inner layer ground plane is recommended. kept small and not routed near any noisy switch- • Each power component requires a short, low ing connections or power components. impedance connection to the PGND plane. • Place the SS capacitor near the SS pin with a • Place vias to the PGND plane directly near the short direct connection to the AGND plane. component pins. • Place the R resistor near the IC. For an accurate LIM • Use short wide traces for the pin connections I current sense connection, route the R trace LIM LIM from the SC508 (LX, DH, DL and BST). Do not directly to the drain of the low-side MOSFET (LX). route these traces near the sensitive low-noise Use an inner routing layer if needed. analog signals (FB, FBL, SS, TON, V ). OUT 28 SC508/SC508A Applications Information (continued) • Place the R resistor near the TON pin. Route TON R to the TON pin and to AGND using short TON traces and avoid all switching signals. Bypass Capacitors The device requires bypass capacitors for the following pins. • VDDA pin with respect to AGND. This 0.1μF minimum capacitor must be placed and routed close to the IC pins, on the same layer as the IC. This capacitor also functions as bypass for the LDO output, since the VDDA and VLDO pins are adjacent. • VDDP with respect to PGND. This 1μF minimum capacitor must be placed and routed close to the IC pins and on the same layer as the IC. • BST pin with respect to LX. This 0.1μF minimum capacitor must be placed near the IC, on either side of the PCB. Use short traces for the routing between the capacitor and the IC. • VIN pin with respect to AGND. This 0.1μF minimum capacitor must be placed and routed close to the IC pins. This capacitor provides noise filtering for the input to the internal LDO. 29 SC508/SC508A Outline Drawing — MLPQ-UT20 3x3 B DIMENSIONS A D INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .020 .024 0.50 0.60 - - A1 .000 .002 0.00 0.05 A2 (.006) (0.1524) PIN 1 E b .006 .008 .010 0.15 0.20 0.25 INDICATOR D .114 .118 .122 2.90 3.00 3.10 (LASER MARK) D1 .061 .067 .071 1.55 1.70 1.80 E .114 .118 .122 2.90 3.00 3.10 E1 .061 .067 .071 1.55 1.70 1.80 e .016 BSC 0.40 BSC L .012 .016 .020 0.30 0.40 0.50 A2 N 20 20 aaa .003 0.08 A bbb .004 0.10 SEATING PLANE aaa C C A1 D1 e LxN E/2 E1 2 1 N D/2 bxN bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3. DAP is 1.90 x 190mm. 30 SC508/SC508A Land Pattern — MLPQ-UT20 3x3 H R DIMENSIONS DIM INCHES MILLIMETERS (.114) (2.90) C G .083 2.10 Z (C) K G H .067 1.70 K .067 1.70 P .016 0.40 R .004 0.10 Y X .008 0.20 .031 0.80 Y X Z .146 3.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. 2. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 31 SC508/SC508A © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse- quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. 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