SEMTECH SC493

SC493 TM EcoSpeed Step-down Controller 2 with I C Interface POWER MANAGEMENT Features Description TM  Input supply voltage range — 3.0V to 28V The SC493 is a synchronous EcoSpeed buck power supply 2  Controller supply voltage range — 3.0V to 5.5V controller. It features an I C interface and a bootstrap switch in  All ceramic solution enabled a space-saving MLPQ 3X3-20 pin package. The SC493 uses 2  I C interface Semtech’s advanced patented adaptive on-time control archi-  Output voltage fine adjust control tecture to provide excellent light load efficiency and fast tran-  Output voltage margining sient response with small external components. 2  Supports dynamic voltage transitions via the I C 2 The I C interface is used to program the output voltage interface offset, the power-on delay time, the soft-start time, the  Programmable power-on delay time and soft-start time TM power save operating mode, and it can enable/disable the  EcoSpeed architecture with pseudo fixed-frequency controller. Additionally, a status register provides informa- adaptive on-time control tion on device state and faults.  Switching frequency programmable up to 1MHz  Selectable power save, including ultrasonic The controller is capable of operating with all ceramic solu-  Non-synchronous start-up into pre-biased loads tions and switching frequencies up to 1MHz. The program-  Over-voltage/under-voltage fault protection mable frequency and selectable power save mode offer the  Smart power save flexibility to optimize the controller for high efficiency and  Power good Output TM small size. The power save mode can be enabled to maximize  Smart drive efficiency over the entire load range (PSAVE), or switched to  Status register monitoring device operation ultrasonic mode to set the minimum frequency to the desired  Ultra-thin package — 3 x 3 x 0.6 (mm), 20 pin MLPQ-UT value (UPSAVE). Power save mode can be disabled for opera-  Lead-free and halogen-free tion in continuous conduction mode at all loads.  WEEE and RoHS compliant Additional features include output voltage margining, Applications cycle-by-cycle current limit, output voltage soft-start, over and under-voltage protection, controller over-tempera-  Printers ture protection, and output voltage soft-shutdown when  Computer peripherals disabled. The SC493 also provides a power good output. Typical Application Circuit VIN VDD Q1 CIN R1 R2 R3 RILIM BST EN EN L CBST LX VOUT PGD PGD SC493 SCL SCL SDA SDA R4 A0 COUT Q2 DL A1 A2 R5 US Patent: 7,714,547 B2 June 10, 2010 © 2010 Semtech Corporation 1 AVDD AGND PVDD FB VIN VOUT DH PGND ILIM SC493 Pin Configuration Ordering Information Device Package (1)(2) SC493ULTRT MLPQ-UT-20 3X3 SC493EVB Evaluation Board 20 19 18 17 16 Notes: VOUT 1 15 PGOOD (1) Available in tape and reel only. A reel contains 3,000 devices. TOP VIEW FB 2 14 PVDD (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen-free. AVDD 3 13 PGND SDA 12 DL 4 PAD 11 NC SCL 5 6 7 8 9 10 MLPQ-UT-20 3X3, 20 LEAD θ =40°C/W JA Marking Information 493 yyww xxxxx yyww = Date Code xxxxx = Semtech Lot No. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 EN AGND VIN A0 DH A1 BST A2 LX ILIM SC493 Absolute Maximum Ratings Recommended Operating Conditions BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Ambient Temperature (°C) . . . . . . . . . . . . . . . . . . . . -40 to +85 BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 Input Voltage VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 LX to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Controller Supply Voltage AVDD, PVDD (V) . . . . .3.0 to 5.5 PVDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Output Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 5.0 VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Thermal Information AVDD to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -65 to +150 All other pins to AGND (V) . . . . . . . . . . . . . -0.3 to AVDD +0.3 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150 (1) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Operating Junction Temperature (°C) . . . . . . . . -40 to +125 (2) Thermal Resistance, Junction to Ambient (°C/W) . . . . 40 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . . .260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5(in.) 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Test Condition (unless otherwise noted): V (1)=5V, V =5V, T = 125°C. Typ. values at 25°C, Min. and Max. at -40°C < T < 85°C, V = 0%. VDD IN J(MAX) A FBadj Parameter Symbol Condition Min Typ Max Units Input Supply (1) VDD Input Voltage VDD 3.0 5.5 V (1) VDD UVLO Threshold VDD VDD rising 2.8 V UVLO (1) VDD UVLO Hysteresis VDD 0.2 V UVLO_HYS Shut down, EN pin = 0V 0.1 2 2 I C Standby, controller disabled 150 µA (1) No switching, PSAVE, FB>0.5V 1000 VDD Supply Current I VDD f = 25kHz, UPSAVE 2 sw mA Operating f = 250kHz, no load 10 sw Switch-mode Controller 2 FB On-Time Threshold V Static VIN and Load, no offset via I C 0.496 0.5 0.504 V VFB_TON Deviation from the ideal on-time to meet On-Time Accuracy t -10 10 % ON the set switching frequency Minimum On Time t 100 ns ON_MIN Minimum Off Time t 250 ns OFF_MIN 3 SC493 Electrical Characteristics (continued) Parameter Symbol Condition Min Typ Max Units Startup 2 Delay before the I C bus and the Power-on (2) Initialization Time t 1 ms INIT delay ramp are enabled Soft-Start Time Accuracy t -20 +20 % SS Power-on Delay Time Accuracy t -20 +20 % DLY Powersave Zero-Crossing Detector Threshold VT V - PGND -3 0 +3 mV ZC LX UPSV mode Frequency f UPSV enabled, UPSV1 = 1, UPSV0 = 1 20 25 30 kHz UPSV Power Good FB with respect to set point, under voltage, PGD Rising Threshold VT 90/120 % PGD_RISE and over voltage FB with respect to set point, under voltage, PGD Falling Threshold VT 80/110 % PGD_FALL and over voltage PGD Leakage ILEAK Device operating, no fault, V =V (1) 1 µA PGD PGD VDD PGD Output Low Voltage V I =3mA 0.4 V PGD_LOW PGD Fault Protection I Source Current I 9 10 11 μA LIM LIM I Temperature Coefficient TC 3000 ppm LIM ILIM I Comparator Offset VOFF -10 0 +10 mV LIM ILIM FB with respect to set point, Output Under-Voltage Fault VT 70 % UV 8 consecutive switching cycles Output Over-Voltage Fault VT 120 % FB with respect to set point rising/ falling OV (2) Over-Voltage Fault Delay t 5 μs DLY_OV (2) Smart Power-save Protection Threshold VT 110 % FB with respect to set point rising SMRTPSV Over-Temperature Shutdown T Rising T 160 °C OT J Over-Temperature Hysteresis T 10 °C OT_HYS Analog Inputs and Outputs Controller enabled 500k V Input Resistance R Ω OUT VOUT Controller disabled/internal load enabled 10 4 SC493 Electrical Characteristics (continued) Parameter Symbol Condition Min Typ Max Units Digital Input Electrical Specifications (A0, A1, A2, EN) V 1.6 V Input High Threshold V (1) = 5.5V IH VDD Input Low Threshold V V (1) = 3.0V 0.4 V IL VDD Input High Current I V (1) = 5.5V -1 +1 μA IH VDD I -1 +1 μA Input Low Current V (1) = 5.5V IL VDD 2 I C Interface 2 2 Interface complies with slave mode I C interface as described by Philips I C specifications version 2.1 dated January, 2000 Digital Input Voltage Low V 0.4 V B-IL Digital Input Voltage High 1.6 V V B-IH SDA Output Low Level I (SDA) ≤ 3mA 0.4 V V DN SDA_LOW Digital Input Current I -0.2 +0.2 μA B-IN Hysteresis of Schmitt Trigger Inputs V 0.1 V HYS Maximum Glitch Pulse t 50 ns SP Rejection I/O Pin Capacitance 10 C pF IN 2 I C Timing Clock Frequency f 400 440 kHz SCL (2) SCL Low Period t 1300 ns LOW (2) SCL High Period t 600 ns HIGH (2) Data Hold Time t 0 ns HD_DAT (2) Data Setup Time t 100 ns SU_DAT Setup Time for Repeated START t 600 ns (2) SU_STA Condition Hold Time for Repeated START t 600 ns (2) HD_STA Condition (2) Setup Time for STOP Condition t 600 ns SU_STO Bus-Free Time Between STOP and START t 1300 ns (2) BUF 5 SC493 Electrical Characteristics (continued) Parameter Symbol Condition Min Typ Max Units Gate Drivers (2) Shoot-Through Protection Delay t DH or DL Rising 30 ns PROT DL Pull-Down Resistance R DL Low 0.3 0.6 Ω DL_DOWN DL Sink Current I V = 2.5V 8.3 A DL_SINK DL DL Pull-Up Resistance R DL High 1 2 Ω DL_UP DL Source Current I V = 2.5V 2.5 A DL_SOURCE DL DH Pull-Down Resistance R DH Low, BST-LX = 5V 0.6 1.2 Ω DH_DOWN DH Sink Current I V = 2.5V 4.2 A DH_SINK DH - LX DH Pull-Up Resistance R DH High, BST-LX = 5V 1 2 Ω DH_UP DH Source Current I V = 2.5V 2.5 A DH_SOURCE DH - LX Note: (1) VDD refers to both AVDD and PVDD (2) Guaranteed by design. 6 SC493 Typical Characteristics Switching Frequency vs. Load — CCM Efficiency vs Load — CCM and PSAVE V = 1.8V, V = 5V, f = 1MHz V = 1.8V, V = 5V, f = 1MHz OUT IN SW OUT IN SW 100 1200 1150 90 PSAVE 1100 1050 80 CCM 1000 70 950 900 60 850 50 800 0.1 1 10 100 5 10 0 15 20 25 Output Current (A) Output Current (A) Load Regulation — PSAVE Load Regulation — CCM VOUT = 1.8V, VIN = 5V, fSW = 250kHz VOUT = 1.8V, VIN = 5V, fSW = 250kHz 1.9 1.9 1.86 1.86 +1% +1% 1.82 1.82 1.78 1.78 -1% -1% 1.74 1.74 1.7 1.7 0 5 10 15 20 25 0 5 10 15 20 25 Output Current (A) Output Current (A) Output Voltage vs. Margin — CCM Output Voltage vs. VFBadj — CCM V = 1.8V, V = 5V, f = 1MHz V = 1.8V, V = 5V, f = 1MHz OUT IN SW OUT IN SW 2 2 1.9 1.9 1.8 1.8 1.7 1.7 1.6 1.6 -10 -5 0 5 10 -10 -5 0 5 10 Margin Command (%) VFBadjust Command(%) 7 Output Voltage (V) Output Voltage (V) Efficiency (%) Switching Frequency (kHz) Output Voltage (V) Output Voltage (V) SC493 Typical Characteristics (continued) 2 Soft Start — EN Pin Soft Start — I C V = 5V, V = 1.8V, Soft Start = 1ms, Power-on Delay = 0ms V = 5V, V = 1.8V, Soft Start = 2ms, Power-on Delay = 2ms IN OUT IN OUT EN (5V/div) SCL (5V/div) V (500mV/div) V (500mV/div) OUT OUT PGOOD (5V/div) PGOOD (5V/div) Time (500μs/div) Time (1ms/div) Load Transient Response Output Over Current Response — Normal Operation V = 5V, V = 1.2V, f = 1MHz, L = 0.2μH, C = 220μF V = 5V, V = 1.8V, f = 1MHz, L = 0.2μH, C = 1000μF IN OUT SW IN OUT SW I = 20A OUT I (10A/div) L I OUT (5A/div) V (1V/div) OUT V (20mV/div) OUT LX (5V/div) PGOOD (5V/div) Time (500μs/div) Time (20μs/div) Switching — Forced Continuous Mode Switching — Ultrasonic PSAVE Mode V = 5V, V = 1.8V, f = 1MHz, Load = 3A V = 5V, V = 1.8V, f = 500kHz, No load IN OUT SW IN OUT SW V (20mV/div) OUT LX (5V/div) V (20mV/div) DH (5V/div) FB V (20mV/div) OUT DL (5V/div) Time (4μs/div) Time (1μs/div) 8 SC493 Typical Characteristics (continued) Slew-Up — CCM, No Load, EnIntLd=0/1 Slew-Down — CCM, No Load, EnIntLd=0 V = 5V, V = 1.8V, f = 1MHz, VFBadj command change -9% to +9% V = 5V, V = 1.8V, f = 1MHz, VFBadj command change +9% to -9% IN OUT SW IN OUT SW SCL (5V/div) SCL (5V/div) V (100mV/div) OUT V (100mV/div) OUT PGOOD (5V/div) PGOOD (5V/div) Time (500μs/div) Time (500μs/div) Slew-Up — CCM, No Load, EnIntLd=0/1 Slew-Down — CCM, No Load, EnIntLd=1 V = 5V, V = 1.8V, f = 1MHz, Margin command change -10% to +10% V = 5V, V = 1.8V, f = 1MHz, Margin command change +10% to -10% IN OUT SW IN OUT SW SCL (5V/div) SCL (5V/div) V (100mV/div) OUT V (100mV/div) OUT PGOOD (5V/div) PGOOD (5V/div) Time (500μs/div) Time (500μs/div) Slew-Up — CCM, 3A Load, EnIntLd=0/1 Slew-Down — CCM, 3A Load, EnIntLd=0/1 V = 5V, V = 1.8V, f = 1MHz, Margin command change -10% to +10% V = 5V, V = 1.8V, f = 1MHz, Margin command change +10% to -10% IN OUT SW IN OUT SW SCL (5V/div) SCL (5V/div) V (100mV/div) OUT V (100mV/div) OUT PGOOD (5V/div) PGOOD (5V/div) Time (500μs/div) Time (500μs/div) 9 SC493 Pin Descriptions Pin # Pin Name Pin Function 1 VOUT Output voltage 2 FB Feedback pin 3 AVDD Chip supply voltage 2 4 SDA I C data input/output 2 5 SCL I C clock input 6 EN Enable pin 7 VIN Power stage input voltage 8 DH High side gate driver pin Bootstrap pin — a capacitor is connected from BST to LX to develop the bias voltage for the high side gate 9 BST drive. 10 LX Switching (phase) node — connect to the switching side of the power inductor. 11 NC No Connect 12 DL Low side gate driver pin 13 PGND Power ground 14 PVDD Supply voltage for driver 15 PGOOD Power good 16 ILIM Current limit sense point — to program the current limit connect a resistor from ILIM to LX 2 17 A2 Input for bit 2 of the I C device address 2 18 A1 Input for bit 1 of the I C device address 2 19 A0 Input for bit 0 of the I C device address 20 AGND Analog ground Thermal pad for heat sinking purposes — connect to ground plane using multiple vias — not connected PAD internally. 10 SC493 Block Diagram EN A0 PGOOD PVDD VIN SCL SDA A2 A1 7 6 5 4 17 18 19 15 14 PVDD 2 Control, Status, and I C Interface Reference DL Feedback Adjustment Status Register Frequency Setting Output Voltage Margining Current Limit Setting Power On Delay Power Save Mode Soft Start Time 9 BST Soft Start & Slew Control 8 DH AVDD + On-time AVDD 3 Gate Drive Generator 10 LX - Control PVDD Comparator AGND 20 12 DL 16 ILIM Zero Cross Detector 2 FB Valley Current Limit 13 PGND 1 VOUT 11 SC493 Applications Information become high when the specified condition happens, but General Description will not turn low when the specified condition disappears. The SC493 is a step down synchronous buck DC-DC For the above mentioned status and flag bits, only discon- controller optimized for use in 3.3V/5V input small form- tinuous mode and power good are status bits, the rest of factor applications. It has the following key features: them are all flag bits. The flag bits remain set until one of 2 • I C control over output voltage offset, margin- the following events occurs: ing, power-on delay, switching frequency, soft- • The input voltage is cycled start duration, and power save mode. • EN pin is cycled • Integrated bootstrap switch • CLF bit is set • Programmable switching frequency from 250kHz to 1MHz to optimize board space and efficiency. Enable/Disable • Protection features — over-current, over-voltage, The converter is enabled by applying power to VDD under-voltage, and over-temperature (VDD when used refers to AVDD and PVDD together) and • Power save operation — low quiescent current VIN, and pulling the EN pin high. The output voltage will and ultrasonic power save rise to the voltage programmed by the FB pin and the • Status and flag bits for diagnosis and protection external FB network. Pulling the EN pin low turns the purposes converter off and clears all flag bits. The converter can • Supports 25A operation 2 also be turned on/off via the I C interface. When the EN pin is high, setting the ENSW bit low will turn off the 2 I C Compatible Interface Functions converter, but the flag bits will not be cleared. Setting the 2 The I C interface can be used to read & write the following ENSW bit back high will turn on the converter again. functions: Diagnosis and Protection Features • Shutdown/Start-up of output When the device detects fault conditions, the SC493 sets • Power-on delay and soft-start duration the flag bits indicating what fault conditions have • Output voltage offset and margining occurred. In addition, depending upon what kind of faults • Power save mode have been detected, the SC493 will provide appropriate • Switching frequency actions to safeguard the device from catastrophic failures. 2 The following paragraphs describe how these fault condi- Additionally, the I C interface can be used to read status tions are handled by the SC493. and flag bits for the following functions: Did Not Start Indication • Under voltage If the FB voltage does not rise to 90% of nominal voltage • Over voltage after the converter is enabled, the soft-start duration has • Over temperature passed, and the power good delay has elapsed, the Did • Current limit Not Start (DNS) flag bit is set. Note that the converter does • Brown out not latch off just because this bit is set. • Did not start • Discontinuous mode Output Over Voltage Protection • Power good When the FB pin voltage exceeds 120% of the nominal voltage, DL goes high, forcing the low-side MOSFET on, Status and Flag Bits and the OVO flag bit is set. The low side MOSFET stays on The status and flag bits are used to indicate the status of (and the high side MOSFET remains off ) until the output the converter. The status bits always indicate the current voltage comes back into regulation. However, the CLF bit state of the converter — the status bit becomes high will successfully clear the OVO flag as soon as the FB falls when the specified condition happens and turns low below 120% of the normal voltage. The converter does not when the specified condition disappears. The flag bits also 12 SC493 Applications Information (continued) latch off just because this bit is set. The PGD output is Over Temperature Protection driven low when the FB pin is above 120% of the nominal When the temperature of the device reaches the over voltage and returns to high when the FB pin is below 110% temperature rising threshold, the OT flag bit is set, turning of the nominal voltage. off both high side and low side MOSFETs. After the temperature of the device drops to the over temperature Output Over Current Protection falling threshold, the converter restarts as if the device The SC493 features adjustable current limit capability. has been enabled. The converter will go through power- The R of the external low side MOSFET is used as the on delay and soft start. DS(ON) current sensing element. The over current limit is set by R (connected externally). Internally there is a 10μA Synchronous Buck Converter Operation, Ben- ILIM current source that feeds the ILIM pin when the low side efits, and Features MOSFET has turned on. This current flows through the R The SC493 employs pseudo-fixed frequency adaptive on- ILIM resistor and creates a voltage drop across it. When the low time control. This control method allows fast transient side MOSFET turns on, the inductor current flowing response thereby lowering the size of the power through it creats a voltage across the MOSFET due to its components needed in the system. R . If this voltage drop exceeds the voltage across the DS(ON) R resistor, current limit will activate. This prevents the The on time is determined by an internal one-shot with a ILIM high side MOSFET from turning on until the voltage drop period proportional to the output voltage and inversely across the low side MOSFET falls below the voltage across proportional to the input voltage. The output ripple the R resistor. This effectively sets a valley current limit voltage generated by the ESR of the output capacitance is ILIM of R x 10μA/R . Please note that R of the MOSFET used as the PWM ramp signal. This ripple voltage ILIM DS(ON) DS(ON) is dependent on the V voltage (equals to PVDD applied determines the off time for the controller. GS to SC493). The ILIM flag bit is set whenever current limit For the SC493 the operating frequency range is from 250kHz occurs. The converter does not latch off just because this 2 to 1MHz , programmable via the I C interface. bit is set. Output Under Voltage Protection Adaptive on-time control has significant advantages over The output under voltage condition occurs with or without traditional control methods. Some of the advantages of current limit. The output under voltage without current the adaptive on-time control are: limit is normally a result of low input voltage. The control- • No error amplifier, which reduces external com- ler will look at the inductor current to differentiate these ponents used for compensation two situations and respond accordingly. After PGD is • Predictable frequency spread because of adap- asserted, if the FB voltage falls below the PGD falling tive on-time architecture threshold (80%) and current limit does not happen simul- • Fast transient response — operation with taneously, the Brown Out (BO) flag bit is set. This indicates minimum output capacitance an output under voltage has happened because of low • Overall superior performance compared to fixed input voltage. The converter does not latch off just frequency architectures because the BO bit is set. After PGD is asserted, if FB voltage falls below 70% of the nominal voltage for 8 con- On-Time One-Shot Generator (TON) secutive current limited switching cycles, the UVO flag bit Adaptive on-time controllers like the SC493 have an is set. This latches the converter off, with both the high internal on-time one-shot generator. The one-shot timer side and low side MOSFETs turned off. uses an internal comparator and a capacitor. The positive input of the comparator is a voltage proportional to the To restart, either the EN pin or ENSW register bit must be output voltage and the negative input is connected to the set low and then back to high. capacitor charged by a current proportional to the input voltage. The TON time is the time required to charge this 13 SC493 Applications Information (continued) capacitor from 0V to the voltage at the positive input. This The switching frequency is changed to the programmed makes the on-time proportional to the output voltage and value by scaling the on time as needed. inversely proportional to the input voltage, providing a near- constant switching frequency when the input and output Power Save Mode Programming voltage vary. A second comparator compares the voltage at The SC493 provides selectable power-save operation at the feedback pin to a fixed internal reference voltage to light loads. When register bits PSV1,0 are set to 01 or 10 determine when to turn on the high side MOSFET. the power save mode is enabled. With power save enabled, the zero crossing comparator monitors the Power-on Delay Programming inductor current via the voltage across the low-side 2 The power-on delay is programmable via the I C interface. MOSFET. If the inductor current falls to zero for 8 consecu- The power-on delay is defined as the time from when the tive cycles then the controller enters power save and turns ENSW bit is set to when the PWM control is enabled and the off the low-side FET on each subsequent cycle as long as part begins switching. At the end of the power-on delay time, the current crosses zero. If the inductor current does not the PWM control circuit is enabled in a phased manner to reach zero for 8 consecutive switching cycles the control- ensure proper operation. The phased enabling of internal ler immediately exits power save. The controller counts circuitry adds up to 48μs to the power-on delay time. On start- zero crossings and therefore the converter can sink current up (controller enabled by applying power and driving the EN as long as the current does not cross zero on 8 consecu- pin high). The controller can take up to 1ms for internal tive consecutive cycles. This allows the output voltage to initialization following which the power-on delay is applied. recover quickly in response to negative load steps. Soft-Start Operation and Programming The SC493 can also be operated in forced Continuous Soft-start is achieved in the PWM controller by using an Conduction Mode (CCM) by setting PSV1,0 = 00 or 11. internal voltage ramp as the reference for the FB Comparator. With these settings the device will not enter PSAVE and The voltage ramp is generated using an internal charge operates at programmed frequency even at light loads. pump which drives the reference from zero to 500mV in ~ This feature provides user flexibility for system design. 2mV increments, using an internal oscillator. When the Figure 1 shows operation under power save and continu- ramp voltage reaches 500mV, the ramp is ignored and the ous conduction mode at light loads. FB comparator switches over to a fixed 500mV threshold. Dead time varies During soft-start the output voltage tracks the internal according to load FB Ripple ramp, which limits the start-up inrush current and provides Voltage a controlled soft-start profile for a wide range of applica- FB threshold (V ) FB (500mV) tions. Soft-start programmability is achieved by changing the frequency of the oscillator. The soft-start ramp reaches Inductor Zero (0A) 500mV in 90% of the programmed soft-start time. The Current remaining 10% of the programmed soft-start time is used to allow the system to stabilize before enabling the PGOOD On-time (T ) ON comparator to drive the PGOOD pin high. DH On-time is triggered when V reaches the FB Threshold. During soft-start the controller turns off the low-side FB DH MOSFET on any cycle if the inductor current falls to zero. This prevents negative inductor current, allowing the DL device to start into a pre-biased output. DL drives high when on-time is completed. Frequency Programming DL remains high until inductor current reaches zero. The nominal switching frequency in continuous 2 conduction mode is programmable via the I C interface. Figure 1 — Power-save Operation 14 SC493 Applications Information (continued) Ultrasonic Power-save UVLO and POR When ultrasonic PSAVE is enabled (PSV1,0 =10) the Under-Voltage Lockout (UVLO) circuitry inhibits switching minimum operating frequency in power save for the and tri-states the output until VDD rises above 2.8V. An SC493 is set by UPSV1,0 bits . This is accomplished by internal Power-On Reset (POR) occurs until VDD exceeds 2 using a built-in timer that detects the time between con- 2.8V, which resets the internal registers, enables the I C secutive high-side gate pulses. interface, and resets the soft-start circuitry. As soon as the time exceeds the the programmed upper Smart Power-save Protection limit, the bottom gate is turned on. This prevents the con- Active loads may leak current from a higher voltage into troller from going below the set limit in frequency when the switcher output. Under light load conditions with the power save is enabled. Figure 2 shows ultrasonic power-save enabled, this can force V to slowly rise and OUT power-save operation. reach the over-voltage threshold. Smart power-save pre- vents this condition. When the FB voltage exceeds 10% Minimum F ~ 20kHz SW above nominal (exceeds 550mV), the device immediately disables power-save, and DL drives high to turn on the FB Ripple low-side MOSFET. This draws current from V through OUT Voltage (V ) FB threshold FB the inductor and causes V to fall. When V drops back (500mV) OUT FB to the 500mV trip point, a normal T switching cycle ON (0A) begins. This method prevents an OVP fault and also cycles Inductor Current energy from V back to V . The device will return to OUT IN power-save operation on the next switching cycle if the DH On-Time is triggered when On-time load remains light. Smart Power-Save allows the user to V reaches the FB Threshold FB (T ) ON minimize operating power by allowing the use of power save mode in load conditions that would normally require DH the use of forced continuous conduction mode. Figure 3 40µsec time-out shows typical waveforms for the Smart Power-save DL feature. V drifts up to due to leakage OUT After the 40µsec time-out, DL drives high if V FB current flowing into C V discharges via inductor OUT OUT has not reached the FB threshold. and low-side MOSFET Smart Power Save Threshold (550mV) Normal V ripple OUT Figure 2 — Ultrasonic Power-save (UPSV 1,0 = 11) FB threshold DH and DL off Power Good Output The Power Good (PGD) output is an open-drain output High-side Drive (DH) which requires a pull-up resistor. When the FB voltage falls Single DH on-time pulse lower than 80% (typical) of the nominal voltage, PGD is after DL turn-off pulled low. It is held low until the FB voltage rises above 90% (typical) of the nominal voltage. PGD is held low Low-side Drive (DL) during start-up and will not be allowed to transition high DL turns on when Smart Normal DL pulse after DH until soft-start is completed. PGD also transitions low if the PSAVE threshold is reached on-time pulse FB voltage rises above 120% (typical) of the nominal DL turns off when FB threshold is reached voltage, it is held low until the FB voltage drops below 110% (typical) of the nominal voltage. Figure 3 — Smart Power-save 15 SC493 Applications Information (continued) Dynamic Output Voltage Control abled or set to ultrasonic before the output is slewed. This SC493 allows changing the output voltage when the part will ensure that the low side MOSFET will turn back on at is already switching. Whenever the output voltage is the end of the slewing sequence even if there is no load changed via margining or by fine adjust, the controller and bring the output voltage back into regulation. Figure changes the internal reference by small intermediate steps 4 demonstrates this with a 1000µF output capacitor and using 32us per step. This ensures that the output keeps up with psave disabled before slewing from VFBadj = +9% to with internal slewing and excessive current does not build VFBadj = -9%. up in the inductor. The faults are blanked till the end of the slewing. Blanking is released when 8 switching cycles occur after the end of internal slewing since the switching SCL (5V/div) cycles indicate that the part is in regulation. The part is enabled to operate in DCM mode to prevent negative V (100mV/div) OUT current build up in the inductor when slewing down. The part returns to the previous operational state (DCM or CCM) at the end of blanking. Since the controller operates in DCM, it depends on the PGOOD (5V/div) load to discharge the output when slewing down. Therefore, no switching cycles may occur if the load is very light and Time (500μs/div) the output will not keep pace with the internal slew. In such cases, the blanking at the end of slewing will end after a Figure 4 — Slew Down in CCM with Large Output 1ms timeout whether any switching cycles occur or not and Capacitors the part will return to its previous operational state. Soft-shutdown For applications that need to have the output slew down at SC493 features a soft-shutdown feature: whenever switch- the same rate as the internal slewing, register bit Enable ing is disabled, an internal 10Ω pull-down activates on the Internal Load (EnIntLd) can be set. This activates an internal Vout pin which discharges the output capacitor and holds 10Ω pull down on Vout when the part is slewing down. This Vout low. The pull-down stays active even if the EN pin is resistance discharges the output capacitor and helps the subsequently driven low. Note that the pull-down will not output keep pace with internal slewing. To help maximize activate if EN pin has not been high after power has been efficiency, the pulldown will not activate when slewing up applied or power is cycled with EN pin low. even if the feature is enabled via register settings. TM SmartDrive When the internal pull down is enabled, it is active only for For each DH pulse, the DH driver initially turns on the the time it takes the internal reference to reach its target. high-side MOSFET at a slower speed, allowing a softer, For example, when slewing from VFBadjust of +9% to 0%, smooth turn-off of the low-side diode. Once the diode is the pull down is active only for 12 x 32µs = 384µs. In appli- off and the LX voltage has risen 0.5V above PGND, the cations with large output capacitors, this time may not be SmartDrive circuit automatically drives the high-side sufficient to discharge the output to keep up with the MOSFET on at a rapid rate. This technique reduces switch- internal reference. Therefore, the output can be higher ing noise while maintaining high efficiency, reducing the than the desired regulation value at the end of the slewing need for snubbers or series resistors in the gate drive. sequence. If the part was in DCM before slewing began, the output will stay at the higher value at the end of the sequence. If there is no load, the output will return to the desired value very slowly. In such applications, to ensure that the controller quickly brings the output voltage into regulation, it is recommended that either PSAVE be dis- 16 SC493 Applications Information (continued) implemented is calculated according to the next Power Stage Design Procedure equation. When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor t ON ripple current must be specified. D MAX t t ON OFF(MIN) The maximum input voltage (V ) is the highest speci- If a maximum load step occurs instantly, the voltage INMAX fied input voltage. The minimum input voltage ( V ) is undershoot can be derived by the next equation. INMIN determined by the lowest input voltage after evaluating 2 'I uL the voltage drops due to connectors, fuses, switches, and V UV PCB traces. 2uCuD uV V  MAX IN OUT For load release, the worst case happens when the The following parameters define the design: maximum load release occurs at the same time as the high • Nominal output voltage (V ) side turns on. The over-shoot in this situation can be OUT • Static or DC output tolerance derived by the next equation. • Transient response 2 Lu'I 'Iut • Maximum load current (I ) ON OUT V  OV 2uCuV 2uC OUT There are two values of load current to evaluate — con- Using the previous two equations, the output capacitor tinuous load current and peak load current. Continuous can be calculated based upon the required performance load current relates to thermal limitations which drive the metrics (under-shoot or over-shoot voltage during the selection of the inductor and input capacitors. Peak load transient). Note that the above equations show the worst current determines instantaneous component stresses case analysis. In practice, the load normally changes with and filtering requirements such as inductor saturation, certain slew rate limits, so the required capacitance value output capacitors, and design of the current limit circuit. may be much smaller than the value calculated using these equations. Inductor Selection Low inductor values result in smaller size but create higher Input Capacitor Selection ripple current, and are less efficient because of that ripple The input capacitor should be chosen to handle the RMS current flowing in the inductor. Higher inductor values ripple current of a synchronous buck converter. This value will reduce the ripple current/voltage and are more effi- is shown by the next equation. cient, but are larger and more costly. The inductor selec- tion is based upon the ripple current which is typically set 2 2 I (ID)uI Du(I I ) RMS IN OUT IN between 20% and 50% of the maximum load current. Cost, size, output ripple, and efficiency are all used in the where selection process. The equation for determining the induc- V V uI tance is shown by the next equation. OUT OUT OUT D , I IN V V IN IN (V V )ut IN OUT ON L When the input voltage is also used as VDD, it is desirable to I RIPPLE limit the input voltage ripple to less than 20mV. The input voltage ripple can be calculated by the next equation. Output Capacitor Selection Two parameters need to be determined in order to select the output capacitor — the output capacitance and the t ON V I I u IN_RIPPLE OUT IN capacitor ESR. These two parameters are determined C IN based upon the dynamic and the static regulation require- ments. On a load step, the maximum duty ratio that is 17 SC493 Applications Information (continued) Stability Considerations L Unstable operation occurs in two related but distinctly dif- ferent ways — double-pulsing and fast-feedback loop insta- High-side bility. Double-pulsing occurs due to switching noise seen at C L R L the FB input or because the FB ramp voltage is too low. This R 1 causes the high side to turn on prematurely after the 250ns C C C OUT Low-side minimum off-time has been completed. Double-pulsing will result in higher ripple voltage at the output, but in most R 2 applications will not adversely affect operation. However, In FB pin some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. Figure 5 – Virtual ESR Network The best method for checking stability is to apply a zero-to- full load transient and observe the output voltage ripple This network creates a ramp voltage across C which is envelope for overshoot and ringing. Over one cycle of L analogous to the ramp voltage generated across the ESR ringing after the initial step is an indication that the ESR of a standard capacitor. This ramp is then capacitively should be increased. One simple way to solve this problem coupled into the FB pin via capacitor C . This circuit is ana- is to add trace resistance in the high current output path. A C lyzed as follows. The AC equivalent circuit used to calcu- side effect of adding trace resistance is output voltage late the injected signal at FB pin is shown in Figure 6 droop with load. (without considering the output ripple voltage). The on-time control regulates the valley of the output ripple voltage. This ripple voltage consists of a term gener- ated by the ESR of the output capacitor and a term based V SW upon the capacitance charging and discharging during V RIPPLE the switching cycle. A minimum ESR is required to gener- R L R1 ate the required ripple voltage for regulation. For stability C L C the ESR zero of the output capacitor should be lower than C V INJ approximately one-third of the switching frequency. The formula for minimum ESR is shown by the next equation. R2 FB pin 3 ESR MIN 2uSuC uf OUT SW Where f is the switching frequency. SW Figure 6 – AC Equivalent Circuit For applications using ceramic output capacitors, the ESR is normally too small to meet the above ESR criteria. In The DC voltage at V is the same as V , which is the RIPPLE SW these applications it is necessary to add a small virtual ESR same as V . The current through resistance R during the OUT L network composed of two capacitors and one resistor, as on time is shown by the next equation. shown in the Figure 5. 18 SC493 Applications Information (continued) The ripple due to the capacitance ESR alone is shown V V IN OUT I INJ by the next equation. R L The following describes one way to design the virtual ESR V = I x R ESR_RIPPLE RIPPLE ESR circuit. The output ripple voltage due to output capacitance has 1 C t C !! a 90° phase lag with respect to the ripple voltage gener- L C § R uR · 1 2 ¨ ¸ ated by the virtual ESR. The actual ripple voltage seen at 2Su f u SW ¨ ¸ R  R © 1 2¹ the FB pin (VFB_RIPPLE) can be approximated by the next The current through resistance R will all go through C and equation. L L the voltage change through capacitor C will be shown by L 2 the next equation. 2 V (V V ) V FB_RIPPLE INJ ESR_RIPPLE COUT_RIPPLE V V t IN OUT ON V | u INJ R C Resistor Divider Selection L L The DC voltage at the FB pin is shown by the next equation. All of this voltage will be coupled into the FB pin if the rules previously stated are followed. Note that the output V FB_RIPPLE V |0.5V ripple voltage has not been taken into account. The FB 2 output voltage ripple will also be coupled through the C L The resistor divider value should be selected using the and C path into the FB pin. The ripple voltage at the C next equation. output due to the output capacitance (ignoring the capacitance ESR) is shown by the next equation. V R R OUT 1 2 V R I FB 2 RIPPLE V | COUT_RIPPLE 8uC uf OUT SW 19 SC493 Applications Information (continued) 2. Both the high side loop and low side loop should use Layout Guidelines short traces. The high side loop includes the input The switching converter can be an EMI source if the cir- capacitors, the high side MOSFET, the inductor, and the cuitry is not properly laid out on the PCB. The suggested output capacitors. The low side loop includes the low layout guidelines are shown in Figure 7. The following are side MOSFET, the inductor, and the output capacitors. several simple rules that should be followed to prevent 3. The LX trace should be short, since it is the main EMI issues. noise source of the circuit. All sensitive analog signals 1. The ground connection between the input capacitor, should be routed away from the LX trace. the output capacitor, and the MOSFET ground should 4. Standard techniques such as snubbers can also be use a short and wide trace. This can reduce the used to remove the high frequency ringing at the resistive losses and high frequency ringing due to stray phase node. inductance. COUT CLDO3 VOUT AGND RPGOOD VOUT PGOOD FB PVDD VDD PGND SC493 PGND SDA DL SCL NC RILIM CBST LX PGND MOSFETs CIN VIN Figure 7 — Suggested Layout Guidelines 20 C1 EN AGND VIN A0 DH A1 BST A2 LX ILIM C2 SC493 Register Map Address D7 D6 D5 D4 D3 D2 D1 D0 Access Reset Description 00h PGD DCM DNS BO ILIM OT OVO UVO RO 40h Status Register (1) (1) (1) (1) (1) 01h 0 0 0 0 0 EnIntLd CLF ENSW R/W 01h Control Register 1 (1) (1) 02h 0 0 UPSV0 POD2 POD1 POD0 Freq1 Freq0 R/W 20h Control Register 2 (1) (1) 03h 0 0 UPSV1 SST2 SST1 SST0 PSV1 PSV0 R/W 2Eh Control Register 3 (1) (1) (1) 04h 0 0 0 VFBadj4 VFBadj3 VFBadj2 VFBadj1 VFBadj0 R/W 0Fh Control Register 4 (1) (1) (2) (2) (2) 06h 0 0 1 1 1 Margin2 Margin1 Margin0 R/W 3Bh Control Register 6 Notes: (1) Always write 0 (2) Always write 1 Definition of Registers and Bits Status and Flag Bits Description — Register 0 A status bit reflects the current state of the converter. It becomes high when the specified condition has occurred and turns low when the specified condition has disappeared. A flag bit becomes high when the specified condition has occurred and will not turn low when the specified condition has disappeared. Name Bit Definition Description Flag bit when high indicates that the output voltage fell below 70% of the regulation level UVO 00h[0] Under Voltage Output Flag while being current limited. OVO 00h[1] Over Voltage Output Flag Flag bit when high indicates output voltage has been above the regulation level by 20%. OT 00h[2] Over Temperature Flag Flag bit when high indicates that the over temperature circuit has tripped. ILIM 00h[3] Output Current Limit Flag Flag bit when high indicates that the inductor current threshold has been reached. Flag bit when high indicates that the FB voltage has fallen below PGD falling threshold (80%) BO 00h[4] Brown Out Flag with the device not in current limit. This normally means the output under voltage has been caused by low input voltage. Flag bit when high indicates that the FB voltage did not reach the power good rising thresh- DNS 00h[5] Did Not Start Flag old (90%) within the predetermined time. This time interval is the programmed soft start time. The power good delay is 10% of the programmed soft start time. Status bit when high indicates that the part is operating in discontinuous mode. The part is Discontinuous Mode only permitted to operate in DCM if PSAVE or UPSAVE is enabled. The part also enters into DCM 00h[6] Status DCM mode before the soft start process is complete. Therefore, in the shut down state and during the soft start process, this bit is also set. Status bit when high indicates that the PGD pin is not being pulled low and therefore the PGD 00h[7] Power Good Status output is within regulation by +20%. 21 SC493 Definition of Registers and Bits (continued) Switching and Status Control — Register 1 Name Bit Description Description This bits controls whether the output is enabled or not. 0: The output is disabled, both high side and low side switches are off. ENSW 01h[0] Enable Switching 1: power-on delay and soft start process can start when this bit is 1 and the EN pin is pulled high. CLF 01h[1] Clear Fault Status Set to clear fault indicator flags (UVO, OVO, OT, ILIM, BO, & DNS). This bit is self clearing. EnIntLd 01h{2} Enable Internal Load Set to enable internal pull down on VOUT when slewing down. Timing Control — Registers 2 and 3 These registers provide software control over key timing parameters of the controller: frequency setting (Freq), Power- On Delay (POD) time, Soft-Start Time (SST) setting, power save (PSV) mode control, and minimum switching frequency in Ultrasonic Power Save (UPSV) mode. The details of each setting are listed in the table below. Name Bit Definition Description 2 bits that control the switching frequency from 250kHz to 1MHz. 00 : 250kHz Freq1 02h Frequency Setting 01 : 500kHz Freq0 [1:0] 10 : 750kHz 11 : 1MHz 3 bits that control the power-on delay from 0μs to 16ms. 000 : 0μs 001 : 250μs POD2 010 : 500μs 02h POD1 Power-on Delay Time 011 : 1000μs [4:2] POD0 100 : 2ms 101 : 4ms 110 : 8ms 111 : 16ms 3 bits that control the soft start time from 250μs to 16ms. 000 : 250μs 001 : 500μs SST2 010 : 1000μs 03h SST1 Soft Start Time Setting 011 : 2ms [4:2] SST0 100 : 4ms 101 : 8ms 110 : 16ms 111 : 16ms These bits control whether the device is permitted to enter power save when input, output, and load conditions dictate. If permitted to enter power save, they also control what mode of power save the part can enter. PSV1 03h Power Save Mode Control 00 : PSAVE is disabled PSV0 [1:0] 01 : PSAVE enabled (low I , no ultrasonic mode) Q 10 : UPSAVE enabled (ultrasonic mode) 11 : PSAVE is disabled 22 SC493 Definition of Registers and Bits (continued) Name Bit Definition Description 2 bits that control the nominal minimum switching frequency in ultrasonic mode. 03h 00 : 6.25kHz UPSV1 [5] Ultrasonic Power Save 01 : 12.5kHz UPSV0 02h Frequency 10 : 18.75kHz [5] 11 : 25kHz Output Voltage Control — Registers 4 and 6 These registers provide fine & coarse control over the output voltage. Margin bits can vary the the output by +/-10% in 5% steps. VFBadj can move the output by +/-9% in 0.75% steps. When both registers are used together, the change in the output voltage is determined by the multiplication of the 2 settings, i.e., setting Margin to +10% with +9% VFBadj will change the output by +19.9% whereas a setting Margin to +10% with -9% VFBadj will change the output by +0.1%. Name Bit Definition Description 000xx : -9% 00100 : -8.25% 00101 : -7.50% 00110 : -6.75% 00111 : -6% 01000 : -5.25% 01001 : -4.50% 01010 : -3.75% 01011 : -3% 01100 : -2.25% 01101 : -1.50% VFBadj4 01110 : -0.75% VFBadj3 Output Voltage 01111 : -0% VFBadj4 04h[4:0] Adjustment 10000 : -0% VFBadj1 10001 : +0.75% VFBadj0 10010 : +1.50% 10011 : +2.25% 10100 : +3% 10101 : +3.75% 10110 : +4.50% 10111 : +5.25% 11000 : +6% 11001 : +6.75% 11010 : +7.50% 11011 : +8.25% 111xx : +9% These bits control whether margining is disabled, set to high or set to low. 000 : Margining disabled 001 : Set output to 10% below set value 010 : Set output to 5% below set value Margin1 06h[2:0] Margin Control 011 : Margining disabled Margin0 100 : Margining disabled 101 : Set output to 5% above set value 110 : Set output to 10% above set value 111 : Margining disabled 23 SC493 Serial Interface 2 address. The slave acknowledges and the master sends The I C General Specification 2 the appropriate 8 bit data byte. Once again the slave The SC493 is a read-write slave-mode I C device and com- 2 acknowledges and the master terminates the transfer with plies with the Philips I C standard Version 2.1, dated January 2000. The SC493 has six user-accessible internal the stop condition [P]. 2 8-bit registers. The I C interface has been designed for Combined Format — Read program flexibility, supporting direct format for write After the start condition [S], the slave address is sent, fol- operation. Read operations are supported on both com- 2 lowed by an eighth bit indicating a write. The I C logic bined format and stop separated format. While there is 2 then acknowledges that it is being addressed, and the no auto increment/decrement capability in the SC493 I C master responds with an 8 bit data byte consisting of the logic, a tight software loop can be designed to randomly register address. The slave acknowledges and the master access the next register independent of which register sends the repeated start condition [Sr]. Once again, the was accessed first. The start and stop commands frame slave address is sent, followed by an eighth bit indicating the data-packet and the repeat start condition is allowed a read. The slave responds with an acknowledge and the if necessary. previously addressed 8 bit data byte; the master then 2 sends a non-acknowledge (NACK). Finally, the master ter- SC493 Limitations to the I C Specifications minates the transfer with the stop condition [P]. The SC493 only recognizes seven bit addressing. This means that ten bit addressing and CBUS communication Stop Separated Reads are not compatible. The device can operate in either stan- Stop-separated reads can also be used. This format allows dard mode (100kbit/s) or fast mode (400kbit/s). a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In Slave Address Assignment this format the slave address followed by a write command The seven bit slave address is 0001A A A x, where A A A 2 1 0 2 1 0 are sent after a start [S] condition. The SC493 then are set by the respective pins on the device. Bit 8 is the acknowledges it is being addressed, and the master data direction bit: 0001A A A 0 is used for a write opera- 2 1 0 responds with the 8-bit register address. The master sends tion, and 0001A A A 1 is used for a read operation. 2 1 0 a stop or restart condition and may then address another slave. After performing other tasks, the master can send a Supported Formats start or restart condition to the SC493 with a read The supported formats are described in the following command. The device acknowledges this request and subsections. returns the data from the register location that had previ- ously been set up. Direct Format — Write 2 The simplest format for an I C write is direct format. After the start condition [S], the slave address is sent, followed 2 by an eighth bit indicating a write. The I C logic then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register 24 SC493 Serial Interface (continued) 2 I C Direct Format Write S Slave Address W A Register Address A Data A P Slave Address – 7-bit S – Start Condition Register address – 8-bit W – Write = ‘0’ Data – 8-bit A – Acknowledge (sent by slave) P – Stop condition 2 I C Stop Separated Format Read Master Addresses Register Read Access Register Address Setup Access other Slaves S Slave Address W A Register Address A P S Slave Address B S/Sr Slave Address R A Data NACK P S – Start Condition Slave Address – 7-bit W – Write = ‘0’ Register address – 8-bit R – Read = ‘1’ Data – 8-bit A – Acknowledge (sent by slave) NAK – Non-Acknowledge (sent by master) Sr – Repeated Start condition P – Stop condition 2 I C Combined Format Read W A A NACK P S Slave Address Register Address Sr Slave Address R A Data S – Start Condition Slave Address – 7-bit W – Write = ‘0’ Register address – 8-bit R – Read = ‘1’ Data – 8-bit A – Acknowledge (sent by slave) NAK – Non-Acknowledge (sent by master) Sr – Repeated Start condition P – Stop condition 25 SC493 Outline Drawing - MLPQ-UT-20 3x3 B DIMENSIONS A D INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .020 .024 0.50 0.60 - - A1 .000 .002 0.00 0.05 A2 (.006) (0.1524) PIN 1 E b .006 .008 .010 0.15 0.20 0.25 INDICATOR D .114 .118 .122 2.90 3.00 3.10 (LASER MARK) D1 .061 .067 .071 1.55 1.70 1.80 E .114 .118 .122 2.90 3.00 3.10 E1 .061 .067 .071 1.55 1.70 1.80 e .016 BSC 0.40 BSC L .012 .016 .020 0.30 0.40 0.50 A2 N 20 20 aaa .003 0.08 A bbb .004 0.10 SEATING PLANE aaa C C A1 D1 e LxN E/2 E1 2 1 N D/2 bxN bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3. DAP is 1.90 x 190mm. 26 SC493 Land Pattern - MLPQ-UT-20 3x3 H R DIMENSIONS DIM INCHES MILLIMETERS (.114) (2.90) C G .083 2.10 (C) Z K G H .067 1.70 K .067 1.70 P .016 0.40 R .004 0.10 Y X .008 0.20 Y .031 0.80 X Z .146 3.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. 2. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 27 SC493 © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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