SEMTECH SC4905A

SC4905A/B High Performance Voltage Mode PWM Controller POWER MANAGEMENT Description Features The SC4905A/B is a 10 pin BICMOS primary side voltage ‹ Operation to 1MHz mode controller for use in Isolated DC-DC and off-line ‹ Accurate programmable maximum duty cycle switching power supplies. It is a highly integrated solution, ‹ Integrated oscillator/voltage feed forward requiring few external components. The device features a compensation high speed oscillator with integrated feed forward ‹ Line voltage monitoring compensation, accurately programmable maximum duty ‹ External frequency synchronization cycle, voltage mode of operation, line voltage monitoring, ‹ Bi-phase mode of operation for ripple reduction supply UVLO, low start up current, low voltage current limit ‹ Under 100µA start-up current threshold and user accessible reference. ‹ Accessible reference voltage ‹ VDD undervoltage lockout The SC4905A/B device operates at a fixed frequency, ‹ -40°C to 105°C operating temperature highly desirable for Telecom applications. Features a separate SYNC pin which simplifies synchronization to ‹ 10-Pin MSOP Lead-free package available. Fully WEEE and RoHS compliant an external clock. Feeding the oscillator of one device to the SYNC of another forces biphase operation (180 Applications degrees apart) which reduces input ripple and filter size. ‹ Telecom equipment and power supplies The SC4905A has a typical turn-on threshold of 4.4V ‹ Networking power supplies and the SC4905B has a typical turn-on threshold of ‹ Power over LAN applications about 11.6 volts. ‹ Industrial power supplies ‹ Isolated power supplies These devices are available in the 10 lead MSOP package. Typical Application Circuit Revision: January 4, 2006 1 www.semtech.com SC4905A/B POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymboMs aximu Unit Supply Voltage 1V 8 Input Voltage (RC, ILIM) -V 0.3 to VREF + 0.3 Input Voltage (VFF) -V 0.3 to VREF + 0.7 Input Current (VFF) 2A m Input Voltage (FB) -V 0.3 to VREF + 0.7 Output Current (REF) DC 5A m OUT -V 0.3 to VREF + 0.3 Power Dissipation 1W 80 m ST torage Temperature Range -C 65 to +150 ° STG JT unction Temperature -C 55 to +150 ° J LT ead Temperature (Soldering) 10 Sec. +C 300 ° LEAD ED SD Rating (Human Body Model) E2 S KV Electrical Characteristics Unless otherwise specified, V = 12V, V = 48V, R = 499k, C = 220pF, R = 280k, R = 2k, R = 8.25k, C = 0.1uF, Ta = Tj = -40 to 105 °C. DD IN OSC OSC T M B VDD Ps arameter Tn est Condition Mp i Tx y Mt a Uni Supply Curent Section SV tartup Current = UVLO Start - 1, VDD 1A 00 µ DD Comparator Off IAV ctive = Comparator On, DD DD 32 .5 4A . m Oscillator Running Line Under Voltage Lockout Start Threshold Voltage measured at V pin10 .16416 .20 1V .23 FF Hysteresis 80 5 15 0 1V 1 m I(V VFF) =0 1.2V +/- 3%-0 30 3A 0 n IB FF Oscillator Section MV aximum Frequency =8 1.2V to 4.8V 00 . 12 . 1z . MH FF (1) CT Peak Voltage V=2 1.2V 1V . FF V=6 3.6V 3V . FF (1) CT Valley Voltage 2V 00 m Sync/CLOCK Clock SYNC Threshold .45 *V .50 *V .55 *V V FF FF FF (1) Sync Input Detect Time F>0 Fosc 5S n SYNC  2006 Semtech Corp. 2 www.semtech.com SC4905A/B POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = 12V, V = 48V, R = 499k, C = 220pF, R = 280k, R = 2k, R = 8.25k, C = 0.1uF, Ta = Tj = -40 to 105 °C. DD IN OSC OSC T M B VDD Ps arameter Tn est Condition Mp i Tx y Mt a Uni Sync/CLOCK (Cont.) (1) Sync Frequency 1.2 *F Hz OSC Current Limit Section Input Bias Current 02-A µ Current Limit Threshold 10 70 20 0 2V 3 m (1) Propagation Delay, ILIM to OUT55 0mV Overdrive 3s n VREF Section VA REF (A version) 0% - 5m -4 3 +V 3% VA REF (B version) 0% - 5m -5 3 +V 3% VDD UVLO Section (A version) Start Threshold 44 .1 46 . 4V . Hysteresis 20 00 3V 0 m VDD UVLO Section (B version) Start Threshold 16 1 12 1. 1V Hysteresis 34 .6 V Pulse Width Modulator Section FV B Input current =1 0V to Vref uA FB (1) Minimum Duty Cycle V<0 500mV % FB MV aximum Duty Cycle = V , V=5 Vref 9% DMAX FF FB (1) PWM Gain V=5 3.6 2V 7. %/ FF (1) Propagation Delay, PWM to OUT 7s 5 n Output OI utput VSAT Low =0 1mA 5V 0 m OUT OI utput VSAT High =5 1mAVV REF - 0. OUT (1) Rise Time C=0 20pF 1s n OUT (1) Fall Time C=0 20pF 1s n OUT Note 1: Guaranteed by design. Not 100% tested in production.  2006 Semtech Corp. 3 www.semtech.com SC4905A/B POWER MANAGEMENT Pin Configuration Ordering Information (1) Pe art Number Packag Temp. Range (T ) A (Top view) SC4905AIMSTR VDD REF (2) SC4905AIMSTRT MC SOP-10 -40°C to 105° FB OUT SC4905BIMSTR VFF GND (2) SC4905BIMSTRT DMAX ILIM Notes: RC SYNC (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and (MSOP-10) RoHS compliant.  2006 Semtech Corp. 4 www.semtech.com SC4905A/B POWER MANAGEMENT Pin Descriptions Where VFF is the voltage at the VFF pin at a given Vin, VDD: The supply input for the device. Once VDD has ex- frequency is in Hertz, resistance in ohms, and capaci- ceeded the UVLO limit, the internal reference, oscillator, tance in farads. drivers and logic are powered up. This pin should be by- The recommended range if timing resistors is between passed with a low ESR capacitance right at the IC pin to 10 kohm and 500kohm and range of timing capacitors minimize noise problems, and to ensure proper opera- tion. is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. Refer to layout guide lines on page 12 to achieve best FB: Input to the PWM comparator with an offset voltage results. of 700mV. The feedback analog signal from the output of an error amplifier or an Optoisolator will be connected to this pin to provide regulation. SYNC: SYNC is a positive edge triggered input with a threshold precisely set to VFF: The VFF pin provides the controller with a voltage 0.5*VFF proportional to the power supply input voltage to achieve feed-forward function. RM plus RB in conjunction with RT In the Bi-Phase operation mode SYNC pins should be con- will set the Vff level (see page 1 circuit). nected to the Cosc (Timing Capacitors) of the other con- troller. This will force a 180° out of phase operation. () R + R B M VFF = × VIN (see page9). () R + R + R T B M In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with Fre- DMAX: Programmable duty cycle is achieved via resis- quency higher than the on board oscillator Frequency (see tive divider from the VFF. The duty cycle percentage is page 2). set by the ratio of the divider RM, and RB (see page 1 circuit) from the VFF signal. When RM is shorted, maxi- ILIM: Current sense input is provided via the ILIM pin. mum duty cycle of 100% is achieved. RM plus RB in con- The current sense input from a sense resistor provides a junction with RT will also be used as the divider to set the pulse by pulse current limit by terminating the PWM pulse Vff level. when the input is above 180mV. GND: Device power and analog ground. Careful atten- VDMAX DutyCycle% = tion should be paid to the layout of the ground planes VFF (see page 12). RC: The oscillator programming pin. The oscillator should OUT: The output is intended to drive an external FET driver be referenced to Vin to achieve the line feed forward func- or other high impedance circuit. The output voltage swings tion. Only two components are required to program the from GND to Vref with a typical output impedance of 500Ω. oscillator, a resistor R (tied to the Vin and RC), and a OSC capacitor C (tied to the RC and GND). Since the peak OSC REF: The REF pin provides a 4 or 5V user accessible oscillator voltage is VFF, constant frequency operation is voltage reference. This pin should be decoupled with a maintained over the full power supply. When the DMAX µF capacitor. 1 pin is shorted to the VFF pin, the oscillator can run at the largest duty cycle possible. Following formula can be used for a close approximation of the Oscillator Frequency. VFF   Vin −   2   F ≅ OSC () R • C • VFF •1.05 OSC OSC  2006 Semtech Corp. 5 www.semtech.com SC4905A/B POWER MANAGEMENT Block Diagram Marking Information SC4905AIMSTR SC4905BIMSTR Top Mark Top Mark ALOA ALOB yyww yyww Bottom Mark Bottom Mark yyww = Date Code (Example: 0012) xxxx xxxx xxxx = Semtech Lot No. (Example: E901 xxxx xxxx 01-1) xxxx  2006 Semtech Corp. 6 www.semtech.com SC4905A/B POWER MANAGEMENT Application Information THEORY OF OPERATION The SC4905 is a versatile 10 pin BICMOS primary side This feed forward action provides an immediate duty cycle voltage mode controller optimized for applications requir- adjustment while maintaining a constant oscillator fre- ing minimum space such as isolated DC-DC and off-line quency. A maximum duty cycle can be programmed by connect- switching power supplies. ing a resistor divider from the VFF to the DMAX pin. The The device contains all of the control and drive circuity scaling of the VFF signal will set the maximum duty cycle required for isolated or non-isolated power supplies, percentage. where an external error amplifier is used. Fixed oscillator An external error amplifier will provide the error signal to frequency up to 1MHz can be programmed by an exter- nal RC network. the FB pin of the SC4905. The SC4905 is a voltage mode controller, utilizing a feed A current sense input is provided via the ILIM pin. The forward scheme to accommodate for any variations in current sense input from a sense resistor is used for the the input supply voltage resulting in a duty cycle peak current limit comparator. adjustment. This feed forward action results in an Once VDD has exceeded the UVLO (VDD under voltage improved dynamic performance of the converter. lock out) limit, the internal reference, oscillator, drivers and The SC4905 also provides a programmable maximum duty logic are powered up. cycle to prevent core saturation when a transformer is used. SYNC is a positive edge triggered input with a threshold As an added level of protection, SC4905 provides a cycle set to 0.5*VFF. By connecting a faster external control signal to the SYNC by cycle peak current limit during an over current condition. pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. In a SUPPLY single controller operation, SYNC could be grounded or connected to an external synchronization clock within the A single supply, VDD is used to provide the bias for the SYNC frequency (see page 3). internal reference, oscillator, drivers, and logic circuitry In the Bi-Phase operation mode a very unique oscillator of the SC4905. is utilized to allow two SC4905 to be synchronized together and work out of phase. This feature is setup by PWM CONTROLLER simple connection of the SYNC input to the RC pin of the other part. The fastest oscillator automatically becomes The SC4905 is a BICMOS primary side voltage mode the master, forcing the two PWMs to operate out of controller for use in isolated DC-DC and off-line switch- phase. This feature minimizes the input and output ing power supplies. It is a highly integrated solution, re- ripples, and reduces stress on the capacitors. quiring few external components. The device features a high speed oscillator with integrated feed forward compensation, accurately programmable Typical Typical Device maximum duty cycle, voltage mode of operation, line volt- Vdd UVLO Reference Voltage age monitoring, supply UVLO, low start-up current, low SV C4905A 4V .4 4 voltage current limit threshold and user accessible refer- ence. SV C4905B1V 1.6 5 Two voltage options are available for the SC4905. The SC4905A version has a typical VDD under voltage of 4.4V, and a 4V reference, while the SC4905B version provides a 11.6V VDD UVLO, and a 5V reference. The Oscillator frequency is programmed by a resistor and a capacitor network connected to the line supply voltage . Any variations in the input supply voltage result in a duty cycle adjustment, provided by the change of the oscillator peak voltage via the VFF pin.  2006 Semtech Corp. 7 www.semtech.com SC4905A/B POWER MANAGEMENT Application Information (Cont.) VDD UNDER VOLTAGE LOCK OUT According to the application, and the voltages available, Since the Rosc is referenced to the input supply voltage, the SC4905A (UVLO = 4.4V), or the SC4905B (UVLO = any variation in the supply is directly translated into a 11.6V) can be used to provide the VDD undervoltage variation in the duty cycle, while maintaining the fixed lock out function to ensure the converters controlled frequency operation. start up. Following equation can be used to calculate the oscilla- Before the VDD UVLO has been reached, the internal ref- tor frequency: erence, oscillator, OUT driver, and logic are disabled.  VFF  REFERENCE Vin −   2   F ≅ A 4V (SC4905A) or a 5V(SC4905B) reference voltage is OSC () R • C • VFF •1.05 OSC OSC available that can be used to source a typical current up to 5mA to the external circuitry. The REF can be used to provide the feed back circuitry with a regulated bias. The recommended range if timing resistors is between 10 kohm and 500kohm and range of timing capacitors OSCILLATOR is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. The oscillator frequency is set by connecting a RC network as shown below. Vin SC4905 U1 1 10 VDD REF RT Rosc 2 9 280k 499k FB OUT 3 8 VFF GND 4 7 DMAX ILIM RM 5 6 2k RC SYNC RB Cosc 8.25k 220p, 16V The oscillator has a ramp voltage that will track the volt- age at the VFF pin (1.2VVFF. The FB signal range is from 600mv to 4V. During start up of the converter, the discharged output capacitor, and the load current demand large supply cur- OVER CURRENT rent requirements. To avoid this a soft start scheme is usually implemented where the duty cycle of the regula- A pulse by pulse current limit is provided by the SC4905. tor is gradually increased from 0% until the soft start The current information is sensed at the ILIM pin and duration is elapsed. compared to a peak current limit level of 180mV. If the Programmable soft start duration can implemented ex- 180mV limit is exceeded, the OUT pulse is terminated. ternally by utilizing a simple external circuitry shown be- low. REF VDD REF SC4905 R13 0 U1 R22 SC4905 1.1k 1 U1 C17 VDD REF 1 10 VDD REF 3 6 2 9 C22 FB OUT C30 2 9 M1 FB OUT 3 8 3 8 VFF GND 4 5 VFF GND 4 7 4 7 R17 56.2K DMAX ILIM DMAX ILIM MOCD207 5 6 5 6 RC SYNC R30 RC SYNC Rsense D7 C26 D15 R11 Csoft start VDD SC1301A C18 3 5 D8 Approximate soft start duration can be calculated as be- 1 4 low: D11 U2 2  2006 Semtech Corp. 10 www.semtech.com SC4905A/B POWER MANAGEMENT Application Information (Cont.) START UP SEQUENCE Initially during the power up, the SC4905 is in the under voltage lock out condition. As the VDD supply exceeds the UVLO limit of the SC4905 and the VFF pin exceeds the line under voltage lock out of about 1.2V, the inter- nal reference, oscillator, and logic circuitry are powered up. The OUT driver is not enabled until the line under voltage lock out limit is reached. At that point, once the FB pin has reached above 600mV, the output driver is enabled. As the output voltage starts to increase, the error signal from the error amplifier starts to decrease. If isolation is required, the error amplifier output can drive the LED of the opto isolator. The output of the opto is connected in a common emitter configuration with a pull up resistor to a reference voltage connected to the FB pin of the SC4905. The voltage level at the FB pin provides the duty cycle necessary to achieve regulation.  2006 Semtech Corp. 11 www.semtech.com SC4905A/B POWER MANAGEMENT Application Information (Cont.) LAYOUT GUIDELINES Careful attention to layout requirements are necessary for 7) If an opto isolator is used for isolation, quiet primary successful implementation of the SC4905 PWM control- and secondary ground planes should be used. Same ler. precautions should be followed for the primary GND plane High currents switching are present in the application as mentioned in item 5 mentioned above. For the sec- and their effect on ground plane voltage differentials must ondary GND plane, the GND plane method mentioned be understood and minimized. in item 4 should be followed. 1). The high power parts of the circuit should be laid out 8) All the noise sensitive components such as VFF, DMAX first. A ground plane should be used. The number and resistive divider, reference by pass capacitor, VDD bypass position of ground plane interruptions should be such as capacitor, current sensing circuitry, feedback circuitry, and to not unnecessarily compromise ground plane integrity. the oscillator resistor/capacitor network should be con- Isolated or semi-isolated areas of the ground plane may nected as close as possible to the SC4905. The GND be deliberately introduced to constrain ground currents to return should be connected to the quiet SC4905 GND particular areas, for example the input capacitor and FET plane. ground. 9) The connection from the OUT of the SC4905 should be 2). The loop formed by the Input Capacitor(s) (Cin), the minimized to avoid any stray inductance. If the layout FET must be kept as small as possible. This loop contains can not be optomized due to constraints, a small all the high current, fast transition switching. Connections Schottky diode maybe connected from the OUT pin to should be as wide and as short as possible to minimize the ground directly at the IC. This will clamp excessive loop inductance. Minimizing this loop area will a) reduce negative voltages at the IC. If drivers are used, the EMI, b) lower ground injection currents, resulting in electri- Schottky diodes should be connected directly at the IC, cally “cleaner” grounds for the rest of the system and c) from the output of the driver to the driver ground. minimize source ringing, resulting in more reliable gate 10) If the SYNC function is not used, the SYNC pin should switching signals. be grounded at the SC4905 GND to avoid noise pick up. 3). The connection between FETs and the Transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The output capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load cur- rents are supplied by Cout only. Connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC4905 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VDD supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin and FET loop. This can be achieved by making a star connec- tion between the quiet GND planes that the SC4905 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible, and the GND connections should be to the quiet GND used for the SC4905.  2006 Semtech Corp. 12 www.semtech.com SC4905A/B POWER MANAGEMENT Typical Step Load Vout 20mV/Div Iout 0.5A/Div 500us/Div Cout = 6X100uF (600uF) Tantalum Typical SC4905 Forward converter Step Load plot at Vin = 48V, Vout = 12V, Step = 50% to 75% Iout, Fosc = 245kHz  2006 Semtech Corp. 13 www.semtech.com SC4905A/B POWER MANAGEMENT SC4905A Typical Characteristics (SC4808A) 78 198 Current limit rising Start up Iq, Vdd = 3V 197 76 196 74 195 72 194 70 193 68 192 66 191 64 190 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Iq (start up) vs. Temperature Current Limit vs. Temperature 3.200 65 Idd Active, Vdd = 4V Current limit Input current 3.100 60 3.000 55 2.900 50 2.800 45 2.700 40 2.600 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Idd (operating) vs. Temperature Current Limit bias current vs. Temperature 4.025 4.55 Vdd UVLO (Rising) Reference, Iref = 0mA, Vdd = 5V Vdd UVLO (Falling) Reference, Iref = 5mA, Vdd = 5V 4.50 4.020 4.45 4.015 4.40 4.010 4.35 4.30 4.005 4.25 4.000 4.20 3.995 4.15 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Reference vs. Temperature Vdd UVLO vs. Temperature  2006 Semtech Corp. 14 www.semtech.com Reference (V) Iq (mA) Iq(uA) Vdd UVLO (V) Ics(nA) Current limit (mV) SC4905A/B POWER MANAGEMENT SC4905A Typical Characteristics (Cont.) 0.250 220 Vdd UVLO (Hysteresis) Input Bias current IFF 0.240 200 0.230 180 0.220 160 0.210 140 0.200 120 0.190 100 0.180 80 0.170 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Vdd UVLO Hysteresis vs. Temperature Vff pin leakage current vs. Temperature 1.240 1400 LUVLO (Rising) Oscillator Frequency 1MHz LUVLO (falling) Oscillator Frequency 300kHz 1.220 1200 1.200 1000 1.180 1.160 800 1.140 600 1.120 400 1.100 1.080 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO vs. Temperature Oscillator Frequency vs. Temperature 200 103.6 LUVLO (Hysteresis) Input leakage current Irc 103.5 180 103.5 103.4 160 103.4 140 103.3 103.3 120 103.2 103.2 100 103.1 80 103.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO Hysteresis vs. Temperature RC pin leakage current vs. Temperature  2006 Semtech Corp. 15 www.semtech.com LUVLO Hysteresis (mV) LUVLO (V) Vdd UVLO Hysteresis (mV) Irc(nA) Oscillator Frequency (kHz) IFF(nA) SC4905A/B POWER MANAGEMENT SC4905A Typical Characteristics (Cont.) 1.792 0.075 Vout Low, Vdd = 4V Sync. Threshold 0.070 1.790 0.065 1.788 0.060 1.786 0.055 0.050 1.784 0.045 1.782 0.040 1.780 0.035 0.030 1.778 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Synchronization Threshold vs. Temperature VOUT Low vs. Temperature 280 3.942 Input leakage current IFB, Vfb = 0 Vout High, Vdd = 4V 260 3.940 240 3.938 220 3.936 200 3.934 180 3.932 160 3.930 140 3.928 120 100 3.926 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) FB pin leakage current vs. Temperature VOUT high vs. Temperature  2006 Semtech Corp. 16 www.semtech.com IFB(nA) Synchronization Threshold (V) Vout High (V) Vout Low (V) SC4905A/B POWER MANAGEMENT SC4905B Typical Characteristics 209 79 Current limit rising Start up Iq, Vdd = 3V 208 78 207 77 206 76 205 75 204 74 203 73 202 72 201 71 200 70 199 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Iq (start up) vs. Temperature Current Limit vs. Temperature 3.460 70 Idd Active, Vdd = 4V Current limit Input current 3.410 60 3.360 50 3.310 40 3.260 30 3.210 20 3.160 10 3.110 3.060 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Idd (operating) vs. Temperature Current Limit bias current vs. Temperature 5.030 13.00 Vdd UVLO (Rising) Reference, Iref = 0mA, Vdd = 5V Vdd UVLO (Falling) Reference, Iref = 5mA, Vdd = 5V 12.00 5.025 11.00 5.020 10.00 5.015 9.00 5.010 8.00 5.005 7.00 5.000 6.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Reference vs. Temperature Vdd UVLO vs. Temperature  2006 Semtech Corp. 17 www.semtech.com Reference (V) Iq (mA) Iq(uA) Vdd UVLO (V) Ics(nA) Current limit (mV) SC4905A/B POWER MANAGEMENT SC4905B Typical Characteristics (Cont.) 200 3.740 Vdd UVLO (Hysteresis) Input Bias current IFF 3.720 180 3.700 160 3.680 140 3.660 120 3.640 100 3.620 80 3.600 60 3.580 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Vdd UVLO Hysteresis vs. Temperature Vff pin leakage current vs. Temperature 1.240 1400 LUVLO (Rising) Oscillator Frequency 1MHz LUVLO (falling) 1.220 Oscillator Frequency 300kHz 1200 1.200 1000 1.180 1.160 800 1.140 600 1.120 400 1.100 1.080 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO vs. Temperature Oscillator Frequency vs. Temperature 101.8 200 LUVLO (Hysteresis) Input leakage current Irc 101.7 180 101.6 160 101.5 101.4 140 101.3 120 101.2 101.1 100 101.0 80 100.9 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO Hysteresis vs. Temperature RC pin leakage current vs. Temperature  2006 Semtech Corp. 18 www.semtech.com LUVLO (V) Vdd UVLO Hysteresis (mV) LUVLO Hysteresis (mV) Irc(nA) Oscillator Frequency (kHz) IFF(nA) SC4905A/B POWER MANAGEMENT SC4905B Typical Characteristics (Cont.) 1.796 0.060 Vout Low, Vdd = 4V Sync. Threshold 1.794 0.055 1.792 0.050 0.045 1.790 0.040 1.788 0.035 1.786 0.030 1.784 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Synchronization Threshold vs. Temperature Vout Low vs. Temperature 190 4.958 Input leakage current IFB, Vfb = 0 Vout High, Vdd = 4V 180 4.957 170 4.956 4.955 160 4.954 150 4.953 140 4.952 130 4.951 120 4.950 110 4.949 100 4.948 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) FB pin leakage current vs. Temperature Vout high vs. Temperature  2006 Semtech Corp. 19 www.semtech.com IFB(nA) Synchronization Threshold (V) Vout High (V) Vout Low (V) CON1 9 Vout+ L2 D4 LQH4N102K04 LS4448 PA0273 1 2 6 VDD C16 C1 10u,16V D5 470pF,100V R1 10 R2 GRM42-2X5R106K16 (Murata) LS4448 8 Sense+ L1 0 5 1 P1173 T491X107K016AS 4 3 10 11 12 4 1 2 3 CON2 R3 R4 .47uF,100V 4 10R5 9uH 500 D1 + + + + + + 1 49.9k MBRD660CT 470pF,100V 7 R6 R7 Vin+ GRM44-1X7R105K250AL (Murata) Trim FZT853 D2 C11 C2 C3 C4 C5 C6 C7 C8 C9 D3 Q1 C10 5000 5000 100u,16V 100u,16V 100u,16V 100u,16V 100u,16V 100u,16V C 1u,100V 1u,100V 1 3 0.1u,16V 0.1u,16V B 1 2 9 7 8 R8 TBD MBRD660CT VDD MURA120T3 T1 R9 C12 C13 2 6 3 E ON/OFF 0 Sense- M1 0 SUD15N15-95 VDD = 12V ZM4742A 1 C15 C14 .33uF,250V 0.1u,16V 10u,16V C37 4 5 Vin- D6 2 0 Vout- R30 39.2k D7 2.2 R10 3input_half_brick 5output_half_brick LR2512-01-R025FTR R11 1N5819HW R12 TBD GRM42-2X5R106K16 (Murata) J1 J2 REF VDD VDD VDD Secondary Supply R13 D14 0 B140T SC1301A SC1301A SC4905 CMOSH-3 U1 C17 C18 OUT 1u, 16V 1u, 16V 3 5 3 5 T2 1 10 1u, 16V 1u, 16V D8 C21 D9 1 6 D10 VDD REF R14 R15 C22 1u, 16V C19 C20 C23 CMOSH-3 2 9 2.2u, 16V 1 4 1 4 CMOSH-3 10u,16V 280k 499k FB OUT 3 8 1u, 16V VFF GND 500 D11 3 4 1u, 16V 4 7 R17 U2 CMOSH-3 U3 D12 C24 DMAX ILIM D15 R16 PE-68386 D13 C25 2 2 CMOSH-3 5 6 C26 2k RC SYNC CMOSH-3 220p, 16V CMOSH-3 GRM42-2X5R106K16 (Murata) 0 JP1 R18 C27 SYNC1 8.25k 220p, 16V Secondary Supply R19 1.1k R28 SC4431 2.2k R20 1 5 39.2k 4 U5 C28 C29 0.1u,16V 22n, 16V U4 8 1 R21 REF 3.74k 7 2 Vref R22 1.1k 2 6 3 C30 NA 4.7nF C36 Secondary Supply 5 4 22pF C31 SC4431 SEMTECH CORPORATION R24 C33 MOCD207 C32 R25 680pF 3.74k Title R29 1nF 100k NA R26 R23 1 SC4905 Single Switch Forward (RCD Reset) non Synchronous 12V 50W 5 80.2k 5.1k 4 C34 C35 Size Document Number Rev 0.1u,16V 22n, 16V U6 SC4905EVB 1b R27 9.1k Vref Date: Monday, January 28, 2002 Sheet of 11 2 SC4905A/B POWER MANAGEMENT Evaluation Board Schematics  2006 Semtech Corp. 20 www.semtech.com SC4905A/B POWER MANAGEMENT Evaluation Board Bill of Materials Revised: Monday, March 8, 2003 SC4905 Single Switch Forward (RCD Reset) non Synchronous 12V 50W Bill Of Materials Revised: January 28,2002 Revision: 1b Item Quantity Reference Part Manufacturer # Foot Print 1 1 CON1 5output_half_brick CON\5OUTPUT_HALF_BRICK 2 1 CON2 3input_half_brick CON\3INPUT_HALF_BRICK 3 2 C11,C1 470pF,100V SM/C_0805 4 6 C2,C3,C4,C5,C6,C7 100u,16V EEJL1CD476R 5 5 C8,C9,C14,C28,C34 0.1u,16V SM/C_0805 6 1 C10 .47uF,100V GHM1545X7R474K250 (Murata) SM/C_2220 7 2 C12,C13 1u,100V GRM44-1X7R105K250AL (Murata) SM/C_2220 8 3 C15,C16,C23 10u,16V GRM42-2X5R106K16 (Murata) SM/C_1210_GRM C17,C18,C19,C20,C21,C24, 97 1u, 16V SM/C_0805 C25 10 1 C22 2.2u, 16V SM/C_0805 11 2 C26,C27 220p, 16V SM/C_0805 12 2 C29,C35 22n, 16V SM/C_0805 13 1 C30 NA SM/C_0805 14 1 C31 22pF SM/C_0805 15 1 C32 1nF SM/C_0805 16 1 C33 680pF SM/C_0805 17 1 C36 4.7nF SM/C_0805 18 1 C37 .33uF,250V C4532X7R2E334K (TDK) SM/C_2220 19 2 D1,D2 MBRD660CT DIODE_DPAK 20 1 D3 MURA120T3 SM/DO214AA 21 2 D4,D5 LS4448 SM/DO213AC 22 1 D6 ZM4742A ZM4742A (Diodes Inc.) SMB/DO214 23 1 D7 1N5819HW SOD123 D8,D9,D10,D11,D12,D13, 24 7 CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523 D15 25 1 D14 B140T SM/DO213AC 26 1 JP1 short VIA\2P 27 1 J1 REF ED5052 28 1 J2 VDD ED5052 29 1 L1 9uH P1173.123T (Pulse) P1173 30 1 L2 LQH4N102K04 LQH4N102K04 (Murata) SDIP0302 31 1 M1 SUD15N15-95 SUD15N15-95 (Vishay) DPAKFET 32 1 OUT OUT ED5052 33 1 Q1 FZT853 FZT853 (Zetex) SM/SOT223_BCEC 34 2 R5,R1 10 SM/R_0805 35 3 R2,R9,R13 0 SM/R_0805 36 1 R3 49.9k SM/R_1206 37 1 R4 500 MRC1-100-5000-F-7 SM/R_1210_MCR 38 2 R6,R7 5000 MRC1-100-5001-F-7 SM/R_1210_MCR 39 2 R8,R12 TBD SM/R_0805 40 1 R10 LR2512-01-R025FTR LR2512-01-R025FTR (IRC) ERJL1W 41 1 R11 2.2 SM/R_0805 42 1 R14 280k SM/R_0805 43 1 R15 499k SM/R_0805 44 1 R16 2k SM/R_0805 45 1 R17 500 SM/R_0805 46 1 R18 8.25k SM/R_0805 47 2 R22,R19 1.1k SM/R_0805 48 2 R20,R30 39.2k SM/R_0805 49 2 R24,R21 3.74k SM/R_0805 50 1 R23 5.1k SM/R_0805 51 1 R25 100k SM/R_0805 52 1 R26 80.2k SM/R_0805 53 1 R27 9.1k SM/R_0805 54 1 R28 2.2k SM/R_0805 55 1 R29 NA SM/R_0805 56 1 SYNC1 SYNC ED5052 57 1 T1 PA0273 PA0273 (Pulse) PA0273 58 1 T2 PE-68386 PE-68386 (Pulse) PE-68386 59 1 U1 SC4905 SC4905 (Semtech) MSOP10 60 2 U2,U3 SC1301A SC1301A (Semtech) SOT23_5PIN 61 2 U4,U6 SC4431 SC4431 (Semtech) SOT23_5PIN 62 1 U5 MOCD207 MOCD207(Fairchild) SO-8  2006 Semtech Corp. 21 www.semtech.com SC4905A/B POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly Top Board Layout Assembly Bottom Board Layout Top Board Layout Bottom  2006 Semtech Corp. 22 www.semtech.com SC4905A/B POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout INNER1 Board Layout INNER2  2006 Semtech Corp. 23 www.semtech.com SC4905A/B POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS e INCHES MILLIMETERS DIM A MIN NOM MAX MIN NOM MAX D - - - - A .043 1.10 N - - A1 .000 .006 0.00 0.15 - - A2 .030 .037 0.75 0.95 - - b .007 .011 0.17 0.27 2X E/2 c - - .003 .009 0.08 0.23 D .114 .118 .122 2.90 3.00 3.10 E1 E E1 .114 .118 .122 2.90 3.00 3.10 PIN 1 E .193 BSC 4.90 BSC INDICATOR e .020 BSC 0.50 BSC L .016 .024 .032 0.40 0.60 0.80 ccc C 12 (.037) (.95) L1 N 10 10 2X N/2 TIPS B - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .003 0.08 ccc .010 0.25 D aaa C H A2 A SEATING PLANE c GAGE A1 C PLANE bxN bbb C A-B D 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIMENSIONS DIM INCHES MILLIMETERS (.161) (4.10) C (C) G .098 2.50 G Z P .020 0.50 X .011 0.30 Y .063 1.60 Y Z .224 5.70 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 24 www.semtech.com