SEMTECH SC4901

SC4901 COMBI-SYNC Secondary Side Synchronous Rectifier and Regulator POWER MANAGEMENT Description Features SC4901 is a unique secondary side regulator designed ‹ Single controller performs synchronous rectification for implementing Semtech’s proprietary Combi-Sync and post regulation topology for isolated convertors with multiple outputs. The ‹ Independent regulation of multiple outputs from a Combi-Sync is a true all-MOSFET topology that allows common secondary winding synchronous rectification and post regulation of ‹ Turn on shoot through inherently eliminated transformer isolated outputs, resulting in higher efficiency ‹ Primary switch turns ON and OFF with zero current and low component count. Details of this unique topology ‹ No synchronising or any other signals needed across are described in the Application Information section. the isolation boundary ‹ Eliminates the need for a secondary bias supply Multiple outputs can be synchronously rectified and ‹ Independent soft start, ON/OFF, remote sense and independently regulated by individual SC4901s. Each current limit for each output output has its own ON/OFF control, soft start, remote sense ‹ Resistive or inductive current sensing with 2V current and current limits. They can be turned on or off without signal and 2.5V reference for external applications. affecting the primary or other outputs. The secondary side ‹ 4.5 to 18V operation control makes it much easier to design tight control loops ‹ Max operating frequency to 1 MHz and implement load current sharing and hot swap features. All devices are synchronised to the transformer ‹ Low profile 16 pin TSSOP package winding. The current sense can be either from the output ‹ Based on Semtech’s patented Combi Sync inductor for high efficiency or a resistor for better accuracy. concept An amplified current signal is provided for external use. Applications Each device is capable of driving high side MOSFETs with ‹ Telecom isolated DC to DC converters with multiple 2A current. The forward drive is configured for direct low voltage outputs connection to a 1:1 pulse transformer. SC4901 has an ‹ High density brick and sub brick modules with undervoltage lockout with typical turn-on threshold of 4.5V independently regulated multiple outputs and is available in a low cost TSSOP-16 package ‹ Distributed power architectures Typical Application Circuit ‹ Isolated VRMs VOUT QS QF R1 R2 R3 L1 R4 R5 SINGLE •• R8 ENDED QR C1 C2 FORWARD R9 R6 R7 R10 C3 CONVERTOR T2 T1 RTN C4 C5 C6 D1 D2 R11 R12 RZ RT R13 D3 R14 U1 SC4901 CAO D4 C7 C8 CT C9 C10 R15 United States Patent 6,788,554 Revision: May, 2005 www.semtech.com 1 •• 9 8 PVCC PGND 10 7 OUTA XFRA 11 6 REF OUTB 12 5 VEA- VCC 13 4 VEA SSEN 14 3 RCT CAO 15 2 ZCD CS- 16 1 AGND CS+ SC4901 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit SC upply Voltage A8 VCC, PVC 1V GD round voltages A+ GND to PGN 0V .3V OB utput Voltages OC UTA, XFRA, OUT PV VC C- S+ and CS- common mode voltage C2 S+, CS VV CC - ZCD pin wrt to AGND 0V to 6V V ZCD All other pins wrt AGND -V 0.3 to +6 Max current into ZCD pin 5A mA m I ZCD Max current into RCT pin 2A mA m I RCT OUTA, XFRA Current Source or Sink +02A . OUTB Current Source or Sink +01A . I OUTB AT mbient Temperature Range -C 40 to +125 ° A JT unction Temperature Range -C 40 to +125 ° J ST torage Temperature Range -C 60 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 2C 60 ° LEAD ESD Rating (Human Body Model) 2V .0 k V ESD Electrical Characteristics Unless specified: T = 25°C, VCC = 12V A Ps arameter Tn est Condition Mp i Tx y Mt a Uni Power Supply Operating Current 701A m SSEN = 5V, VCC = 15V I = 0 OUTX Undervoltage Lockout Sg tart Threshold A3 VCC risin 45 . 48 . 4V . Ug VLO Hysteresis A3 VCC fallin 0V . Soft Start and Enable Enable Threshold 05 .5505 .6 0V .7 V ENA SI S Charge Current 80121A µ SS SI S Effective Discharge Current - 1A .5 µ SS  2005 Semtech Corp. 2 www.semtech.com SC4901 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = 25°C, VCC = 12V A Ps arameter Tn est Condition Mp i Tx y Mt a Uni VREF Reference Output Voltage 25 .4 26 . 2V . T = T = -40 °C to +125°C A J Output Current 5A m I REF LV ine Regulation 80 V < AVCC < 15 1V m Load Regulation 1V 0 m 0 mA < I < 5 mA REF Error Amplifier Reference Voltage Level 0V .76 00 .74 0.75 T = 25 °C A 05 .735 0V .76 T = T = -40 °C to +125°C A J Input Bias Current 0.1 2A µ (1) Offset Voltage 2 mV (1) Open Loop Gain 80 dB (1) Unity Gain Bandwidth 3 MHz (1) Slew Rate 2.0 V/µS Output High Voltage V I=7 0.1 mA source 29 . 2. COMP Output Low Voltage I=8 0.1 mA sink 0. V COMP ZCD and RCT Frequency Range F0 requency range Min 5 KHz F0 requency range Max 100 (1) Peak Voltage C0 lamped internally 3. V (1) Valley Voltage 1.0 V (1) Timing Capacitor Discharge Current mA 11 Current Limit Cycle by Cycle Threshold V 25 .3 27 . 2. V CAO Hiccup Mode Threshold V5 EA- falling 0.37 V (1) Delay to Output 75 nS Current Amplifier offset 25 mV  2005 Semtech Corp. 3 www.semtech.com SC4901 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = 25°C, V = 12V A CC Ps arameter Tn est Condition Mp i Tx y Mt a Uni Output Drivers (1) V I=0 0.2 A Source 15 10. Output High Voltage OUTA OUTA (1) V I=0 0.1 A Source 15 10. Output High Voltage OUTB OUTB (1) V I=1 0.2 A Sink 1.2 Output Low Voltage - OUTA OUTA (1) V I=1 0.2 A Sink 1.2 Output Low Voltage - XFRA XFRA (1) V Output Low Voltage - OUTB I=1 0.1 A Sink 1.2 OUTB Rise and Fall Time C=0 2000 pF 3 nS OUTA nS C=0 1000 pF 3 OUTB OUTA Falling to OUTB Rising 1S 35 n 80 5 11 T = T = -40 °C to +125°C A J Notes: (1) Assured by design. Not tested in production. Pin Configurations Ordering Information Pe art NumberPT ackag Temp. Range ( ) A TOP VIEW (2) (1) SC4901ITSTRT TSSOP-16 -40°C to +125°C Notes: CS+ 1 16 AGND 1) Only available in tape and reel packaging. A reel CS- 2 15 ZCD contains 2500 devices. CAO 3 14 RCT 2) Lead free product. This product is fully WEEE and RoHS SSEN 4 13 VEA compliant. AVCC 5 12 VEA- OUTB 6 11 REF XFRA 7 10 OUTA PGND 8 9 PVCC  2005 Semtech Corp. 4 www.semtech.com SC4901 POWER MANAGEMENT Pin Descriptions Pe in #Pn in Nam Pin Functio Current sense non inverting input to the differential current amplifier. 1+ CS Maximum differential wrt to CS- is 200 mV. 2-C. S Current sense inverting input to the differential current amplifier 3O CA Output of the differential current amplifier. Current limit threshold is set to 2.5V at this pin. 4N SSE Soft Start and Enable pin. Taking this pin below 0.65V will shut down both the gate drives 5CA. VC Analog supply voltage. Max rating is up to 18V 6BO. UT Gate drive for the low side rectifying MOSFET Transformer connection for the gate driver of the bidirectional forward MOSFET pair. 7A XFR High current sinking open collector terminal synchronised to OUTA. Connect the lower end of the gate drive transformer to this pin. 8DP. GN Ground return for gate drive currents Power supply for the gate drive circuits. 9C PVC Bypass with a minimum of 10 uF electrolytic and a 1 uF Ceramic capacitor to PGND. 1A 0O. UT Gate drive for the high side bidirectional forward MOSFET pair Reference out voltage of 2.5V for external use. 1F 1 RE Up to 5 mA can be drawn from the pin. 1- 2 VEA Output voltage sense feedback to error amplifier inverting input. Reference level is 0.75V 1A 3V. E Error amplifier output for feedback compensation 1T 4R. C Connection pin for the timing resistor and capacitor Zero Crossover Detect. Detects the transitions of the transformer secondary and 1D 5 ZC synchronises the ramp set up by RCT components. Internally clamped to AGND on the low side 1D 6A. GN Analog Ground for all the signal return paths  2005 Semtech Corp. 5 www.semtech.com SC4901 POWER MANAGEMENT Block Diagram  2005 Semtech Corp. 6 www.semtech.com SC4901 POWER MANAGEMENT Charecteristic Curves Quiescent Current vs AVCC Current Amplifier Offset vs Temperature 8.000 4.00 7.900 3.50 7.800 3.00 2.50 7.700 2.00 7.600 1.50 7.500 1.00 7.400 0.50 7.300 0.00 7.200 -0.50 7.100 -1.00 7.000 -40 -30 -20-10 0 10 20304050 607080 90 10 11 12 13 14 15 16 17 18 19 20 Temperature (°C) AVCC Volts Internal Reference vs Temperature External Reference vs Temperature 2.51 0.7550 2.51 0.7530 2.50 0.7510 2.50 2.50 0.7490 2.50 0.7470 2.50 0.7450 2.49 -40-30-20-10 0 10 20 304050 60 7080 90 -40 -30 -20 -10 0 10 20 304050 60 7080 90 Temperature (°C) Temperature (°C)  2005 Semtech Corp. 7 www.semtech.com Quiescent Current mA Internal Ref. (mV) Current Amp Offset (mV) External Refernce SC4901 POWER MANAGEMENT Application Information Introduction ZCD and RCT The SC4901 is a voltage mode PWM controller for Since the SC4901 is specifically designed for secondary implementing secondary side synchronous rectification side control, the oscillator is always derived from the and simultaneous post regulation in forward convertors. transformer winding. Special care must be taken to ensure Multiple outputs can be derived off the same transformer that the transformer voltage, with all its variations in rise winding. Each output is independently regulated by time, shape, magnitude and duty ratio is translated into a modulating the on time of the forward MOSFET pair which steady ramp on a cycle by cycle basis. SC4901 provides acts as a bidirectional switch. An introduction to this unique two pins, ZCD and RCT, for this purpose. Combi Sync topology is presented later in this section. The device takes the transformer secondary voltage as the The transformer voltage is sensed at the Zero Crossover clock input and generates an internal ramp. The switching Detect or the ZCD pin. A limiting resistor, RZ in the Typical frequency and maximum duty cycle are always determined Application Circuit, from the winding to ZCD pin is required by the transformer waveform. to limit the peak input current into the pin to 5 mA under all conditions. The ZCD pin has two comparators with The output current is sensed as a low level differential input hysteretic thresholds. One comparator has lower thresholds signal. An amplified current signal is put out by the device of 0.75/0.25V and the other has 3.5V/2.5V. Together they for further use in current share and hot swap applications. ensure proper turn on and turn off timings for the forward Overload protection is achieved by peak current limiting and the rectifying FETs. There is also an internal clamp followed by hiccup mode under short circuit. A buffered which prevents the pin voltage from going below zero. 2.5V reference is also put out for system monitoring and Ensure that the ZCD pin is not forced into any negative other purposes. voltage by external circuits. During the rise, ZCD pin voltage is also internally clamped to one diode drop above the 3.5V The controller implements the classical trailing edge threshold. modulation and the outputs are complementary PWM VOUT signals that drive the forward and rectifying MOSFETs. The QS QF L1 SINGLE •• high side outputs can source up to + 2A peak current and ENDED QR C2 FORWARD can be easily configured for driving a pulse transformer CONVERTOR T2 T1 with duty ratios greater than 50%. RTN Undervoltage, Soft Start and Enable U? C3 D1 SC4901 The SC4901 has an operating range of 4.5V to 18V with RZ RT undervoltage lockout. Two conditions must be met before the controller is operational. The input supply should be above the undervoltage threshold of 4.5V and the SSEN pin should be above 0.65V typical. If not, the device is CT deactivated - the outputs are held active low, the SSEN and the VEA pins are also held low. The controller is in standby mode and draws only the quiescent current of 7 mA typical. Once the undervoltage threshold has been Fig 1. Generating the Zero Crossover Detect (ZCD) and the exceeded and the SSEN pin is released, the soft start Timing Ramp (RCT) signals capacitor at pin 5 is charged by a constant current of 10 µA. The VEA follows the SSEN voltage and the output The waveform at the ZCD pin should be held tightly in phase gradually ramps up. Once the SSEN pin charges to 3.3V, with the transformer secondary voltage. In some cases it the soft start cycle is complete and the device is fully may be useful to have a small capacitor in parallel with RZ operational. to speed up the rise of ZCD input.  2005 Semtech Corp. 8 www.semtech.com •• 9 8 PVCC PGND 10 7 OUTA XFRA 11 6 REF OUTB 12 5 VEA- AVCC 13 4 VEA SSEN 14 3 RCT CAO 15 2 ZCD CS- 16 1 AGND CS+ SC4901 POWER MANAGEMENT Application Information (Cont.) The RCT pin has a timing capacitor CT connected to AGND The timings for the idealised waveforms above are easier and a charging resistor RT connected to the source, which to implement if the transformer has some form of constant is typically derived from the transformer voltage. The RCT volt-second operation or control; the secondary voltage can pin is clamped to 3V peak internally and the ramp operates be directly used to charge the timing capacitor CT. The between 0V and 3V. The high side forward pulse is maximum input current into the RCT pin under clamped terminated whenever the RCT ramp hits the 3V peak. conditions should be limited to 2 mA. Turn On Sequence Ensure that the ramp reaches this peak only after the negative transition of the transformer voltage, even under Prior to transformer voltage going positive, the ramp the worst case conditions of high line and maximum capacitor is at its maximum of 3.0V. On the rising edge of applicable duty ratio. Otherwise the available pulse width transformer secondary, 0.75V at the ZCD pin is detected for post regulation will be limited. On the other hand, the first and OUTB gate drive goes low which turns off the low timing capacitor should get charged fully to 3V prior to side rectifying FET QR (Fig. 1). Simultaneously a current positive transition of the transformer voltage. This will sink of 10 mA is activated to discharge the timing capacitor ensure that the dead time between the rectifying and CT to the lower threshold of 1V. This discharge time forward gate drives is consistently maintained. Ideally the provides the delay between turn off of rectifying FET and ramp should be charged to its peak of 3V just after the turn on of the forward MOSFETs and is given by falling edge of the transformer secondary voltage so that the voltage error amplifier output utilises the full range of 0 to 3V. This is shown in the idealised waveforms below. DLon=CT× 0.2 where CT is the ramp capacitor value in pF and DLon is the dead time in nS. The actual dead time is extended by XFR SEC the propagation delays internal to the controller, which VOLTAGE should be taken into account while choosing CT. The propagation delays are typically in the range of a few tens of nanoseconds. When the RCT pin goes down to 1V, OUTA is enabled to drive the high side pair of FETs. Meanwhile, on the rising edge of ZCD pin, a higher threshold of 3.5V is detected. Once both these conditions have been met, OUTA goes high, XFRA and the forward FETs QS and QF are turned on. Setting the RCT Ramp ZCD INPUT The CT capacitor is typically charged from the transformer secondary voltage through RT. The current through RT is given by (V - V - V ) / RT where SEC FWD CT RCT RAMP = Peak of the transformer secondary voltage V SEC V = Forward drop of the signal diode (D1 in Fig 1) FWD V = Instantaneous capacitor voltage CT As a first approximation the average current can be Fig 2. Idealised ZCD and RCT waveforms assumed to be (V - 2V ) / RT. SEC  2005 Semtech Corp. 9 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) Current Sense and Current Limit Having chosen CT to meet dead time requirements, the resistor is chosen so that the ramp voltage is just below Current sensing is done as the input of an uncommitted 3.0V peak at the end of the maximum ON time. differential amplifier. The current limit threshold is 2.5V at 300000 × (Vsec − 2) × D the CAO pin. This allows the user considerable flexibility to RT ≅ Fsw × CT design the current sensing circuit. A very low value sense resistor which results in a current signal of a few tens of where millivolts or inductor drop sensing can be used for simple protection and maximum efficiency. The current amplifier RT = Timing resistor in kΩ gain has to be correspondingly higher. A larger current Fsw = Switching frequency in kHz sense signal with lower gain may be preferred for better D = Operating duty cycle at which Vsec is applied noise immunity and more precise current limit. Maximum CT = Timing capacitor in pF recommended differential input is 200 mV and minimum differential gain for the current amplifier is 10, to ensure If the primary side is PWM modulated in a feedback loop proper operation. The CAO output is typically 2V at full load. or has a volt second clamp, the product Vsec x D is fairly This signal can be brought out and used further for current constant. If it is free running with a fixed duty cycle, use sharing applications. The current sense pins have a the maximum value of Vsec. The formula assumes that maximum common mode range of AVCC - 2V. Vsec is much larger than the ramp voltage of 3.0V. For lower secondary voltages, use a smaller value of RT. When 2.5V limit is reached at CAO pin, the bidirectional forward switch QS/QF is turned off for the rest of the cycle. REF Output and Error Amplifier The rectifying FET is kept ON throughout to discharge the high inductor current. As the overload level is increased, The reference level for output voltage feedback is 0.75V the ON time continues to reduce and the output drops bandgap. This is amplified, buffered and put out as a 2.5V gradually. The output is continuously monitored for REF output. The REF voltage can be used for external undervoltage and when it falls below 50% of the nominal monitoring circuits or for regulating output voltages less voltage, an abnormal condition is detected and both the than 0.75V. The output of the error amplifier can swing outputs are shut down. The soft start capacitor is between 0.3V to 2.9V, just below the clamped peak of the discharged by a 2 uA current sink down to 0.8V at which timing ramp. The REF pin should be bypassed to AGND point a soft start cycle is initiated to restart the convertor. with a 0.1 uF ceramic capacitor. A maximum of 5 mA can This effectively provides hiccup mode of protection under be drawn from the REF output. short circuit. Delays and Turn Off Sequence Output Drivers The delay between turn off of the rectifying MOSFET QR to There are two complementary outputs designated A and the turn on of the forward MOSFETs QS and QF is B. Output A and XFRA are the PWM drives that control the determined by the discharge of the ramp capacitor CT bidirectional forward MOSFETs. The complementary output through a 10 mA current. The other delay, between turn for driving the ground referenced rectifying MOSFET QR is off of the forward MOSFETs and turn on of the rectifying designated as OUTB. This drive is capable of sourcing and MOSFET is fixed and typically 110 nS. This delay is valid sinking +1A. OUTA is enabled when the transformer when the output is in regulation and the forward FETs are voltage turns on and ZCD voltage exceeds 3.5V. It is turned turned off by the PWM comparator. During transients or if off on any one of the three conditions. the output loses regulation, QS and QF will be turned off on the falling edge of the transformer voltage. First, the a) the ramp voltage on RCT exceeds the error amplifier high comparator detects the 2.5V threshold and pulls down output at VEA or OUTA. This turns off the forward FETs. Further down, the b) ZCD detects that the transformer voltage is turning off lower comparator detects the 0.25V threshold and turns and gone below 2.5V or on OUTB. This ensures that the forward FET pair is off c) overcurrent is detected at 2.5V on the CAO pin. before transformer voltage goes negative.  2005 Semtech Corp. 10 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) In all these cases OUTA and XFRA are turned off and, after If maximum duty ratio is more than 50% a ceramic a fixed delay of 110 nS, the rectifier MOSFET is turned on. capacitor C RES may be added in series to the transformer Both OUTA and XFRA can sink or source + 2A peak current. primary as shown in Fig 3b). The capacitor carries a small voltage only when duty ratio is more than 50% which Since OUTA has to drive a level shifted MOSFET gate, it correspondingly reduces the gate drive voltage during the must be used with a pulse transformer. Note that the ON time. common source of the high side FETs presents a negative voltage to the return pin of any high side drive circuit and Alternately an additional zener Z RES may be used to reset therefore a semiconductor driver is not recommended in the transformer during the OFF time as shown in Fig 3c). this application. Another pin called XFRA is provided to The zener voltage V should be Z simplify the gate drive design with a 1:1 transformer. The XFRA is configured as a high current open collector V > PVCC x (2D -1 ) / (1-D) to reset the transformer Z transistor and is turned on and off synchronously with OUTA. If the maximum duty cycle expected is less than 50%, Note that in this arrangement the OFF voltage applied to the pulse transformer can be connected directly between the MOSFET gates increases to ( PVCC + V ). Z OUTA and XFRA. This ensures that the gate is always driven with PVCC during both on and off periods. A 1A Schottky or Inside the SC4901, the drive circuits are powered by a ultrafast rectifier should be connected in reverse across separate supply and ground pair, designated as PVCC and the XFRA transistor. This is required to discharge the PGND. Adequate and independent noise bypassing of both MOSFET gate rapidly during turn off. Refer to DTO in Fig. AVCC and PVCC to the corresponding grounds is strongly 3a) In addition, a smaller signal diode should be connected recommended. from XFRA to PVCC supply to reset the driver transformer. This diode may be rated to carry the magnetising current of the drive transformer. Refer DRES in Fig 3a) below. VSEC VOUT QS QF L SINGLE •• RGS EN DED RZ QR COUT OPTIONAL FORWARD DVCC CONVERTOR RTN CT RT PVCC RG XFRA PIN IS PROVIDED TO SIM PLIFY PULSE TRAN SFORM ER DESIGN 16 15 14 13 12 11 10 9 XFRA IS AN OPEN GND ZCD RCT VEA VEA- REF OUTA PVCC COLLECTOR THAT TURN S ON WHEN OUTA IS ON - + TRANSFORMER FOR OPERATIN G DUTY SECONDARY •• P W M L O G I C RATIOS OF 50% THE PULSE SYNC AND RAMP A N D TRAN SFORM ER IS O U T P U T DRES CONN ECTED DIRECTLY D R I V E R S BETW EEN OUTA AND XFRA +- SC4901 'DRES' RESETS THE PULSE CS+ CS- CAO SSEN VCC OUTB XFRA PGND XFR DURING THE OF F 1 2 3 4 5 6 7 8 TIM E. XFRA 'DTO' PROVIDES A HIGH C SS Current CURRENT TURN OFF PATH Sense DTO FOR THE GATE CHARGES PGND OF QS AN D QF Fig 3a. Driving a Pulse Transformer using XFRA and OUTA with < 50% duty ratio  2005 Semtech Corp. 11 www.semtech.com C VCC OUTA Gate Drive Transform er SC4901 POWER MANAGEMENT Application Information (Cont.) VSEC VOUT L QS QF SINGLE •• RGS ENDED RZ QR COUT OPTIONAL DVCC FORWARD CONVERTOR RTN CT RT PVCC XFRA PIN IS PROVIDED TO RG SIM PLIF Y PULSE TRAN SFORM ER DESIGN 16 15 14 13 12 11 10 9 C RES XFRA IS AN OPEN GND ZCD RCT VEA VEA- REF OUTA PVCC COLLECTOR THAT TURNS ON W HEN OUTA IS ON - FOR OPERATING DUTY + TRANSFORMER RATIOS OF > 50% A SECONDARY P W M L O G I C •• DRES SYNC AND RAM P CAPACITOR CAN BE A N D C ON NEC TED IN SERIES O U T P U T D R I V E R S WITH PULSE TRAN SFORM ER +- SC4901 'DRES' AND 'C RES' CS+ CS- CAO SSEN VCC OUTB XFRA PGND TOGETHER RESET THE 1 2 3 4 5 6 7 8 PULSE XFR DURING THE XFRA OFF TIM E. C SS DTO Current GATE DRIVE VOLTAGE Sense APPLIED IS REDUCED BY PGND THE VOLTAGE AC ROSS 'C RES'. THIS HAPENS ONLY W HEN D > 50% Fig 3b. Driving the Pulse Transformer with > 50% duty ratio using using a series capacitor VSEC VOUT QS QF L SINGLE •• RGS QR COUT ENDED OPTIONAL RZ DVCC FORWARD CONVERTOR RTN CT RT PVCC RG XFRA PIN IS PROVIDED TO SIM PLIFY PULSE 16 15 14 13 12 11 10 9 TRANSFORM ER DESIGN GND ZCD RCT VEA VEA- REF OUTA PVCC XFRA IS AN OPEN COLLECTOR THAT TURNS ON W HEN OUTA - IS ON + TRANSFORMER DRES SECONDARY P W M L O G I C •• FOR OPERATING DUTY RATIOS SYNC AND RAM P A N D OF > 50% A ZENER M AY BE O U T P U T ADDED IN REVERSE SERIES D R I V E R S W ITH D RES AS SHOW N Z RES +- SC4901 XFRA PIN W ILL BE STRESSED CS+ CS- CAO SSEN VCC OUTB XFRA PGND TO PVCC + ZENER VOLTAGE 1 2 3 4 5 6 7 8 DURING THE OFF PERIOD XFRA GATE VOLTAGE W ILL ALW AYS C SS Current BE EQUAL TO PVCC DURING Sense DTO ON TIM E IRRESPECTIVE OF PGND DUTY RATIO Fig 3c. Driving a Pulse Transformer with > 50% duty ratio using using a zener for reset  2005 Semtech Corp. 12 www.semtech.com C VCC C VCC OUTA Gate Drive Gate Drive Transform er Transformer SC4901 POWER MANAGEMENT Application Information (Cont.) Layout Guidelines Reference Design and Typical Waveforms The complete schematic of a secondary channel delivering The Combi Sync topology and SC4901 are intended for use in multi output convertors and demand careful 3.3V/10A is shown in Fig 4). Typical waveforms are shown attention to good layout practices. The topology has an in Figs 5) to Fig 8) These waveforms were taken on a dual output convertor with 48V input and a transformer turns inherent advantage in that all switching circuits naturally ratio of 6:1. Both outputs were generated off a single operate at the same frequency set by the primary controller. secondary winding. The primary topology was a free But the operating duty ratio is different for different outputs and this may cause unexpected interferences. Make sure running, active reset, forward convertor operating at 225 that the currents in the RTN path are kept separate and kHz. Volt second control was implemented using input feedforward with a maximum duty ratio of 65% at 40V returned to a single node at the transformer end. High input. The two outputs were rated at 3.3V/13A and 2.5V/ current returns from one output should be isolated from 13A for a total of 75W power. Of special interest are the the signal current returns going into the AGND pins of other outputs. A dedicated ground plane is strongly primary side waveforms shown in Fig 8). The zero current recommended to improve noise immunity. turn on can be clearly seen. During turn off, the current decreases as 2.5V forward FETs turn off first, followed by 3.3V output. The last small step at final turn off represents SC4901 requires a clean synchronising signal at the ZCD the magnetising current in transformer primary. pin to ensure proper operation. There are several sources that may contribute to the noise at this pin. The traces from the transformer terminals to the corresponding QS drain and QR source pins must be kept to the absolute minimum. When the FETs are turned ON or OFF, the current in the transformer secondary winding is subjected to a rapid rate of di/dt. Long traces that encompass wide areas have higher parasitic lead inductances. The combination of a rapid di/dt and large parasitic inductance is a dip or spike in the transformer waveform which can confuse the ZCD pin and lead to random transitions at the output. The series resistor RZ shown in the Typical Application Circuit should have a separate connection to the transformer secondary terminal where the source waveform is relatively free of distortions. The primary side layout also requires special attention. Excessive ringing or spikes on the primary side will be reflected to the secondary and interfere with the controller operation. It is important to physically separate the primary and secondary circuits and use separate ground planes to minimise interference. The drive transformer for the forward FETs can contribute significantly to the overall performance. For fast rise and fall times and low switching losses, choose a driver with low inductances. The traces from the transformer to OUTA and XFRA pins must be kept short to minimise the overall inductance in the drive path.  2005 Semtech Corp. 13 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) R24 R54  2005 Semtech Corp. 14 www.semtech.com 7344 7344 3.3V Q5 CSRC1 Q6 PH1 VOUT1 R20 VSEC L1 2.8 uH J2-1 TP4 D5 D6 10K GDH1 J2-2 Q11 4148 13V 4126 3704Z R22 C16 C17 C18 C19 D17 D19 4148 Q7 GDL1 4148 511R 1 uF 4 5 R23 R25 R26 T2 184 1R 10K 10K J2-3 1 8 10K RTN J2-4 R27 301K 4148 C20 C21 R28 CS+1 D7 10 uF 47 nF 301K CS-1 AVCC1 J2-5 ENA1 R29 4148 D8 D15 5.1R SC4901 4.7V R30 U3 R31 1R 100R TP5 4148 10K R32 R33 C23 1% D9 C24 100K 2R 2.2 nF OUTA1 1% 100 uF VFB1 RCT1 C25 100 pF ZCD1 R35 R34 3.3K C26 C27 C29 R36 C30 2.94K VEA1 1% 33 pF 10 uF 0.1 uF 5% NPO C28 10 pF TP3 100K 2.2 nF J2-6 RTN Fig 4) Complete secondary side schematic for a 3.3V/10A output. •• 9 8 PVCC PGND XFRA1 10 7 OUTA XFRA 11 6 REF OUTB 12 5 VEA- VCC 13 4 VEA SSEN 14 3 RCT CAO 15 2 ZCD CS- 16 1 GND CS+ 470 uF 470 uF 100 uF SC4901 POWER MANAGEMENT Application Information (Cont.) Fig 7) Transformer scondary voltage (top), FIg 5) Transformer secondary voltage and ramp at RCT rectified PWM output for 2.5V (center) pin and rectified PWM output for 3.3V (bottom) Fig 8) Primary MOSFET waveforms Fig 6) Transformer scondary voltage (top), Drain to Source Voltage (Blue) and OUTA gate drive for forward MOSFET pair (center) Current (green) . and OUTB gate drive for the rectifying FET (botom)  2005 Semtech Corp. 15 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) Combi-Sync Topology Combi-Sync is a unique secondary side topology that DR •• overcomes most of the problems associated with synchronous rectification of isolated outputs. It also QR incorporates synchronous post regulation, making it the ideal solution for low voltage, high current outputs. QF Independently regulated multiple outputs can be derived DF from a common transformer winding. The output stage replaces the conventional rectifiers and regulators with three MOSFETs, two of which switch at zero voltage. The topology inherently eliminates turn on shoot through Fig 9) Isolated Synchronous Rectification without complicated timing or look ahead circuits to maximise efficiency. All secondary switching circuits are One is that QR can conduct synchronously only while the naturally synchronised to primary which simplifies noise transformer is being reset. Thereafter there is no gate suppression. There are no separate synchronising, current voltage to drive it and the circuit must employ diode. sensing or gate driving signals crossing the isolation Secondly since the gate voltages, and the peak of boundary. In most cases, there will be no need for a transformer secondary, must be with 4.5V to 20V under separate bias supply on the secondary side further all conditions, the scheme may fail at lower voltage and simplifying the system design. wide input ranges. The primary side in a Combi-Sync circuit is a typical single An alternative is to use a control driven approach where a ended forward convertor which may be regulated or free synchronous controller provides the gate drive. This running. An additional benefit of the Combi-Sync topology provides the low loss FET conduction over the entire cycle is the zero current turn on and turn off for the primary and is not limited by output or input ranges. However it is MOSFET as well. The free running mode is preferred when not without its own problems. At the instant transformer there are multiple outputs without minimum load and cross voltage turns positive the body diode of QF gets forward regulation constraints. Input voltage feedforward is biased. At the same time, QR would also be fully conducting recommended to achieve volt-second clamp and minimise and the result is a shorted winding just when the primary core losses in the free running mode. switch is trying to turn ON. To prevent catastrophe it is necessary to turn QR OFF prior to transformer voltage going Background on Synchronous Rectification and Post positive. This requires an advanced signal from the primary Regulation side crossing the isolation boundary. Attempts have been made to avoid this by complex timing or look ahead circuits The synchronous rectifier technology is widely used in non on the secondary side itself and several patents have been isolated DC-DC convertors but its use has been limited in issued for them. isolated convertors because of various difficulties. An example of synchronous rectification on the secondary side It should be understood that all these techniques for of a forward convertor is shown in Fig 9. DF and DR are isolated synchronous rectification have been restricted to the parasitic body diodes of their respective FETs. The a single unregulated secondary output. . . The existing . . forward MOSFET QF is turned ON when the transformer circuits only rectify the output but do not synchronously secondary voltage goes positive and the rectifying MOSFET regulate it any further. Nor is it possible to generate multiple QR is turned ON when the transformer secondary is outputs from the same winding. Post regulation of the negative. Two approaches have been used to drive the isolated outputs has been implemented so far using either MOSFETs. One is the self driven scheme where the the saturable magnetic inductor or a power MOSFET in transformer secondary itself provides the gate voltage for series with the forward diode. The saturable magnetic the appropriate FET. While the scheme is simple and has element is bulky and inefficient at high frequencies. The a very low cost, it has several limitations. circuit with series MOSFET is widely known and well documented. Fig 10) shows a standard implementation.  2005 Semtech Corp. 16 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) The series FET QS is turned ON and OFF in a controlled d) After the forward FETs QS and QF are turned OFF, the manner synchronously with the secondary waveform. The rectifying FET QR is turned after a short delay. QR continues width of the ON time pulse is varied to regulate the output. to conduct until the beginning of the next cycle when transformer secondary voltage goes positive again. By modulating the ON time of the high side power MOSFETs DS output regulation is achieved. T This arrangement of MOSFETs and their control provides QS OUTPUT •• a highly efficient combination of synchronous rectification C and simultaneous control of isolated secondary voltages. Trailing Edge Modulation The Combi Sync topology offers the option of both leading and trailing edge modulations to achieve synchronous post regulation. With leading edge modulation, QS and QF are turned on during the forward mode, with a PWM dictated Fig 10) Synchronous Post Regulation delay, but the turn off is synchronised to the falling edge of the transformer voltage. This results in zero current turn Again it should be understood that all previous attempts on for the primary switch but a hard turn off with full load. have used a non synchronously rectified secondary. . . That . . On the other hand, in conventional secondary side post is, the transformer secondary was rectified using power regulation, the trailing edge modulation results in hard turn diodes and the series MOSFET was added to synchronously on and zero current turn off for the primary switch. However, regulate it further. the Combi Sync topology already has an inherent turn on The Combi Sync Technique delay for the forward FETs on the secondary side. This ensures zero current turn on for the primary switch, The Combi Sync, as the name indicates is a unique irrespective of the modulation scheme used. It is therefore secondary configuration that combines synchronous advantageous to use trailing edge modulation which now rectification and post regulation on transformer isolated results in both zero current turn on and turn off for the multiple secondary voltages. The proposed implementation primary switch. If some form of ZVS is used in primary as well as typical waveforms are shown in Fig 11) on the control, all of the switching losses may be eliminated on next page. The highlights of its operation are as follows the primary side. Trailing edge modulation is the method employed in SC4901. a) Prior to the transformer voltage going positive, the Switching Waveforms rectifying MOSFET QR is conducting. When the voltage goes positive, QR is turned OFF. Theoretical switching waveforms of the Combi Sync topology are shown on the next page. The first is the b) After a delay, both QF and QS are turned ON. This delay transformer secondary voltage which acts as the reference. prevents both high and low side FETs conducting at the Second and third are the gate drives for forward and same time and shorting the secondary winding. rectifying FETs respectively. Rectified and pulse width modulated output that appears before the LC filter stage c) The forward pair of QS and QF acts as a bidirectional is shown next. Notice that this rectified output rises after a switch and can be turned off in a controlled manner delay which is crucial to isolated synchronous rectification. irrespective of the polarity of the transformer voltage. This In the simple isolated synchronous rectifiers, there is no is the key to the topology. With SC4901 the forward pair is QS, and QF begins to conduct (initially through its body turned off on any of the following conditions i) end of the diode) at the same instant as the transformer voltage going active PWM duration ii) peak current crosses the overload positive. Transformer secondary and inductor currents are limit or, iii) transformer secondary voltage begins to fall. also shown. The delay T1-T0 is set by the capacitor CT and the T3-T2 delay is fixed internally in SC4901  2005 Semtech Corp. 17 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) FIg 11) Theoretical waveforms of Combi Sync topology DS DF L Sec C urrent Ind C urrent T QS QF OUTPUT SINGLE ENDED •• QR FORWARD C Vsec DR Vrec GATE F CONVERTOR GATE R PRIM ARY +VE Vsec Transform er Sec Voltage -VE GATE F Gate Drive for Forward MOSFETS QS, QF GATE R Gate Drive For QR Vrec Pulse W idth M odulated by RECTIFIED SECON DARY VOLTAGE Secondary Side Controller W ITH POST REGULATION Transform er Secondary C urrent Inductor C urrent T0 : Transformer secondary voltage goes +ve, QR is turned OFF at this instant. T1 : Forward MOSFETs QS and QF are switched ON T1 - T0 : Forward delay to prevent shorting the secondary winding T0 T1 T2 T3 T2 : QS, QF are turned OFF. This edge is Pulse Width Modulated to post - regulate the output. T3 : QR is turned ON T3 - T2 : Turn OFF delay to prevent shoot through  2005 Semtech Corp. 18 www.semtech.com SC4901 POWER MANAGEMENT Application Information (Cont.) Features and Applications of the Combi Sync Circuit f) It is necessary to drive the forward FETs through a with SC4901 transformer interface. The common source of the two devices is a floating return and will swing to the peak The Combi Sync topology is quite versatile and has a negative voltage appearing at the transformer secondary; number of useful features see the Vsec waveform in Fig 11). This negative swing does not allow a semiconductor device to be used for a) There is no connection between primary and secondary driving the forward FET pair. An additional pin called XFRA sides. No synchronising signals, drive pulses, voltage or is provided in SC4901 to simplify the design of driver current information needs to be exchanged across the transformer interface, particularly with duty ratios of >50%. isolation boundary. The bias supply for the controller is XFRA is an open collector sink which turns on and off also generated on the secondary side, eliminating the simultaneously with OUTA. additional burden of a low power bias supply. SC4901 is designed to operate over a range of 4.5V to 18V AVCC g) The no load condition at the output needs special supply which is the typical range for MOSFET gate drives. consideration in this topology. Under light load, the inductor current is negative as in any synchronous rectifier. When b) For multiple secondary windings, each winding can have the synchronous MOSFET QR is turned off, the current is its own set of synchronous MOSFETs and each set can be interrupted and tends to charge the drain source capacitor controlled by an individual SC4901 to generate of QR. The back to back connected forward FETs prevent independently regulated outputs. There is no cross this current being returned to the source. The resulting regulation or minimum load requirement, each output can overshoot on QR can be clamped by connecting a zener be turned ON or OFF independently of others. Placing the and diode combination across the inductor as shown in controller on the secondary side also helps to optimise Fig 4). The zener clamp conducts only during the dead the transient response. time and also provides a small benefit of reducing the voltage across the forward FETs during turn on. The detailed c) It is possible to have multiple sets of synchronous FETs application schematic in Fig 4) shows diode D1 and zener attached to the same transformer secondary and control D2 connected across the output inductor L1 to reduce the them individually as shown in Fig 12. This way multiple no load spike. secondary outputs with a common ground can be regulated DS1 DF1 L1 off the same secondary winding. QS1 QF1 OUTPUT1 •• QR1 d) All secondary switching is synchronised automatically C1 DR1 GATE DRV1 with the transformer waveform. There is only one switching frequency in the convertor which simplifies EMI filter DS2 DF2 design. Zero current switching of the primary FET further L2 reduces the switching noise generated on the primary side. QS2 QF2 OUTPUT2 QR2 C2 DR2 GATE DRV2 e) A number of options can be used to generate and control the transformer secondary voltage. i) The primary may be free running, that is without being regulated by a feedback loop. It may further employ DSN DFN constant volt second operation to reduce magnetic LN stresses. In this mode the duty cycle is always at an QSN QFN OUTPUT N optimum value to maximise the efficiency. QRN CN DRN GATE DRV N ii) The primary may be regulated in a feedback loop by one of the outputs; such regulation will typically employ voltage mode or average current mode control. Note that peak Fig 12) Generating Multiple Outputs from the same current mode control is not suitable with the trailing edge secondary winding using Combi Sync Topology modulation.  2005 Semtech Corp. 19 www.semtech.com SC4901 POWER MANAGEMENT Outline Drawing - TSSOP-16 DIMENSIONS INCHES MILLIMETERS NOTES: A DIM D e MIN NOM MAX MIN NOM MAX A - - .047 - - 1.20 N 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). - - A1 .002 .006 0.05 0.15 A2 .031 - .042 0.80 - 1.05 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 2X E/2 - - b .007 .012 0.19 0.30 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS c .003 - .007 0.09 - 0.20 OR GATE BURRS. E1 E D .192 .196 .201 4.90 5.00 5.10 E1 .169 .173 .177 4.30 4.40 4.50 4. REFERENCE JEDEC STD MO-153, VARIATION AB. PIN 1 E .252 BSC 6.40 BSC INDICATOR e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 (.039) (1.0) ccc C 1 2 3 L1 e/2 N 16 16 2X N/2 TIPS 01 0° - 8° 0° - 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW Land Pattern - TSSOP-16 X DIMENSIONS DIM INCHES MILLIMETERS (.222) (5.65) C G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 20 www.semtech.com