SEMTECH SC4810B

SC4810B/E High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay POWER MANAGEMENT Description Features The SC4810B/E is a 16 pin BICMOS primary side PWM ‹ Operation to 1MHz controller for use in Isolated DC-DC and off-line switching ‹ Accurate programmable maximum duty cycle power supplies. It is a highly integrated solution, requiring ‹ Line voltage monitoring few external components. It features a high frequency ‹ External frequency synchronization of operation, accurately programmable maximum duty ‹ Bi-phase mode of operation for low ripple cycle, current mode control, line voltage monitoring, supply ‹ Independent programmable delays UVLO, low start-up current, and programmable soft start ‹ Hiccup mode current limit with user accessible reference. It operates in a fixed ‹ Under 250µA start-up current frequency, highly desirable for Telecom applications. The ‹ Programmable maximum volt-second clamp output for switch is complementary to each other with ‹ Accessible reference voltage programmable delay between each transition. The active ‹ VDD undervoltage lockout technique allows single ended converters beyond 50% ‹ -40°C to 105°C operating temperature duty cycle and greater flux swing for the power transformer while reducing voltage stresses on the ‹ 16 lead TSSOP or MLPQ lead free packages. Both switches. The separate sync pin simplifies synchronization fully WEEE and RoHS compliant to an external clock. Feeding the oscillator of one device Applications to the sync of another forces biphase operation which reduces input ripple and filter size. ‹ Telecom equipment and power supplies ‹ Networking power supplies The SC4810B/E has a turn-on voltage threshold of 7V. ‹ Power over LAN applications In the SC4810B, OUT2 is inverted to drive the N-MOSFET. ‹ Industrial power supplies In the SC4810E, OUT2 is non-inverted to drive the ‹ Isolated power supplies P-MOSFET. These devices are available in a TSSOP-16 or ‹ VoIP phones MLPQ-16 lead package. Typical Application Circuit D1 T1 R1 D3 L1 C1 D2 Q1 Vout C2 D4 +48V C3 C4 R2 C5 C6 Q2 C7 U1 R3 T2 SC1302A R4 D5 C8 R7 C9 R6 R5 2 7 U2 C10 6 13 R9 Q3 RAMP OUT2 4 5 3 15 SYNC OUT1 R11 R10 4 10 RCT CS SC4810 U3 5 11 C11 DMAX FB R8 R12 R13 1 7 16 6 DELAY1 VREF R15 5 2 R14 C12 C13 8 9 DELAY2 SS R16 C14 C15 Q4 U4 R17 R18 R19 SC431L R20 R22 R21 R23 C16 Revision: July 27, 2006 1 www.semtech.com 12 2 GND LUVLO 14 1 PGND VDD 8 6 1 3 7 SC4810B/E POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Pl arameter Sm ymbo Ms aximu Unit SV upply Voltage 1V 9 DD SI upply Current 2A 5 m DD LV UVLO 1V 0 LUVLO SS, DMAX, RCT, FB, CS, RAMP, SYNC -0.3V to V+V 0.3V REF CI urrent VREF 1A 5 m REF CI urrent LUVLO -A 1 m LUVLO ST torage Temperature Range -C 65 to +150 ° STG JT unction Temperature Range -C 40 to +150 ° J LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD PT eak IR Reflow Temperature 20 - 40 Sec. 2C 60 ° PKG Electrical Characteristics Unless specified: V = 12V, C = 1nF, F = 420kHz, R = 10k, C = 220pF, D = 2V, R = 75kΩ, T = T = -40ºC to 105ºC DD SS OSC T T MAX DELAY A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni Supply Section Supply Voltage 1V 5 I V=N 15V, O LOAD 35 .5 4A . m DD DD ISS hutdown S=00 V 10 0 2A 5 µ DD Ramp Section Ramp Clamp Threshold Voltage 3V UVLOSection (B/E version) Start Threshold 8488 . 8V . Hysteresis 2V  2006 Semtech Corp. 2 www.semtech.com SC4810B/E POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 12V, C = 1nF, F = 420kHz, R = 10k, C = 220pF, D = 2V, R = 75kΩ, T = T = -40ºC to 105ºC DD SS OSC T T MAX DELAY A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni VREF Section VA REF (B/E version) 05 - 5m 45 .8 5V .15 Line Under Voltage Lockout Start Threshold 23 .91 3V .09 Hysteresis 1V 50 m (1) Input Bias Current L0 UVLO = 3.2V -A 10 n Comparator Section (1) CS Input Current -A 200 n PWM to OUT Propagation Delay 7s 5 n (1) (No Load) CurrentLimitSection Current Limit Threshold 55 90 60 2 6V 6 m (1) I to OUT Propagation Delay 7s 5 n LIM SoftStartSection I V=5 0V -5 2. -5-A 7. µ SS SS Shutdown Threshold 5V 00 m Oscillator Section (2) Frequency Range 50 0 1z 10 kH RCT Peak Voltage 3V .00 RCT Valley Voltage 0V .05 M1 aximum Duty Cycle D5 MAX = 2.8V, OUT 8% M1 aximum Duty CycleD9 MAX = 1.25V, OUT 2% Frequency 30 80 40 2 4z 6 kH Sync/CLOCK Cd lock SYNC Threshold P2 ositive Edge Triggere V (1) Minimum Sync Input Pulse Width F>0 Fosc 5s n SYNC  2006 Semtech Corp. 3 www.semtech.com SC4810B/E POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 12V, C = 1nF, F = 420kHz, R = 10k, C = 220pF, D = 2V, R = 75kΩ, T = T = -40ºC to 105ºC DD SS OSC T T MAX DELAY A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni OutputSection (OUT1 and OUT2) OI utput VSAT Low =0 5mA sinking 5V 0 m OUT OI utput VSAT High =V 5mA sourcing-V 0.6 OUT REF (1) Rise Time C=0 20pF 1s n OUT (1) Fall Time C=0 20pF 1s n OUT Program Delay Section OUT1 Fall to OUT2 Rise (SC4810B) 1s 20 n OUT2 Fall to OUT1 Rise (SC4810B) 1s 40 n OUT1 Fall to OUT2 Fall (SC4810E) 1s 20 n OUT2 Rise to OUT1 Rise (SC4810E) 1s 40 n Notes: (1) Guaranteed by design. (2) Guaranteed by characterization. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2006 Semtech Corp. 4 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Configurations Ordering Information (2) (1) PartNumber Package Temp.Range (T ) TOP VIEW J SC4810BITSTRT TSSOP-16 VDD 1 16 VREF SC4810EITSTRT -40°C to 105°C LUVLO 2 15 OUT1 SC4810BIMLTRT SYNC 3 14 PGND MLPQ-16 SC4810EIMLTRT RCT 4 13 OUT2 DMAX 5 12 GND Notes: (1) Only available in tape and reel packaging. A reel RAMP 6 11 FB contains 2500 devices for TSSOP and 3000 parts DELAY 1 7 10 CS for MLP package. DELAY 2 8 9 SS (2) Lead free product. This product is fully WEEE and RoHS compliant. (16 Pin TSSOP ) TOP VIEW (16 Pin MLPQ)  2006 Semtech Corp. 5 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Descriptions Pin # Pin # Pn in Name Pin Functio TSSOP MLPQ 151D VD The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor. 261O LUVL Line undervoltage lock out pin. An external resistive divider will program the undervoltage lock out level. During the LUVLO, the Driver OUT1 is disabled and the softstart is reset. OUT2 continues with a fixed on time of DELAY 1 + DELAY2 approximately. 31 SYNC SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC frequency should be 30% greater for guaranteed SYNC operation. 42 RCT The oscillator frequency is configured by connecting resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT frequency. 1 F =    V  P−K   − (RT +1k) • CT • ln 1−     V   REF    where VP-K = RCT peak voltage 53 DMAX Duty cycle up to 95% can be programmed via R18 and R12 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. 64 RAMP A resistor from the RAMP to the input voltage and a capacitor from the RAMP to GND forms the ramp signal of maximum allowable volt-second product. The RAMP is discharged to GND when OUT1 is low and allowed to charge when OUT1 is high. A volt-second comparator compares the ramp signal to 3V to limit the maximum allowable volt-second product: Volt-second product clamp = 3 •Rramp • Cramp. 75 DELAY1 A resistor from these pins to GND programs the non-overlap delay time between OUT1 and OUT2. 86 DELAY2 A resistor from these pins to GND programs the non-overlap delay time between OUT2 and OUT1.  2006 Semtech Corp. 6 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Descriptions (Cont.) Pin # Pin # Pn in Name Pin Functio TSSOP MLPQ 97 SS This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 5µA current source. Under normal soft start SS is discharged to less than 0.65V and then ramps positive to 1V during which time the OUT1 is held low. As SS charges from 1V to 2.5V, soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 4V (A and D) or 5V (B, C and E) voltage reference also goes low and IDD = 100µA. 18 0 CS Current sense input is provided via the CS pin. The current sense input from a sense resistor provides current feedback to the PWM comparator and current limit signal to terminate the PWM pulse. When a pulse peak voltage provided at this pin exceeds 600mV, a soft-restart sequence will follow. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal PNP transistor. 19 1 FB This pin is used to generate a reset signal when compared to CS for the PWM comparator with an offset voltage of 600mV and 1/2 attenuation. The feedback analog signal from the output of an error amplifier or an opto-coupler will be connected to this pin to provide regulation. 10 2 1DG. N Signal ground for all functions 11 3 12 OUT This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the complementary switch. 12 4 1D PGN Ground connection for the gate drivers. Connect PGND and GND at a single point. 13 5 11 OUT This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the main switch. 14 6 1F VRE The 5V reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0µF ceramic capacitor. NL /A THERMA Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not PAD connected internally.  2006 Semtech Corp. 7 www.semtech.com SC4810B/E POWER MANAGEMENT Block Diagram  2006 Semtech Corp. 8 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information Introduction Circuit Description The SC4810B/E is a 16 pin BICMOS peak current mode The schematic of the active clamp forward converter is controlled PWM controller for isolated DC-DC and off- illustrated in Figure. 1 below. T4 is the power transformer. line switching power supplies. It features a high switching M17 is the N-channel main switching MOSFET and M15 frequency of operation, programmable limits for both is the auxiliary N-channel MOSFET. C35 is the reset power transformer voltage-second product and maximum capacitor for resetting the power transformer’s core. M14 PWM duty cycle, line under-voltage lockout, auxiliary switch and M16 construct the synchronous rectification circuit. activation complementary to main power switch drive, L2 and C32 and C33 construct the low-pass output programmable leading-edge delay time between filtering circuit. T6 is the current sensing transformer. R62 activation of each switch, multiple protection features is the reset resistor for resetting the magnetic core of with programmable cycle -by-cycle current limit and hiccup the current sensing transformer. D18 is the rectifying mode over-current protection plus soft-restart. It diode. R63 is the current sensing resistor. R60 and C41 operates in a fixed frequency programmed by external construct the low-pass filtering circuit for the sensed components. The separate sync pin simplifies current signal. The primary bias circuit consists of R55, synchronization to an external clock. Feeding the oscillator R58, D17, Q8, C40, C31, D14 and R51. R55 and R58 of one device to the sync of another forces biphase construct a voltage divider, which limits the bias voltage operation which reduces input ripple and input and output to 6.9V until the line voltage reach 36V. D17 is a zener filter size. diode that limits the bias voltage to under 8V. R51, D14 The SC4810 can be applied in an active clamp forward and C31 construct the peak charge circuit. The peak topology with the input voltage ranging from 36V to 72V. charge circuit will provide bias to the PWM IC U9 (SC4810) This topology allows the converter to achieve an efficiency and the driver U8 (SC1302A) after the converter starts of 92.4% at normal input voltage of 48V. Figure 1: Active Clamp Forward Converter 1N4148WS R50 3.3V/30A D13 T4 10 D14 1N4148WS M14 R51 1 5.11 Si4842DY 11 C31 5.11 7 0.1uF 6 1.3uH 100uF L2 C32 48V 8 C33 2 9 680uF C35 8 1 M15 C34 3300pF 7 2 Si4488DY 1u,100V 6 3 4 5 4 R53 10K 10K R52 D15 1N4148WS R54 M16 Q7 C36 20K Si4842DY FZT458 0.1uF R55 8 1 R56 30K 7 2 10K 6 3 R57 Q8 T5 5 4 FZT458 PE68386 0.1uF 5.11K C39 C37 C38 D16 R58 0.1uF 0.1uF 1K 8K D17 1N4148WS open C40 open P8208T D18 R60 R59 10uF T6 8 1 R61 10 1.1M D19 R62 R63 330pF 7 3 C41 1N5819HW 10K 6.8 C42 M17 open SC1302A Si4488DY U8 C43 R65 R66 R67 R64 100pF 100K 2 7 165k open U9 50 R68 1K C44 220pF 6 13 RAMP OUT2 4 5 3 15 R69 SYNC OUT1 D20 C45 10K R70 R71 1N5819HW open open 10K 4 10 RCT CS SC4810 R72 R73 5.11K C46 5 11 DMAX FB open 3.01K C47 R74 U10 4.3K 0.01uF 100K 7 16 DELAY1 VREF U11 R75 SC431 MOC207 C49 8 9 0.1uF 1 R76 180pF DELAY2 SS C48 6 3.01K Q9 R77 5 2 FMMT718 R78 18K R79 1000pF 5.6K C50 100K R80 1.47K R81 4.7K R82 C51 5.11K 0.01uF  2006 Semtech Corp. 9 www.semtech.com 12 2 GND LUVLO 14 1 PGND VDD 8 6 1 3 1 6 3 4 4 5 3 6 2 7 1 8 7 4 5 3 6 2 7 1 8 SC4810B/E POWER MANAGEMENT Application Information (Cont.) A self-driven configuration was adopted on the secondary up so that the total power loss is less. D19, R59, C37, side for driving the synchronous rectification FETs. One T5, C36, D15 and R53 construct the driving circuit for extra winding (Pin8~Pin9) was added at the bottom side the auxiliary reset switch M15. The secondary side bias of the power transformer’s secondary side to drive the circuit composed of R50, D13 and C38 is regulated to freewheeling FET. The forward FET was driven directly about 7.5V via a linear regulator composed of R57, Q7 from the top of the power winding. Primary side auxiliary D16 and C39. The feedback of the converter is composed winding was used to generate primary side bias to improve of U10 (SC431), U11, R73, C47, C45, R72, R76, R70 the converter’s efficiency. and C46. The final configuration of the power transformer is SC4810 is the PWM controller which processes the illustrated as Fig. 2. voltage feedback plus current signal and generates driving signals to drive the main switch and auxiliary reset switch. SC1302A is a dual driver IC which is capable of sourcing 3A peak current. To obtain the best performance, SC1302A is adopted to drive M17 and M15 in the 2 11 Semtech application circuits. SC4810 features dual 6T(PRI) 1T(SEC) complementary driving signals. And SC4810 also provides 4 10 adjustable leading-edge delay time for the driving signals, 9 1 which helps to achieve zero-voltage switching in active 1T(SEC AUX) 2T(PRI AUX) clamp forward converter. R75 and R79 are the two 8 resistors available to adjust the delay for the 6 complementary driving. C50 is the soft-start capacitor. 1T(SEC) R61 and R65 construct the voltage divider for the line 7 under voltage lock out protection. R64 and C44 construct Fig.2 Illustration of the power transformer the circuit for the programmable power transformer PA0944G (PUSLE ENGINEERING) voltage-second production protection limits. This special protection function provide the voltage-second balance for the power transformer under different input line conditions. R78 and R74 also provide an extra maximum Power MOSFET Selection duty cycle protection for the power converter. The selection of the switching power MOSFET is based on the peak & RMS current rating, the total gate charge, Rds and drain to source voltage rating. In this application, The clock signal is generated by C49 and R77. When VDD SI4842 was chosen for the secondary side synchronous of SC4810 hits the threshold voltage, VREF jumps up to 5.0V. VREF charges C49 via R77. C49 will be discharged rectification MOSFET. And SI4488 was chosen for the via an internal FET whenever the voltage on C49 reaches primary side main switching and reset MOSFET. 3.0V. The selection of C49 and R77 is described in the Output Filter Design “Set Clock Frequency” section on the following page. Q9 The output filtering circuit consists of the output inductor works as a buffer between the clock signal and the slope compensation signal to minimize the interference on the and output capacitors. The design of the output capacitor system clock signal. R80 is a pull-up resistor tied to VREF. usually depends on the specification of the requirement of the output ripple. Given the worst case output ripple Since SYNC function is not utilized, SYNC pin is grounded requirement and peak to peak output current ripple plus via R71. the duty ratio under the different line and load condition, Power Transformer Design output capacitance is calculated to meet the output ripple A power transformer with the turns ratio of 6 to 1 was requirement. After all, ESR and ESL of the output capacitor under certain switching frequency should also designed for this application. With the turns ratio of 6:1, be considered during the calculation. The value of the the duty ratio under different input line and load conditions output inductance would affect the peak to peak value were calculated to verify feasibility. of the output current, which would also influence the  2006 Semtech Corp. 10 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) output voltage ripple. The designer needs to take the output inductance and output capacitance and the ESL VRCT and ESR of the output capacitor into consideration during 3V VPK the design. 0V t For this application, one Panasonic power choke output Fig.4 Voltage Waveform on RCT Pin inductor was selected and three 6.3V, 100uF TDK ceramic capacitors were adopted in the design. As illustrated, the capacitor C is charged via the resistor Selection of the Current Sensing Resistor R from VREF. Whenever the voltage on the RCT pin reaches 3V, the capacitor C will be discharged through The selection of the current sensing resistor is based on an internal FET shorted to ground. When the clock signal the over-current protection triggering point. SC4810 circuit is connected as in Fig.3, the frequency of the clock employs a Hiccup mode over-current protection with an signal is defined, as in equation 2. overcurrent threshold of 600mV. A voltage signal above 600mV on the CS pin will trigger hiccup mode overcurrent 1 protection. Suppose the over-current protection setpoint F = ........(2)     V P−K is set to be Iov. The threshold voltage of SC4810 is − (RT + 1k) • CT • ln 1−      V  REF     Vthreshold. The turns ratio of the power transformer is Ns/Np. The turns ratio of the current sensing transformer is Ncs:1. Then the Rsense would be calculated as: V is the reference voltage of the SC4810, 4V for REF SC4810A/D and 5V for SC4810B/C/E. V × N × N Threshold P CS R = ......(1) In this application, to get 600kHz, C = 180pF, sense I × N OV S (R + 1k) = 10k ohms and V = 3V. P-K Maximum Duty Ratio Limit Set Clock Frequency SC4810 features maximum duty ratio limitation for ex- The SC4810 uses a pair of resistors and capacitors to tra protection. The maximum duty ratio is determined by generate a triangle signal as the clock signal, as illustrated the voltage on DMAX pin. As illustrated as in Fig. 5, V in Fig. 3. DMAX will be compared with V and DMAX is determined by RCT the comparison of the two signals. VRCT RCT VREF R C Fig. 3 Configuration for Clock Signal The voltage waveform on the RCT pin is illustrated as in Fig. 4.  2006 Semtech Corp. 11 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) Voltage waveform on RAMP pin Clock Signal of SC4810 VRAMP VRCT 3V 3V VDMAX 0V t 0V t OUT1 Maximum OUT1 of SC4810 DMAX 0V t 0V Fig. 6 Illustration of the programmable limits for power t transformer voltage-second product Fig. 5 Illustration for DMAX In this application, V was designed to be 2.8V. So the DMAX D = 90%. MAX V IN Limit for Power Transformer Voltage Second Product R The SC4810 also features programmable limits for power RAMP transformer voltage-second product. As illustrated in Fig. 6 and Fig. 7 RAMP pin is charged up via a resistor R from C the input line voltage. The capacitor C will be discharged via an internal FET shorted to ground and the output OUT1 will be pulled low whenever the voltage on RAMP pin hits 3V. By adjusting the values of the resistor R and Fig. 7 Illustration for Maximum voltage- the value of the capacitor C, the maximum voltage-sec- second product on the power transformer ond product imposed on the power transformer is pre- set. The maximum voltage-second product limitation helps The selection of the R and C should consider the maxi- prevent saturation of the power transformer. mum voltage rating of the main switching FET. In this application, the voltage rating of SI4488 is 150V. Since Vin*D/(1-D) = 150V, D = 0.8 for low line 36V. So to get 80% at low line, R = 165kOhms and C = 220pF were selected using volt-second product equation: 3 • Ramp • Cramp.  2006 Semtech Corp. 12 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) VDD and LUVLO SC4810 features three different input turn-on voltage thresholds, as specified in the Electrical Characteristics on page 2. V starts to regulate when the supply voltage REF on the VDD pin is above the turn-on voltage threshold. V drops to ground when VDD is lower than the turn-on REF threshold minus the hysteresis value. The soft start cap remains grounded as long as LUVLO is below the thresh- old voltage 3V. The soft start cap will be charged up through an internal 5uA current source when LUVLO is above the threshold voltage. Soft Start The soft-start function is implemented by charging the soft-start cap through an internal 5uA current source. Under normal soft-start, the SS pin is discharged below 0.65V and ramps up to 1V, during which time the output driving signals OUT1 and OUT2 are held low. During the time when the SS pin is charged from 1V to 2.5V, soft- start is implemented by an increasing output duty ratio. The duty ratio is completely under the control of the feedback after the SS pin is above 2.5V. When the SS pin is pulled down below 0.5V, OUT1 and OUT2 will be held low and the VREF pin will be grounded via an internal FET. Complementary Driving with Programmable Delays The SC4810 features dual driving signals to drive two power switches complementarily. This feature makes the SC4810 suitable for a variety of applications in which Over Current Protection dual complimentary driving signals are needed. The SC4810 even provides programmable driving delay as The SC4810 provides Hiccup mode over-current an extra feature for applications such as active-clamp protection when the sensed current signals are beyond forward topology. The users can program the driving delay 0.6V. When the hiccup mode over-current protection is by adjusting the resistors tied to pin DELAY1 and pin triggered, the soft-start cap will be discharged DELAY2 respectively to achieve the optimum delay for immediately by an internal grounded FET. When the soft- each output. The delay of OUT1 is controlled by the start pin SS is pulled down below 1V, OUT1 and OUT2 will resistor tied to pin DELAY1 and the delay of OUT2 is be disabled, and a soft re-start sequence will follow. controlled by the resistor tied to pin DELAY2. For illustration, see Fig. 8. SC4810 can also be configured to implement cycle-by- cycle over-current limit. As illustrated in Fig. 9, cycle-by- cycle over-current limitation can be achieved by adjusting the values of R1 and R2 to limit the voltage of FB pin to less than the threshold voltage (0.6Volt) of the hiccup over-current protection, using equations (3) and (4).  2006 Semtech Corp. 13 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) guaranteed synchronization. SYNC pin should be grounded if synchronization is unused. (The patent for the synchronization scheme is pending). VREF VBias The synchronous function is illustrated as in Fig. 10. R3 R1 Vout FB Clock Signal of the Master SC4810 VRCT R4 3V R2 2.1V SC431 R5 GND 0V t Fig.9 Cycle-by-cycle over-current limitation OUT1 of the Master SC4810 V = 2 • V +1.3V........(3) FB CS R 2 V = V • ........(4) FB REF R + R 1 2 0V t Synchronization SC4810 features a special synchronization function OUT1 of the Slave SC4810 which is leading-edge triggered with a threshold set to 2.1V. Applications like multi-phase interleaving can be achieved using the SYNC pin. When the SYNC pin is con- nected to the RCT pin of the master SC4810, the out- 0V puts of the two SC4810’s will be out of phase. The fre- t quency of the master SC4810 clock signal should be at least 30% faster than that of the slave SC4810 for the Fig. 10 Illustration for Synchronization  2006 Semtech Corp. 14 www.semtech.com SC4810B/E POWER MANAGEMENT Applications Information (Cont.) PCB Layout Guidelines PCB layout is very critical, and the following should be 6) The feed back connection between the error ampli- used to insure proper operation of the SC4810. High fier and the FB pin should be kept as short as possible, switching currents are present in applications and their and the GND connections should be to the quiet GND effect on ground plane must be understood and used for the SC4810. minimized. 7) If an opto-coupler is used for isolation, quiet primary and secondary ground planes should be used. The same 1) The high power parts of the circuit should be placed precautions should be followed for the primary GND plane on a board first. A ground plane should be used. Isolated as mentioned in item 5. For the secondary GND plane, or semi-isolated areas of the ground plane may be delib- the GND plane method mentioned in item 4 should be erately introduced to constrain ground currents to par- followed. ticular areas, for example the input capacitor and the 8) All the noise sensitive components such as VDD by- main switch FET ground. pass capacitor, RCT oscillator resistor/capacitor network, 2) The loop formed by the Input Capacitor(s) (Cin), the DMAX resistive divider, VREF by pass capacitor, delay main transformer and the main switch FET must be kept setting resistors, current sensing circuitry and feedback as small as possible. This loop contains all the high fast circuitry should be connected as close as possible to the transient switching current. Connections should be as SC4810. The GND return should be connected to the wide and as short as possible to minimize loop induc- quiet SC4810 GND plane. tance. Minimizing this loop area will a) reduce EMI, b) 9) The connection from the OUT of the SC4810 should lower ground injection currents, resulting in electrically be minimized to avoid any stray inductance. If the layout “cleaner” grounds for the rest of the system and c) mini- can not be optimized due to constraints, a small Schottky mize source ringing, resulting in more reliable gate switch- diode may be connected from the OUT pin to the ground ing signals. directly at the IC. This will clamp excessive negative volt- 3) The connection between FETs and the main trans- ages at the IC. former should be a wide trace or copper region. It should 10) If the SYNC function is not used, the SYNC pin should be as short as practical. Since this connection has fast be grounded at the SC4810 GND to avoid noise pick up. voltage transitions, keeping this connection short will minimize EMI. 4) The output capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load cur- rents are supplied by Cout only. Connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) A 0.1uF to 1uF ceramic capacitor should be directly connected between VDD and PGND and a 1uF to 4.7uF ceramic capacitor between VREF and PGND. The SC4810 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin and the main switch FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VDD supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin and the main switch FET loop. This can be achieved by making a star connection between the quiet GND planes that the SC4810 will be connected to and the noisy high current GND planes connected to the FETs.  2006 Semtech Corp. 15 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - Schematic  2006 Semtech Corp. 16 www.semtech.com D1 D2 Q1 FMMT618 10Vbias R54 5.1 C1 2.2nF/630V 1N4148WS 1N4148WS R2 R3 R1 5.1K C2 5.11K R12 0.1uF 5.11 D4 C3 C52 5.1K T1 D3 C4 0.1uF 0.1uF MMSZ4698(11V) Vout=3.3V/20A PA0944G 0.1uF MMSZ4702(15V) 10 Q3 TP4 TP5 D5 1N4148WS L1 FZT853 1 1.3uH M1 Open M2 Open M3 Si4842DY M4 Si4842DY D8 11 C5 MMSZ4698(11V) 7 0.1uF 6 Vin=48V C6 8 C7 C8 C9 680uF 2 9 100uF 100uF 100uF M6 Open 8 1 8 1 M5 C13 C10 C11 C12 7 2 7 2 Si4488DY 1u,100V 1u,100V 1u,100V 22nF/100V 6 3 4 6 3 R8 5 4 5 4 10K R9 10K R10 TP3 M7 SI2308 10K M8 Si4842DY TP2 8 1 7 2 Q2 6 3 FMMT718 5 4 M9 SI2308 TP6 TP14 R61 D6 R13 200K Q10 1N4148WS open M10Si4842DY FMMT493 8 1 D7 7 2 D20 TP7 6 3 1N4148WS MMSZ4697(10V) D21 R15 5 4 C15 0.1uF open C16 1N4148WS 47uF/16V C17 T2 R18 180pF PE68386 1K R57 P8208T T3 5.1 8 1 R56 R19 R20 5.1 10K 8.2(16//16) C18 7 3 0.1uF TP9 R22 M14SI2308 C53 R21 M11 Open 1uF 1.1M 10 D9 M12 Open U2 M13 C20 1N5819HW Si4488DY C19 1uF R23 C21 R24 1uF 100pF 160K 100K 2 7 U3 TP10 SC1302A C22 220pF D10 1N4148WS 6 13 RAMP OUT2 4 5 R52 3 15 D11 R28 51 Q5 SYNC OUT1 10K 1N5819HW FMMT718 R30 10K 4 10 RCT CS SC4810 10Vbias 5 11 DMAX FB R62 R31 4.75K R50 7.5K 7 16 R16 1K open U1 MOCD207 C23 open DELAY1 VREF TP8 8 1 R32 R37 C25 8 9 C24 5.1K R34 1K C51 220pF 100K DELAY2 SS 1uF R60 open Q6 open 7 2 C14 R14 R35 FMMT718 R36 C26 10K 0.1uF R17 7.5K R33 open open 47nF C50 1K 100K U6 R38 6 3 1.47K SC431 R42 2.4K R63 R40 5 4 10K 15.8K R25 5.1K U4 R43 C27 R44 SC431 R29 10K 0(short) 1.5K 6.34K TP11 TP12 TP13 12 2 GND LUVLO 14 1 PGND VDD 8 6 1 3 1 6 3 4 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - BOM Item Quantity Reference Part Package Manufacturer P/N 1 1 C1 2.2nF/630V SM0805 TDK C3216X7R2J222K C2,C3,C4,C5, 211 C15,C18,C19, 0.1uF SM0805 C20,C50,C52,C53 3 1 C6 680uF SM/CT_7343_12 Sanyo 4TPB680M 4 3 C7,C8,C9 100uF SM/C_1812 TDK C4532X5ROJ107MT 5 3 C10,C11,C12 1u,100V SM/C_1210 TDK C3225X7R2A105K 6 1 C13 22nF/100V SM1206 TDK C3216X7R2J223M 8 1 C16 47uF/16V SM/CT_7343 Sanyo 16TQC47M 9 1 C17 180pF SM0805 10 1 C21 100pF SM0805 11 2 C25,C22 220pF SM0805 12 1 C24 1uF SM0805 13 1 C26 47nF SM0805 14 1 C27 0(short) SM0805 D1,D2,D5, 15 7 1N4148WS SOD123 Vishay 1N4148WS D6,D7,D10,D21 16 1 D3 MMSZ4702(15V) SOD123 On Semi MMSZ4702T1 17 2 D4,D8 MMSZ4698(11V) SOD123 On Semi MMSZ4698T1 18 2 D9,D11 SL04 SOD123 Vishay SL04 19 1 D20 MMSZ4697(10V) SOD123 On Semi MMSZ4697T1 20 1 L1 1.3uH PCC-S1 Panasonic ETQPAF1R3EFA 22 4 M3,M4,M8,M10 Si4842DY SO-8 Vishay Si4842DY 23 2 M5,M13 Si4488DY SO-8 Vishay Si4488DY 24 3 M7,M9,M14 SI2308 SOT-23 Vishay SI2308 25 1 Q1 FMMT618 SOT-23 Zetex FMMT618 26 3 Q2,Q5,Q6 FMMT718 SOT-23 Zetex FMMT718 27 1 Q3 FZT853 SM/SOT223_BCEC Zetex FZT853 28 1 Q10 FMMT493 SOT-23 Zetex FMMT493 29 1 R1 5.11 SM0805 30 4 R2,R12,R25,R32 5.1K SM0805 31 1 R3 5.11K SM0805 R8,R9,R10,R19, 32 9 10K SM0805 R28,R30,R35,R43,R63 33 1 R13 open SM1206 34 1 R16 1K RC0805 35 3 R17,R18,R34 1K SM0805  2006 Semtech Corp. 17 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - BOM (Cont.) 36 1 R20 8.2 SM0805 37 1 R21 1.1M SM0805 38 1 R22 10 SM0805 39 1 R23 160K SM0805 40 1 R24 100K SM0805 41 1 R29 6.34K SM0805 42 2 R31,R36 7.5K SM0805 43 2 R33,R37 100K SM0805 44 1 R38 1.47K SM0805 45 1 R40 15.8K SM0805 46 1 R42 2.4K SM0805 47 1 R44 1.5K SM0805 48 1 R52 51 SM0805 49 3 R54,R56,R57 5.1 SM0805 50 1 R61 200K SM0805 51 1 R62 4.75K SM0805 53 1 T1 PA0944G PA0646 Pulse PA0944G 54 1 T2 PE68386 PE68386 Pulse PE68386 55 1 T3 P8208T P8208 Pulse P8208T 56 1 U1 MOCD207 SO-8 Fairchild MOCD207 57 1 U2 SC1302A MSOP-8 Semtech SC1302A 58 1 U3 SC4810 TSSOP16 Semtech SC4810 59 2 U4,U6 SC431 SOT-23 Semtech SC431  2006 Semtech Corp. 18 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - Schematic  2006 Semtech Corp. 19 www.semtech.com D1 D2 Q1 FMMT618 10Vbias R54 5.1 C1 2.2nF/630V 1N4148WS 1N4148WS R2 R1 R3 5.1K C2 5.11K 0.1uF R12 5.11 D4 C3 C52 5.1K T1 D3 C4 0.1uF 0.1uF MMSZ4698(11V) PA0944G MMSZ4702(15V) Vout=3.3V/20A 0.1uF 10 Q3 TP4 TP5 D5 1N4148WS L1 FZT853 1 1.3uH D8 M1 Open M2 Open M3 Si4842DY M4 Si4842DY 11 C5 MMSZ4698(11V) 7 0.1uF 6 Vin=48V C6 C7 C8 C9 8 680uF 2 9 100uF 100uF 100uF M6 Open M5 C13 8 1 IRF6216 C10 C11 C12 7 2 22nF/100V 1u,100V 1u,100V 1u,100V 1 8 4 6 3 R8 R10 2 7 5 4 10K R9 10K 10K 3 6 M7 SI2308 TP3 4 5 M8 Si4842DY TP2 8 1 D6 7 2 6 3 5 4 M9 SI2308 R61 TP6 TP14 1N5819HW R13 200K Q10 open M10 Si4842DY FMMT493 8 1 7 2 D20 C18 TP7 6 3 MMSZ4697(10V) 0.1uF R15 D21 5 4 open C16 1N4148WS 47uF/16V C17 R18 180pF 1K R57 R22 P8208T T3 5.1 2 8 1 R56 R19 R20 5.1 10K 8.2(16//16) 7 3 TP9 M14SI2308 C53 R21 1uF 1.1M M12 M13 D9 Open U2 Si4488DY C20 1N5819HW C19 1uF R23 C21 R24 1uF 160K 100pF 100K 2 7 U3 TP10 SC1302A C22 220pF D10 1N4148WS 6 13 RAMP OUT2 4 5 R52 3 15 D11 Q5 R28 51 SYNC OUT1 1N5819HW 10K FMMT718 R30 10K 4 10 RCT CS SC4810 10Vbias 5 11 DMAX FB R62 R31 4.75K R50 7.5K 7 16 R16 1K open C23 open DELAY1 VREF U1 MOCD207 TP8 8 1 R32 R37 C25 8 9 1uF 5.1K DELAY2 SS R34 1K C51 220pF 80.6K C24 R60 open Q6 7 2 open C14 R14 R35 R36 FMMT718 C26 10K 7.5K R33 0.1uF R17 open open 47nF 80.6K C50 1K U6 R38 6 3 1.47K SC431 R42 2.4K R63 R40 5 4 10K 15.8K R25 5.1K U4 R43 C27 R44 SC431 R29 10K 0(short) 1.5K 6.34K TP11 TP12 TP13 12 2 GND LUVLO 14 1 PGND VDD 8 6 1 3 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 4 5 3 6 2 7 1 8 SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - BOM Item Quantity Reference Part Package Manufacturer P/N 1 1 C1 2.2nF/630V SM0805 TDK C3216X7R2J222K C2,C3,C4,C5,C18, 210 0.1uF SM0805 C19,C20,C50,C52,C53 3 1 C6 680uF SM/CT_7343 Sanyo 4TPB680M 4 3 C7,C8,C9 100uF SM/C_1812 TDK C4532X5ROJ107MT 5 3 C10,C11,C12 1u,100V SM/C_1210 TDK C3225X7R2A105K 6 1 C13 22nF/100V SM1206 TDK C3216X7R2J223M 8 1 C16 47uF/16V SM/CT_7343 Sanyo 16TQC47M 9 1 C17 180pF SM0805 10 1 C21 100pF SM0805 11 2 C25,C22 220pF SM0805 12 1 C24 1uF SM0805 13 1 C26 47nF SM0805 14 1 C27 0(short) SM0805 15 5 D1,D2,D5,D10,D21 1N4148WS SOD123 Vishay 1N4148WS 16 1 D3 MMSZ4702(15V) SOD123 On Semi MMSZ4702T1 17 2 D4,D8 MMSZ4698(11V) SOD123 On Semi MMSZ4698T1 18 3 D6,D9,D11 SL04 SOD123 Vishay SL04 19 1 D20 MMSZ4697(10V) SOD123 On Semi MMSZ4697T1 20 1 L1 1.3uH PCC-S1 Panasonic ETQPAF1R3EFA 22 4 M3,M4,M8,M10 Si4842DY SO-8 Vishay Si4842DY 23 1 M5 IRF6216 SO-8 I. R. IRF6216 24 3 M7,M9,M14 SI2308 SOT-23 Vishay SI2308 25 1 M13 Si4488DY SO-8 Vishay Si4488DY 26 1 Q1 FMMT618 SOT-23 Zetex FMMT618 27 1 Q3 FZT853 SM/SOT223 Zetex FZT853 28 2 Q5,Q6 FMMT718 SOT-23 Zetex FMMT718 29 1 Q10 FMMT493 SOT-23 Zetex FMMT493 30 1 R1 5.11 SM0805 31 4 R2,R12,R25,R32 5.1K SM0805 32 1 R3 5.11K SM0805 R8,R9,R10,R19, 33 9 10K SM0805 R28,R30,R35,R43,R63 35 1 R16 1K SM0805  2006 Semtech Corp. 20 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - BOM 36 3 R17,R18,R34 1K SM0805 37 1 R20 8.2 SM0805 38 1 R21 1.1M SM0805 39 1 R22 2 SM0805 40 1 R23 160K SM0805 41 1 R24 100K SM0805 42 1 R29 6.34K SM0805 43 2 R31,R36 7.5K SM0805 44 2 R33,R37 80.6K SM0805 45 1 R38 1.47K SM0805 46 1 R40 15.8K SM0805 47 1 R42 2.4K SM0805 48 1 R44 1.5K SM0805 49 1 R52 51 SM0805 50 3 R54,R56,57 5.1 SM0805 51 1 R61 200K SM0805 52 1 R62 4.75K SM0805 54 1 T1 PA0944G PA0646 Pulse PA0944G 55 1 T3 P8208T P8208 Pulse P8208T 56 1 U1 MOCD207 SO-8 Fairchild MOCD207 57 1 U2 SC1302A MSOP-8 Semtech SC1302A 58 1 U3 SC4810 TSSOP16 SC4810 Semtech 59 2 U4,U6 SC431 SOT-23 Semtech SC431  2006 Semtech Corp. 21 www.semtech.com SC4810B/E POWER MANAGEMENT Outline Drawing - TSSOP-16 DIMENSIONS A INCHES MILLIMETERS DIM D e MIN NOM MAX MIN NOM MAX - - - - N A .047 1.20 - - A1 .002 .006 0.05 0.15 - A2 .031 .042 0.80 - 1.05 2X E/2 - - b .007 .012 0.19 0.30 c - - .003 .007 0.09 0.20 E1 E D .192 .196 .201 4.90 5.00 5.10 E1 .169 .173 .177 4.30 4.40 4.50 PIN 1 E .252 BSC 6.40 BSC INDICATOR e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 ccc C 1 2 3 L1 (.039) (1.0) e/2 N 16 16 2X N/2 TIPS - - 01 0° 8° 0° 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB. Land Pattern - TSSOP-16 X DIMENSIONS DIM INCHES MILLIMETERS C (.222) (5.65) G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.  2006 Semtech Corp. 22 www.semtech.com SC4810B/E POWER MANAGEMENT Outline Drawing - MLPQ-16, 4 x 4 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A D - - A .031 .040 0.80 1.00 B - - A1 .000 .002 0.00 0.05 A2 - (.008) - - (0.20) - b .010 .012 .014 0.25 0.30 0.35 D .153 .157 .161 3.90 4.00 4.10 PIN 1 D1 .100 .106 .110 2.55 2.70 2.80 INDICATOR E E .153 .157 .161 3.90 4.00 4.10 (LASER MARK) E1 .100 .106 .110 2.55 2.70 2.80 e .026 BSC 0.65 BSC L .012 .016 .020 0.30 0.40 0.50 N 16 16 aaa .003 0.08 bbb .004 0.10 A2 A SEATING aaa C PLANE A1 C D1 e/2 LxN E/2 E1 2 1 N e bxN bbb C A B D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.  2006 Semtech Corp. 23 www.semtech.com SC4810B/E POWER MANAGEMENT Land Pattern - MLPQ-16, 4 x 4 K DIMENSIONS DIM INCHES MILLIMETERS (.156) (3.95) C G .122 3.10 2x Z H 2x (C) 2x G H .106 2.70 .106 2.70 K P .026 0.65 X .016 0.40 Y Y .033 0.85 Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 24 www.semtech.com