SEMTECH SC4809B

SC4809A/B/C High Performance Current Mode PWM Controller POWER MANAGEMENT Description Features The SC4809A/B/C is a 10 pin BICMOS primary side ‹ Operation to 1MHz current mode controller for use in Isolated DC-DC and ‹ Accurate programmable maximum duty cycle off-line switching power supplies. It is a highly integrated ‹ Line voltage monitoring solution, requiring few external components. It features ‹ External frequency synchronization a high frequency of operation, accurately programmable ‹ Bi-phase mode of operation for low ripple maximum duty cycle, current mode control, line voltage ‹ Under 100µA start-up current monitoring, supply UVLO, low start-up current, and ‹ Accessible reference voltage programmable soft start with user accessible reference. ‹ VDD undervoltage lockout It operates in a fixed frequency, highly desirable for ‹ -40°C to 105°C operating temperature Telecom applications. Features a separate sync pin which ‹ 10 lead MSOP package. Lead free package available. simplifies synchronization to an external clock. Feeding Fully WEEE and RoHS compliant the oscillator of one device to the sync of another forces biphase operation which reduces input ripple and filter Applications size. ‹ Telecom equipment and power supplies The SC4809A/B/C have different threshold and VREF ‹ Networking power supplies to accommodate a wide variety of applications. ‹ Power over LAN applications ‹ Industrial power supplies These devices are available in the MSOP–10 lead free ‹ Isolated power supplies package. Typical Application Circuit T1 +48V C1 R2 R1 D1 D2 U1 SC4809 C7 C8 Vout 1 10 U2 VDD VREF SC1301 R3 2 9 1 LUVLO OUT IN 5 EN Q2 R13 3 8 2 R12 SYNC SYNC GND GND 4 OUT 4 7 3 RCT FB VCC 5 6 DMAX SS U3 R9 C9 R4 R10 R6 R7 U4 C3 R8 R11 SC4431 R14 R5 Q1 C2 C4 C5 C6 -- 48V DISABLE Revision: September 21, 2005 1 www.semtech.com SC4809A/B/C POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit SV upply Voltage 1V 9 DD SI upply Current 2A 5 m DD SS, UVLO, DMAX, RCT -0.3V to V+V 0.3V REF CI urrent VREF 1A 5 m REF CI urrent LUVLO -A 1 m LUVLO ST torage Temperature Range -C 65 to +150 ° STG JT unction Temperature -C 40 to +150 ° J Thermal Resistance θ 1W 13 °C/ JA LT ead Temperature (Soldering) 10 Sec. +C 300 ° LEAD ED SD Rating (Human body model) E2 S kV Electrical Characteristics Unless specified: V = 12V, C =1nF, F = 500kHz, R = 10K, C = 100pF, D = 2V, T = T = -40ºC to +105ºC. DD SS OSC T T MAX A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni Supply Section VDD Clamp 15 6 19 7. 1V B version I 15 .5 2A . m DD I Starting 1A 10 µ DD UVLOSection (Aversion) Start Threshold 45 .35 4V . Hysteresis 0V .3 UVLOSection (B version) Start Threshold 12 1 1V Hysteresis 4V UVLOSection (C version) Start Threshold 65 .55 6V .9 Hysteresis 0V .75 VREF Section VA REF (A version) 0% - 5m -4 3 +V 3% VA REF (B, C version) 0% - 5m -5 3 +V 3%  2005 Semtech Corp. 2 www.semtech.com SC4809A/B/C POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 12V, C =1nF, F = 500kHz, R = 10K, C = 100pF, D = 2V, T = T = -40ºC to +105ºC. DD SS OSC T T MAX A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni Line UnderVoltage Lockout SR tart Threshold = 61.9k, R=% 10k -3 3 -V 3% A B HR ysteresis = 61.9k, R=0 10k 1V 5 m A B IV nput Bias Current L0 UVLO = 3.2 -0 10 -A 25 n ComparatorSection If FB O0 utput Of -A 10 n Comparator Threshold (A, B version) 50 70 60 0 6V 3 m Comparator Threshold (C version) 90 50 10 00 1V 05 m OV UT Propagation Delay (No Load) = 0.8V to 1.2V at T=5 10ns 701s 0 n FB R SoftStartSection I V=T 0V; -40 °C <+2 105°C-0-A 8. µ SS SS a Shutdown Threshold (A, B version) 30 003V 4 m Shutdown Threshold (C version) 40 405V 0 m OscillatorSection Frequency range 50 0 1z 10 kH RCT Peak Voltage 3V .00 RCT Valley Voltage 0V .05 MV inimum Duty Cycle Pulse Width =0 2V 5s n FB Maximum Duty Cycle 9% 0 Sync/CLOCK Cd lock SYNC ThresholdP1 ositive Edge Triggere 2V . MF inimum Sync Input Pulse Width >0 Fosc 5s n SYNC OutputSection OI utput VSAT Low =0 1mA 5V 0 m OUT OI utput VSAT High =V 1mA -V 0.5 OUT REF RC ise Time =0 20pF 152s n OUT FC all Time =0 20pF 152s n OUT  2005 Semtech Corp. 3 www.semtech.com SC4809A/B/C POWER MANAGEMENT Pin Configuration Ordering Information (1) Pe artNumber Packag Temp.Range (T ) J Top View SC4809AIMSTR (2) SC4809AIMSTRT MC SOP-10 -40°C to +150° SC4809BIMSTR (2) SC4809BIMSTRT SC4809CIMSTR (2) SC4809CIMSTRT Notes: MSOP-10 (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.  2005 Semtech Corp. 4 www.semtech.com SC4809A/B/C POWER MANAGEMENT Pin Descriptions FB: This pin is the summing node for current sense feed- DMAX: Duty cycle up to 98% can be programmed via R4 back, voltage sense feedback (by optocoupler) and slope and R5 (the resistor divider from Vref in the Application compensation. Slope compensation is derived from the Circuit). When DMAX pin is taken above 3V, 100% duty rising voltage at the time capacitor and can be buffered cycle is achieved. with an external small signal NPN transistor. External high frequency filter capacitance applied from this node SS: This pin serves two functions. The soft start timing to GND is discharged by an internal 250Ω on-resistance capacitor connects to SS and is charged by an internal NMOS FET during PWM off -time and offers effective lead- 8µA current source. Under normal soft start SS is dis- ing edge blanking set by the RC time constant of the charged to less than 1V and then ramps positive to 1V feedback resistance from the current sense resistor to during which time the output driver is held low. As SS the FB input and the high frequency filter capacitor ca- charges from 1V to 2V, soft start is implemented by an pacitance at this node to GND. increasing output duty cycle. If SS is taken below shut- down threshold, the output driver is inhibited and held GND: Reference ground and power ground for all func- low. The user accessible voltage reference also goes tions. low and IDD < 100µA. OUT: This pin is the logic level drive output to the exter- VDD: The power input connection for this device. This pin nal MOSFET driver circuit (similar to SC1301). is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD VREF: The internal 4V (A) / 5V (B & C) reference output. should be bypassed with a 1µF ceramic capacitor. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0µF ce- LUVLO: Line undervoltage lock out pin. An external resis- ramic capacitor. tive divider will program the undervoltage lock out level. During the LUVLO, the Driver outputs are disabled and RCT: The oscillator frequency is configured by connect- the softstart is reset. ing resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT SYNC: SYNC is a positive edge triggered input with a and CT can be selected to provide the desired OUT fre- threshold set to 2.1V. In the Bi-Phase operation mode quency. the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force 1 F = a out of phase operation. In a single controller opera-     V P−K tion, SYNC could be grounded or connected to an exter-   − RT • CT • ln 1−     V   REF  nal synchronization clock with a frequency higher than   the on-board oscillator frequency. The external OSC fre- quency should be 30% greater for guaranteed SYNC where V = RCT peak voltage P-K operation.  2005 Semtech Corp. 5 www.semtech.com SC4809A/B/C POWER MANAGEMENT Block Diagram Marking Information Top Mark Top Mark Top Mark AF0A AF0B yyww AF0C yyww yyww Bottom Mark Bottom Mark Bottom Mark xxxx xxxx xxxx xxxx xxxx xxxx Part Number (Example: 1456) yyww = Datecode (Example: 0012) xxxxx = Semtech Lot # (Example: E901 xxxxx = 01-1)  2005 Semtech Corp. 6 www.semtech.com SC4809A/B/C POWER MANAGEMENT Flyback, 90V - 300V to 5V @ 1A typ. Applications Information  2005 Semtech Corp. 7 www.semtech.com Q1 FZT458 D1 SD103C R1 Z1 750k BZX84C12 D3 L1 US1B T1 (Opt.) 11 C4 Z3 C1 90 - 300VDC 47/400V SMBJ85 1/450V C13 Np2 R5 Np1 4.7/20V/1.8 Ohm 510 C2 C3 R2 D2 2.2n 2.2n 2M US1G Z2 U1 CMZ5929 C5 D4 SC4809 L2 0.1 B240 C12 10uH R3 0.1 820k 1 10 U2 VDD VREF + SC1301A C18 Ns1 C19 C20 330/6.3V/0.04 Ohm 2 9 1 5V@1A LUVLO OUT IN 10uF/6.3V 0.1 Q3 _ R6 5 R4 C11 EN C6 IRFR420 10k 0.33 100k 100p 3 8 2 SYNC GND GND R12 2.2 4 OUT R17 R18 C21 R16 2.2n 1k 3k 4 7 3 150 RCT FB VCC C14 C16 R13 220pF C7 2.7n 300 100p 5 6 DMAX SS 71 6 C9 C17 33n 1n R20 Fsw = 500kHz 316 5 2 R7 R8 R9 R19 R14 U3 10k 7.5k 4.3k 5.6k R15 100 MOC207 1.5 C10 Vcc 1n C15 R10 U4 0.1 1k SC4431 R21 102 Q2 FMMT718 R11 C8 3k 0.1 T1 CRITICAL COMPONENTS: ----------------------------------------- Core: EFD15, 3C85 Q3: IRFR420, Dpak, Inter.Rect. Magnetizing L = 230uH B240, SMB, Vishay Np1 = 24 ts C17: 6TPB330M, "7343", Sanyo Np2 = 5 ts L2: TOKO, A920CY-100M or similar Ns1 = 2 ts U1: SC4809AIMSTR, MSOP-10, SEMTECH Approximate Gap = 0.038mm U2: SC1301AISKTR, SOT-23-5, SEMTECH AL value = 397 nH/N² U4: SC4431CSK, SOT-23-5, SEMTECH SC4809A/B/C POWER MANAGEMENT Application Information The flyback power stage is very popular in 48V input telecom applications for output power levels up to approximately 50 watts. The exact power rating of the flyback power stage, of course, is dependent on the input voltage/output voltage combination, its operating environment and many other factors. Additional output voltages can be generated easily by simply adding another winding to the coupled inductor along with an output diode and output capacitor. Obtaining multiple output voltages from a single power stage is another advantage of the flyback power stage. A simplified schematic of the flyback power stage with a drive circuit block included is shown in Figure 1. In the schematic shown, the secondary winding of the coupled inductor is connected to produce output voltage. The power switch, Q1, is an N-channel MOSFET. The secondary inductance, L and capacitor C, make up the SEC output filter, The resistor R, represents the load seen by the power supply output. Figure 2: Discontinuous Mode Flyback Waveforms The simplified voltage conversion relationship for the flyback power stage operating in CCM is given by: Figure 1: Flyback Power Converter N D S V = V • • O I N 1− D P The important waveforms of the flyback power stage operating in DCM are shown in Figure 2. The simplified voltage conversion relationship for the flyback power stage operating in DCM is given by: N D S V = V • • O I N K P Where K is defined as: 2 • L SEC K = R • T S  2005 Semtech Corp. 8 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) Control-to-Output transfer function for the flyback power The DC transfer function of a CCM flyback converter is: stage operating in CCM is given by:   V + V 1 D O D max   = •   V − V N 1− D     S S IN(min) Rds(on)  max  1+  • 1−      ω ω dV V N O S  z1   z2  I = • • 2 2 dD N where V = output voltage, (1− D) S S P O 1+ + 2 ω • Q ω O O V = forward voltage drop across rectifier D1, D where: N = turns ratio, equal to N /N , P S 1 ωz1 = R • C D = duty cycle. C 2 (1− D) • R ω ≈ z2 Transformer Design D • L SEC 1− D ω ≈ The transformer in a flyback converter is actually a coupled O L • C SEC inductor with multiple windings. Transformers provide (1− D) x R coupling and isolation whereas inductors provide energy Q ≈ storage. The energy stored in the air gap of the inductor L SEC is equal to: C 2 L •() I P PEAK E = Control-to Output transfer function for the flyback power 2 stage operating in DCM is given by: where E is in Joules, L is the primary inductance in P Henries, and I is the primary peak current in Amperes. dV N R • T 1 PEAK O S S = V • • • I When the switch is on, D1 is reverse biased due to the S dD N 2 • L P SEC 1+ dot configuration of the transformer. No current flows in ω P the secondary windings and the current in the primary where: winding ramps up at a rate of: 2 V − V ΔI ω = IN(min) Rds(on) P L = R • C Δ t L P Peak current mode control requires simpler The output capacitor, C , supplies all of the load current OUT compensation, has pulse-by-pulse current limiting, and at this time. Because the converter is operating in the has better load current regulation. Primary and secondary continuous conduction mode, ΔI is the change in the L RMS currents can be up to two times higher for inductor current which appears as a positive slope ramp discontinuous mode than for CCM. Discontinuous on a step. The step is present because there is still conduction mode would require using a transistor with a current left in the secondary windings when the primary higher current rating. Because the output ripple current turns on. When the switch turns off, current flows through is less than it would be continuous mode were used, the the secondary winding and D1 as a negative ramp on a output capacitors are smaller. Continuous conduction step, replenishing C and supplying current directly to OUT mode (CCM) was therefore chosen. the load.  2005 Semtech Corp. 9 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) MOSFET Selection The primary inductance can be calculated given an The switching element in a flyback converter must have acceptable current ripple, ΔI . ΔI was set to equal one- L L a voltage rating high enough to handle the maximum input half the peak primary current. For a CCM flyback design, voltage and the reflected secondary voltage, not to the peak primary current is calculated: mention any leakage inductance induced spike that is inevitably present. Approximate the required voltage  I    1 ΔI OUT(max) L rating of the MOSFET using.     I = • + PEAK     N 1− D 2    max      N P   V =() V + V + •() V + V •1.3   ds IN(max) L O D   N    S    Because the converter is operating in the continuous mode, the maximum peak flux density B , is limited by MAX where V = the required drain to source voltage rating of the saturation flux density, B . Taking all this into ds SAT the MOSFET, consideration, the maximum core size is determined by. 1.31 4   L •I •I •10 P PEAK RMS = the voltage spike due to the leakage inductance of V   AP = L   420 • k •B the transformer, estimated to be thirty percent of V ,  MAX  IN(MAX) and the additions 1.3 factor includes an overall thirty 4 percent margin. where AP = the core area product in cm , k = winding factor, This FET will experience both switching and conduction B ≈ B , 2 MAX SAT losses. The conduction losses will be equal to the I R losses, as shown by: The result is compared to the product of the winding area, 2 2 2 Aw (cm ), and effective core area, Ae (cm ), listed in the P =() I •R COND RMS DS(ON) core manufacturer’s data sheet. Switching losses are the result of overlapping drain The minimum number of primary turns is determined by: current and drain to source voltage at turn on and turn 4 L •I •10 P PEAK off. N = P B • Ae MAX The total switching losses are estimated based on equation: Based upon this result and the predetermined turns ratio, 2 the number of secondary turns is established. C • (V ) • f OSS DS SW P = + V •I • t • f SW DS PEAK ch sw 2 The energy stored in the flyback transformer is actually where t : ch stored in an air gap in the core. This is because the high permeability of the ferrite material can’t store much Q •R gd g energy without saturating first. By adding an air gap, the t = CH VDD − V hysteresis curve of the magnetic material is actually tilted, gs(th) requiring a much higher field strength to saturate the core. The length of the air gap is calculated by: Diode Selection 2 −2 Schottky rectifiers have a lower forward voltage drop than µ • µ • (N ) • Ae •10 o r P l = g typical PN devices, making it the rectifier of choice when L P considering reducing converter losses and improving overall efficiency. Selecting the appropriate Schottky for a specific application depends mainly on the working peak reverse voltage rating and peak repetitive forward current.  2005 Semtech Corp. 10 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) Slope Compensation Input and Output Capacitors Sensing peak inductor current instead of average The input capacitors are chosen based upon their ripple inductor current results in a loop response that is Less current rating and their rated voltage. The actual capacitor than ideal. Adding slope compensation to the current value is not that critical as long as the minimum signal cancels this error by maintaining a constant average capacitance gives an acceptable ripple voltage current independent of duty cycle. Slope compensation determined by the following equation: is required for open loop stability in a current mode system I RMS C = with 50% or greater duty cycles, but will benefit any MIN 8 • f • ΔV SW current mode application at the cost of a few small parts. The output capacitors are also chosen based upon their Loop Compensation low equivalent series resistance (ESR), ripple current and voltage ratings. The ripple current that the output The continuous current mode flyback will contain a right- capacitor experiences is a result of supplying the load half-plane (RHP) zero in its transfer function. Any increase current during the FET conduction time and its charging in load current will require the primary peak inductor current during the FET off-time. current to increase. The duty cycle must increase to accomplish this. In a flyback converter, the inductor Voltage Feedback current flows to the output only when the FET is off and the diode is conducting. Increasing the duty cycle The FB pin of the SC4809 sums the voltage feedback increases the FET condition time but decreases the diode signal to the current sense signal and any added slope conduction time. The result of this is the average diode compensation. The voltage feedback signal is from an current, the current that supplies the load, actually optocoupler, which is driven from an error amplifier on decreases. This is a temporary situation; as the inductor the secondary side of the converter. The signal from the current rises, the diode current eventually reaches its optocoupler is designed to trip the FB threshold of the proper value. The condition where the average diode SC4809 internal comparator when the output voltage current must actually decrease before it can increase is exceeds its specified limit. referred to as a right-half-plane zero. To complicate matters, this zero contributes a phase lag, not a phase Current Limit lead as a normal zero would. This zero moves in frequency as a function of load and input voltage, making it Selection of the current sense resistor is accomplished impossible to cancel out by the insertion of a pole. by dividing the FB threshold value by the peak primary current at the desired current limit point. This ground- 2 N• V IN referenced R must be a low inductance type and have f = SENSE RHPZERO 2 • π •R •L • (V + N• V ) 2 OUT P IN OUT a rated power level to meet the (I ) • R RMS SENSE requirement. The easiest way to deal with a right-half-plane zero is to roll off the loop gain at a relatively low frequency using Current spikes caused by the leakage inductance of the simple dominant pole compensation. Unfortunately, the flyback transformer and the reverse recovery of the diode result of this is poor dynamic response. could trip the current sense latch and prematurely shut off the output. This unwanted spike can be suppressed The primary goal of the compensation network is to by adding a small RC filter for effective leading edge provide good line and load regulation and dynamic blanking. response. These objectives are best met by providing high gain at low frequencies for good DC regulation and high bandwidth for good transient response. Optimum closed loop performance can only be achieved by first  2005 Semtech Corp. 11 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) knowing what the transfer characteristic of the PWM and The scheme shown below will handle most compensation switching circuit looks like. Constructing a Bode plot of requirements. There is a pole at the origin which the known poles and zeros in the power stage does this. contributes a -1 slope in the gain plot, a low frequency Bode plots give a visual interpretation of the gain versus zero, f flattens out the slope so the mid-range gain EAZERO frequency and phase versus frequency characteristics is equal to Rf/Ri. A high frequency pole, f helps EAPOLE of a system. In the gain plot, the gain shown at each suppress any high frequency noise from propagating frequency represents the amount by which the feedback through the system. Rd forms a voltage divider with Ri loop will reduce a disturbance at that frequency. and provides a DC offset. Besides the RHP zero, the output capacitor and the load 1 contribute a pole and the output capacitor alone will f = EAZERO 2 • π •R • C f f contribute a zero based upon its ESR. 1 1+ D f = EAPOLE f = 2 • π •R • C pole f p 2 • π •R • C OUT OUT 1 f = zero 2π •ESR • C OUT The control to output gain is calculated by:  I •R • V  SC OUT IN GAIN = 20 • log•   V • (1− D) • (2 •N • V + V )  C O IN  Once the frequency response of the uncompensated system is determined, the next step is to determine what compensation is needed around the error amplifier for optimum performance. As stated earlier, optimum By combining the Bode plots of the PWM and power stage performance requires a high gain at low frequencies for with the error amplifier compensation, a plot of the entire good DC regulation and high bandwidth for good transient system is realized. response. The crossover frequency, f , is the frequency c at which the gain magnitude equals 0dB. High bandwidth is achieved by having the highest possible f . Because of c the RHP zero, the highest possible crossover frequency is limited to f /π. The phase margin, or the amount RHPZERO the phase lag measures at f less 180°, should be at c least 45° for good transient response with little overshoot. The magnitude of the gain at the frequency where the phase plot measures - 180° is referred to as the gain margin. If the slope of the gain plot is -2, or -40dB/decade, at low frequencies, it much transition to a -20dB/decade slope, also known as a -1 slope, one decade before crossing the 0dB point. If the slope remains at the -2 slope the resultant gain margin would be too small causing sever underdamped oscillations at fc.  2005 Semtech Corp. 12 www.semtech.com SC4809A/B/C POWER MANAGEMENT Applications Information (Cont.) Out of Phase, Synchronized, Dual Converter  2005 Semtech Corp. 13 www.semtech.com Qa TIP30C Ra Rb 300 1W 300 1W GND C1 R1 R2 Za 1.0/100V 1k ZMM5242B 20k L1 C10 C11 R9 10uH R17 R18 150/16V 200 1W 1.0 100 1k U1 Z1 C7 SC4809 0.1 ZMM5242B C8 D1 1 10 U2 MURD620CT VDD VREF 1.0 SC1301 R3 +12V 1k 2 9 1 LUVLO OUT IN Z2 5 EN ZMM5242B 3 8 2 R13 SYNC GND GND 10 4 C9 OUT 1n 4 7 3 Q3 RCT FB VCC BSS64ZXCT Q2 IRF640N 5 6 R10 "SLAVE" DMAX SS R15 47k 22k R11 7.5k R4 C3 R6 R7 R8 R12 2.7k 0.47 10k 1k 3.9k 1k R16 47k Q1 R14 R5 C2 MMBT2907A 0.2 1/2W 7.5k C4 C5 C6 150p 0.1 0.47 200p DISABLE GND +48V C1 1.0/100V R2 20k L1 R18 R9 10uH R17 C10 C11 200 1W 1.0 100 1k 150/16V U1 Z1 C7 0.1 SC4809 ZMM5242B D1 C8 MURD620CT 1 10 U2 VDD VREF SC1301 1.0 R3 +12V 1k 2 9 1 LUVLO OUT IN Z2 5 EN ZMM5242B 3 8 2 R13 SYNC GND GND 10 C9 4 "MASTER" OUT 1n 4 7 3 Q3 RCT FB VCC BSS64ZXCT Q2 IRF640N 5 6 R10 DMAX SS R15 47k 22k R11 7.5k C3 R4 R8 R6 R7 R12 2.7k 0.47 3.9k 10k 1k 1k R16 Q1 R14 47k R5 C2 MMBT2907A 0.2 1/2W 7.5k C4 C5 C6 100p 0.1 0.47 200p -- 48V DISABLE SC4809A/B/C POWER MANAGEMENT Evaluation Board Schematic 50W Forward Converter  2005 Semtech Corp. 14 www.semtech.com 5 C10 1.0/16V 6 R14 3.3k 1W 1 C11 C1 R12 R3 0.01/100V * 1.0/100V 100k C13 R11 R19 D2 3 100 20 1/4W 1nF/50V ES1D SMA 2 C14-16 C17 Z1 L1 C9 470/6.3V 10.0 2.5uH@10A ZMM5245B C2 7,8,9 1/25V U1 U2 0.01 SC4809_A_B_C SC1301A 4 D3 C3 1 10 1 VDD VREF IN MBRB1530CT 0.1/25V R4 5 EN 10k 10,11,12 2 9 2 R15 LUVLO OUT GND 3.3 Q3 4 R25 OUT IRF640NS R20 R21 3 8 3 3.83k SYNC SYNC GND VCC 1k 1k R22 R5 39.2k 10k 4 7 R26 RCT FB U3 0 R16 R23 MOC207 * 62k 5 6 5 2 DMAX SS Q1 R1 Q2 R17 5.1k MMBT2222A MMBT2907A 6 1 * Fsw=330kHz C6 7 C20 C21 0.033 430pF 0.01 Vcc C8 R18 R8 C12 R7 R9 C7 * * C18 R2 U4 R24 220pF 1.5k 7.5k 0.022 C19 1k C4 0.47 SC4431 10k 0.01 1.21k * R6 2k R10 C5 * 0.01 T1: PA0273, Pulse Eng. R10 R16 R17 R18 R12 C4 C8 L1: ETQP6F2R5SFA, Panasonic A 10k 62 604 0.15 2x12k| | 200p 680p C14-16: 6TPB470M, PosCap, Sanyo B 10k 62 604 0.15 3x12k| | 300p 680p C 8.2k 100 1k 0.22 2x10k| | 300p 390p SC4809A/B/C POWER MANAGEMENT Evaluation Board Layout 50W Forward Converter Layout Top Bottom  2005 Semtech Corp. 15 www.semtech.com SC4809A/B/C POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS e INCHES MILLIMETERS DIM A MIN NOM MAX MIN NOM MAX D A - - .043 - - 1.10 N A1 .000 - .006 0.00 - 0.15 - - A2 .030 .037 0.75 0.95 - - b .007 .011 0.17 0.27 2X E/2 c - - .003 .009 0.08 0.23 D .114 .118 .122 2.90 3.00 3.10 E1 E E1 .114 .118 .122 2.90 3.00 3.10 PIN 1 4.90 BSC E .193 BSC INDICATOR e .020 BSC 0.50 BSC L .016 .024 .032 0.40 0.60 0.80 ccc C 12 L1 (.037) (.95) N 10 10 2X N/2 TIPS B - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .003 0.08 ccc .010 0.25 D aaa C H A2 A SEATING PLANE c GAGE A1 C PLANE bxN bbb C A-B D 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIMENSIONS DIM INCHES MILLIMETERS (.161) (4.10) C (C) G .098 2.50 G Z P .020 0.50 X .011 0.30 Y .063 1.60 Z .224 5.70 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 16 www.semtech.com