SEMTECH SC4808C

SC4808C High Performance Dual Ended PWM Controller POWER MANAGEMENT Description Features The SC4808C is a dual-ended, high frequency, integrated ‹ 120µA starting current PWM controller, optimized for isolated applications that ‹ Pulse by pulse current limit require minimum space. It can be configured for current ‹ Programmable operation up to 1MHz or voltage mode operation with required control circuitry ‹ Internal soft start where secondary side error amplifier is used. ‹ Programmable line undervoltage lockout ‹ Over current shutdown Some of the key features are high frequency operation of ‹ Dual output drive stages on push-pull configuration 1 MHz that allows the use of smaller components thus ‹ Programmable internal slope compensation saving cost and valuable board space. An internal ramp ‹ Programmable mode of operation (peak current mode on the Current Sense pin allows Internal Slope or voltage mode) Compensation programmed by an external resistor. Other ‹ External frequency synchronization features include programmable frequency up to 1MHz, Pulse by Pulse current and Line Monitoring Input with ‹ Bi-phase mode of operation Hysteresis to reduce stress on the power components. ‹ -40 to 105 °C operating temperature ‹ MSOP-10 lead free package. This product is fully WEEE A unique oscillator is used to synchronize two SC4808C’s and RoHS compliant to work out of phase. This minimizes the input and output Applications ripple thus reducing noise on the output line and reducing stress and size of input/output filter components. The dual ‹‹ ‹‹‹ Telecom equipment and power supplies outputs can be configured in Push-Pull, Half Bridge and ‹‹‹‹‹ Networking power supplies Full Bridge format with programmable dead time between ‹ Industrial power supplies two outputs depending on the size of the timing ‹ Push-pull converter components. ‹ Half bridge converter ‹ Full bridge converter The SC4808C also features a turn on threshold of 8V and ‹ Isolated VRM’s is available in MSOP-10 package. Typical Application Circuit Vo Vin Gnd_Out RSENSE Gnd_In OUTA RC OUTB REF CS VCC FB SYNC SYNC LUVLO GND SC4808 Revision: July 13, 2006 1 www.semtech.com SC4808C POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymboMs aximu Unit SV upply Voltage -V 0.5 to18 CC SI upply Current 2A 0 m CC SYNC, RC,CS, LUVLO, REF to GND -V 0.5 to 7 FV B to GND -0.5 to (V+V 0.5) FB REF RI EF Current 1A 0 m REF OV UTA/OUTB to GND -V 0.5 to 18 OUTA/B OI UTA/OUTB Source Current (peak) -A 250 m source OI UTA/OUTB Sink Current (peak) 2A 50 m sink Thermal Resistance 1W 36* °C/ θ JA JT unction Temperature -C 40 to 150 ° J ST torage Temperature Range -C 65 to 150 ° STG LT ead Temperature (Soldering) 10 Sec. +C 300 ° LEAD EV SD Rating (Human Body Model) 2V k ESD *Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. Electrical Characteristics Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A Ps arameter Tn est Condition Mp i Tx y Mt a Uni PWM M, aximum Duty Cycle Fosc = 50kHz, FB = 3.5V 49 8 405% Measured at OUTA or OUTB M, inimum Duty Cycle Fosc = 50kHz, FB = 1.5V 0% Measured at OUTA or OUTB Current Sense Gain 3 Maximum Input Signal 45 75 55 2 5V 7 m CS to Output Delay 1s 00 n Over Current Threshold 60 00 70 0 8V 0 m Internal Slope Compensation Resistor 2k 5 Ω FB to CS Offset 10 .3010 .5 1V .7 Output OUT Low Level 00.0 5 .V 7 OUT High Level 15 1.010 1.2 1V 2.0 Rise Time 2s 5 n Fall Time 2s 5 n  2006 Semtech Corp. 2 www.semtech.com SC4808C POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A Ps arameter Tn est Condition Mp i Tx y Mt a Uni VCC Under Voltage Lockout Turn-on 78 .5 8V .5 Turn-off 67 .5 7V .5 Line Under Voltage Lockout SR tart Threshold = 14kΩ, R = 10kΩ -F 3%V% RE +V 3 TOP BOT 5.6% of HR ysteresis = 14kΩ, R = 10kΩ mV TOP BOT VREF Soft Start Internal Soft Start Ramp 2V 00 µs/ Sk oft Start Duration Rcs = 1 Ω 1s 2 µ (See formula in the Application Information Soft Start section) Soft Start Delay 1s 40 µ Oscillator OR scillator Frequency = 11kΩ, C=0 200pF 40 5 50 0 5z 5 KH osc osc Oscillator Ramp VREF/2 V +0.25 RC pin to GND capacitance 2F 2 p Oscillator Frequency Range 50 0 1z 00 KH Sync/CLOCK Clock SYNC Threshold 1V .0 Sync Frequency Range F*z 1.3 KH osc Bandgap Reference Voltage 25 .97030 .12 3V .28 Rt eference Curren 5A m Overall Sd tartup Current V0 CC < start threshol 1A 5 µ OV perating Supply CurrentF7 B = 0V, CS = 0 mA VA CC Zener Shunt Voltage I6 DD = 10m 1V  2006 Semtech Corp. 3 www.semtech.com SC4808C POWER MANAGEMENT Pin Configuration Ordering Information Pe art NumberPk ackag Top Mar Top View (1)(2) SC4808CMSTRTMC SOP-10 AB0 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (MSOP-10) Block Diagram VCC CS Slope Comp. OVER CURRENT Peak Current OUTA Enable OSC SQ R Disable 500mv Q T SQ Q LUVLO R REF Bandgap SOFT UVLO START R OUTB SYNC 2R LUVLO GND LUVLO FB RC SYNC  2006 Semtech Corp. 4 www.semtech.com SC4808C POWER MANAGEMENT Pin Descriptions FB: The inverting input to the PWM comparator. Stray in- LUVLO: Line undervoltage lockout pin. An external resis- ductances and parasitic capacitance should be minimized tive divider will program the undervoltage lockout level. The external divider should be referenced to the quiet analog by utilizing ground planes. ground. During the LUVLO, the driver outputs are disabled REF: Bandgap reference output It should be by passed with and the softstart is reset. This pin can also function as an a 2.2uF low ESR capacitance, right at the IC pin. Enable/Disable. SYNC: SYNC is a positive edge triggered input with a thresh- CS: Current sense input and internal slope compensation are both provided via the CS pin. The current sense input old set to 1.0V. In a single controller operation, SYNC could from a sense resistor is used for the peak current and be grounded or connected to an external synchronization overcurrent comparators. An internal 1 to 3 feed back volt- clock within the SYNC frequency range. In the Bi-Phase age divider provides a 3X amplification of the CS signal. operation mode SYNC pins could be connected to the Cosc (Timing Capacitors) of the other controller. This will force This is used for comparison to the external error amplifier an out of phase operation. signal. If an external resistor is connected from CS to the current sense resistor, the internal current source will pro- GND: Device power and analog ground. Careful attention vide a programmable slope compensation. The value of should be paid to the layout of the ground planes (see page the resistor will determine the level of compensation. At 16.) higher compensation levels, voltage mode of operation can be achieved. OUTA and OUTB: Out of phase gate drive stages. The driver’s peak source and sink current drive capability of RC: The oscillator programming pin. The oscillator should 100mA, enables the use of an external MOSFET driver or be referenced to a stable reference voltage for an accu- a NPN/PNP transistor buffer. rate and stable frequency. Only two components are re- The oscillator RC network programs the oscillator frequency, quired to program the oscillator, a resistor (tied to Vref and which is twice the OUTA/OUTB frequency. To insure that RC), and a capacitor (tied to the RC and GND). The follow- the outputs do not overlap, a dead time can be generated ing formula can be used for a close approximation of the between the two outputs by sizing the oscillator timing oscillator frequency. capacitor. 1 F ≅ OSC R C × 0.8 OSC TOT VCC: The supply input for the device. Once VCC has ex- ceeded the UVLO limit, the internal reference, oscillator, drivers and logic are powered up. A low ESR capacitance, where: should be used for decoupling right at the IC pin to mini- mize noise problems. C = C + C + C TOT OSC SC4808 Circuit C ≅ 22pF SC4808 Where the frequency is in Hertz, resistance in ohms, and capacitance in farads. The recommended range of timing resistors is between 10 kOhm and 200kOhm and range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kOhm should be avoided.  2006 Semtech Corp. 5 www.semtech.com SC4808C POWER MANAGEMENT Application Information THEORY OF OPERATION The SC4808C is a versatile double ended, high speed, low The current sense input and internal slope compensation power, pulse width modulator that is optimized for applica- are both provided via the CS pin. The current sense input tions requiring minimum space. from a sense resistor is used for the peak current and The device contains all of the control and drive circuity re- overcurrent comparators. An internal 1 to 3 feedback volt- quired for isolated or non isolated power supplies where age divider provides a 3X amplification of the CS signal. an external error amplifier is used. A fixed oscillator fre- This is used for comparison to the external error amplifier quency (up to 1MHz) can be programmed by an external signal. If an external resistor is connected from CS to the RC network. current sense resistor, the internal current source will pro- The SC4808C is a peak current or voltage mode controller, vide a programmable slope compensation. The value of depending on the amount of slope compensation, the resistor will determine the level of compensation. At programmable with only one external resistor. The cycle by higher compensation levels, voltage mode of operation can cycle peak current limit prevents core saturation when a be achieved. The error amplifier signal at the FB pin will be transformer is used for isolation while the overcurrent used in conjunction with the CS signal to achieve regula- circuitry initiates the softstart cycle. tion. The SC4808C dual output drive stages are arranged in a Two levels of undervoltage lockout are also available. The push-pull configuration. Both outputs switch at half the LUVLO (line under voltage lockout) pin via an external re- oscillator frequency using a toggle flip flop. The dead time sistive divider will program the undervoltage lockout level. between the two outputs is programmable depending on During the LUVLO, the driver outputs are disabled and the the values of the timing capacitor and resistors, thus limiting softstart is reset. each output stage duty cycle to less than 50%. Once VCC has exceeded the UVLO (VCC under voltage lock- The SC4808C also provides flexibility with programmable out) limit, the internal reference, oscillator, drivers and logic LUVLO thresholds, with built-in hysteresis. are powered up. SUPPLY SYNC is a positive edge triggered input with a threshold set to 1.0V. A single supply, VCC is used to provide the bias for the By connecting an external control signal to the SYNC pin, internal reference, oscillator, drivers, and logic circuitry of the internal oscillator frequency will be synchronized to the SC4808C. To ensure proper operation during start up, VCC positive edge of the external control signal. In a single con- slew rate of less than 10V/mS is recommended. troller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC fre- PWM CONTROLLER quency range . In the Bi-phase operation mode a very unique oscillator SC4808C is a double ended PWM controller that can be is utilized to allow two SC4808C to be synchronized used in voltage or current mode applications. The SC4808C together and work out of phase. This feature is setup by provides a 7.5V VCC UVLO, and a 3.125V reference. The simple connection of the SYNC input to the RC pin of the oscillator frequency is programmed by a resistor and a ca- other part. The fastest oscillator automatically becomes pacitor network connected to an external reference pro- the master, forcing the two PWMs to operate out of vided by the SC4808C. The two outputs, OUTA and OUTB, phase. This feature minimizes the input and output are 180 degrees out of phase and run at half of the oscil- ripples, and reduces stress on the capacitors. lator frequency. An external error amplifier will provide the error signal to the FB pin of the SC4808C.  2006 Semtech Corp. 6 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) VCC UNDER VOLTAGE LOCK OUT The oscillator frequency is set by connecting a RC network Depending on the application and the voltages available, as shown below. the SC4808C can be used to provide the VCC undervoltage lock out function to ensure the converters controlled start up. REF VCC 0 Before the VCC UVLO has been reached, the internal refer- C26 2.2u,16V ence, oscillator, OUTA/OUTB drivers, and logic are disabled. R27 U4 R28 15k 5 6 10 LINE UNDER VOLTAGE LOCK OUT REF GND 4 7 FB OUTB 3 8 CS OUTA The SC4808C also provides a line undervoltage (LUVLO = 2 9 RC VCC Vref) function. The LUVLO pin is programmed via an exter- C31 C33 1 10 SYNC LUVLO 200p 0.1u,25V nal resistor divider connected as shown below. The actual SC4808 0 start-up voltage can be calculated by using the equation SYNC 56.2k 10k below: Vin R23 R33 () R 23 + R 33 V = V × Startup REF R 33 The oscillator has a ramp voltage of about Vref/2. The os- cillator frequency is twice the frequency of the OUTA and OUTB gate drive controls. R24 10k REF VCC 15 C26 The oscillator capacitor C31 is charged by a current sourced 2.2u,16V from the Vref through R27. Once the RC pin reaches about R25 18 Vref/2, the capacitor is discharged internally by the R26 R27 U4 R28 2.2k 15k 5 6 10 REF GND SC4808C. It should be noted that larger capacitor values 4 7 FB OUTB will result in a longer dead time during the down slope of 3 8 CS OUTA the ramp. C29 2 9 RC VCC The following equation can be used as an approximation 82p C31 C33 1 10 SYNC LUVLO 200p 0.1u,25V of the oscillator frequency and the Dead time: SC4808 SYNC 1 56.2k 10k F ≅ OSC R C × 0.8 OSC TOT Vin R23 R33 where: REFERENCE C = C + C + C TOT OSC SC4808 Circuit A 3.125V(SC4808C) reference voltage is available that can be used to source a typical current of 5mA to the external C ≅ 22pF SC4808 circuitry. The Vref can be used to provide the oscillator RC C × V × 0.5 OSC REF T ≅ network with a regulated bias. deadtime −3 3 ⋅10 The recommended range of timing resistors is between 10 OSCILLATOR kOhm and 200kOhm, range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kOhm should be avoided.  2006 Semtech Corp. 7 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) SYNC/Bi-Phase operation FEED BACK In noise sensitive applications where synchronization of The error signal from the output of an external error ampli- the oscillator frequency to a reference frequency is required, fier such as SC431 or SC4431 is applied to the inverting the SYNC pin can accept the external clock. By connecting input of the PWM comparator at the FB pin either directly an external control signal to the SYNC pin, the internal os- or via an opto coupler for the isolated applications. For best cillator frequency will be synchronized to the positive edge stability, keep the FB trace length as short as possible. of the external control signal. SYNC is a positive edge trig- gered input with a threshold set to 1.0V (SC4808C). Vref Vout Vout In a single controller operation, SYNC should be grounded R37 C35 2.2k or connected to an external synchronization clock within R34 R32 6 3 C36 R35 FB C40 the SYNC frequency range. 22pF 5 4 R36 1 5 C37 MOCD207 4 C38 C39 0.1u 22n OUTA (PWM1) SC4431 R38 Vref 2 OUTB (PWM1) The signal at the FB pin is then compared to the 3X ampli- OUTA (PWM2) fied signal from the current sense/ slope compensation CS pin. Matched out of phase signals are generated to OUTB (PWM2) control the OUTA and OUTB gate drives of the two phases. A single ramp signal is used to generate the control sig- nals for both phases, hence achieving a tightly matched REF REF per phase operation. Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to pro- Rosc1 Rosc2 U1 U2 5 6 5 6 vide enough head room for the opto coupler used in iso- REF GND REF GND 4 7 4 7 FB OUTB FB OUTB lated applications. 3 8 3 8 CS OUTA CS OUTA 2 9 2 9 RC VCC RC VCC GATE DRIVERS Cosc1 1 10 Cosc2 1 10 SYNC LUVLO SYNC LUVLO OUTA and OUTB are out of phase bipolar gate drive output SC4808 SC4808 stages, that are supplied from VCC and provide a peak source/sink current of about 100mA. Both stages are ca- pable of driving the logic input of external MOSFET drivers or a NPN/PNP transistor buffer. The output stages switch In the Bi-phase operation mode a very unique oscillator is at half the oscillator frequency. When the voltage on the utilized to allow two SC4808C’s to be synchronized together RC pin is rising, one of the two outputs is high, but during and work out of phase. This feature is set up by a simple fall time, both outputs are off. This “dead time” between connection of the SYNC input to the RC pin of the other the two outputs, along with a slower output rise and fall part. The fastest oscillator automatically becomes the time, insures that the two outputs can not be on at the master, forcing the two PWMs to operate out of phase. This same time. The dead time is programmable and depends feature minimizes the input and output ripples, and reduces upon the timing capacitor. stress on the capacitors.  2006 Semtech Corp. 8 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) It should be noted that if high speed/high current drivers such as the SC1301 are used, careful layout guide lines must be followed in order to minimize stray inductance, which might cause negative voltages at the output of the drivers. This negative voltage can be clamped to a reason- able level by placing a small Schottky diode directly at the output of the driver as shown below. VCC EN SC1301A U3 3 5 C23 F VCC 0.1u 1 4 Gate_B C26 2.2u,16V D_B 2 U4 R28 5 6 10 REF GND 4 7 FB OUTB 3 8 CS OUTA VCC EN 2 9 RC VCC SC1301A C33 1 10 U6 3 5 SYNC LUVLO 0.1u,25V C34 SC4808 0.1u SYNC 1 4 Gate_A 56.2k 10k D_A Vin R23 R33 2 OVER CURRENT Two levels of over current protection are provided by the SC4808C. The current information is sensed at the CS pin and compared to a peak current limit level of 525mV. If the 525mV limit is exceeded, the OUTA and OUTB pulse widths and duty cycle is reduced until the CS pin reaches a second threshold of 700mV. At that point, the OUTA and OUTB are disabled, and after a delay of 140µs, the inter- nal softstart sequence is started. After the softstart dura- tion, normal operation is achieved, unless the over cur- rent condition is still present.  2006 Semtech Corp. 9 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) SLOPE COMPENSATION (Current or Voltage mode of operation) In applications where a current mode control is used for regulation, the peak inductor current information is used to produce the average output current. If a small perturbation due to changes in supply voltage or noise pick up is gener- ated, instability may occur if the duty cycle is >50%. This phenomenon is graphically shown below. The inductor current and disturbed inductor current are shown for three different duty cycles conditions. The top wave form shows the applications where the duty cycle D is less than 50%. As shown, even if an error is introduced, after only a few cycles the error converges to zero. The second wave form shows the case where D = 50%. Under this condition, even though the error does not completely disappear, it stays constant and is not getting larger. This will be seen as jitter at the inductor voltage. The bottom wave form shows D>50%. As shown, a very small error results in a much larger error only after a few cycles. This will cause instability in the converter and the average output inductor current. The output load will not be able to be kept in regulation. Instability in current mode operation due to Duty cycle >50% i L : Small Inductor current perturbation : Inductor current IL D<50% I i L L Note: After afew cycles the perturbation disappears and stable operation returns. Time D=50% i L I iL L Note: After afew cycles the perturbation is still present, although this will cause jitter, but there is no instability. Time D>50% I L iL iL Note: After afew cycles the perturbation becomes larger, and causes instability. Time  2006 Semtech Corp. 10 www.semtech.com Error Error Error SC4808C POWER MANAGEMENT Application Information (Cont.) If the R is increased, the internal ramp becomes the The instability can be corrected by modification of the peak slope comp dominant signal and more voltage mode of operation is current information slope. One of the methods to alter the achieved. As it can be calculated from the second formula peak current information is to add a positive going ramp to below, a 100% voltage mode operation can be achieved by the output of the current sensing circuitry. choosing R to be greater than 6.25kOhm. Also if a The SC4808C achieves this by using an internal slope com- slope comp 100% current mode of operation is required, R is pensation circuit. The oscillator ramp is internally buffered slope comp reduced to zero and the contribution from the internal ramp and an internal 25kOhm resistor in conjunction with an is completely eliminated. external resistor at the CS pin will program the level of slope compensation. () R + R slope_Comp sense V × Ramp () R + R + R slope_Comp sense internal %Slope_ Comp= Current Transformer V CS N = 100 or 10k R REF D C  0.2 ×() %slope_ Comp  2.2u,16V R ≅ R • external internal   Rsense 1−() 0.2 × %slope_ Comp   Rosc RSlope Comp 15k 5 6 REF GND Next page illustrates how the buffered oscillator ramp is 4 7 FB 25k used to modify the sensed inductor current. 3 CS Cfilter 2 It should be noted that in order for the slope compensa- RC Cosc 82p 1 tion to be effective, the current sensed signal slope should SYNC 200p be at least 50% less steeper than the oscillator positive SC4808 ramp slope. The slope will include the magnetizing current RSlope Comp value will determine the Mode of operation (Voltage or Current) of the transformer and the inductor output current in iso- lated applications. In non-isolated applications, the slope will only include the inductor output current. The Peak current information is sensed and the result is realistically summed to the buffered oscillator ramp, as shown above. The value of the external resistor R slope comp will determine the percentage of the slope compensation. As the value for R is reduced, the current informa- slope comp tion becomes more dominant and the mode of operation becomes more current mode. At the same time the slope of the current information is modified to provide the slope compensation.  2006 Semtech Corp. 11 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) i : Small Inductor current perturbation L Slope Compensation generation from : Inductor current Buffered Oscillator Ramp I L I : Sensed Mosfet current Sense D>50% I : Summation of Isense and slope compensation, at the CS pin of the SC4808. Note: Below wave forms are not to scale. CS I L ISense Buffered Oscillator Ramp I CS  2006 Semtech Corp. 12 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) Below the benefits from the slope compensation become apparent. The top wave form shows the stable operation before the perturbation. The second wave form shows the perturbation and the instability caused from it if no slope compensation is added to the current information. The last wave form shows the slope compensation and the effect of it. The increase in the slope of the current information results in an early termination of the inductor current, hence a reduction in the amount of error. As the cycle is repeated, the perturbation is reduced and finally eliminated. δ Stable current mode operation with Slope iL : Small Inductor current perturbation Δ Compensation : Inductor current I L I : Sensed Mosfet current Sense D>50% : Summation of Isense and slope compensation, at the CS pin of the SC4808. ICS Stable operation ( no perturbation) Error Signal from Error amplifier Δ IL I Sense Note: After a few cycles the perturbation becomes larger, and causes instability. Instable operation ( with perturbation) Error Signal from Error amplifier Δ IL δ i L I Sense Note: After a few cycles the perturbation disappears and stable operation returns. Stable operation (Slope Compensation Added) Error Signal from Error amplifier Δ I L δ I CS i L  2006 Semtech Corp. 13 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) SOFT START START UP SEQUENCE Initially during the power up, the SC4808C is in under volt- During start up of the converter, the discharged output ca- age lock out condition. As the Vcc supply exceeds the UVLO pacitor and the load current have large supply current re- quirements. To avoid this a soft start scheme is usually limit of the SC4808C, the internal reference, oscillator, and implemented where the duty cycle of the regulator is gradu- logic circuitry are powered up. The OUTA and OUTB drivers are not enabled until the line ally increased from 0% until the soft start duration is under voltage lock out limit is reached. At that point, once elapsed. the FB pin is above 1.5V, soft start circuitry starts the out- SC4808C has an internal soft start circuit that limits the duty cycle for a duration approximated by the formula be- put drivers, and gradually increases the duty cycle from low. Also the soft start circuitry is activated if an over cur- 0%. The soft start duration is internally set (see formula in Soft Start section). rent condition occurs. After an over current condition, OUTA As the output voltage starts to increase, the error signal and OUTB are disabled and kept low for a duration of about from the error amplifier starts to decrease. If isolation is 140µs. After the delay, the OUTA and OUTB are enabled while the soft start limits the duty cycle. If the over current required, the error amplifier output can drive the LED of condition persists, the soft start cycle repeats indefinitely. the opto isolator. The output of the opto is connected in a common emitter configuration with a pull-up resistor to a Approximate internal soft start duration can be calculated reference voltage connected to the FB pin of the SC4808C. as below: The voltage level at the FB pin provides the duty cycle nec-  VREF  essary to achieve regulation. () Ramp ×   SoftStart 2   If an over current condition occurs, the outputs are dis- T ≅ SoftStart abled and after a soft start delay time of about 100µs, the  R  Internal _ SlopeComp   + 1 softstart sequence mentioned above is repeated.   R CS _ to _ GND   If longer soft start durations are required, the simple exter- nal circuit shown below can be implemented. REF VCC C26 2.2u,16V REF R37 R27 U4 R28 1k 15k 5 6 10 REF GND 6 4 7 FB OUTB C40 NA 3 8 CS OUTA 5 2 9 56.2K RC VCC C31 C33 MOCD207 1 10 200p SYNC LUVLO 0.1u,25V Csoft start SC4808 SYNC 56.2k 10k Vin R23 R33 Approximate soft start duration can be calculated as be- low: T ≅ C × R37 SoftStart SoftStart  2006 Semtech Corp. 14 www.semtech.com SC4808C POWER MANAGEMENT Application Information (Cont.) LAYOUT GUIDELINES Careful attention to layout requirements are necessary for 7) If an Opto isolator is used for isolation, quiet primary successful implementation of the SC4808C PWM control- and secondary ground planes should be used. The same ler. precautions should be followed for the primary GND plane High current switching is present in the application and as mentioned in item 5 mentioned above. For the second- their effect on ground plane voltage differentials must be ary GND plane, the GND plane method mentioned in item understood and minimized. 4 should be followed. 1). The high power parts of the circuit should be laid out 8) All the noise sensitive components such as LUVLO re- first. A ground plane should be used, the number and po- sistive divider, reference by pass capacitor, Vcc bypass ca- sition of ground plane interruptions should be such as to pacitor, current sensing circuitry, feedback circuitry, and not unnecessarily compromise ground plane integrity. Iso- the oscillator resistor/capacitor network should be con- lated or semi-isolated areas of the ground plane may be nected as close as possible to the SC4808C. The GND deliberately introduced to constrain ground currents to return should be connected to the quiet SC4808C GND particular areas, such as the input capacitor and FET plane. ground. 9) The connection from the OUTA and OUTB of the 2). In the loop formed by the Input Capacitor(s) (Cin), the SC4808C should be minimized to avoid any stray induc- FET must be kept as small as possible. This loop contains tance. If the layout can not be optimized due to constraints, all the high current, fast transition switching. Connections a small Schottky diode may be connected from the OUTA/ should be as wide and as short as possible to minimize B pins to the ground directly at the IC. This will clamp ex- loop inductance. Minimizing this loop area will a) reduce cessive negative voltages at the IC. If drivers are used, the EMI, b) lower ground injection currents, resulting in electri- Schottky diodes should be connected directly at the IC from cally “cleaner” grounds for the rest of the system and c) the output of the driver to the driver ground. minimize source ringing, resulting in more reliable gate 10) If the SYNC function is not used, the SYNC pin should switching signals. be grounded at the SC4808C GND to avoid noise pick up. 3). The connection between FETs and the Transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize in- ductance and resistance. 5) The SC4808C is best placed over a quiet ground plane area. Avoid pulse currents in the Cin FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VCC supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. Avoid making a star connection between the quiet GND planes that the SC4808C will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible The GND connections should be connected to the quiet GND used for the SC4808C.  2006 Semtech Corp. 15 www.semtech.com SC4808C POWER MANAGEMENT Gain & Phase Margin 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 36V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz  2006 Semtech Corp. 16 www.semtech.com Gain (dB) Phase (deg) SC4808C POWER MANAGEMENT Gain & Phase Margin (Cont.) 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 48V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz  2006 Semtech Corp. 17 www.semtech.com Gain (dB) Phase (deg) SC4808C POWER MANAGEMENT Gain & Phase Margin (Cont.) 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 72V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz  2006 Semtech Corp. 18 www.semtech.com Gain (dB) Phase (deg) SC4808C POWER MANAGEMENT Typical Step Load Vout 500mV/Div Iout 5A/Div 100us/Div Cout = 6X22uF (132uF) Ceramic Typical SC4808C Push Pull Converter Step Load plot at Vin = 48V, Vout = 3.3V, Step = 37% to 75% Iout, Fosc = 650kHz  2006 Semtech Corp. 19 www.semtech.com CON1 9 Vout+ PA0500 MBRB2535CTL 1 2 10 4 R1 3 8 Murata GRM32DR60J226KA01 Sense+ PG0006.102T 10 R2 6T 1T 0 T2 D1 GRM55DR72E105KW01 4 L1 GRM55DR72E105KW01 P8208T 2.2n C1 9 1 2 C2 3 8 7 C4 C5 C6 C7 C8 C9 CON2 R3 R4 10 R5 C10 0.9uH 250 6T 1T MBRB2535CTL 7 Trim 1 1 22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V 0.1u 0.1u 20k 2.2n C3 Vin+ FZT853 5 8 4 1 3 C11 C12 Q1 C C13 R6 B TBD 0 D2 R7 4T 6 1u,100V 1u,100V VCC 1u,100V 3 3 16.2 R31 N = 100 Sense- 2 R8 SUD19N20-90 SUD19N20-90 6 ON/OFF E 0 C A 4 3 T1 1 3 1 1 VCC = 15V 0 D3 1N5819HW M1 M2 D4 1N5819HW 1N5819HW U7 CBRHD-02 5 2 2 Vout- 4 R10 R9 Vin- 2.2 2.2 C14 C15 D5 D6 ZM4743A .1u,16V 5output_half_brick 10u,16V 1 2 3input_half_brick L2 LQH43MN102K011 1 2 GRM32DR61C106KA01 VCC C16 R11 G_B G_A TBD 10u,16V GRM32DR61C106KA01 G_B VCC SC1301A 3 5 U2 CMOSH-3 R12 56.2k C17 C18 R13 10k REF VCC 0.1u D7 22nF LS4448 1 4 J1 J2 C19 D8 R15 2.2u,16V D9 R14 15 0 2 CMOSH-3 R16 R17 U1 R18 T3 D10 D11 1k 15k 5 6 10 1 6 REF GND CMOSH-3 CMOSH-3 4 7 1u,16V FB OUTB C20 Sync Drive Supply 3 8 CS OUTA G_A VCC 3 4 C21 2 9 SC1301A 0 D13 D12 RC VCC C22 PE-68386 82p 1 10 R19 3 5 U3 SYNC LUVLO CMOSH-3 CMOSH-3 82p C23 CMOSH-3 Sync Drive Supply C24 0.1u,25V SC4808 0.1u D14 0 JP1 J3 1 4 R20 SYNC 2.2k D15 10k R21 1 R22 2 CMOSH-3 5 37.4k 10nF C25 4 U6 C26 C27 0.1u 22n U4 8 1 SC4431 C34 REF R23 .1uF REF 18.2k 7 2 Vref R24 R32 1k 56.2k 2 6 3 C28 FMMT718 NA Sync Drive Supply Q2 5 4 100pF C29 C35 2.2uF 16V R26 R25 MOCD207 C30 R27 11.5k 2.2k 1nF 15k 1 R28 5 25.5k C31 470pF 4 C32 C33 R29 0.1u 22n U5 100 SC4431 R30 15k C Vref D16 1N5819HW 2 A Note: For output power > 30W, adequate air flow should be provided to avoid over dissipation. SEMTECH CORPORATION Title SC4808 Push Pull 3.3V 50W non Synchronous Size Document Number Rev SC4808EVB__non_sync 1.1 Date: Monday, October 07, 2002 Sheet of 11 SC4808C POWER MANAGEMENT Evaluation Board Schematics  2006 Semtech Corp. 20 www.semtech.com SC4808C POWER MANAGEMENT Evaluation Board Bill of Materials SC4808 Push Pull 3.3V 50W non Synchronous SC4808EVB__non_sync Revision: 1.1 Bill Of Materials October 7,2002 13:35:18 Item Quantity Reference Part Manufacturer # Foot Print 1 1 CON1 5output_half_brick CON\5OUTPUT_HALF_BRICK 2 1 CON2 3input_half_brick CON\3INPUT_HALF_BRICK 3 2 C3,C1 2.2n SM/C_1206 4 6 C2,C10,C17,C24,C26,C32 0.1u SM/C_0805 5 6 C4,C5,C6,C7,C8,C9 22u,6.3V GRM32DR60J226KA01 SM/C_1210_GRM 6 3 C11,C12,C13 1u,100V GRM55DR72E105KW01 SM/C_2220 7 1 C14 .1u,16V SM/C_0805 8 2 C15,C16 10u,16V GRM32DR61C106KA01 SM/C_1210_GRM 9 1 C18 22nF SM/C_1206 10 1 C19 2.2u,16V SM/C_1206 11 1 C20 1u,16V GRM32RR71H105KA011 SM/C_1210_GRM 12 2 C22,C21 82p SM/C_0805 13 1 C23 0.1u,25V SM/C_1206 14 1 C25 10nF SM/C_0805 15 2 C27,C33 22n SM/C_0805 16 1 C28 NA SM/C_0805 17 1 C29 100pF SM/C_0805 18 1 C30 1nF SM/C_0805 19 1 C31 470pF SM/C_0805 20 1 C34 .1uF SM/C_0805 21 1 C35 2.2uF 16V SM/C_0805 22 2 D2,D1 MBRB2535CTL DIODE_D2PAK 23 4 D3,D5,D6,D16 1N5819HW SOD123 24 1 D4 ZM4743A SMB/DO214 25 8 D7,D9,D10,D11,D12,D13, CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523 D14,D15 26 1 D8 LS4448 SM/DO213AC 27 1 JP1 short VIA\2P 28 1 J1 REF ED5052 29 1 J2 Vcc ED5052 30 1 J3 SYNC ED5052 31 1 L1 0.9uH PG0006 32 1 L2 LQH43MN102K011 LQH43MN102K01L SDIP0302 33 2 M1,M2 SUD19N20-90 SUD19N20-90 DPAKFET 34 1 Q1 FZT853 SM/SOT223_BCEC 35 1 Q2 FMMT718 36 4 R1,R7,R15,R19 0 SM/R_0805 37 2 R5,R2 10 SM/R_1206 38 1 R3 20k SM/R_1206 39 1 R4 250 SM/R_1210_MCR 40 2 R6,R11 TBD SM/R_0805 41 1 R8 0 SM/R_1206 42 2 R9,R10 2.2 SM/R_0805 43 1 R12 56.2k SM/R_1206 44 1 R13 10k SM/R_0805 45 1 R14 15 SM/R_0805 46 2 R16,R24 1k SM/R_0805 47 3 R17,R27,R30 15k SM/R_0805 48 1 R18 10 SM/R_0805 49 2 R26,R20 2.2k SM/R_0805 50 1 R21 10k SM/R_1206 51 1 R22 37.4k SM/R_0805 52 1 R23 18.2k SM/R_0805 53 1 R25 11.5k SM/R_0805 54 1 R28 25.5k SM/R_0805 55 1 R29 100 SM/R_0805 56 1 R31 16.2 SM/R_1206 57 1 R32 56.2k SM/R_0805 58 1 T1 PA0500 PA0500 59 1 T2 P8208T P8208T 60 1 T3 PE-68386 PE-68386 61 1 U1 SC4808 MSOP10 62 2 U2,U3 SC1301A SOT23_5PIN 63 2 U4,U5 SC4431 SOT23_5PIN 64 1 U6 MOCD207 SO-8 65 1 U7 CBRHD-02 CBRHD-02  2006 Semtech Corp. 21 www.semtech.com SC4808C POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly Top Board Layout Assembly Bottom Board Layout Top Board Layout Bottom  2006 Semtech Corp. 22 www.semtech.com SC4808C POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout INNER1 Board Layout INNER2  2006 Semtech Corp. 23 www.semtech.com SC4808C POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS e INCHES MILLIMETERS DIM A MIN NOM MAX MIN NOM MAX D A - - .043 - - 1.10 N A1 .000 - .006 0.00 - 0.15 - - A2 .030 .037 0.75 0.95 - - b .007 .011 0.17 0.27 2X E/2 c - - .003 .009 0.08 0.23 D .114 .118 .122 2.90 3.00 3.10 E1 E E1 .114 .118 .122 2.90 3.00 3.10 PIN 1 4.90 BSC E .193 BSC INDICATOR e .020 BSC 0.50 BSC L .016 .024 .032 0.40 0.60 0.80 ccc C 12 L1 (.037) (.95) N 10 10 2X N/2 TIPS B - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .003 0.08 ccc .010 0.25 D aaa C H A2 A SEATING PLANE c GAGE A1 C PLANE bxN bbb C A-B D 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIMENSIONS DIM INCHES MILLIMETERS (.161) (4.10) C (C) G .098 2.50 G Z P .020 0.50 X .011 0.30 Y .063 1.60 Z .224 5.70 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 24 www.semtech.com