SEMTECH SC4808B-2

SC4808B-2 High Performance Dual Ended PWM Controller POWER MANAGEMENT Description Features The SC4808B-2 is a dual-ended, high frequency, integrated u 120µA starting current PWM controller, optimized for isolated applications that u Pulse by pulse current limit require minimum space. It can be configured for current u Programmable operation up to 1MHz or voltage mode operation with required control circuitry u Internal soft start where secondary side error amplifier is used. u Programmable line undervoltage lockout u Over current shutdown Some of the key features are high frequency operation of u Dual output drive stages on push-pull configuration 1 MHz that allows the use of smaller components thus u Programmable internal slope compensation saving cost and valuable board space. An internal ramp u Programmable mode of operation (peak current mode on the Current Sense pin allows Internal Slope or voltage mode) Compensation programmed by an external resistor. Other u External frequency synchronization features include programmable frequency up to 1MHz, u Bi-phase mode of operation Pulse by Pulse current and Line Monitoring Input with Hysteresis to reduce stress on the power components. u -40 to 105 °C operating temperature u MSOP-10 Lead-free package. This product is fully WEEE A unique oscillator is used to synchronize two SC4808B- and RoHS compliant 2’s to work out of phase. This minimizes the input and Applications output ripple thus reducing noise on the output line and reducing stress and size of input/output filter components. u Telecom equipment and power supplies The dual outputs can be configured in Push-Pull, Half Bridge u Networking power supplies and Full Bridge format with programmable dead time u Industrial power supplies between two outputs depending on the size of the timing u Push-pull converter components. u Half bridge converter u Full bridge converter The SC4808B-2 also features a turn on threshold of 4.4V u Isolated VRM’s and is available in MSOP-10 package. Typical Application Circuit Vo Vin Gnd_Out RSENSE Gnd_In OUTA RC OUTB REF CS VCC FB SYNC SYNC LUVLO GND SC4808 Revision: Dec. 9, 2009 1 www.semtech.com SC4808B-2 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage V -0.5 to18 V CC Supply Current I 20 mA CC SYNC, RC,CS, LUVLO, REF to GND -0.5 to 7 V FB to GND V -0.5 to (V + 0.5) V FB REF REF Current I 10 mA REF OUTA/OUTB to GND V -0.5 to 18 V OUTA/B OUTA/OUTB Source Current (peak) I -250 mA source OUTA/OUTB Sink Current (peak) I 250 mA sink Power Dissipation at T = 25°C P 1.105 W A D Thermal Resistance 113.1 °C/W q JA Junction Temperature T -40 to 150 °C J Storage Temperature Range T -65 to 150 °C STG Lead Temperature (Soldering) 10 Sec. T +300 °C LEAD ESD Rating (Human Body Model) V 2 kV ESD Electrical Characteristics Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A Parameter Test Conditions Min Typ Max Unit PWM Maximum Duty Cycle Fosc = 50kHz, FB = 5V, 48 49 50 % Measured at OUTA or OUTB Minimum Duty Cycle Fosc = 50kHz, FB = 1.5V, 0 % Measured at OUTA or OUTB Current Sense Gain 3 Maximum Input Signal 475 525 575 mV CS to Output Delay 100 ns Over Current Threshold .850 .950 1 V Internal Slope Compensation Resistor 25 kW FB to CS Offset 1.30 1.50 1.70 V Output OUT Low Level 0 .50 .70 V OUT High Level 11.0 11.25 12.00 V Rise Time 25 ns Fall Time 25 ns ã 2009 Semtech Corp. 2 www.semtech.com SC4808B-2 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A Parameter Parameter Parameter Test Conditions Test Conditions Test Conditions Min Min Min Typ Typ Typ Max Max Max Unit Unit Unit VCC Under Voltage Lockout VCC Under Voltage Lockout VCC Under Voltage Lockout Start Threshold Start Threshold Start Threshold 4.0 4.0 4.0 4.40 4.40 4.40 4.5 4.5 4.5 V V V Hysteresis Hysteresis Hysteresis 100 100 100 140 140 140 200 200 200 mV mV mV Line Under Voltage Lockout Line Under Voltage Lockout Line Under Voltage Lockout W W W W W W Start Threshold Start Threshold Start Threshold R23 = 14k R23 = 14k R23 = 14k , R33 = 10k , R33 = 10k , R33 = 10k (see page 11) (see page 11) (see page 11) - - -3% 3% 3% VREF VREF VREF +3% +3% +3% V V V 5.6% of 5.6% of 5.6% of W W W W W W Hysteresis Hysteresis Hysteresis R23 = 14k R23 = 14k R23 = 14k , R33 = 10k , R33 = 10k , R33 = 10k (see page 11) (see page 11) (see page 11) mV mV mV VREF VREF VREF Soft Start Soft Start Soft Start Internal Soft Start Ramp Internal Soft Start Ramp Internal Soft Start Ramp 200 200 200 µ µ µs/V s/V s/V W W W Soft Start Duration Soft Start Duration Soft Start Duration Rcs Rcs Rcs = 1k = 1k = 1k 12 12 12 µ µ µs s s (See formula in the application (See formula in the application (See formula in the application information section on page 18) information section on page 18) information section on page 18) Soft Start Delay Soft Start Delay Soft Start Delay 140 140 140 µ µ µs s s Oscillator Oscillator Oscillator W W W Oscillator Frequency Oscillator Frequency Oscillator Frequency R R R = 11k = 11k = 11k , C , C , C = 200pF = 200pF = 200pF 450 450 450 500 500 500 550 550 550 KHz KHz KHz osc osc osc osc osc osc Oscillator Ramp Oscillator Ramp Oscillator Ramp VREF/2 VREF/2 VREF/2 V V V +0.25 +0.25 +0.25 RC pin to GND capacitance RC pin to GND capacitance RC pin to GND capacitance 22 22 22 pF pF pF Oscillator Frequency Range Oscillator Frequency Range Oscillator Frequency Range 50 50 50 1000 1000 1000 KHz KHz KHz Sync/CLOCK Sync/CLOCK Sync/CLOCK Clock SYNC Threshold Clock SYNC Threshold Clock SYNC Threshold 1.0 1.0 1.0 V V V Sync Frequency Range Sync Frequency Range Sync Frequency Range F F F *1.3 *1.3 *1.3 KHz KHz KHz osc osc osc Bandgap Bandgap Bandgap Reference Voltage Reference Voltage Reference Voltage 2.970 2.970 2.970 3.125 3.125 3.125 3.280 3.280 3.280 V V V Reference Reference ReferenceCurrent Current Current 5 5 5 mA mA mA Overall Overall Overall Startup Current Startup Current Startup Current VCC < start threshold VCC < start threshold VCC < start threshold 150 150 150 µ µ µA A A Operating Supply Current Operating Supply Current Operating Supply Current FB = 0V, CS = 0V FB = 0V, CS = 0V FB = 0V, CS = 0V 7 7 7 mA mA mA VCC VCC VCC Zener Zener Zener Shunt Voltage Shunt Voltage Shunt Voltage IDD = 10mA IDD = 10mA IDD = 10mA 16 16 16 V V V ã 2009 Semtech Corp. 3 www.semtech.com SC4808B-2 POWER MANAGEMENT Pin Configuration Ordering Information Part Number Package Temp. Range (T ) A Top View (1)(2) SC4808B-2MSTRT MSOP-10 -40°C to 105°C Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (MSOP-10) ã 2009 Semtech Corp. 4 www.semtech.com SC4808B-2 POWER MANAGEMENT Pin Descriptions FB: The inverting input to the PWM comparator. Stray in- LUVLO: Line undervoltage lockout pin. An external resis- ductances and parasitic capacitance should be minimized tive divider will program the undervoltage lockout level. The by utilizing ground planes and correct layout guide lines external divider should be referenced to the quiet analog (see page 19). ground (see page 19). During the LUVLO, the driver out- puts are disabled and the softstart is reset. This pin can REF: A 0.1µF or 47nF low ESR capacitor is required and also function as an Enable/Disable. must be placed right at the pin. SYNC: SYNC is a positive edge triggered input with a thresh- old set to 1.0V. In a single controller operation, SYNC could CS: Current sense input and internal slope compensation are both provided via the CS pin. The current sense input be grounded or connected to an external synchronization from a sense resistor is used for the peak current and clock within the SYNC frequency range (see page 3). In the Bi-Phase operation mode SYNC pins could be con- overcurrent comparators. An internal 1 to 3 feed back volt- nected to the Cosc (Timing Capacitors) of the other con- age divider provides a 3X amplification of the CS signal. troller. This will force an out of phase operation (see page This is used for comparison to the external error amplifier 12). signal. If an external resistor is connected from CS to the current sense resistor, the internal current source will pro- GND: Device power and analog ground. Careful attention vide a programmable slope compensation. The value of should be paid to the layout of the ground planes (see page the resistor will determine the level of compensation. At higher compensation levels, voltage mode of operation can 19). be achieved. OUTA and OUTB: Out of phase gate drive stages. The driver’s peak source and sink current drive capability of RC: The oscillator programming pin. The oscillator should 100mA, enables the use of an external MOSFET driver or be referenced to a stable reference voltage for an accu- a NPN/PNP transistor buffer. rate and stable frequency. Only two components are re- The oscillator RC network programs the oscillator frequency, quired to program the oscillator, a resistor (tied to Vref and which is twice the OUTA/OUTB frequency. To insure that RC), and a capacitor (tied to the RC and GND). The follow- the outputs do not overlap, a dead time can be generated ing formula can be used for a close approximation of the between the two outputs by sizing the oscillator timing oscillator frequency. capacitor (see page 11). 1 1 F @ F @ OSC_ A OSC_ B R C ´0.8 R C ´0.9 OSC TOT OSC TOT VCC: The supply input for the device. Once VCC has ex- ceeded the UVLO limit, the internal reference, oscillator, where: drivers and logic are powered up. A low ESR capacitance, should be used for decoupling right at the IC pin to mini- C = C + C + C TOT OSC SC 4808 Circuit mize noise problems. C @ 22pF SC 4808 Where the frequency is in Hertz, resistance in ohms, and capacitance in farads. The recommended range of timing resistors is between 10 kohm and 200kohm and range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. Refer to layout guide lines on (page 19) to achieve best results. ã 2009 Semtech Corp. 5 www.semtech.com SC4808B-2 POWER MANAGEMENT Block Diagram VCC CS Slope Comp. OVER CURRENT Peak Current OUTA Enable OSC S Q R Disable 500mv Q T S Q Q LUVLO R REF Bandgap SOFT START UVLO R OUTB SYNC 2R LUVLO GND LUVLO FB RC SYNC Marking Information Top Mark AB2B yyww Bottom Mark xxxx xxxx yyww =Datecode (Example: 9912) xxxx = Semtech Lot # (Example: E901 xxxx 01-1) ã 2009 Semtech Corp. 6 www.semtech.com SC4808B-2 POWER MANAGEMENT SC4808B-2 Typical Characteristics (SC4808B-2A) 100.0 1.69 FB to CS Offset Start up Iq, Vcc = 4V 1.68 95.0 1.67 90.0 1.66 1.65 85.0 1.64 80.0 1.63 1.62 75.0 1.61 70.0 1.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Iq (start up) vs. Temperature FB to CS Offset vs. Temperature 3.90 1100 Max Current Sense Signal Operating Iq, Vcc = 5V Over Current Signal Operating Iq, Vcc = 5.25V 1000 3.85 900 3.80 800 3.75 700 3.70 600 3.65 500 3.60 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Iq (operating) vs. Temperature Current sense vs. Temperature 3.22 4.500 Vcc UVLO (Rising) Reference, Vcc = 5V Vcc UVLO (Falling) 3.21 4.450 3.2 4.400 3.19 4.350 3.18 4.300 3.17 4.250 3.16 4.200 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Reference vs. Temperature Vcc UVLO vs. Temperature ã 2009 Semtech Corp. 7 www.semtech.com Reference (V) Iq(uA) Iq (mA) Current Sense (mV) FB to CS offset (V) Vcc UVLO (V) SC4808B-2 POWER MANAGEMENT SC4808B-2 Typical Characteristics (Cont.) 100 1400 Oscillator Frequency 1MHz Vcc UVLO (Hysteresis) Oscillator Frequency 500kHz 98 1200 96 1000 94 92 800 90 600 88 400 86 84 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Vcc UVLO Hysteresis vs. Temperature Oscillator Frequency vs. Temperature 664 3.170 LUVLO (Rising) Sync. Frequency @ Fosc = 500kHz 3.165 662 3.160 660 3.155 3.150 658 3.145 656 3.140 3.135 654 3.130 652 3.125 3.120 650 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO vs. Temperature Synchronization Frequency vs. Temperature 49.5 140 LUVLO (Hysteresis) Maximum Duty Cycle 135 49.5 130 49.5 125 49.4 120 49.4 115 49.4 110 49.4 105 49.4 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Ta (°C) Line UVLO Hysteresis vs. Temperature Maximum Duty Cycle vs. Temperature ã 2009 Semtech Corp. 8 www.semtech.com LUVLO Hysteresis (mV) LUVLO (V) Vcc UVLO Hysteresis (mV) Synchronization Frequency (kHz) Maximum Duty Cycle (%) Oscillator Frequency (kHz) SC4808B-2 POWER MANAGEMENT SC4808B-2 Typical Characteristics (Cont.) 180 Soft Start Delay Time 170 160 150 140 130 120 110 100 90 80 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ta (°C) Soft Start Delay time vs. Temperature ã 2009 Semtech Corp. 9 www.semtech.com Soft Start Delay Time (us) SC4808B-2 POWER MANAGEMENT Application Information THEORY OF OPERATION The SC4808B-2 is a versatile double ended, high speed, age divider provides a 3X amplification of the CS signal. low power, pulse width modulator that is optimized for ap- This is used for comparison to the external error amplifier plications requiring minimum space. signal. If an external resistor is connected from CS to the The device contains all of the control and drive circuity re- current sense resistor, the internal current source will pro- quired for isolated or non isolated power supplies where vide a programmable slope compensation. The value of an external error amplifier is used. A fixed oscillator fre- the resistor will determine the level of compensation. At quency (up to 1MHz) can be programmed by an external higher compensation levels, voltage mode of operation can RC network. be achieved. The error amplifier signal at the FB pin will be The SC4808B-2 is a peak current or voltage mode used in conjunction with the CS signal to achieve regula- controller, depending on the amount of slope tion. compensation, programmable with only one external Two levels of undervoltage lockout are also available. The resistor. The cycle by cycle peak current limit prevents core LUVLO (line under voltage lockout) pin via an external re- saturation when a transformer is used for isolation while sistive divider will program the undervoltage lockout level. the overcurrent circuitry initiates the softstart cycle. During the LUVLO, the driver outputs are disabled and the The SC4808B-2 dual output drive stages are arranged in a softstart is reset. push-pull configuration. Both outputs switch at half the Once VCC has exceeded the UVLO (VCC under voltage lock- oscillator frequency using a toggle flip flop. The dead time out) limit, the internal reference, oscillator, drivers and logic between the two outputs is programmable depending on are powered up. the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. SYNC is a positive edge triggered input with a threshold The SC4808B-2 also provides flexibility with programmable set to 1.0V. LUVLO thresholds, with built-in hysteresis. By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the SUPPLY positive edge of the external control signal. In a single con- troller operation, SYNC should be grounded or connected A single supply, VCC is used to provide the bias for the to an external synchronization clock within the SYNC fre- internal reference, oscillator, drivers, and logic circuitry of quency range (see page 3). SC4808B-2. To ensure proper operation during start up, In the Bi-phase operation mode a very unique oscillator VCC slew rate of less than 10V/mS is recommended. is utilized to allow two SC4808B-2 to be synchronized together and work out of phase. This feature is setup by PWM CONTROLLER simple connection of the SYNC input to the RC pin of the other part. The fastest oscillator automatically becomes SC4808B-2 is a double ended PWM controller that can be the master, forcing the two PWMs to operate out of used in voltage or current mode applications. The phase. This feature minimizes the input and output SC4808B-2 provides a 4.4V VCC UVLO, and a 3.125V ref- ripples, and reduces stress on the capacitors. erence. The oscillator frequency is programmed by a resis- tor and a capacitor network connected to an external refer- ence provided by the SC4808B-2. The two outputs, OUTA and OUTB, are 180 degrees out of phase and run at half of the oscillator frequency. An external error amplifier will provide the error signal to the FB pin of the SC4808B-2. The current sense input and internal slope compensation are both provided via the CS pin. The current sense input from a sense resistor is used for the peak current and overcurrent comparators. An internal 1 to 3 feedback volt- ã 2009 Semtech Corp. 10 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) VCC UNDER VOLTAGE LOCK OUT OSCILLATOR Depending on the application and the voltages available, The oscillator frequency is set by connecting a RC network as shown below. the SC4808B-2 (UVLO = 4.4V) can be used to provide the VCC undervoltage lock out function to ensure the convert- ers controlled start up. Before the VCC UVLO has been reached, the internal refer- REF VCC ence, oscillator, OUTA/OUTB drivers, and logic are disabled. C26 2.2u,16V LINE UNDER VOLTAGE LOCK OUT R27 U4 R28 15k 5 6 10 REF GND 4 7 FB OUTB The SC4808B-2 also provides a line undervoltage (LUVLO 3 8 CS OUTA = Vref) function. The LUVLO pin is programmed via an ex- 2 9 RC VCC ternal resistor divider connected as shown below. The ac- C31 C33 1 10 SYNC LUVLO 200p 0.1u,25V tual start-up voltage can be calculated by using the equa- SC4808 tion below: SYNC 56.2k 10k Vin R23 R33 (R23 + R33) V = V ´ Startup REF R33 The oscillator has a ramp voltage of about Vref/2. The os- cillator frequency is twice the frequency of the OUTA and OUTB gate drive controls. R24 10k REF VCC D15 C26 The oscillator capacitor C31 is charged by a current sourced 2.2u,16V from the Vref through R27. Once the RC pin reaches about R25 18 Vref/2, the capacitor is discharged internally by the R26 R27 U4 R28 2.2k 15k 5 6 10 REF GND SC4808B-2. It should be noted that larger capacitor val- 4 7 FB OUTB ues will result in a longer dead time during the down slope 3 8 CS OUTA of the ramp. C29 2 9 RC VCC The following equation can be used as an approximation 82p C31 C33 1 10 SYNC LUVLO 200p 0.1u,25V of the oscillator frequency and the Dead time: SC4808 SYNC 1 1 56.2k 10k F @ F @ OSC_ A OSC_ B R C ´0.8 R C ´0.9 OSC TOT OSC TOT Vin R23 R33 where: REFERENCE C = C + C + C TOT OSC SC 4808 Circuit A 3.125V(SC4808B-2) reference voltage is available that can be used to source a typical current of 5mA to the ex- C @ 22pF SC 4808 ternal circuitry. The Vref can be used to provide the oscilla- C ´V ´ 0.5 OSC REF T @ tor RC network with a regulated bias. deadtime -3 3×10 The recommended range of timing resistors is between 10 kohm and 200kohm, range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. ã 2009 Semtech Corp. 11 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) SYNC/Bi-Phase operation FEED BACK In noise sensitive applications where synchronization of The error signal from the output of an external error ampli- the oscillator frequency to a reference frequency is required, fier such as SC431 or SC4431 is applied to the inverting the SYNC pin can accept the external clock. By connecting input of the PWM comparator at the FB pin either directly an external control signal to the SYNC pin, the internal os- or via an opto coupler for the isolated applications. For best cillator frequency will be synchronized to the positive edge stability, keep the FB trace length as short as possible. of the external control signal. SYNC is a positive edge trig- gered input with a threshold set to 1.0V (SC4808B-2). Vref Vout Vout In a single controller operation, SYNC should be grounded R37 C35 2.2k or connected to an external synchronization clock within R34 R32 6 3 C36 R35 FB C40 the SYNC frequency range (see page 3). 22pF 5 4 1 R36 5 C37 MOCD207 4 C38 C39 0.1u 22n SC4431 R38 Vref 2 The signal at the FB pin is then compared to the 3X ampli- fied signal from the current sense/ slope compensation CS pin. Matched out of phase signals are generated to control the OUTA and OUTB gate drives of the two phases. A single ramp signal is used to generate the control sig- nals for both phases, hence achieving a tightly matched per phase operation. REF REF Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to pro- Rosc1 Rosc2 U1 U2 5 6 5 6 vide enough head room for the opto coupler used in iso- REF GND REF GND 4 7 4 7 FB OUTB FB OUTB lated applications. 3 8 3 8 CS OUTA CS OUTA 2 9 2 9 RC VCC RC VCC GATE DRIVERS Cosc1 1 10 Cosc2 1 10 SYNC LUVLO SYNC LUVLO OUTA and OUTB are out of phase bipolar gate drive output SC4808 SC4808 stages, that are supplied from VCC and provide a peak source/sink current of about 100mA. Both stages are ca- pable of driving the logic input of external MOSFET drivers or a NPN/PNP transistor buffer. The output stages switch In the Bi-phase operation mode a very unique oscillator is at half the oscillator frequency. When the voltage on the utilized to allow two SC4808B-2’s to be synchronized RC pin is rising, one of the two outputs is high, but during together and work out of phase. This feature is set up by a fall time, both outputs are off. This “dead time” between simple connection of the SYNC input to the RC pin of the the two outputs, along with a slower output rise and fall other part. The fastest oscillator automatically becomes time, insures that the two outputs can not be on at the the master, forcing the two PWMs to operate out of phase. same time. The dead time is programmable and depends This feature minimizes the input and output ripples, and upon the timing capacitor. reduces stress on the capacitors. ã 2009 Semtech Corp. 12 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) It should be noted that if high speed/high current drivers such as the SC1301 are used, careful layout guide lines must be followed in order to minimize stray inductance, which might cause negative voltages at the output of the drivers. This negative voltage can be clamped to a reason- able level by placing a small Schottky diode directly at the output of the driver as shown below. VCC EN SC1301A U3 3 5 C23 REF VCC 0.1u 1 4 Gate_B C26 2.2u,16V D_B 2 U4 R28 5 6 10 REF GND 4 7 FB OUTB 3 8 CS OUTA VCC EN 2 9 RC VCC SC1301A C33 1 10 U6 3 5 SYNC LUVLO 0.1u,25V C34 SC4808 0.1u SYNC 1 4 Gate_A 56.2k 10k D_A Vin R23 R33 2 OVER CURRENT Two levels of over current protection are provided by the SC4808B-2. The current information is sensed at the CS pin and compared to a peak current limit level of 525mV. If the 525mV limit is exceeded, the OUTA and OUTB pulse widths and duty cycle is reduced until the CS pin reaches a second threshold of 950mV. At that point, the OUTA and OUTB are disabled, and after a delay of 140µs, the inter- nal softstart sequence is started. After the softstart dura- tion (see page 21 for calculation of softstart time), normal operation is achieved, unless the over current condition is still present. ã 2009 Semtech Corp. 13 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) SLOPE COMPENSATION (Current or Voltage mode of operation) In applications where a current mode control is used for regulation, the peak inductor current information is used to produce the average output current. If a small perturbation due to changes in supply voltage or noise pick up is gener- ated, instability may occur if the duty cycle is >50%. This phenomenon is graphically shown below. The inductor current and disturbed inductor current are shown for three different duty cycles conditions. The top wave form shows the applications where the duty cycle D is less than 50%. As shown, even if an error is introduced, after only a few cycles the error converges to zero. The second wave form shows the case where D = 50%. Under this condition, even though the error does not completely disappear, it stays constant and is not getting larger. This will be seen as jitter at the inductor voltage. The bottom wave form shows D>50%. As shown, a very small error results in a much larger error only after a few cycles. This will cause instability in the converter and the average output inductor current. The output load will not be able to be kept in regulation. Instability in current mode operation due to Duty cycle >50% d iL : Small Inductor current perturbation D : Inductor current I L D<50% D d IL iL Note: After afew cycles the perturbation disappears and stable operation returns. Time d D d D=50% iL i IL L Note: After afew cycles the perturbation is still present, although this will cause jitter, but there is no instability. Time D D>50% d IL iL d iL Note: After afew cycles the perturbation becomes larger, and causes instability. Time ã 2009 Semtech Corp. 14 www.semtech.com Error Error Error SC4808B-2 POWER MANAGEMENT Application Information (Cont.) If the R is increased, the internal ramp becomes the The instability can be corrected by modification of the peak slope comp dominant signal and more voltage mode of operation is current information slope. One of the methods to alter the achieved. As it can be calculated from the second formula peak current information is to add a positive going ramp to below, a 100% voltage mode operation can be achieved by the output of the current sensing circuitry. choosing R to be greater than 6.25K ohms. Also if a The SC4808B-2 achieves this by using an internal slope slope comp 100% current mode of operation is required, R is compensation circuit. The oscillator ramp is internally buff- slope comp reduced to zero and the contribution from the internal ramp ered and an internal 25kOhms resistor in conjunction with is completely eliminated. an external resistor at the CS pin will program the level of slope compensation. (R +R ) slope _Comp sense V ´ Ramp (R + R ) +R slope_ Comp sense int ernal %Slope _Comp= Current Transformer V CS N = 100 or 10k R REF D C é 0.2´ (%slope_Comp) ù 2.2u,16V R @ R · external int ernal ê ú Rsense 1- (0.2´%slope_ Comp) ë û Rosc RSlope Comp 15k 5 6 REF GND Next page illustrates how the buffered oscillator ramp is 4 7 FB 25k used to modify the sensed inductor current. 3 CS Cfilter 2 It should be noted that in order for the slope compensa- RC Cosc 82p 1 tion to be effective, the current sensed signal slope should SYNC 200p be at least 50% less steeper than the oscillator positive SC4808 ramp slope. The slope will include the magnetizing current RSlope Comp value will determine the Mode of operation (Voltage or Current) of the transformer and the inductor output current in iso- lated applications. In non-isolated applications, the slope The Peak current information is sensed and the result is will only include the inductor output current. realistically summed to the buffered oscillator ramp, as shown above. The value of the external resistor R slope comp will determine the percentage of the slope compensation. As the value for R is reduced, the current informa- slope comp tion becomes more dominant and the mode of operation becomes more current mode. At the same time the slope of the current information is modified to provide the slope compensation. ã 2009 Semtech Corp. 15 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) d i : Small Inductor current perturbation L Slope Compensation generation from D : Inductor current Buffered Oscillator Ramp I L I : Sensed Mosfet current Sense D>50% I : Summation of Isense and slope compensation, at the CS pin of the SC4808. Note: Below wave forms are not to scale. CS D IL I Sense Buffered Oscillator Ramp I CS ã 2009 Semtech Corp. 16 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) Below the benefits from the slope compensation become apparent. The top wave form shows the stable operation before the perturbation. The second wave form shows the perturbation and the instability caused from it if no slope compensation is added to the current information. The last wave form shows the slope compensation and the effect of it. The increase in the slope of the current information results in an early termination of the inductor current, hence a reduction in the amount of error. As the cycle is repeated, the perturbation is reduced and finally eliminated. d Stable current mode operation with Slope iL : Small Inductor current perturbation D : Inductor current Compensation IL I : Sensed Mosfet current Sense D>50% : Summation of Isense and slope compensation, at the CS pin of the SC4808. ICS Stable operation ( no perturbation) Error Signal from Error amplifier D I L I Sense Note: After a few cycles the perturbation becomes larger, and causes instability. Instable operation ( with perturbation) Error Signal from Error amplifier D IL d i L I Sense Note: After a few cycles the perturbation disappears and stable operation returns. Stable operation (Slope Compensation Added) Error Signal from Error amplifier D IL d I CS i L ã 2009 Semtech Corp. 17 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) SOFT START START UP SEQUENCE During start up of the converter, the discharged output ca- Initially during the power up, the SC4808B-2 is in under voltage lock out condition. As the Vcc supply exceeds the pacitor and the load current have large supply current re- quirements. To avoid this a soft start scheme is usually UVLO limit of the SC4808B-2, the internal reference, oscil- implemented where the duty cycle of the regulator is gradu- lator, and logic circuitry are powered up. ally increased from 0% until the soft start duration is The OUTA and OUTB drivers are not enabled until the line under voltage lock out limit is reached. At that point, once elapsed. SC4808B-2 has an internal soft start circuit that limits the the FB pin is above 1.5V, soft start circuitry starts the out- duty cycle for a duration approximated by the formula be- put drivers, and gradually increases the duty cycle from 0%. The soft start duration is internally set (see formula in low. Also the soft start circuitry is activated if an over cur- rent condition occurs. After an over current condition, OUTA Soft Start section). As the output voltage starts to increase, the error signal and OUTB are disabled and kept low for a duration of about from the error amplifier starts to decrease. If isolation is 140µs. After the delay, the OUTA and OUTB are enabled while the soft start limits the duty cycle. If the over current required, the error amplifier output can drive the LED of the opto isolator. The output of the opto is connected in a condition persists, the soft start cycle repeats indefinitely. Approximate internal soft start duration can be calculated common emitter configuration with a pull-up resistor to a reference voltage connected to the FB pin of the SC4808B- as below: 2. The voltage level at the FB pin provides the duty cycle æ VREF ö necessary to achieve regulation. (Ramp )´ ç ÷ SoftStart 2 è ø If an over current condition occurs, the outputs are dis- T @ SoftStart æ ö abled and after a soft start delay time of about 100µs, the R Internal _ SlopeComp ç ÷ + 1 softstart sequence mentioned above is repeated. ç ÷ R CS _ to _ GND è ø If longer soft start durations are required, the simple exter- nal circuit shown below can be implemented. REF VCC C26 2.2u,16V REF R37 R27 U4 R28 1k 15k 5 6 10 REF GND 6 4 7 FB OUTB C40 NA 3 8 CS OUTA 5 2 9 56.2K RC VCC C31 C33 MOCD207 1 10 200p SYNC LUVLO 0.1u,25V Csoft start SC4808 SYNC 56.2k 10k Vin R23 R33 Approximate soft start duration can be calculated as be- low: T @ C ´R37 SoftStart SoftStart ã 2009 Semtech Corp. 18 www.semtech.com SC4808B-2 POWER MANAGEMENT Application Information (Cont.) LAYOUT GUIDELINES Careful attention to layout requirements are necessary for 7) If an Opto isolator is used for isolation, quiet primary successful implementation of the SC4808B-2 PWM con- and secondary ground planes should be used. The same troller. precautions should be followed for the primary GND plane High current switching is present in the application and as mentioned in item 5 mentioned above. For the second- their effect on ground plane voltage differentials must be ary GND plane, the GND plane method mentioned in item understood and minimized. 4 should be followed. 1). The high power parts of the circuit should be laid out 8) All the noise sensitive components such as LUVLO re- first. A ground plane should be used, the number and po- sistive divider, reference by pass capacitor, Vcc bypass ca- sition of ground plane interruptions should be such as to pacitor, current sensing circuitry, feedback circuitry, and not unnecessarily compromise ground plane integrity. Iso- the oscillator resistor/capacitor network should be con- lated or semi-isolated areas of the ground plane may be nected as close as possible to the SC4808B-2. The GND deliberately introduced to constrain ground currents to return should be connected to the quiet SC4808B-2 GND particular areas, such as the input capacitor and FET plane. ground. 9) The connection from the OUTA and OUTB of the 2). In the loop formed by the Input Capacitor(s) (Cin), the SC4808B-2 should be minimized to avoid any stray induc- FET must be kept as small as possible. This loop contains tance. If the layout can not be optimized due to constraints, all the high current, fast transition switching. Connections a small Schottky diode may be connected from the OUTA/ should be as wide and as short as possible to minimize B pins to the ground directly at the IC. This will clamp ex- loop inductance. Minimizing this loop area will a) reduce cessive negative voltages at the IC. If drivers are used, the EMI, b) lower ground injection currents, resulting in electri- Schottky diodes should be connected directly at the IC from cally “cleaner” grounds for the rest of the system and c) the output of the driver to the driver ground (See page 9). minimize source ringing, resulting in more reliable gate 10) If the SYNC function is not used, the SYNC pin should switching signals. be grounded at the SC4808B-2 GND to avoid noise pick 3). The connection between FETs and the Transformer up. should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize in- ductance and resistance. 5) The SC4808B-2 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VCC supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. Avoid making a star connection between the quiet GND planes that the SC4808B-2 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible The GND connections should be connected to the quiet GND used for the SC4808B-2. ã 2009 Semtech Corp. 19 www.semtech.com SC4808B-2 POWER MANAGEMENT Gain & Phase Margin 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 36V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz ã 2009 Semtech Corp. 20 www.semtech.com Gain (dB) Phase (deg) SC4808B-2 POWER MANAGEMENT Gain & Phase Margin (Cont.) 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 48V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz ã 2009 Semtech Corp. 21 www.semtech.com Gain (dB) Phase (deg) SC4808B-2 POWER MANAGEMENT Gain & Phase Margin (Cont.) 50 225 Gain Phase (deg) 180 Gain 40 135 30 Phase 90 20 45 10 0 -45 0 -90 -10 -135 -20 -180 -30 -225 10 100 1000 10000 100000 Freq (Hz) Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 72V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz ã 2009 Semtech Corp. 22 www.semtech.com Gain (dB) Phase (deg) SC4808B-2 POWER MANAGEMENT Typical Step Load Vout 500mV/Div Iout 5A/Div 100us/Div Cout = 6X22uF (132uF) Ceramic Typical SC4808B-2 Push Pull Converter Step Load plot at Vin = 48V, Vout = 3.3V, Step = 37% to 75% Iout, Fosc = 650kHz ã 2009 Semtech Corp. 23 www.semtech.com SC4808B-2 POWER MANAGEMENT Evaluation Board Schematics ã 2009 Semtech Corp. 24 www.semtech.com SC4808B-2 POWER MANAGEMENT Evaluation Board Bill of Materials SC4808 Push Pull 3.3V 50W non Synchronous SC4808EVB__non_sync Revision: 1.1 Bill Of Materials October 7,2002 13:35:18 Item Quantity Reference Part Manufacturer # Foot Print 1 1 CON1 5output_half_brick CON\5OUTPUT_HALF_BRICK 2 1 CON2 3input_half_brick CON\3INPUT_HALF_BRICK 3 2 C3,C1 2.2n SM/C_1206 4 6 C2,C10,C17,C24,C26,C32 0.1u SM/C_0805 5 6 C4,C5,C6,C7,C8,C9 22u,6.3V GRM32DR60J226KA01 SM/C_1210_GRM 6 3 C11,C12,C13 1u,100V GRM55DR72E105KW01 SM/C_2220 7 1 C14 .1u,16V SM/C_0805 8 2 C15,C16 10u,16V GRM32DR61C106KA01 SM/C_1210_GRM 9 1 C18 22nF SM/C_1206 10 1 C19 2.2u,16V SM/C_1206 11 1 C20 1u,16V GRM32RR71H105KA011 SM/C_1210_GRM 12 2 C22,C21 82p SM/C_0805 13 1 C23 0.1u,25V SM/C_1206 14 1 C25 10nF SM/C_0805 15 2 C27,C33 22n SM/C_0805 16 1 C28 NA SM/C_0805 17 1 C29 100pF SM/C_0805 18 1 C30 1nF SM/C_0805 19 1 C31 470pF SM/C_0805 20 1 C34 .1uF SM/C_0805 21 1 C35 2.2uF 16V SM/C_0805 22 2 D2,D1 MBRB2535CTL DIODE_D2PAK 23 4 D3,D5,D6,D16 1N5819HW SOD123 24 1 D4 ZM4743A SMB/DO214 25 8 D7,D9,D10,D11,D12,D13, CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523 D14,D15 26 1 D8 LS4448 SM/DO213AC 27 1 JP1 short VIA\2P 28 1 J1 REF ED5052 29 1 J2 Vcc ED5052 30 1 J3 SYNC ED5052 31 1 L1 0.9uH PG0006 32 1 L2 LQH43MN102K011 LQH43MN102K01L SDIP0302 33 2 M1,M2 SUD19N20-90 SUD19N20-90 DPAKFET 34 1 Q1 FZT853 SM/SOT223_BCEC 35 1 Q2 FMMT718 36 4 R1,R7,R15,R19 0 SM/R_0805 37 2 R5,R2 10 SM/R_1206 38 1 R3 20k SM/R_1206 39 1 R4 250 SM/R_1210_MCR 40 2 R6,R11 TBD SM/R_0805 41 1 R8 0 SM/R_1206 42 2 R9,R10 2.2 SM/R_0805 43 1 R12 56.2k SM/R_1206 44 1 R13 10k SM/R_0805 45 1 R14 15 SM/R_0805 46 2 R16,R24 1k SM/R_0805 47 3 R17,R27,R30 15k SM/R_0805 48 1 R18 10 SM/R_0805 49 2 R26,R20 2.2k SM/R_0805 50 1 R21 10k SM/R_1206 51 1 R22 37.4k SM/R_0805 52 1 R23 18.2k SM/R_0805 53 1 R25 11.5k SM/R_0805 54 1 R28 25.5k SM/R_0805 55 1 R29 100 SM/R_0805 56 1 R31 16.2 SM/R_1206 57 1 R32 56.2k SM/R_0805 58 1 T1 PA0500 PA0500 59 1 T2 P8208T P8208T 60 1 T3 PE-68386 PE-68386 61 1 U1 SC4808 MSOP10 62 2 U2,U3 SC1301A SOT23_5PIN 63 2 U4,U5 SC4431 SOT23_5PIN 64 1 U6 MOCD207 SO-8 65 1 U7 CBRHD-02 CBRHD-02 ã 2009 Semtech Corp. 25 www.semtech.com SC4808B-2 POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly Top Board Layout Assembly Bottom Board Layout Top Board Layout Bottom ã 2009 Semtech Corp. 26 www.semtech.com SC4808B-2 POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout INNER1 Board Layout INNER2 ã 2009 Semtech Corp. 27 www.semtech.com SC4808B-2 POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS e INCHES MILLIMETERS DIM A D MIN NOM MAX MIN NOM MAX A - - .043 - - 1.10 N - - A1 .000 .006 0.00 0.15 - - A2 .030 .037 0.75 0.95 - - 2X E/2 b .007 .011 0.17 0.27 c .003 - .009 0.08 - 0.23 D .114 .118 .122 2.90 3.00 3.10 E E1 E1 .114 .118 .122 2.90 3.00 3.10 PIN 1 E .193 BSC 4.90 BSC INDICATOR e .020 BSC 0.50 BSC L .016 .024 .032 0.40 0.60 0.80 ccc C 1 2 (.037) (.95) L1 N 10 10 2X N/2 TIPS B - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .003 0.08 ccc .010 0.25 D aaa C H A2 A SEATING PLANE c A1 GAGE C PLANE bxN bbb C A-B D 0.25 L 01 (L1) DETAIL A A SEE DETAIL SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIMENSIONS DIM INCHES MILLIMETERS (.161) (4.10) C (C) G .098 2.50 G Z P .020 0.50 X .011 0.30 Y .063 1.60 Z .224 5.70 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 ã 2009 Semtech Corp. 28 www.semtech.com