SEMTECH SC4806

SC4806 Multiple Function Double Ended PWM Controller POWER MANAGEMENT Description Features The SC4806 is a double ended, high speed, highly ‹ 90 µA starting current integrated PWM controller optimized for applications ‹ Pulse-by-pulse current limit for both voltage/current requiring minimum space. The device is easily configurable modes for current mode or voltage mode operation and contains ‹ Programmable operating frequency up to 1MHz all the control circuitry required for isolated applications, ‹ Programmable external soft start where a secondary side error amplifier is used. ‹ Programmable line undervoltage lockout Designed for simplicity, the SC4806 is fully featured and ‹ Programmable external slope compensation requires only a few external components. It features a ‹ Over current shutdown with separate pin programmable frequency up to 1MHZ, external ‹ Dual output drive stages on push-pull configuration programmable soft start, pulse-by-pulse current limit and ‹ Programmable mode of operation (peak current mode over current protection for both voltage and current or voltage mode) modes, as well as a line monitoring input with hysteresis to reduce stress on the power components. A ramp pin ‹ External frequency synchronization allows for slope compensation to be programmed by ‹ Bi-phase mode of operation external resistors for current mode. This also allows for ‹ Lead free MLP-12 package,WEEE and RoHS operation in voltage mode with voltage feed forward. compliant A unique oscillator is utilized which allows two SC4806 ‹ -40 to 105 °C operating temperature to be synchronized together and work out-of-phase. This Applications feature minimizes the input and output ripples, and reduces stress and size on input/output filter components. ‹‹‹‹‹ Telecom equipment and power supplies The outputs are configured for push-pull format, dead time ‹‹‹‹‹ Networking power supplies between the 2 outputs is programmable depending on the ‹ Industrial power supplies size of the timing components. ‹ Push-pull converter The SC4806 features a turn on threshold of 8 volts . ‹ Half bridge converter The device is available at a MLP-12 package. ‹ Full bridge converter ‹ Isolated VRMs Typical Application Circuit +VIN +Vo + + -VIN -Vo I sense ON/OFF Vcc REF Rsense REF SYNC SC4806 Vcc 4 12 RC VCC FB SC1301A SC1301A 5 11 ILIM OUTA SC431 6 10 RAMP OUTB REF FB I sense Revision: October 13, 2006 1 www.semtech.com 7 3 FB SYNC 8 2 REF SS 0 GND(heatsink) 9 1 GND LUVLO SC4806 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymboMs aximu Unit SV upply Voltage -V 0.5 to18 CC SI upply Current 2A 0 m CC SYNC, RC,RAMP, LUVLO, REF, ILM, SS to GND -V 0.5 to 7 FV B to GND -0.5 to (V+V 0.5) FB REF RI EF Current 1A 0 m REF OV UTA/OUTB to GND -V 0.5 to 18 OUTA/B OI UTA/OUTB Source Current (peak) -A 250 m source OI UTA/OUTB Sink Current (peak) 2A 50 m sink Thermal Resistance, Junction to Ambient 3W 2 °C/ θ JA Thermal Resistance, Junction to Case 3W °C/ θ JC JT unction Temperature -C 55 to 150 ° J ST torage Temperature Range -C 65 to 150 ° STG PT eak IR Reflow Temperature 10 - 40s 2C 60 ° PKG ED SD Rating (Human Body Model) E2 S kV Electrical Characteristics Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A 45455 Ps arameter Tn est Condition Mp i Tx y Ms a Unit VCC Supply V Start Threshold 78 .4 8V .6 CC Hysteresis 15 .17 13 . 1V .8 Sd tartup Current V0 CC < start threshol 1A 5 µ OV perating Supply CurrentF7 B = 0V, RAMP = 0 mA VA CC Zener Shunt Voltage I6 DD = 10m 1V PWM M, aximum Duty Cycle Fosc = 50kHz, FB = 5V 49 8 405% Measured at OUTA or OUTB Minimum Duty Cycle Fosc = 50kHz, FB = 1.5V, 0% Measured at OUTA or OUTB Current Sense/Limit ILM Cycle by Cycle Current Limit Threshold 45 50 50 2 6V 0 m ILM to Output Delay 5s 0 n ILM Auto Restart Over Current Threshold 70 50 80 5 9V 5 m FB to RAMP Offset 10 .20 10 .4 1V .6  2006 Semtech Corp. 2 www.semtech.com SC4806 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 12V; CL = 100pF; T = -40°C to 105°C A Ps arameter Tn est Condition Mp i Tx y Mt a Uni Line Under Voltage Lockout Sk tart Threshold Rhigh = 14 Ω, Rlow = 10kΩ -F 3%V% RE +V 3 5.5% of Hk ysteresis Rhigh = 14 Ω, Rlow = 10kΩ mV VREF Soft Start Internal Soft Start Charge V=5 1.5V 25354A µ SS Current (I ) SS IV nternal Discharge Current =0 1.5V 1A µ SS Oscillator OR scillator Frequency = 10kΩ, C=0 200pF 40 5 50 0 5z 5 KH osc osc VREF/2 Oscillator Ramp V +0.25 On scillator Fall TimeG0 uaranteed by characterizatio 20 0 2s 5 n RC pin to GND Capacitance 2F 2 p On scillator Frequency RangeG0 uaranteed by characterizatio501z 00 KH Sync/CLOCK Clock SYNC Threshold 1V .75 Sn ync Frequency RangeGF uaranteed by characterizatio *z 1.3 KH OSC Bandgap ReferenceVoltage 40 .75 55 . 5V .2 RI eference Load Regulation =0 0 - 5mA 1A mV/m REF RV eference Line Regulation=3 8.5V to 15V 0V . mV/ CC Output OUT Low Level 07 .5 0V . OV UT High Level =5 12V 10 0.81V 1.2 CC RF ise Time L5 oad 1n 3s n FF all Time L5 oad 1n 3s n Minimal Dead Time 20 00 2s 5 n Thermal Shutdown Thermal Shutdown 1C 75 ° Threshold T SD Thermal Shutdown 1C 5 ° Hysteresis  2006 Semtech Corp. 3 www.semtech.com SC4806 POWER MANAGEMENT Pin Configuration Ordering Information (1) DEVICEPT ACKAGE Temp. Range ( ) TOP VIEW J (2) SC4806MLTRTMC LPQ-12 -40°C to 105° VCC OUTA OUTB Notes: (1) Only available in tape and reel packaging. A reel 12 11 10 contains 3000 devices. LUVLO 1 9 GND (2) Lead free product. This product is fully WEEE and RoHS compliant. SS 2 8 REF SYNC 3 7FB 4 5 6 RC ILIM RAMP BOTTOM VIEW RC ILIM RAMP 4 5 6 SYNC 3 7FB GND SS 2 8 REF LUVLO 1 9 GND 12 11 10 VCC OUTA OUTB (MLPQ-12 4x4)  2006 Semtech Corp. 4 www.semtech.com SC4806 POWER MANAGEMENT Pin Descriptions LUVLO (Pin 1): RC (Pin 4): Line undervoltage lockout pin. An external resistive di- The oscillator programming pin. The oscillator should be vider from the Input supply will program the undervoltage referenced to a stable reference voltage for an accu- rate and stable frequency. Only two components are re- lockout level. The external divider should be referenced to the quiet analog ground. During the LUVLO, the driver quired to program the oscillator, a resistor (tied to Vref outputs are disabled. This pin can also function as an and RC), and a capacitor (tied to the RC and GND). The Enable/Disable. following formula can be used for a close approximation of the oscillator frequency. SS (Pin 2): 1 F ≅ OSC R C OSC TOT An internal 35µA current source charges the external capacitor connected to this pin. This pin is connected to where: one of the inputs of the PWM comparator. When the volt- age on this SS pin increases, but less than 1/3 of the C = C + C + C feedback voltage V , the pulse width of OUTA and OUTB TOT OSC SC4806 Circuit FB gradually increases to achieve soft start. As the output voltage increases and feedback loop enters regulation, C ≅ 22pF SC4806 the PWM modulator is controlled by V . At normal opera- FB tion, the voltage at SS pin is clamped at Vref. The recommended range of timing resistors is between When the Over Current is tripped, both OUTA and OUTB 10kohm and 200kohm and range of timing capacitors are pulled low after a typical time delay (Typ. 100ns). At is between 100pF and 1000pF. Timing resistors less the same time, the SS cap is gradually discharged via an than 10kohm should be avoided. equivalent 10µA internal current source. When the volt- Refer to layout guidelines in Application Information sec- age on SS pin is dropped below 0.8V, a new SS cycle is tion to achieve best results. initiated while the SS cap is charged with 35µA again. ILim (Pin 5): The internal thermal protection circuit monitors the die o temperature. If the temperature exceeds 175 C, the con- The current signal from a sense resistor is applied to troller is completely shutdown. When the temperature is peak current and overcurrent comparators through ILM o dropped below 160 C, defined by the hysteresis, the con- pin. troller re-starts with soft start process. Under normal operation condition, the comparators are not trigged. When the current signal sensed at ILM pin SYNC (Pin 3): exceeds the first threshold -- pulse-by-pulse current limit, the corresponding on-time is terminated for the remain- SYNC is a positive edge triggered input with a threshold der of the switching cycle. In this case, the circuit output set to 1.75V. In a single controller operation, SYNC could voltage loses regulation even though it continues to pro- be grounded or connected to an external synchroniza- vide full load current. tion clock within the SYNC frequency range. In Bi-Phase operation mode SYNC pins could be connected to the When the load current continuously increases and the Cosc (Timing Capacitors) of the other controller. This will sensed signal at ILM pin reaches the second threshold - force an out-of-phase operation (see Application Infor- - over current limit, the controller turns off both OUTA mation part). and OUTB. At the same time, the SS cap is discharged with equivalent 10uA current source. When the voltage at SS pin is below 0.5V, the controller initiates re-start. The pins Ramp and ILM are discharged by the internal FETs at the end of each switching cycle.  2006 Semtech Corp. 5 www.semtech.com SC4806 POWER MANAGEMENT Pin Descriptions (Cont.) Ramp (Pin 6): GND (Pin 9): The signal at this pin will be used as the PWM ramp sig- Device power and analog ground. The exposed paddle nal that will be compared to the FB to achieve regula- area on the back of the package must be connected to tion. The modes of operation can be programmed de- the GND (pin9). Careful attention should be paid to the pending on how this pin is configured (For more details layout of the ground planes. see Application section). OUTB (Pin 10) and OUTA (Pin 11): For voltage mode control, the PWM ramp is generated via external RC circuit connected from a voltage source Out of phase gate drive stages. The driver’s peak source to the Ramp pin. Connection to a fixed voltage source and sink current drive capability of 100mA, enables the (REF) will provide a constant peak ramp with a frequency use of an external MOSFET driver or a NPN/PNP transis- set by the internal oscillator frequency programed at tor totem pole driver. the RC pin. Connection to a variable source such as the VIN will provide the added benefit of the feed forward The oscillator RC network programs the oscillator fre- function enhancing the converter static and dynamic per- quency, which is twice the OUTA/OUTB frequency. To in- formance. sure that the outputs do not overlap, a dead time can be generated between the two outputs by sizing the oscilla- For Current mode control the current information from tor timing capacitor (see Application Information section). the ILim pin can be directly connected to the Ramp pin without the need for the external RC circuit at the Ramp VCC (Pin 12): pin. The supply input for the device. Once VCC has exceeded If current mode of operation with slope compensation is the UVLO limit, the internal reference, oscillator, drivers required, an external resistor connected from the ILim and logic are powered up. A low ESR capacitor, should pin to the Ramp pin will provide the slope compensa- be placed right at the pin to minimize noise problems. It tion. The percentage of the slope compensation will be is recommended that the V rising rate during start-up CC inversely proportional to the value of the resistor ( the be smaller than 10V/mS. higher resistor lower slope compensation, the lower re- sistor higher slope compensation). 1/3 of external feed- THERMAL PAD: back signal to FB pin by an internal 3 to 1 resistor di- vider compares to the combined current signal to gener- Pad for heatsinking purposes. Connect to ground plane ate PWM control signal. using multiple thermal vias. Not connected internally. FB (Pin 7): The inverting input to the PWM comparator through an internal 3 to 1 resistor divider. Stray inductances and parasitic capacitance should be minimized by utilizing ground planes and correct layout guidelines. REF (Pin 8): Bandgap reference output. It is recommended by plac- ing a minimum 2.2uF low ESR capacitor right at the pin.  2006 Semtech Corp. 6 www.semtech.com SC4806 POWER MANAGEMENT Block Diagram RAMP 35uA 10uA ABOA Marking Information Top View yyww = Date Code (Example: 0012) xxxxxx = Semtech Lot #  2006 Semtech Corp. 7 www.semtech.com SC4806 POWER MANAGEMENT Application Information To generate PWM control signal, 1/3 of external feed- back signal to FB pin by an internal 3 to 1 resistor divider SC4806 is a versatile double ended, high speed, low compares to the combined current signal if an external power, pulse width modulator optimized for applications resistor is connected from ILIM to RAMP. The value of requiring minimum space. the resistor will determine the level of slope compensa- tion. The slope signal to RAMP is generated from either The device contains all of control and drive circuity re- quired for isolated or non isolated power supplies where input voltage or VREF with external RC. Voltage mode of an external error amplifier is used. A fixed oscillator fre- operation can be achieved if the slope signal is only used. quency (up to 1MHz) can be programmed by an external RC network. Two levels of undervoltage lockout are also available. The LUVLO (line under voltage lockout) pin via an exter- SC4806 is a peak current or voltage mode controller, nal resistive divider programs input voltage turn-on level. depending on the amount of slope compensation, During the LUVLO, the driver outputs are disabled and programmable with only one external resistor. The cycle the soft-start is reset. by cycle peak current limit prevents core saturation when a transformer is used for isolation while the auto-restart The VCC UVLO (under voltage lockout) determines VCC over-current circuitry initiates the soft-start cycle. voltage turn-on level. Once VCC exceeds the UVLO limit, the internal reference, oscillator, drivers and logic are SC4806 dual output drive stages are arranged for double powered up. ended configurations. Both outputs switch at half the oscillator frequency using a toggle flip flop. The dead time SYNC is a positive edge triggered input with a threshold between the two outputs is programmable depending set to 1.75V. By connecting an external control signal to on the values of the timing capacitor and resistors, thus the SYNC pin, the internal oscillator frequency will be limiting each output stage duty cycle to less than 50%. synchronized to the positive edge of the external control signal. In a single controller operation, SYNC should be SC4806 also provides flexibility with programmable grounded or connected to an external synchronization LUVLO thresholds, with built-in hysteresis. clock within the SYNC frequency range. In the Bi-phase operation mode, a very unique oscillator is utilized to al- PO POWER SUPPL WER SUPPLY Y PO PO POWER SUPPL WER SUPPL WER SUPPLY Y Y low two SC4806s to be synchronized together and work out of phase. This feature is set up by simple connection A single supply, VCC is used to provide the bias for the of the SYNC input of one part to the RC pin of the other. internal reference, oscillator, drivers, and logic circuitry The master oscillator forces the two PWMs to operate of SC4806. out of phase. This feature minimizes the input and out- put ripples, and may reduce input and output capaci- PWM CONTROLLER PWM CONTROLLER PWM CONTROLLER PWM CONTROLLER PWM CONTROLLER tors. SC4806 is a double ended PWM controller that can be VCC UNDER V CC UNDER V CC UNDER VOL OL OLT T TA A AGE L GE L GE LOCK OUT OCK OUT OCK OUT CC UNDER V CC UNDER VOL OLT TA AGE L GE LOCK OUT OCK OUT used in voltage or current mode applications. The oscil- lator frequency is programmed by a resistor and a ca- Depending on the application and the voltages available, pacitor network connected to an external reference pro- the SC4806 (UVLO = 8V) can be used to provide the VCC vided by the SC4806. The two outputs, OUTA and OUTB, undervoltage lock out function to ensure the converters are 180 degrees out-of-phase and run at half of the controlled start up. oscillator frequency. Before the VCC UVLO has been reached, the internal ref- An external error amplifier will provide the error signal to erence, oscillator, OUTA/OUTB drivers, and logic are dis- the FB pin of the SC4806. The current limit input and abled. external slope compensation are provided separately via the ILIM and RAMP pins. The current limit signal from a LINE UNDER V LINE UNDER VOL OLT TA AGE L GE LOCK OUT OCK OUT LINE UNDER V LINE UNDER V LINE UNDER VOL OL OLT T TA A AGE L GE L GE LOCK OUT OCK OUT OCK OUT sense resistor or a current sense transformer is used for the peak current and auto-restart overcurrent The SC4806 also provides a line undervoltage (LUVLO = comparators. Vref) function. The LUVLO pin is programmed via an ex-  2006 Semtech Corp. 8 www.semtech.com SC4806 POWER MANAGEMENT The oscillator has a ramp voltage of about Vref/2. The Application Information (Cont.) oscillator frequency is twice the frequency of the OUTA ternal resistor divider connected as shown below. The and OUTB gate drive controls. actual start-up voltage can be calculated by using the equation below: The oscillator capacitor CT is charged from the Vref R1 through RT. Once the RC pin reaches about Vref/2, the V = V × (1 + ) Startup REF R2 capacitor is discharged internally by the SC4806. It should be noted that larger capacitor values will result in a longer dead time during the down slope of the ramp. +VIN The following equation can be used as an approximation + of the oscillator frequency and the Dead time: -VIN R1 1 F ≅ OSC R C OSC TOT ON/OFF R2 REF SYNC where: SC4806 Vcc C = C + C + C TOT OSC SC4806 Circuit 4 12 RC VCC C ≅ 22pF 5 11 SC4806 ILim OUTA 6 10 RAMP OUTB C × V × 0.5 OSC REF T ≅ deadtime −3 3 ⋅10 REF The recommended range of timing resistors is between FB I sense 10 kohm and 200kohm, range of timing capacitors is between 100pF and 1000pF. Timing resistors less than REFERENCE REFERENCE REFERENCE REFERENCE REFERENCE 10 kohm should be avoided. A 5V reference voltage is available that can be used to SYNC/Bi-Phase operation SYNC/Bi-Phase operation SYNC/Bi-Phase operation SYNC/Bi-Phase operation SYNC/Bi-Phase operation source a typical current of 5mA to the external circuitry. The Vref can be used to provide the oscillator RC net- In noise sensitive applications where synchronization of work with a regulated bias. the oscillator frequency to a reference frequency may be required, the SYNC pin can accept the external clock. OSCILLA OSCILLA OSCILLA OSCILLA OSCILLATOR TOR TOR TOR TOR By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to The oscillator frequency is set by connecting a RC net- the positive edge of the external control signal. SYNC is work as shown below. a positive edge triggered input with a threshold set to +VIN 1.75V. In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range. REF SYNC SC4806 Vcc In the Bi-phase operation mode a very unique oscillator RT 4 12 RC VCC is utilized to allow two SC4806’s to be synchronized CT 5 11 ILIM OUTA together and work out of phase. This feature is set up 6 10 RAMP OUTB by a simple connection of the SYNC input to the RC pin of the other part. The master oscillator forces two PWMs to operate out of phase. This feature minimizes REF the input and output ripples, and may reduce input and FB output capacitors. I sense  2006 Semtech Corp. 9 www.semtech.com 7 3 FB SYNC 8 2 REF SS 7 3 FB SYNC 0 GND(heatsink) 9 1 8 2 GND LUVLO REF SS 0 GND(heatsink) 9 1 GND LUVLO SC4806 POWER MANAGEMENT Application Information (Cont.) The signal at the FB pin is then compared to the 3X sig- nal from the current sense/ slope compensation RAMP pin. Matched out of phase signals are generated to con- REF REF Slave M aster trol the OUTA and OUTB gate drives of the two phases. A SC 4806 SC 4806 Vcc Vcc single ramp signal is used to generate the control signals Rosc1 Rosc2 4 12 4 12 for both phases, hence achieving a tightly matched per RC VCC RC VCC Cosc1 Cosc2 phase operation. 5 11 5 11 ILIM OUTA ILIM OUTA 6 10 6 10 RAMP OUTB RAMP OUTB Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to provide enough head room for the opto coupler used in isolated applications. G G G G GA A A A ATE DRIVERS TE DRIVERS TE DRIVERS TE DRIVERS TE DRIVERS OUTA (PWM1) OUTA and OUTB are out of phase bipolar gate drive out- put stages, that are supplied from VCC and provide a OUTB (PWM1) peak source/sink current of about 100mA. Both stages are capable of driving the logic input of external MOSFET OUTA (PWM2) drivers or a NPN/PNP transistor buffer. The output stages switch at half the oscillator frequency. When the voltage on the RC pin is rising, one of the two outputs is high, but OUTB (PWM2) during fall time, both outputs are off. This “dead time” between the two outputs, along with a slower output rise and fall time, insures that the two outputs can not be on at the same time. The dead time is programmable and FEED BACK FEED BACK FEED BACK FEED BACK FEED BACK depends upon the timing capacitor. The error signal from output of an external error ampli- It should be noted that if high speed/high current drivers fier such as SC431 or SC4431 is applied to the inverting such as the SC1301 are used, careful layout guide lines input of the PWM comparator at the FB pin either di- must be followed in order to minimize stray inductance, rectly or via an opto-coupler for the isolated applications. which might cause negative voltages at the output of For best stability, keep the FB trace length as short as the drivers. This negative voltage can be clamped to a possible. reasonable level by placing a small Schottky diode di- rectly at the output of the driver as shown below: +Vo Lo1 + VCC Co1 -Vo D_B1 1 4 Gate_A SC 4806 D_B2 REF 4 12 RC VCC SC1301A 5 11 ILIM OUTA 6 10 RAMP OUTB VCC FB D_A1 1 4 Gate_B SC431 D_A2 SC1301A  2006 Semtech Corp. 10 www.semtech.com 7 3 FB SYNC 8 2 REF SS 0 GND(heatsink) 9 1 GND LUVLO 7 3 FB SYNC 8 2 REF SS 0 GND(heatsink) 9 1 GND LUVLO 7 3 FB SYNC 8 2 REF SS 0 GND(heatsink) 9 1 GND LUVLO 2 3 2 3 5 5 SC4806 POWER MANAGEMENT In current mode control, the ramp voltage is not derived Application Information (Cont.) artificially from a ramp generator. It is instead provided OPERA OPERATION MODE TION MODE OPERA OPERA OPERATION MODE TION MODE TION MODE from a power converter inductor current by a current sensing transformer or resistor. Thus a second, inner SC4806 can be configured in either voltage mode or cur- control loop is formed by comparing the inductor current rent mode. In voltage mode, a ramp is externally gener- ramp to control voltage from outer voltage loop. Now ated by RC network. The R can be connected to Vref or the control voltage programs the inductor current via the other fixed voltage source as shown below. By compar- inner loop and no longer controls the duty cycle directly. ing control signal to the ramp, PWM duty cycle is derived. The current mode control corrects most of problems with direct duty cycle control in voltage mode. The chief ad- vantage of the methods its inherent feed-forward char- SC4806 Voltage mode (Non-Feed Forward) acteristics and simplified loop dynamics. An added ben- Vref or other fixed Voltage source efits is the reduction or elimination of transformer satu- ration problems in full-bridge or push-pull isolated con- verters. The current mode configuration with SC4806 is R1 as shown below: Ramp C1 SC4806 100% Current mode (No Slope Compensation) R3 Isense ILIM Ramp C2 R3 Isense ILIM C2 Voltage mode with feed-forward operation is imple- mented if the R is connected to input voltage as shown below. With this implementation, the ramp amplitude varies directly with input voltage. If control signal to FB is The current mode control ling the peak inductor current constant, the duty cycle varies inversely with input volt- results in circuit instability whenever the steady state duty age. Thus the volt-second product, Vin*D, remains con- cycle is greater than 0.5. An artificial slope has to be stant without any control change. Open loop line regula- added to avoid such problem. Power transformer mag- tion better than direct duty cycle control as shown above. netizing current riding on the reflected inductor current Good dynamic response is achieved with less closed loop acts to provide some slope compensation, but the gain required. amount is rather variable and indeterminate. The cur- rent mode with slope compensation is as shown below: SC4806 Voltage mode (Feed Forward) SC4806 Current mode (With Slope Compensation) Vin Vref or other fixed Voltage source R1 Ramp RC C1 Ramp R3 Isense ILIM ILIM C2 Isense  2006 Semtech Corp. 11 www.semtech.com SC4806 POWER MANAGEMENT Application Information (Cont.) LA LAY YOUT GUIDELINES OUT GUIDELINES LA LA LAY Y YOUT GUIDELINES OUT GUIDELINES OUT GUIDELINES SOFT S SOFT S SOFT S SOFT S SOFT ST T T T TART ART ART ART ART Careful attention to layout requirements are necessary for successful implementation of the SC4806 PWM control- During start up of the converter, the discharged output ler. capacitor and the load current have large supply current requirements. To avoid this a soft start scheme is usu- High current switching is present in the application and ally implemented where the duty cycle of the regulator is their effect on ground plane voltage differentials must be gradually increased from 0% until the soft start duration understood and minimized. is elapsed. 1) The high power parts of the circuit should be laid out SC4806 has soft start circuit with an external capacitor first. A ground plane should be used, the number and po- that limits the duty cycle for a duration approximated by sition of ground plane interruptions should be such as to the formula below. Also the soft start circuitry is acti- not unnecessarily compromise ground plane integrity. Iso- vated if an over current condition occurs. After an over lated or semi-isolated areas of the ground plane may be current condition, OUTA and OUTB are disabled and kept deliberately introduced to constrain ground currents to low. After the delay, the OUTA and OUTB are enabled while particular areas, such as the input capacitor and FET the soft start limits the duty cycle. If the over current ground. condition persists, the soft start cycle repeats indefinitely. 2) In the loop formed by the Input Capacitor(s) (Cin), the S S S S ST T T T TART UP SEQUENCE ART UP SEQUENCE ART UP SEQUENCE ART UP SEQUENCE ART UP SEQUENCE FET must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections Initially during the power up, the SC4806 is in under volt- should be as wide and as short as possible to minimize age lock out condition. As the Vcc supply exceeds the loop inductance. Minimizing this loop area will a) reduce UVLO limit of the SC4806, the internal reference, oscil- EMI, b) lower ground injection currents, resulting in electri- lator, and logic circuitry are powered up. cally “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate The OUTA and OUTB drivers are not enabled until the line switching signals. under voltage lock out limit is reached. At that point, once the FB pin is above 1.5V, soft start circuitry starts the 3) The connection between FETs and the Transformer output drivers, and gradually increases the duty cycle from should be a wide trace or copper region. It should be as 0%. short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize As the output voltage starts to increase, the error signal EMI. from the error amplifier starts to decrease. If isolation is required, the error amplifier output can drive the LED of 4) The Output Capacitor(s) (Cout) should be located as the opto isolator. The output of the opto is connected in close to the load as possible. Fast transient load cur- a common emitter configuration with a pull-up resistor rents are supplied by Cout only, and connections between to a reference voltage connected to the FB pin of the Cout and the load must be short, wide copper areas to SC4806. The voltage level at the FB pin provides the minimize inductance and resistance. duty cycle necessary to achieve regulation. 5) A SC4806 is best placed over a quiet ground plane If an over current condition occurs, the outputs are dis- area. Avoid pulse currents in the Cin FET loop flowing in abled and after a soft start delay time of about 100µs, this area. GND should be returned to the ground plane the soft-start sequence mentioned above is repeated. close to the package and close to the ground side of (one of) the VCC supply capacitor(s). Under no circum- stances should GND be returned to a ground inside the Cin, Q1, Q2 loop. Avoid making a star connection be-  2006 Semtech Corp. 12 www.semtech.com SC4806 POWER MANAGEMENT Application Information (Cont.) tween the quiet GND planes that the SC4806 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error ampli- fier and the FB pin should be kept as short as possible The GND connections should be connected to the quiet GND used for the SC4806. 7) If an Opto isolator is used for isolation, quiet primary and secondary ground planes should be used. The same precautions should be followed for the primary GND plane as mentioned in item 5 mentioned above. For the second- ary GND plane, the GND plane method mentioned in item 4 should be followed. 8) All the noise sensitive components such as LUVLO resistive divider, reference by pass capacitor, Vcc bypass capacitor, current sensing circuitry, feedback circuitry, and the oscillator resistor/capacitor network should be connected as close as possible to the SC4806. The GND return should be connected to the quiet SC4806 GND plane. 9) The connection from the OUTA and OUTB of the SC4806 should be minimized to avoid any stray induc- tance. If the layout can not be optimized due to con- straints, a small Schottky diode may be connected from the OUTA/B pins to the ground directly at the IC. This will clamp excessive negative voltages at the IC. If drivers are used, the Schottky diodes should be connected di- rectly at the IC from the output of the driver to the driver ground. 10) If the SYNC function is not used, the SYNC pin should be grounded at the SC4806 GND to avoid noise pick up.  2006 Semtech Corp. 13 www.semtech.com CON2 9 Vout+ MBRB2535CTL JP3 PA0810 JP9 1 2 11 4 R13 3 8 Sens 10 R14 6T 1T 0 Vin+ D1 L1 4 10 JP11 2.2n C13 1 2 3 8 CON1 R8 R9 JP1 JP2 JP12 10 R16 0.9uH 250 MBRB2535CTL 7 JP6 6T 1T JP10 Trim 1 49.9k 2.2n C15 1 Vin+ FZT853 5 7 4 Q2 1 3 R42 B TBD 0 D2 R20 4T VCC 6 Sens 2 6 ON/OFF 0 T1 VCC = 12V R18 T3 16.2 P8208T 5 Vout- 4 Vin- MA1 MB1 U2 SUD19N20-90 100 SUD19N20-90 100 RH02 5output_half _brick 0 R15 0 R10 1 1 100p 100p 2 10k C23 10k C7 2.2 R17 2.2 R11 L2 R19 R12 C24 10u,16V 1 0 0 R21 56.2k JP5 JP4 JP8 JP7 VCC G_A G_B LUVLO & ON/OFF & OVP J1 C25 R22 1nF 10k SS J2 C26 G_A G_A_cap 0.1uF 16V VCC J3 R23 TBD REF R24 C27 C28 SYNC U1 JP25 10 0.1u D7 22nF 1 4 SC4806 R26 R25 15k D8 4 12 0 D10 RC VCC T4 D9 U3 ILim 1 6 5 11 Sync Drive Supply ILim OUTA SC1301A 1u,16V C31 Sync Drive Supply 6 10 R28 RAMP OUTB G_B R_Pull_Up VCC 3 4 U5 3.01k 0 D11 2.2k PE-68386 D12 R31 SC4431 R_Slope_V R_Slope_I R30 J4 J5 5 37.4k C33 20k 301 0.1u D13 0 4 C36 1 4 U7 C34 C35 2.2u,16V 0.1u 22n Q_Slope_Comp 8 1 C37 D14 REF R32 .1uF FMMT718 18.2k J7 7 2 J6 R33 U6 1k SC1301A 6 3 Sync Drive Supply 5 4 100pF C40 1k ILim_in R37 R36 R1 LS4448 MOCD207 C41 R38 11.5k C A 2.2k 1nF 15k 82p 15 D3 10k R39 C2 R4 R3 5 25.5k C42 470pF 4 JP28 C43 C44 R43 0.1u 22n 100 U8 R41 15k SC4431 D15 1N5819HW SC4806 POWER MANAGEMENT Push Pull Evaluation Board Sch C30 82pF C8 1u,100V C9 1u,100V D4 ZM4743A A C 7 3 C11 FB SYNC .1u,16V REF 8 2 REF SS 0 C12 GND(heatsink) 9 1 10u,16V GND LUVLO E C C10 1u,100V 0.1u,25V C29 2 3 2 3 5 5 A AC C A AC C CMOSH-3 CMOSH-3 CMOSH-3 CMOSH-3 R_GS_MA1 2 3 R_GS_MB1 2 3 1 8 N = 100 7 3 1 4 2 3 CMOSH-3 CMOSH-3 C A A C CMOSH-3 A C C A CMOSH-3 A C C16 22u,6.3V C17 22u,6.3V C18 22u,6.3V C19 2 1 2 1 22u,6.3V C20 Vref Vref 22u,6.3V C21 22u,6.3V C22 0.1u C14 0.1u  2006 Semtech Corp. 14 www.semtech.com VCC SC4806 POWER MANAGEMENT Evaluation Board Bill of Materials SC4806 Slope Compensation Current Mode Push Pull 3.3V 35W non Synchronous SC4806EVB__non_sync Revision: 1.1 Bill Of Materials March 30,2005 11:27:17 Item Quantity Reference Part Manufacturer # Foot Print 1 1 CON1 3input_half_brick CON\3INPUT_HALF_BRICK 2 1 CON2 5output_half_brick CON\5OUTPUT_HALF_BRICK 3 1 C2 82p SM/C_0805 4 2 C23,C7 100p SM/C_1206 5 3 C8,C9,C10 1u,100V GRM44-1X7R105K250AL(muRata) SM/C_2220 6 1 C11 .1u,16V SM/C_0805 7 2 C24,C12 10u,16V GRM32DR61C106KA01(muRata) SM/C_1210_GRM 8 2 C13,C15 2.2n SM/C_1206 9 6 C14,C22,C27,C33,C34,C43 0.1u SM/C_0805 10 6 C16,C17,C18,C19,C20,C21 22u,6.3V GRM32DR60J226KA01(muRata) SM/C_1210_GRM 11 2 C41,C25 1nF SM/C_0805 12 1 C26 0.1uF 16V SM/C_0603 13 1 C28 22nF SM/C_1206 14 1 C29 0.1u,25V SM/C_1206 15 1 C30 82pF SM/C_0805 16 1 C31 1u,16V GRM32RR71H105KA011(muRata) SM/C_1210_GRM 17 2 C44,C35 22n SM/C_0805 18 1 C36 2.2u,16V SM/C_1206 19 1 C37 .1uF SM/C_0805 20 1 C40 100pF SM/C_0805 21 1 C42 470pF SM/C_0805 22 2 D2,D1 MBRB2535CTL DIODE_D2PAK 23 1 D3 LS4448 SM/DO213AC 24 1 D4 ZM4743A SMB/DO214 D5,D6,R12,R13,R19,R20, 25 8 0 SM/R_0805 R26,R31 D7,D8,D9,D10,D11,D12,D13, 26 8 CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523 D14 27 1 D15 1N5819HW SOD123 JP1,JP2,JP3,JP4,JP5,JP6, 28 14 JP7,JP8,JP9,JP10,JP11, short VIA\2P JP12,JP25,JP28 29 1 J1 SS ED5052 30 1 J2 Vcc ED5052 31 1 J3 SYNC ED5052 32 1 J4 OUTA ED5052 33 1 J5 OUTB ED5052 34 1 J6 REF ED5052 35 1 J7 FB ED5052 36 1 L1 0.9uH PG0006.102(Pulse) PG0006 37 1 L2 LQH43MN102K011 LQH43MN102K01L(muRata) SDIP0302 38 2 MB1,MA1 SUD19N20-90 SUD19N20-90(vishay) DPAKFET 39 1 Q_Slope_Comp FMMT718 FMMT718 (Zetex) SM/SOT23_BEC 40 1 Q2 FZT853 FZT853 (Zetex) SM/SOT223_BCEC 41 3 R_GS_MB1,R_GS_MA1,R3 10k SM/R_0805 42 1 R_Pull_Up 3.01k SM/R_0805 43 1 R_Slope_I 301 SM/R_0805 44 1 R_Slope_V 20k SM/R_0805 45 2 R1,R33 1k SM/R_0805 46 1 R4 15 SM/R_0805 47 1 R8 49.9k SM/R_1206 48 1 R9 250 SM/R_1210_MCR 49 2 R10,R15 100 SM/R_1206 50 2 R17,R11 2.2 SM/R_0805 51 2 R16,R14 10 SM/R_1206 52 1 R18 16.2 SM/R_0805 53 1 R21 56.2k SM/R_1206 54 1 R22 10k SM/R_1206 55 2 R42,R23 TBD SM/R_0805 56 1 R24 10 SM/R_0805 57 3 R25,R38,R41 15k SM/R_0805 58 2 R37,R28 2.2k SM/R_0805 59 1 R30 37.4k SM/R_0805 60 1 R32 18.2k SM/R_0805 61 1 R36 11.5k SM/R_0805 62 1 R39 25.5k SM/R_0805 63 1 R43 100 SM/R_0805 64 1 T1 PA0810 PA0810(Pulse) PA0810 65 1 T3 P8208T P8208T(Pulse) P8208T 66 1 T4 PE-68386 PE-68386(Pulse) PE-68386 67 1 U1 SC4806 SC4806(Semtech) MLPQ-12 (4X4) 68 1 U2 RH02 RH02(Diodes Inc.) RH02 69 2 U6,U3 SC1301A SC1301A(Semtech) SOT23_5PIN 70 2 U5,U8 SC4431 SC4431(Semtech) SOT23_5PIN 71 1 U7 MOCD207 SO-8  2006 Semtech Corp. 15 www.semtech.com SC4806 POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly TOP Board Layout Assembly Bottom 2 1 Board Layout Top Board Layout Bottom  2006 Semtech Corp. 16 www.semtech.com SC4806 POWER MANAGEMENT Evaluation Board Gerber Plots (Cont.) Board Layout Inner1 Board Layout Inner2 Evaluation Board Modifications 1 R Slope I Q Slope Comp D15 R43 R Pull up R Slope V 2 Board Layout Bottom  2006 Semtech Corp. 17 www.semtech.com Vin+ JP17 CON1 R8 R9 CON2 250 1 49.9k 9 Vin+ Vout FZT853 MB1 Q2 SUD19N20-90 100 B 2.2 0 R10 1 MBRB2535CTL VCC JP22 1 PA0801 2 R11 100p 2 11 4 R13 N/OFF 10k C7 3 8 1T Sens 0 10 10 R14 VCC = 12V JP19 4T 0 D1 1T JP24 L1 4 2.2n C13 R12 JP20 9 1 2 JP18 4 3 Vin- 10 R16 1T 1.9uH 8 MBRB2535CTL 7 4T JP21 JP23 Trim 2.2n C15 1 1T 5 7 4 1 3 R42 TBD MA1 D2 0 R20 4T SUD19N20-90 100 6 Sens 0 R15 6 0 1 T1 100p R18 10k C23 T3 16.2 R17 P8208T 5 Vout- 2.2 U2 RH02 5output_half _brick R19 0 2 JP15 JP16 JP13 JP14 L2 R21 56.2k C1 R6 C5 R7 C24 10u,16V 1 2.2n 10 2.2n 10 VCC T2 PA0264 G_A_cap G_B LUVLO & ON/OFF & OVP J1 C25 R22 1nF 10k SS J2 C26 G_A 0.1uF 16V VCC J3 R23 TBD Vin+ REF R24 C27 C28 U1 JP25 SYNC 10 0.1u D7 22nF 1 4 SC4806 R26 R25 JP26 15k D8 4 12 0 D10 RC VCC T4 D9 U3 ILim 1 6 5 11 Sync Drive Supply ILim OUTA SC1301A R27 1u,16V 316k C31 Sync Drive Supply 6 10 R28 RAMP OUTB G_B VCC 3 4 U5 D11 0 2.2k PE-68386 D12 R31 SC4431 R30 J4 J5 5 37.4k C33 0.1u D13 0 4 C36 1 4 U7 C34 C35 2.2u,16V 0.1u 22n 8 1 C37 D14 REF R32 .1uF 18.2k J7 7 2 J6 R33 U6 1.1k SC1301A 6 3 C39 R35 6.8nF 0 Sync Drive Supply 5 4 47pF C40 ILim_in 1k R37 R36 R1 MOCD207 C41 R38 1.62k U4 1.1k 1 4 2.2nF 25.5k 82p 15 R39 C2 R4 5 25.5k C42 2 3 680pF 4 RH02 C43 C44 R43 0.1u 22n 100 U8 R41 15k SC4431 D15 1N5819HW SC4806 POWER MANAGEMENT HB Evaluation Board Schematics C32 82pF C30 82pF C8 1u,100V C9 1u,100V D4 ZM4743A A C 7 3 C11 FB SYNC .1u,16V REF 8 2 REF SS 0 C12 GND(heatsink) 9 1 10u,16V GND LUVLO E C C10 1u,100V 0.1u,25V C29 2 3 2 3 5 5 C6 C4 2.2u,50V 2.2u,50V A AC C A AC C CMOSH-3 CMOSH-3 CMOSH-3 CMOSH-3 2 1 5 6 4 3 R_GS_MA1 R_GS_MB1 2 3 2 3 1 8 N = 100 7 3 1 4 2 3 CMOSH-3 CMOSH-3 C A A C CMOSH-3 A C C A CMOSH-3 A C C16 47u,6.3V C17 47u,6.3V C18 47u,6.3V C19 2 1 2 1 47u,6.3V C20 Vref Vref 47u,6.3V C21 47u,6.3V C22 0.1u C14 0.1u  2006 Semtech Corp. 18 www.semtech.com VCC SC4806 POWER MANAGEMENT Evaluation Board Bill of Materials SC4806 Feed Forward Half bridge 3.3V 35W non Synchronous SC4806EVB__non_sync Revision: 1.1 Bill Of Materials March 30,2005 10:47:27 Item Quantity Reference Part Manufacturer # Foot Print 1 1 CON1 3input_half_brick CON\3INPUT_HALF_BRICK 2 1 CON2 5output_half_brick CON\5OUTPUT_HALF_BRICK 3 2 C1,C5 2.2n SM/C_0805 4 1 C2 82p SM/C_0805 5 2 C4,C6 2.2u,50V SM/C_2220 6 2 C23,C7 100p SM/C_1206 7 3 C8,C9,C10 1u,100V GRM44-1X7R105K250AL(muRata) SM/C_2220 8 1 C11 .1u,16V SM/C_0805 9 2 C12,C24 10u,16V GRM32DR61C106KA01(muRata) SM/C_1210_GRM 10 2 C15,C13 2.2n SM/C_1206 11 6 C14,C22,C27,C33,C34,C43 0.1u SM/C_0805 12 6 C16,C17,C18,C19,C20,C21 47u,6.3V GRM43-2X5R476K6.3(muRata) SM/C_1210_GRM 13 1 C25 1nF SM/C_0805 14 1 C26 0.1uF 16V SM/C_0603 15 1 C28 22nF SM/C_1206 16 1 C29 0.1u,25V SM/C_1206 17 2 C32,C30 82pF SM/C_0805 18 1 C31 1u,16V GRM32RR71H105KA011(muRata) SM/C_1210_GRM 19 2 C44,C35 22n SM/C_0805 20 1 C36 2.2u,16V SM/C_1206 21 1 C37 .1uF SM/C_0805 22 1 C39 6.8nF SM/C_0603 23 1 C40 47pF SM/C_0805 24 1 C41 2.2nF SM/C_0805 25 1 C42 680pF SM/C_0805 26 2 D1,D2 MBRB2535CTL DIODE_D2PAK 27 1 D4 ZM4743A SMB/DO214 D5,D6,R12,R13,R19,R20, 28 8 0 SM/R_0805 R26,R31 D7,D8,D9,D10,D11,D12,D13, 29 8 CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523 D14 30 1 D15 1N5819HW SOD123 JP13,JP14,JP15,JP16,JP17, 31 14 JP18,JP19,JP20,JP21,JP22, short VIA\2P JP23,JP24,JP25,JP26 32 1 J1 SS ED5052 33 1 J2 Vcc ED5052 34 1 J3 SYNC ED5052 35 1 J4 OUTA ED5052 36 1 J5 OUTB ED5052 37 1 J6 REF ED5052 38 1 J7 FB ED5052 39 1 L1 1.9uH PG0006.212(Pulse) PG0006 40 1 L2 LQH43MN102K011 LQH43MN102K01L(muRata) SDIP0302 41 2 MB1,MA1 SUD19N20-90 SUD19N20-90(vishay) DPAKFET 42 1 Q2 FZT853 FZT853 (Zetex) SM/SOT223_BCEC 43 2 R_GS_MB1,R_GS_MA1 10k SM/R_0805 44 1 R1 1k SM/R_0805 45 1 R4 15 SM/R_0805 46 3 R6,R7,R24 10 SM/R_0805 47 1 R8 49.9k SM/R_1206 48 1 R9 250 SM/R_1210_MCR 49 2 R15,R10 100 SM/R_1206 50 2 R17,R11 2.2 SM/R_0805 51 2 R16,R14 10 SM/R_1206 52 1 R18 16.2 SM/R_0805 53 1 R21 56.2k SM/R_1206 54 1 R22 10k SM/R_1206 55 2 R23,R42 TBD SM/R_0805 56 2 R41,R25 15k SM/R_0805 57 1 R27 316k SM/R_0805 58 1 R28 2.2k SM/R_0805 59 1 R30 37.4k SM/R_0805 60 1 R32 18.2k SM/R_0805 61 2 R33,R37 1.1k SM/R_0805 62 1 R35 0 SM/R_0603 63 1 R36 1.62k SM/R_0805 64 2 R39,R38 25.5k SM/R_0805 65 1 R43 100 SM/R_0805 66 1 T1 PA0801 PA0801(Pulse) PA0805 67 1 T2 PA0264 PA0264 (Pulse) PE-68386 68 1 T3 P8208T P8208T(Pulse) P8208T 69 1 T4 PE-68386 PE-68386(Pulse) PE-68386 70 1 U1 SC4806 SC4806(Semtech) MLPQ-12 (4X4) 71 2 U4,U2 RH02 RH02(Diodes Inc.) RH02 72 2 U6,U3 SC1301A SC1301A(Semtech) SOT23_5PIN 73 2 U5,U8 SC4431 SC4431(Semtech) SOT23_5PIN 74 1 U7 MOCD207 SO-8  2006 Semtech Corp. 19 www.semtech.com SC4806 POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly TOP Board Layout Assembly Bottom 2 Board Layout Top Board Layout Bottom  2006 Semtech Corp. 20 www.semtech.com SC4806 POWER MANAGEMENT Evaluation Board Gerber Plots (Cont.) Board Layout Inner1 Board Layout Inner2 Evaluation Board Modifications D15 R43 2 Board Layout Bottom  2006 Semtech Corp. 21 www.semtech.com SC4806 POWER MANAGEMENT Outline Drawing - MLPQ-12, 4 x 4 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A D B - - A .031 .040 0.80 1.00 - - A1 .000 .002 0.00 0.05 A2 - (.008) - - (0.20) - b .010 .012 .014 0.25 0.30 0.35 PIN 1 D .153 .157 .161 3.90 4.00 4.10 INDICATOR E D1 .074 .085 .089 1.90 2.15 2.25 (LASER MARK) .153 .157 .161 3.90 4.00 4.10 E E1 .074 .085 .089 1.90 2.15 2.25 e .031 BSC 0.80 BSC L .018 .022 .026 0.45 0.55 0.65 N 12 12 aaa .003 0.08 bbb .004 0.10 A2 A SEATING PLANE aaa C C A1 D1 LxN E/2 2 E1 1 N bxN bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Land Pattern - MLPQ-12, 4 x 4 K DIMENSIONS DIM INCHES MILLIMETERS (.148) (3.75) C G .106 2.70 2x Z H 2x (C) 2x G H .091 2.30 K .091 2.30 P .031 0.80 X .016 0.40 Y Y .041 1.05 Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 22 www.semtech.com