SEMTECH SC4624

SC4624 Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator POWER MANAGEMENT Features Description Features The SC4624 is a highly integrated synchronous step-down u VIN Range: 2.3 – 5.5V DC/DC regulator designed for low input voltage range of u 4A Continuous Output Current u Adjustable Output Voltage 0.5V to Vin 2.3V to 5.5 Volts. It can deliver 4A continuous output u Low R integrated FETs: 74mΩ and 47mΩ current with the output voltage as low as 0.5 Volts. The DS(ON) internal low R synchronous power switches eliminate u Up to 95% Efficiency DS(ON) the need for external Schottky diode while delivering u Synchronizable and Programmable Frequency: overall converter efficiency up to 95%. 200kHz – 2MHz u Power Good Monitor u <1.5µA of Shutdown Current A power good pin is available to monitor the output voltage status. Operating frequency is adjustable from 200 kHz u Programmable Soft Start to 2MHz with a single resistor and it can be synchronized u Programmable Current Limit to an external clock. u Over Temperature protection u Starts into pre-biased output u 4x4mm MLPQ-20 and SOIC-16EDP packages- The SC4624 offers adjustable current limit, soft start and over temperature protection to safeguard the device under WEEE and RoHS Compliant extreme operating conditions. The soft start provides a controlled output voltage ramp up at startup. When a logic low is applied to the Enable pin, the SC4624 enters Applications the shutdown mode and it consumes less than 1.5µA of u Low Voltage Distributed DC-DC Converters current. u Telecommunication Power Supplies u Portable Equipment The SC4624 is available in 4x4 MLPQ-20 and SOIC-16EDP u xDSL packages. Typical Application Circuit R R4 4 C C11 11 Vin L1 L1 Vout PVIN PH R R5 5 C C8 8 SYNC/EN R R7 7 R R6 6 C C9 9 R R8 8 PGOOD C C4 4 FB R R2 2 VCC R R9 9 C C3 3 R R1 1 C C1 1 SC SC4 46 62 24 4 C C2 2 SS ISET FS COMP C C7 7 C C5 5 R R11 11 R R3 3 Revision: August 27, 2010 www.semtech.com 1 AGND PGND SC4624 POWER MANAGEMENT Pin Configuration Ordering Information 5 4 3 2 1 Top View Device Top Mark Package D D SC (1) (2) SC4624MLTRT MLPQ-20 4624 (1) (2) SC4624SETRT SC4624 SO-16 EDP 20 16 SC4624EVB-MLPQ 1 15 PGND1 PVIN1 Evaluation Board C C SC4624EVB-SO SYNC/EN ISET SS T Notes: AGND (1) Available in tape and reel only. A reel contains 3,000 devices for MLPQ-20 FS VCC package and 2,500 devices for SO-16 package. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. VCC 5 FB 11 6 10 B B 20Pin MLPQ A A θ = 29°C/W; θ = 2.5°C/W. JA JC 5 4 3 2 1 Top View 5 4 3 2 1 D D SYNC/EN 1 16 AGND PGND1 2 15 VCC PGND2 3 14 FB C C PH1 4 13 COMP T PH2 5 12 PGOOD PVIN1 6 11 VCC B B PVIN2 7 10 FS ISET 8 9 SS 16Pin SOIC-EDP A A θ = 31°C/W; θ = 3.9°C/W. JA JC 5 4 3 2 1  2010 Semtech Corp. www.semtech.com 2 PGOOD PVIN2 NC PH3 NC PH2 NC PH1 COMP PGND2 SC4624 POWER MANAGEMENT A Absolut bsolute Maximum Ratings e Maximum Ratings Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage PV , V -0.3 to 6 V IN CC PVIN to VCC +/- 0.3 V FB, COMP, ISET, SYNC/EN, FS, SS, PGOOD to AGND -0.3 to VCC+ 0.3 V PGND to AGND +/- 0.3 V PHASE Voltage to PGND V -0.3 to PVIN+ 0.3 V PHASE PHASE Pulse Voltage to PGND Tpulse < 50ns V -3 to PVIN+ 2 V PHASE Storage Temperature Range T -65 to 150 °C STG Junction Temperature T 150 °C J Junction Temperature (Operating) -40 to 125 °C IR Reflow Temperature T 260 °C P Lead Temperature (Soldering) 10 sec for SO Package Only T 300 °C LEAD (1) ESD Protection Level V 2 kV ESD Note: 1) Tested in accordance to JEDEC standard JESD22-A114B. Recommended Operating Conditions The Performance is not guarantied if exceeding the specifications below. Parameter Symbol Conditions Min Typ Max Units Power Supply Input Voltage Operating Range V 2.3 5.5 V IN Max. Output Current I 0 4 A OUTMAX Electrical Characteristics Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 125°C IN CC OSC ISET J Parameter Symbol Conditions Min Typ Units Power Supply Start Threshold Voltage, UVLO V V Rising 2 2.25 V IUV IN Hysteresis Voltage, UVLO V 120 mV IUVHY Supply Current, Shutdown I V = 0V 0.2 1.5 µA SD SYNC  2010 Semtech Corp. www.semtech.com 3 SC4624 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 125°C. IN CC OSC ISET J Parameter Symbol Conditions Min Typ Max Units Power Supply (Cont.) I FB = COMP, No Load 7 10 mA Qswitching Supply Current, Operating I FB = 0.6V, No Load 3.5 7 mA QL Thermal Shutdown Thermal Shutdown Trip Point T Temperature Rising 160 °C OTP Thermal Shutdown Hysteresis T 10 °C OTP_HYS Synchronization, Enable Input V Logic Low 0.8 V ENL SYNC/EN Threshold V Logic High 2.0 V ENH Frequency Range, SYNC F 20% Higher than F 200 2000 kHz SYNC OSC Oscillator Osciilator Frequency Range F 200 2000 kHz OSC R = 51.1KΩ 415 500 600 kHz OSC Osciilator Frequency Accuracy R =51.1KΩ, T =T =25°C 435 500 565 kHz OSC A J (1) Ramp Peak to Valley V 1.0 V PV (1) Ramp Peak Voltage V 1.25 V P (1) Ramp Valley Voltage V 0.25 V V Soft Start, Current Limit Soft-Start Charge Current I 4 µA SS ISET Bias Voltage V R = 27.4KΩ 0.45 0.55 0.62 V ISET ISET Over Current Trip I R = 57.6KΩ 1.9 2.55 3.1 A IST ISIT Output UVLO V VFB drop 0.3 V OUV (1) Hiccup period T 131072 clks OCHP Error Amplifier Error Amplifier Open Loop 100 dB (1) Voltage Gain (1) Error Amplifier Unity Gain Bandwidth 10 MHz (1) Output Voltage Slew Rate, COMP 4 V/µs  2010 Semtech Corp. www.semtech.com 4 SC4624 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 125°C. IN CC OSC ISET J Parameter Symbol Conditions Min Typ Max Units Error Amplifier (Cont.) Source Output Current, COMP FB = 0.4V 20 mA Sink Output Current, COMP FB = 0.6V 25 mA Output Voltage High, COMP FB = 0.4V, I = -1mA 2.5 V COMP Output Voltage Low, COMP FB = 0.6V, I = 1mA 0.1 0.25 V COMP 0.4925 0.5 0.5075 V Feedback Voltage V FB Vcc = 2.3V to 5.5V -2 +1 +2 % (1) Input Bias Current I FB=V 300 nA FB REF Power Switches High-Side P-MOSFET R V =V =5V, I = 1A, T =T =25 °C 74 100 mΩ DSH(on) IN CC SOURCE A J Low Side N-MOSFET R V =V =5V, I = 1A, T =T =25 °C 47 85 mΩ DSL(on) IN CC SINK A J Power Good PGood Voltage Low V I = 1mA 0.2 V PGL PGOOD PGood Leakage Current I PGOOD = 5V 1 µA PGOOD (1) PGood Delay Time T Vout rising or Vout falling 1024 clks D With respect to nominal output, PGood High Window +8 +10 +15 % T =T =25 °C A J Note: (1) Guaranteed by design.  2010 Semtech Corp. www.semtech.com 5 SC4624 POWER MANAGEMENT Start up by Vin Start up by Vin Operation Typical Per formance Characteristics Test condition: 5Vin, 1Vo, Io=0A Test condition: 5Vin, 1Vo, Io=0A Circuit condition: Application circuit#1, 5V , 1V IN OUT V V Vin IN Vin IN SS 5V/DIV SS SS SS 5V/DIV 5V/DIV 5V/DIV V V Vout Vout OUT OUT PGOOD 0.5V/DIV PGOOD 0.5V/DIV PGOOD PGOOD 5V/DIV 5V/DIV 10ms/DIV 10ms/DIV Figure 1. Start Up by V @0A Figure 2. Start Up by V @4A IN Shutdown by Vin IN Shutdown by Vin Test condition: 5Vin, 1Vo, Io=4A Test condition: 5Vin, 1Vo, Io=0A 5V/DIV 5V/DIV V V Vin Vin 5V/DIV IN IN 5V/DIV SS SS SSS S 0.5V/DIV 0.5V/DIV VVout V OUT OUT 5V/DIV 5V/DIV Vout PGOOD PGOOD PGOOD PGOOD 5ms/DIV 1ms/DIV Transient response Figure 4. Shutdown by V @4A Figure 3. Shutdown by V @0A IN Stability and Ripple IN Test condition: 5Vin, 1Vo, Io=0 to 4A Test condition: 5Vin, 1Vo, Io=4A, R=F=2.5A/us,T1=T2=0.1ms (Operating stably) Vout VoV ut OUT 20mV/DIV 50mV/DIV V Vout OUT Io 2.0V/DIV l Vph V ase 2A/DIV IOUT OUT PHASE 1us/DIV 20us/DIV Figure 5. Transient Response@ 0 to 4A Figure 6. Ripple and Stability@4A  2010 Semtech Corp. www.semtech.com 6 SC4624 POWER MANAGEMENT Thermal protection Over current protection Operation Typical Performance Characteristics (Cont.) Test condition: 5Vin, 1Vout Test condition: 5Vin, 1Vout Circuit condition: Application circuit#1, 5V , 1V IN OUT 0.6V/DIV V 0.6V/DIV Vout OUT V Vout OUT 5.0V/DIV 5.0V/DIV SS SS SSS S 3V/DIV Vphase 3.0V/DIV V Vphase V PHASE PHASE 100ms/DIV 1s/DIV Figure 7. Over Load Hiccup Figure 8. Thermal Shutdown Protection@0A SYNC Efficiency External clock singal=650kHz, duty=50% 100 95 Sync 90 Signal 85 5Vin 80 75 2.5Vin 70 SYNC 2.0V/DIV 3.3Vin 65 60 55 50 V V phase 2.0V/DIV PHASE 45 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1us/DIV Output Current(A) Output Current(A) Figure 10. Efficiency(V ) Figure 9. Synchronization IN Internal PMOS R @ Room Temperature Internal NMOS R @ Room Temperature DSON DSON 80 130 120 75 .5VIN 110 70 .5V IN .3V IN 100 65 90 60 .3V IN 80 55 V IN V IN 70 50 1 2 3 4 1 2 3 4 I (A) I (A) OUT OUT Figure 12. Low-Side N-MOSFET Figure 11. High-Side P-MOSFET  2010 Semtech Corp. www.semtech.com 7 R (mΩ) DSON R (mΩ) Efficiency(%) DSON Efficiency(%) SC4624 POWER MANAGEMENT Operation Typical Per formance Characteristics (Cont.) CISET=100nF, C9 Regulation During Switching to Linear Mode OCP Trip 4.8 2.54 3.3Vin 4.4 2.52 4.0 2.50 5Vin VOUT 3.6 2.48 3.2 2.46 2.5Vin 2.8 2.44 2.4 2.42 2.0 2.40 1.6 2.38 1.2 2.36 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.8 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I (A) OUT R (KΩ) RISET(Kohm) ISET Figure 13. Loading Regulation Figure 14. Over Current Setting versus R ISET  2010 Semtech Corp. www.semtech.com 8 V (V) OUT I (A) OUT IO(A) SC4624 POWER MANAGEMENT Pin Descriptions Pin Pin Pin Name Pin Functions SO-16 MLPQ-20 6 1 PVIN1 Power supply voltage for high side MOSFETs. Current limit setting pin. A resistor connected between ISET and AGND sets the over 8 2 ISET current protection threshold. A ceramic decoupling between ISET pin to AGND have to be reserved to prevent from noise influence. Soft start time setting pin. A cap connected from this pin to GND sets the soft start up 9 3 SS time. Oscillator frequency setting pin. An external resistor connected from this pin to GND 10 4 FS sets the oscillator frequency. 11,15 5,12 VCC Power supply voltage for the analog section of the controller. Power good indicator. It is an open drain output. Low when the output is below the 12 6 PGOOD power good threshold level. 7,8,9 NC No connection. This is the output of the error amplifier. The voltage at this point is connected to the 13 10 COMP inverting input of the PWM comparator. A compensation network is required in order to optimize the dynamic performance of the voltage mode control loop. The inverting input of the error amplifier. It serves as the output voltage feedback point 14 11 FB for the buck controller. It senses the output voltage through an external divider. 16 13 AGND Analog signal gound. The oscillator frequency of the SC4624 is set by FS when SYNC/EN is pulled and 1 14 SYNC/EN held above 2V. Its synchronous mode is activated as SYNC/EN is driven by an exter- nal clock. Its shutdown mode is invoked if SYNC/EN is pulled and held below 0.8V. 2 15 PGND1 Power ground. 3 16 PGND2 Power ground. 4 17 PH1 Switching nodes 5 18 PH2 Switching nodes 19 PH3 Switching nodes 7 20 PVIN2 Power supply voltage for high side MOSFETs. THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not PAD electrically connected internally.  2010 Semtech Corp. www.semtech.com 9 SC4624 POWER MANAGEMENT Block Diagram ASYNCHRONOUS START UP VCC PVIN1 0.5V THERMAL SHUTDOWN PVIN2 - BANDGAP TOP GATE UVLO BANDGAP HIGH SIDE DRIVER AND LOGIC ISET AGND VREF I = F(R_ISET) ERROR OPAMP PH1 SOFT PH2 START OVER CURRENT PROTECT PH3 SS PWM BOTTOM FB BLOCK GATE COMP PWM SD SYNC/EN LOGIC SHOOT- LOW SIDE DRIVER OSC THRU AND LOGIC FB FS CLOCK PROTECTION PGND1 PGND2 1.1VREF PGOOD 0.9VREF  2010 Semtech Corp. www.semtech.com 10 DELAY CONTROL AND HICCUP - SC4624 POWER MANAGEMENT Application Information Overview During start up or restart, A typical 4µA sourcing current The SC4624 is a programmable high switching frequency, charges the capacitor and then the voltage of capacitor integrated 4A MOSFET, synchronous step down regulator. ramp up the error amp reference slowly. The closed This reduces external component count and makes it loop creates narrow width driver pulses while the output effective for applications which are low in cost and sized voltage is low and allows these pulses to increase to their small. A non-overlap protection is provided for the gate steady state duty cycle as the output voltage reaches drive signals to prevent shoot through of the internal its regulated value. The duration of the soft start in the MOSFET pair. SC4624 is controlled by an external capacitor. The SC4624 is capable of producing an output voltage as The SC4624 starts up in asynchronous mode before SS low as 0.5V and Its operation frequency is programmable voltage reaches to 0.5V, and the bottom FET diode is used up to 2MHz by an external resistor. It features lossless for circulating current during the top FET off time. Ths SS current sensing of the voltage drop across the internal voltage level is clamped at V finally. CC drain to source resistance of the high side MOSFET during its conduction period. Pre-biased Output The SC4624 is able to start into pre-biased output by The quiescent supply current in shutdown mode is adding external RC circuit, where R(10KΩ) is between V CC typically lower than 1µA. An external soft start is provided pin and EN pin, C(0.1uF) is between EN pin and AGND. to prevent output voltage overshoot during start-up. Over If there is a pre-biased load on the output of SC4624 Temperature Protection, Power Good Indicator, External during start-up, the internal low-side MOSFET of SC4624 Clock Synchronization are some of the internal added is always disabled before SS reach to 0.5V, the output features. voltage is maintained. The great feature avoids negative voltage spikes or short circuit on the output, which could Enable cause damage to the down-stream IC during start-up. The SC4624 is enabled by applying a voltage greater than 2V (typical) to the V and SYNC/EN pin. The voltage on Timing between V and EN is very important for pre-biased CC CC the V pin determines the operation of the SC4624. As output. V must lead EN. When V and EN voltage rise CC CC CC V increases during start up, the UVLO block senses V at same time(tied together), the pre-biased output voltage CC CC and keeps the high side and low side MOSFETs off and is pull low before V reach to the voltage of UVLO. If this CC the internal soft start voltage low until V reaches 2V. If isn’t desirable, RC(10KΩ and 0.1uF) must be added at EN CC no faults are present, the SC4624 will initiate a soft start to prevent this from happening. when V exceeds 2V. A typical 120mV hysteresis in the CC UVLO comparator provides noise immunity during its start up. (refer to Figure 1 to 2). Oscillator The FS pin is used to set the PWM oscillator frequency Shutdown through an external resistor that is connected from the The SC4624 is disabled when V falls below 1.88V (typical) FS pin to the AGND. The internal ramp is a triangle at the CC or shutdown mode operation is invoked by clamping the PWM frequency with a peak voltage of 1.25V and a valley SYNC/EN pin to a voltage below 0.8V. During the shutdown voltage of 0.25V. The approximate operating frequency is mode, A typical 0.2µA current draw through the V pin, determined by the value of an external resistor as shown CC the internal soft start voltage is held low and the internal in Figure 15. MOSFETs are turned off. (refer to Figure 3 to 4). Soft Start The soft start function is required for step down controllers to prevent excess in-rush current through the DC bus during start up. An external capacitor is necessary for the soft start function and is connected from SS pin to AGND.  2010 Semtech Corp. www.semtech.com 11 SC4624 POWER MANAGEMENT Operation Application Information (Cont.) Switching Frequency Setting Thermal Shutdown 145 When the junction temperature rises up around 160°C, 135 the internal soft start voltage is held low, the internal high 125 side and low side MOSFETs are turned off and the output 115 105 voltage will fall to zero. Once the junction temperature 95 goes below hysteresis temperature around 10°C, the 85 regulator will restart. (refer to Figure 8). 75 65 5VIN 55 Linear Mode Operation (100% duty) 45 The SC4624 can allows 100% duty cycle operation. The 35 25 2.5VIN Vout is, 15 5 9287 9,15/5'6+u,287 200 400 600 800 1000 1200 1400 1600 1800 2000 F (kHz) OSC where R : Output inductor DC resistance. Figure 15. Switching Frequency vs. R L FS R : Internal high side P-MOSFET resistance. DSH (refer to Figure11). The operation frequency can be programmed up to 2MHz, but there is a minimum on-time limitation which is around As Vin drops gradually and close to Vout, the buck regulator 110ns. Users should take care of minimum limitation will go into 100% duty cycle ratio. A matter needing on the operating duty cycle under high frequency attention is internal high side PMOS has minimum off time application. limitation and is related to duty cycle rate. This condition makes the working duty cycle perform at randon with the Synchronization Frequency output ripple increasing and a poor transient response. Synchronization operation mode is invoked by using an Above phenomenon can be improved by larger output external clock signal and is activated when the SYNC/EN capacitor and smaller output inductor. Users need to is pulled and held above 2V and held below 0.8V. The verify whether above application condition has opposite range of synchronization frequency is from 200kHz to influence on entire circuit. 2MHz. Over Current Protection A jitter happens when sync pulse clock edge is less than A over current setting is programmed by an external 120ns before the phase switches. It is caused by the resistor (R ). It goes through internal sense resistor and ISET ground bounce of synchronization pulse coupled to PWM generates a voltage. comparator. Users try to avoid this application. (refer to 9 9FF,u52QVHQVH Figure 9). where Power Good Indicator I : The current is generated by R , and it is amplified ISET The PGOOD pin is an open-drain and incorporated window by internal current amplifier. comparators output. It’s is necessary that a pull-up R : Internal sense resistor. ONSENSE resistor from the PGOOD pin to the input supply for setting the logic high level of the PGOOD signal. When FB voltage Output inductor current goes through internal high side is within +10% setting output voltages typical, the output P-MOSFET and generate a voltage. of power good comparator becomes high impedance after delay time. The PGOOD signal delay time is around 1024/ 9 9,1,/u5'6+21 F . In shutdown mode the power good output is actively OSC pulled low. where I : Output inductor current. L For example, 1MHz switching frequency applications, the R : High side P-MOSFET conduction resistance. DSH(ON) PGOOD delay time is around 1ms.  2010 Semtech Corp. www.semtech.com 12 R (KΩ) FS SC4624 POWER MANAGEMENT Application information (Cont.) The inductor value can be determined according to its After the high side PMOS turn on around 30ns, the OCP operating point and the switching frequency as follows: comparator will compare between V2 and V1. When the converter detects an over current condition (V2 > V1) as 9287u9,19287 shown in Figure 16, the SC4624 proceeds into the cycle by / cycle protection mode (Point B to Point C), which responds 9,1uI6u',u,20$; to minor over current cases and the output voltage is where monitored. fs = switching frequency. DI = ratio of the peak to peak inductor current to the If the over current and low output voltage (set at 60% of maximum output load current. nominal output voltage) occur at the same time, the SS pin is pull low by an internal switch and the comp pin is The peak to peak inductor current is: pulled low and the devices stops switching. Assume start from FB = 0V, FB and SS voltage rise forward 0.5V. Once ,3  3 ',u,20$; SS voltage exceeds 0.4V, the hiccup comparator becomes 17 enabled. The hiccup period is around 2 /F . (Point C to OSC Point D). After the required inductor value is selected, the proper selection of the core material is based on the peak For example, with a switching frequency application of inductor current and efficiency requirements. The core 550kHz, the hiccup period is around 238ms. (refer to must be able to handle the peak inductor current I PEAK Figure 7). without saturation and produce low core loss during the high frequency operation and is given as follows: A poor layout will make OCP trip point shift and is not ,3  3 easily to calculate by R . This is because it is affected ,3($. ,,20$; ISET by ground bounce, spiker voltage between Vin pin and PH  pin, and internal parameter tolerance. Users can refer to The power loss for the inductor includes its core loss and Figure 14, it shows how to set maximum output current copper loss. If possible, the winding resistance should be by R . ISET minimized to reduce any copper loss of the inductor, (the core loss can be found in the manufacturer’s datasheet). A Vout The inductor’s copper loss can be estimated as follows: B  3&223(5 , /506u5:,1',1* 0 C where 0.6 * Vout I is the RMS current in the inductor. LRMS Vo This current can be calculated as follows: D Imax Iout 0   ,/506 ,20$;u  u',  Figure 16. Over Current Protection Characteristic Output Capacitor Selection Basically there are two major factors to consider in select- Inductor Selection ing the type and quantity of the output capacitors. The For a typical SC4624 application, the inductor selection first one is the required ESR (Equivalent Series Resis- is mainly based on its value, saturation current and DC tance) which should be low enough to reduce the voltage resistance. The inductor should be able to handle the deviation from its nominal one during its load changes. peak current without saturating and its copper resistance The second one is the required capacitance, which should in the winding should be as low as possible to minimize its be high enough to hold up the output voltage. Before the resistive power loss.  2010 Semtech Corp. www.semtech.com 13 SC4624 POWER MANAGEMENT Operation Application Information (Cont.) network to meet the requirements for a specific applica- SC4624 regulates the inductor current to a new value dur- tion. ing a load transient, the output capacitor delivers all the additional current needed by the load. The SC4624 has an internal error amplifier and requires the compensation network to connect among the COMP The ESR and ESL of the output capacitor, the loop para- pin and FB pin, GND, and the output as shown in Figure sitic inductance between the output capacitor and the 17. The compensation network includes C1, C2, R1, R7, load combined with inductor ripple current are all major R8 and C8. R9 is used to program the output voltage ac- contributors to the output voltage ripple. cording to: Input Capacitor Selection 5  92 u  The input capacitor selection is based on its ripple cur- 5  rent level, required capacitance and voltage rating. This 5 4 3 2 1 capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction mode, D C1 SC4624 D the RMS value of the input capacitor can be calculated R1 C2 COMP from: FB Vout L1 PH 9287u9,19287 C C C8 ,&,1506 ,20$;u  9,1 IN R7 R8 C4 R This current gives the capacitor’s power loss as follows: B B R9  3&,1 , &,1506u5&,1(65 A A This capacitor’s RMS loss can be a significant part of the total loss in the converter and reduces the overall convert- 5 Figure 1 4 7. Compensation Netw 3 or 2k 1 er efficiency. The input ripple voltage mainly depends on Provides 3 Poles and 2 Zeros the input capacitor’s ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the For voltage mode step down applications as shown in Fig- input current of the converter is constant, the required ure 17, the power stage transfer function is: input capacitance for a given voltage ripple can be calcu- lated by: 'u' &,1 ,20$;u I6u'9,,20$;u5&,1(65 ∆ where where D = V /V , duty ratio. O I R = load resistance DV = the given input voltage ripple. I R = C4’s ESR. C Loop Compensation Design The compensation network will have these characteris- For a DC/DC converter, it is usually required that the con- tics: verter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low s s 1+ 1+ steady state error, and enough phase margin for its oper- w w w I Z1 Z2 G (s) = ⋅ ⋅ ating stability. Often one can not have all these properties COMP s s s 1+ ⋅1+ at the same time. The purpose of the loop compensation w w P1 P2 is to arrange the poles and zeros of the compensation  2010 Semtech Corp. www.semtech.com 14 SC4624 POWER MANAGEMENT Operation Application Information (Cont.) where The design guidelines for the SC4624 applications are as follows: 1 ω = I 1. Set the loop gain crossover corner frequency w for R ⋅(C +C ) C 7 1 2 given switching corner frequency w = 2pfs, S 2. Place an integrator at the origin to increase DC and 1 low frequency gains. ω = Z1 R ⋅C 1 2 3. Select w and w such that they are placed near w Z1 Z2 O to damp the peaking and the loop gain has a -20dB/ 1 dec rate to go across the 0dB line for obtaining a wide ω = Z2 (R +R )⋅C 7 8 8 bandwidth. 4. Cancel the zero from C4’s ESR by a compensator pole w (w = w = 1/(R C )). C +C P1 P1 ESR C 4 1 2 ω = P1 5. Place a high frequency compensator pole w (w = P2 P2 R ⋅C ⋅C 1 1 2 pfs) to get the maximum attenuation of the switch- ing ripple and high frequency noise with the adequate 1 phase lag at w . ω = P2 C R ⋅C 8 9 8 The compensated loop gain will be as given as show in Figure 18. After the compensation, the converter will have the following loop gain: s 1+ 1 1 s s ⋅ w ⋅ V 1+ 1+ I I V w w R ⋅C M Z1 Z2 C 4 T(s) = G ⋅G (s) ⋅G (s) = ⋅ ⋅ ⋅ PWM COMP VD s s L s 2 1 1+ ⋅1+ 1+ s + s L C 1 w w R s P1 P2 1+ 1 s s 1 ⋅ w ⋅ V 1+ 1+ I I R ⋅C V w w = M Z1 Z2 C 4 T(s) = G ⋅G (s) ⋅G (s) = ⋅ ⋅ ⋅ PWM COMP VD s s L s 2 1 1+ ⋅1+ 1+ s + s L C 1 w w R P1 P2 where G = PWM gain. PWM V = 1.0V, ramp peak to valley voltage of SC4624. M Figure 18. Asymptotic Diagrams of Power Stage and Loop Gain  2010 Semtech Corp. www.semtech.com 15 SC4624 POWER MANAGEMENT Operation Application Information (Cont.) Layout Guidelines the big vias to the bottom layer during the re-flow process In order to achieve optimal thermal and noise immunity . for high frequency converters, special attention must be paid to the PCB layout. The goal of layout optimization is to minimize the high di/dt loops and reduce ground bounce. Output voltage setting, line regulation, stability , switching frequency and OCP trip point shifted are affected by a poor layout. The following guidelines should be used to ensure proper functions of the converters. 1. Both Power ground (PGND) and signal ground (AGND) are separated. 2. A ground plane is recommended to minimize noise and copper losses, and maximize heat dissipation. 3. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. 4. Minimize all high di/dt loops. These loops pass high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. Ground bounce happen to magnetic flux changed and it is proportional to a magnetic filed which goes through high di/dt loops. 5. The input ceramic capacitor (C ) should be close to IN PV pins and PGND pins. IN 6. Both input ceramic capacitor gnd and output ceramic capacitor gnd are at same port. 7. A RC snubber circuit between PV and PH pins is IN helpful for stability operation. Be careful with power derating of snubber circuit. 8. The V bypass capacitor should be placed next to the CC V and AGND pins. CC 9. The OCP setting resistor (R ) and filter capacitor ISET (C ) should be placed next to the ISET and AGND ISET pins. 10. Feedback divider connects to output connector by Kelvin connection and far away from the noise sources such as switching node and switching components. 11. A multilayer chip beads between AGND and PGND will reduce the ground bounce injected to the “quiet” circuit. It’s helpful for stability operation. 12. A large copper area underneath the SC4624 IC is necessary for heat sinking purpose. And multiple layers of large copper area connected through vias can be used for better thermal performance. The size of the vias as the connection between multiple layers should not be too large or solder may seep through  2010 Semtech Corp. www.semtech.com 16 SC4624 POWER MANAGEMENT Operation Application Information (Cont.) 5 4 3 2 1 5V , 1V , 4A, all ceramic capacitors ( application circuit#1 ) IN OUT 5Vin R R5 5 R R6 6 R R2 2 D 1 10 0k k 1 10 0k k 1 10 0R R D C C6 6 U U1 1 C C3 3 1 1n nF F 1 1u uF F 5 12 VCC VCC 6 13 PGOOD AGND R R1 11 1 4 47 7..5 5k k 14 4 SYNC/EN FS 4 47 7n nF F C C7 7 C C1 1 2 2..2 2p pF F 7 3 NC SS R R1 1 C C2 2 10 9 C COMP NC C C C5 5 o op ptt 3 39 90 0p pF F 2 20 0k k R R3 3 11 2 FB ISET 3 30 0k k 1Vout@4A L L1 1 1 1..8 8u uH H 17 1 PH1 PVIN1 C C8 8 2 27 70 0p pF F 18 20 PH2 PVIN2 R R7 7 R R8 8 2 28 8..7 7k k C C9 9 19 15 2 2..3 32 2k k PH3 PGND1 C C4 4 2 22 2u uF F 2 22 2u uF F 8 16 NC PGND2 R R9 9 SC SC4 46 62 24 4 2 28 8..7 7k k B (2) R R1 12 2 B M ML LB B- -1 16 60 08 80 08 8- -0 06 60 00 0R R- -S S2 2 R R4 4 C C1 11 1 o op ptt VIN=5V; Vout=1V/4A o op ptt (1) Switching Frequency=550kHz Note: (1,2) Option for stability L1: TOKO D104C(919AS-1R8N) R12: Multilayer chip inductors; MLB-160808-0600R-S2 Input(C9)/Output Capacitors(C4): Panasonic ECJ33YBOJ226M(22uF/6.3V) A A T T Tiiitttllle e e SC4624 Application Circuit S S Siiiz z ze e e D D Do o oc c cu u um m me e en n nttt N N Nu u um m mb b be e er r r R R Re e ev v v C C Cu u us s sttto o om m m A A A2 2 2 D D Da a attte e e::: M M Mo o on n nd d da a ay y y,,, J J Ju u un n ne e e 2 2 25 5 5,,, 2 2 20 0 00 0 07 7 7 S S Sh h he e ee e ettt 1 1 1 o o offf 1 1 1 5 4 3 2 1  2010 Semtech Corp. www.semtech.com 17 PAD SC4624 POWER MANAGEMENT Operation PCB Layout Component Side (TOP) (TOP layer) (Bottom layer) (IN1 layer) (IN2 layer)  2010 Semtech Corp. www.semtech.com 18 SC4624 POWER MANAGEMENT Outline Drawing - MLPQ - 20 B A D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A .031 .035 .039 0.80 0.90 1.00 A1 .000 .001 .002 0.00 0.02 0.05 - A2 - (.008) - - (0.20) PIN 1 b .007 .010 .012 0.18 0.25 0.30 E D .154 .157 .161 3.90 4.00 4.10 INDICATOR D1 .100 .106 .110 2.55 2.70 2.80 (LASER MARK) E .154 .157 .161 3.90 4.00 4.10 E1 .100 .106 .110 2.55 2.70 2.80 e .020 BSC 0.50 BSC L 0.40 .012 .016 .020 0.30 0.50 N 20 20 aaa .004 0.10 bbb .004 0.10 A2 A SEATING aaa C PLANE A1 C D1 LxN E/2 E1 2 1 N bxN bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2. Land Pattern - MLPQ - 20 K DIMENSIONS DIM INCHES MILLIMETERS (.156) (3.95) C G .122 3.10 Z H .106 2.70 G (C) H K .106 2.70 P .020 0.50 X .010 0.25 Y .033 0.85 Y Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.  2010 Semtech Corp. www.semtech.com 19 SC4624 POWER MANAGEMENT Outline Drawing - SO-16 EDP A D e N DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX 2X E/2 - - A .053 .069 1.35 1.75 E A1 .000 - .005 0.00 - 0.13 E1 - - A2 .049 .065 1.25 1.65 - - b .012 .020 0.31 0.51 c .007 - .010 0.17 - 0.25 1 2 3 D .386 .390 .394 9.80 9.90 10.00 ccc C E1 .150 .154 .157 3.80 3.90 4.00 e/2 E .236 BSC 6.00 BSC 2X N/2 TIPS e .050 BSC 1.27 BSC B F .100 .105 .110 2.54 2.67 2.79 H .080 .085 .090 2.03 2.16 2.29 .010 - - 0.50 h .020 0.25 D L .016 .028 .041 0.40 0.72 1.04 L1 (.041) (1.04) aaa C N 16 16 A2 - - A 01 0° 8° 0° 8° SEATING aaa .004 0.10 PLANE bbb .010 0.25 C A1 ccc .008 0.20 bxN bbb C A-B D F H EXPOSED PAD c GAUGE PLANE H L 0.25 01 (L1) DETAIL A h h SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AC. Land Pattern - SO-16 EDP E SOLDER MASK THERMAL VIA Ø 0.36mm D DIMENSIONS DIM INCHES MILLIMETERS (.205) (5.20) C Z D .114 2.90 (C) F G E .201 5.10 F .094 2.40 G .118 3.00 Y P .050 1.27 X .024 0.60 Y .087 2.20 P X Z .291 7.40 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.  2010 Semtech Corp. www.semtech.com 20 SC4624 POWER MANAGEMENT © 2010 Semtech Corporation All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact Information Semtech Corporation Power Mangement Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com  2010 Semtech Corp. www.semtech.com 21