SEMTECH SC4620

SC4620 Low Input Voltage, High Efficiency, 2.5A Integrated FET Synchronous Step down DC/DC Regulator POWER MANAGEMENT Features Description Features  VIN Range: 2.3 – 5.5V The SC4620 is a highly integrated synchronous step-down  2.5A Continuous Output Current DC/DC regulator designed for low input voltage range of  Adjustable Output Voltage 0.5V to Vin 2.3V to 5.5 Volts. It can deliver 2.5A continuous output  Up to 95% Efficiency current with the output voltage as low as 0.5 Volts. The  Synchronizable and Programmable Frequency: internal low R synchronous power switches eliminate DS(ON) 200kHz – 2MHz the need for external Schottky diode while delivering  Power Good Monitor overall converter efficiency up to 95%.  <1µA of Shutdown Current  Programmable Soft Start A power good pin is available to monitor the output voltage  Programmable Current Limit status. Operating frequency is adjustable from 200 kHz  Over Temperature protection to 2MHz with a single resistor and it can be synchronized  -40 to +85 °C Ambient Temperature Range to an external clock.  4X4mm MLPQ-20 packages- WEEE and RoHS compliant The SC4620 offers adjustable current limit, soft start and over temperature protection to safeguard the device under extreme operating conditions. The soft start provides a controlled output voltage ramp up at startup. When a Applications logic low is applied to the Enable pin, the SC4620 enters the shutdown mode and it consumes less than 1µA of  Low Voltage Distributed DC-DC Converters current.  Telecommunication Power Supplies  Portable Equipment The SC4620 is available in 4x4 MLPQ-20 and it is rated  xDSL over -40°C to +85°C ambient temperature range. Typical Application Circuit 5 4 3 2 1 R R4 4 C C11 11 D D Vin L1 L1 Vout PVIN PH R R5 5 C C8 8 R R7 7 SYNC/EN R R6 6 C C9 9 PGOOD R R8 8 C C4 4 C C FB R R2 2 VCC R R9 9 C C3 3 R R1 1 C C1 1 SC SC4 46 62 20 0 C C2 2 SS B B ISET FS COMP C C7 7 C C5 5 R R3 3 R R11 11 A A 5 4 3 2 1 Revision: July 10, 2008 www.semtech.com 1 AGND PGND SC4620 POWER MANAGEMENT 5 4 3 2 1 Pin Configuration Ordering Information Device Top Mark Package Top View D D SC (1) (2) SC4620MLTRT MLPQ-20 4620 SC4620EVB-MLPQ Evaluation Board 20 16 1 Notes: PVIN 15 PGND (1) Available in tape and reel only. A reel contains 3,000 devices for MLPQ-20 C C PGND package. PVIN (2) Available in lead-free package only. Device is WEEE and RoHS compliant. ISET T AGND SS VCC FS 5 FB 11 6 10 B B 20Pin MLPQ A A θ = 29°C/W; θ = 2.5°C/W. JA JC 5 4 3 2 1  2008 Semtech Corp. www.semtech.com 2 PGOOD NC VCC NC NC PH SYNC/EN PH COMP PH SC4620 POWER MANAGEMENT A Absolut bsolute Maximum Ratings e Maximum Ratings Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage PV , V -0.3 to 6 V IN CC PVIN to VCC +/- 0.3 V FB, COMP, ISET, SYNC/EN, FS, SS, PGOOD to AGND -0.3 to VCC+ 0.3 V PGND to AGND +/- 0.3 V PHASE Voltage to PGND V -0.3 to PVIN+ 0.3 V PHASE PHASE Pulse Voltage to PGND Tpulse < 50ns V -3 to PVIN+ 2 V PHASE Storage Temperature Range T -40 to 150 °C STG Junction Temperature T 150 °C J IR Reflow Temperature T 260 °C P (1) V ESD Protection Level 2 kV ESD Note: 1) Tested in accordance to JEDEC standard JESD22-A114B. Recommended Operating Conditions The Performance is not guarantied if exceeding the specifications below. Parameter Symbol Conditions Min Typ Max Units Power Supply Input Voltage Operating Range V 2.3 5.5 V IN Ambient Temperature Range T -40 85 °C A Junction Temperature T -40 125 °C J Max. Output Current I 0 2.5 A OUTMAX Electrical Characteristics Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 85°C IN CC OSC ISET A Parameter Symbol Conditions Min Typ Max Units Power Supply Start Threshold Voltage, UVLO V V Rising 2 2.25 V IUV IN Hysteresis Voltage, UVLO V 120 mV IUVHY Supply Current, Shutdown I V = 0V 0.2 1 µA SD SYNC I FB = COMP, No Load 7 10 mA Qswitching Supply Current, Operating I FB = 0.6V, No Load 3.5 7 mA QL  2008 Semtech Corp. www.semtech.com 3 SC4620 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 85°C. IN CC OSC ISET A Parameter Symbol Conditions Min Typ Max Units Thermal Shutdown Thermal Shutdown Trip Point T Temperature Rising 160 °C OTP Thermal Shutdown Hysteresis T 10 °C OTP_HYS Synchronization, Enable Input V Logic Low 0.8 V ENL SYNC/EN Threshold V Logic High 2.0 V ENH Frequency Range, SYNC F 20% Higher than F 200 2000 kHz SYNC OSC Oscillator Osciilator Frequency Range F 200 2000 kHz OSC R = 51.1KΩ 415 500 585 kHz OSC Osciilator Frequency Accuracy R =51.1KΩ, T =T =25°C 435 500 565 kHz OSC A J (1) Ramp Peak to Valley V 1.0 V PV (1) Ramp Peak Voltage V 1.25 V P (1) Ramp Valley Voltage V 0.25 V V Soft Start, Current Limit Soft-Start Charge Current I 4 µA SS ISET Bias Voltage V R = 27.4KΩ 0.45 0.55 0.61 V ISET ISET Over Current Trip I R = 57.6KΩ 1.9 2.55 3.1 A IST ISIT Output UVLO V VFB drop 0.3 V OUV (1) Hiccup period T 131072 clks OCHP Error Amplifier Error Amplifier Open Loop 100 dB (1) Voltage Gain (1) Error Amplifier Unity Gain Bandwidth 10 MHz (1) Output Voltage Slew Rate, COMP 4 V/µs Source Output Current, COMP FB = 0.4V 20 mA Sink Output Current, COMP FB = 0.6V 25 mA Output Voltage High, COMP FB = 0.4V, I = -1mA 2.5 V COMP  2008 Semtech Corp. www.semtech.com 4 SC4620 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = V =SYNC/EN=3.3V, R =51.1KΩ, R =27.4KΩ, T = -40°C to 85°C. IN CC OSC ISET A Parameter Symbol Conditions Min Typ Max Units Error Amplifier (Cont.) Output Voltage Low, COMP FB = 0.6V, I = 1mA 0.1 0.25 V COMP 0.4925 0.502 0.5075 V Feedback Voltage V 0 °C to 70 °C 0.497 0.502 0.507 V FB Vcc = 2.3V to 5.5V -0.18 +0.06 +0.18 %/V (1) Input Bias Current I FB=V 300 nA FB REF Power Switches High-Side P-MOSFET R V =V =5V, I = 1A, T =T =25 °C 74 100 mΩ DSH(on) IN CC SOURCE A J Low Side N-MOSFET R V =V =5V, I = 1A, T =T =25 °C 47 85 mΩ DSL(on) IN CC SINK A J Power Good PGood Voltage Low V I = 1mA 0.2 V PGL PGOOD PGood Leakage Current I PGOOD = 5V 1 µA PGOOD (1) PGood Delay Time T Vout rising or Vout falling 1024 clks D With respect to nominal output, PGood High Window +8 +10 +15 % T =T =25 °C A J Note: (1) Guaranteed by design.  2008 Semtech Corp. www.semtech.com 5 SC4620 POWER MANAGEMENT Start up by Vin Start up by Vin Operation T Typical P ypical Per er f formance Charact ormance Characteristics eristics Test condition: 5Vin, 1Vo, Io=0A Test condition: 5Vin, 1Vo, Io=0A Circuit condition: Application circuit#1, 5V , 1V IN OUT V V Vin IN Vin IN SS 5V/DIV SS SS SS 5V/DIV 5V/DIV 5V/DIV V V Vout Vout OUT OUT PGOOD 0.5V/DIV PGOOD 0.5V/DIV PGOOD PGOOD 5V/DIV 5V/DIV 10ms/DIV 10ms/DIV Figure 1. Start Up by V @0A Figure 2. Start Up by V @2.5A IN Shutdown by Vin IN Shutdown by Vin Test condition: 5Vin, 1Vo, Io=4A Test condition: 5Vin, 1Vo, Io=0A 5V/DIV 5V/DIV V V Vin Vin 5V/DIV IN IN 5V/DIV SS SS SSS S 0.5V/DIV 0.5V/DIV VVout V OUT OUT 5V/DIV 5V/DIV Vout PGOOD PGOOD PGOOD PGOOD 5ms/DIV 1ms/DIV Figure 4. Shutdown by V @2.5A Figure 3. Shutdown by V @0A IN IN Transient response Transient response V OUT 20mV/DIV 40mV/DIV V OUT 2.0V/DIV l V 1A/DIV OUT PHASE 1us/DIV 20us/DIV Figure 5. Transient Response@ 0 to 2.5A Figure 6. Ripple and Stability@2.5A  2008 Semtech Corp. www.semtech.com 6 SC4620 POWER MANAGEMENT Thermal protection Over current protection Operation T Typical P ypical Per er f formance Charact ormance Characteristics (Cont.) eristics (Cont.) Test condition: 5Vin, 1Vout Test condition: 5Vin, 1Vout Circuit condition: Application circuit#1, 5V , 1V IN OUT 0.6V/DIV V 0.6V/DIV Vout OUT VV out OUT 5.0V/DIV 5.0V/DIV SS SS SSS S 3V/DIV Vphase 3.0V/DIV V Vphase V PHASE PHASE 100ms/DIV 1s/DIV Figure 7. Over Load Hiccup Figure 8. Thermal Shutdown Protection@0A SYNC Efficiency External clock singal=650kHz, duty=50% ˄˃˃ ˌˈ 5Vin Sync ˌ˃ Signal ˋˈ ˋ˃ 2.5Vin 3.3Vin ˊˈ ˊ˃ SYNC 2.0V/DIV ˉˈ ˉ˃ ˈˈ ˈ˃ V Vphase 2.0V/DIV PHASE ˇˈ ˇ˃ ˃ˁ˃ ˃ˁˈ ˄ˁ˃ ˄ˁˈ ˅ˁ˃ ˅ˁˈ 1us/DIV Output Current(A) ˢ̈̇̃̈̇ʳ˖̈̅̅˸́̇ʻ˔ʼ Figure 10. Efficiency(V ) Figure 9. Synchronization IN Internal PMOS RDSON Internal NMOS RDSON Internal PMOS R @ Room Temperature Internal NMOS R @ Room Temperature DSON DSON 130 80 2.5Vin 120 75 3.3Vin 2.5Vin 110 70 3.3Vin 100 65 90 60 80 55 70 50 5Vin 5Vin 60 45 1 1.5 2 2.5 1 1.5 2 2.5 I (A) I (A) OUT OUT Io(A) Io(A) Figure 12. Low-Side N-MOSFET Figure 11. High-Side P-MOSFET  2008 Semtech Corp. www.semtech.com 7 R (mΩ) DSON R (mΩ) Efficiency(%) DSON ˘˹˹˼˶˼˸́˶̌ʻʸʼ SC4620 POWER MANAGEMENT Operation T Typical P ypical Per erf formance Charact ormance Characteristics (Cont.) eristics (Cont.) ˖˜˦˘˧ː˄˃˃́˙ʿʳ˖ˌ OCP Trip Regulation During Switching to Linear Mode ˆˁ˅ 2.54 ˆˁ˃ 2.52 3.3Vin ˅ˁˋ 2.50 ˅ˁˉ VOUT 5Vin 2.48 ˅ˁˇ 2.46 ˅ˁ˅ 2.44 ˅ˁ˃ 2.5Vin ˄ˁˋ 2.42 ˄ˁˉ 2.40 ˄ˁˇ 2.38 ˄ˁ˅ 2.36 ˄ˁ˃ 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ˆˈ ˇ˃ ˇˈ ˈ˃ ˈˈ ˉ˃ ˉˈ ˊ˃ ˊˈ ˋ˃ ˋˈ ˌ˃ ˌˈ ˄˃˃ I (A) OUT R (KΩ) ˥˜˦˘˧ʻ˞̂˻̀ʼ ISET Figure 13. Loading Regulation Figure 14. Over Current Setting versus R ISET  2008 Semtech Corp. www.semtech.com 8 V (V) OUT I (A) OUT ˜ˢʻ˔ʼ SC4620 POWER MANAGEMENT Pin Descriptions Pin Pin Name Pin Functions MLPQ-20 1,2 PVIN Power supply voltage for high side MOSFETs. Current limit setting pin. A resistor connected between ISET and AGND sets the over current 3 ISET protection threshold. A ceramic decoupling between ISET pin to AGND have to be reserved to prevent from noise influence. 4 SS Soft start time setting pin. A cap connected from this pin to GND sets the soft start up time. Oscillator frequency setting pin. An external resistor connected from this pin to GND sets the 5 FS oscillator frequency. Power good indicator. It is an open drain output. Low when the output is below the power good 6 PGOOD threshold level. 7,12 VCC Power supply voltage for the analog section of the controller. 8,19,20 NC No connection. The oscillator frequency of the SC4624A is set by FS when SYNC/EN is pulled and held above 9 SYNC/EN 2V. Its synchronous mode is activated as SYNC/EN is driven by an external clock. Its shutdown mode is invoked if SYNC/EN is pulled and held below 0.8V. This is the output of the error amplifier. The voltage at this point is connected to the inverting 10 COMP input of the PWM comparator. A compensation network is required in order to optimize the dy- namic performance of the voltage mode control loop. The inverting input of the error amplifier. It serves as the output voltage feedback point for the 11 FB buck controller. It senses the output voltage through an external divider. 13 AGND Analog signal ground. 14,15 PGND Power ground. 16,17,18 PH Switching nodes THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not electrically PAD connected internally.  2008 Semtech Corp. www.semtech.com 9 SC4620 POWER MANAGEMENT Block Diagram ASYNCHRONOUS START UP VCC PVIN1 0.5V THERMAL + SHUTDOWN PVIN2 - BANDGAP TOP GATE UVLO BANDGAP HIGH SIDE DRIVER AND LOGIC ISET AGND VREF I = F(R_ISET) ERROR OPAMP PH1 SOFT PH2 START OVER CURRENT PROTECT PH3 SS PWM BOTTOM FB BLOCK GATE COMP PWM SD SYNC/EN LOGIC SHOOT- LOW SIDE DRIVER OSC THRU AND LOGIC FB FS CLOCK PROTECTION PGND1 PGND2 1.1VREF PGOOD 0.9VREF  2008 Semtech Corp. www.semtech.com 10 DELAY CONTROL AND HICCUP - + SC4620 POWER MANAGEMENT Application Information Overview During start up or restart, A typical 4µA sourcing current The SC4620 is a programmable high switching frequency, charges the capacitor and then the voltage of capacitor integrated 2.5A MOSFET, synchronous step down regula- ramp up the error amp reference slowly. The closed tor. This reduces external component count and makes it loop creates narrow width driver pulses while the output effective for applications which are low in cost and sized voltage is low and allows these pulses to increase to their small. A non-overlap protection is provided for the gate steady state duty cycle as the output voltage reaches drive signals to prevent shoot through of the internal its regulated value. The duration of the soft start in the MOSFET pair. SC4620 is controlled by an external capacitor. The SC4620 is capable of producing an output voltage as The SC4620 starts up in asynchronous mode before SS low as 0.5V and Its operation frequency is programmable voltage reaches to 0.5V, and the bottom FET diode is used up to 2MHz by an external resistor. It features lossless for circulating current during the top FET off time. Ths SS current sensing of the voltage drop across the internal voltage level is clamped at V finally. CC drain to source resistance of the high side MOSFET during its conduction period. Oscillator The FS pin is used to set the PWM oscillator frequency The quiescent supply current in shutdown mode is through an external resistor that is connected from the typically lower than 1µA. An external soft start is provided FS pin to the AGND. The internal ramp is a triangle at the to prevent output voltage overshoot during start-up. Over PWM frequency with a peak voltage of 1.25V and a valley Temperature Protection, Power Good Indicator, External voltage of 0.25V. The approximate operating frequency is Clock Synchronization are some of the internal added determined by the value of an external resistor as shown features. in Figure 15. Enable The SC4620 is enabled by applying a voltage greater than Switching Frequency Setting 2V (typical) to the V and SYNC/EN pin. The voltage on 145 CC 135 the V pin determines the operation of the SC4620. As CC 125 V increases during start up, the UVLO block senses V 115 CC CC and keeps the high side and low side MOSFETs off and 105 95 the internal soft start voltage low until V reaches 2V. If CC 85 no faults are present, the SC4620 will initiate a soft start 75 65 when V exceeds 2V. A typical 120mV hysteresis in the 5VIN CC 55 UVLO comparator provides noise immunity during its start 45 up. (refer to Figure 1 to 2). 35 25 2.5VIN 15 Shutdown 5 The SC4620 is disabled when V falls below 1.88V (typical) 200 400 600 800 1000 1200 1400 1600 1800 2000 CC or shutdown mode operation is invoked by clamping the F (kHz) SYNC/EN pin to a voltage below 0.8V. During the shutdown osc mode, A typical 0.2µA current draw through the V pin, CC Figure 15. Switching Frequency vs. R the internal soft start voltage is held low and the internal FS MOSFETs are turned off. (refer to Figure 3 to 4). The operation frequency can be programmed up to 2MHz, Soft Start but there is a minimum on-time limitation which is around The soft start function is required for step down controllers 110ns. Users should take care of minimum limitation on the to prevent excess in-rush current through the DC bus operating duty cycle under high frequency application. during start up. An external capacitor is necessary for the soft start function and is connected from SS pin to AGND.  2008 Semtech Corp. www.semtech.com 11 R (KΩ) FS SC4620 POWER MANAGEMENT Operation Application Inf Application Information (Cont.) ormation (Cont.) attention is internal high side PMOS has minimum off time Synchronization Frequency limitation and is related to duty cycle rate. This condition Synchronization operation mode is invoked by using an makes the working duty cycle perform at randon with the external clock signal and is activated when the SYNC/EN output ripple increasing and a poor transient response. is pulled and held above 2V and held below 0.8V. The Above phenomenon can be improved by larger output range of synchronization frequency is from 200kHz to capacitor and smaller output inductor. Users need to 2MHz. verify whether above application condition has opposite influence on entire circuit. A jitter happens when sync pulse clock edge is less than 120ns before the phase switches. It is caused by the ground bounce of synchronization pulse coupled to PWM Over Current Protection A over current setting is programmed by an external comparator. Users try to avoid this application. (refer to resistor (R ). It goes through internal sense resistor and Figure 9). ISET generates a voltage. Power Good Indicator The PGOOD pin is an open-drain and incorporated window 9 9FF,u52QVHQVH comparators output. It’s is necessary that a pull-up resis- tor from the PGOOD pin to the input supply for setting the where logic high level of the PGOOD signal. When FB voltage is I : The current is generated by R , and it is amplified ISET within +10% setting output voltages typical, the output of by internal current amplifier. power good comparator becomes high impedance after R : Internal sense resistor. ONSENSE delay time. The PGOOD signal delay time is around 1024/ F . In shutdown mode the power good output is actively OSC Output inductor current goes through internal high side pulled low. P-MOSFET and generate a voltage. For example, 1MHz switching frequency applications, the 9 9,1,/u5'6+21 PGOOD delay time is around 1ms. where Thermal Shutdown I : Output inductor current. L When the junction temperature rises up around 160°C, R : High side P-MOSFET conduction resistance. DSH(ON) the internal soft start voltage is held low, the internal high side and low side MOSFETs are turned off and the output After the high side PMOS turn on around 30ns, the OCP voltage will fall to zero. Once the junction temperature comparator will compare between V2 and V1. When the goes below hysteresis temperature around 10°C, the converter detects an over current condition (V2 > V1) as regulator will restart. (refer to Figure 8). shown in Figure 16, the SC4620 proceeds into the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases and the output voltage is Linear Mode Operation (100% duty) The SC4620 can allows 100% duty cycle operation. The monitored. Vout is, If the over current and low output voltage (set at 60% of nominal output voltage) occur at the same time, the SS Transient response 9287 9,15/5'6+u,287 pin is pull low by an internal switch and the comp pin is pulled low and the devices stops switching. Assume start Test condition: 3.3Vin, 1.2Vo, Io=0 to 3A where from FB = 0V, FB and SS voltage rise forward 0.5V. Once R : Output inductor DC resistance. R=F=2.5A/us,T1=T2=0.3ms L R : Internal high side P-MOSFET resistance. SS voltage exceeds 0.4V, the hiccup comparator becomes DSH 17 (refer to Figure11). enabled. The hiccup period is around 2 /F . (Point C to OSC Point D). As Vin drops gradually and close to Vout, the buck regulator will go into 100% duty cycle ratio. A matter needing For example, with a switching frequency application of Vout  2008 Semtech Corp. www.semtech.com 12 Io SC4620 POWER MANAGEMENT Application information (Cont.) After the required inductor value is selected, the proper 550kHz, the hiccup period is around 238ms. (refer to selection of the core material is based on the peak Figure 7). inductor current and efficiency requirements. The core A poor layout will make OCP trip point shift and is not must be able to handle the peak inductor current I PEAK easily to calculate by R . This is because it is affected without saturation and produce low core loss during the ISET by ground bounce, spiker voltage between Vin pin and PH high frequency operation and is given as follows: pin, and internal parameter tolerance. Users can refer to ,3  3 Figure 14, it shows how to set maximum output current ,3($. ,,20$;  by R . ISET The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be A Vout minimized to reduce any copper loss of the inductor, (the B core loss can be found in the manufacturer’s datasheet). 0 The inductor’s copper loss can be estimated as follows: C 0.6 * Vout  3&223(5 , /506u5:,1',1* Vo D where Imax I is the RMS current in the inductor. LRMS Iout 0 This current can be calculated as follows: Figure 16. Over Current Protection Characteristic  Inductor Selection  ,/506 ,20$;u  u', For a typical SC4620 application, the inductor selection  is mainly based on its value, saturation current and DC resistance. The inductor should be able to handle the Output Capacitor Selection peak current without saturating and its copper resistance Basically there are two major factors to consider in select- in the winding should be as low as possible to minimize its ing the type and quantity of the output capacitors. The resistive power loss. first one is the required ESR (Equivalent Series Resis- tance) which should be low enough to reduce the voltage The inductor value can be determined according to its deviation from its nominal one during its load changes. operating point and the switching frequency as follows: The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the 9287u9,19287 SC4620 regulates the inductor current to a new value / during a load transient, the output capacitor delivers all 9,1uI6u',u,20$; the additional current needed by the load. The ESR and ESL of the output capacitor, the loop para- where sitic inductance between the output capacitor and the fs = switching frequency. load combined with inductor ripple current are all major DI = ratio of the peak to peak inductor current to the contributors to the output voltage ripple. maximum output load current. Input Capacitor Selection The peak to peak inductor current is: The input capacitor selection is based on its ripple cur- rent level, required capacitance and voltage rating. This ,3  3 ',u,20$; capacitor must be able to provide the ripple current by the  2008 Semtech Corp. www.semtech.com 13 SC4620 POWER MANAGEMENT Operation Application Inf Application Information (Cont.) ormation (Cont.) switching actions. For the continuous conduction mode, 5 the RMS value of the input capacitor can be calculated  92 u  from: 5  5 4 3 2 1 SC4620 9287u9,19287 C1 ,&,1506 ,20$;u D D  R1 C2 9 IN,1 COMP FB Vout L1 This current gives the capacitor’s power loss as follows: PH C8 C C  3&,1 , &,1506u5&,1(65 R7 R8 C4 R This capacitor’s RMS loss can be a significant part of the R9 total loss in the converter and reduces the overall convert- B B er efficiency. The input ripple voltage mainly depends on the input capacitor’s ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required A A input capacitance for a given voltage ripple can be calcu- Figure 17. Compensation Network lated by: Provides 3 Poles and 2 Zeros 5 4 3 2 1 'u' &,1 ,20$;u ∆ I6u'9,,20$;u5&,1(65 For voltage mode step down applications as shown in Fig- ure 17, the power stage transfer function is: where D = V /V , duty ratio. O I DV = the given input voltage ripple. I Loop Compensation Design For a DC/DC converter, it is usually required that the con- verter has a loop gain of a high cross-over frequency for where fast load response, high DC and low frequency gain for low R = load resistance steady state error, and enough phase margin for its oper- R = C4’s ESR. C ating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation The compensation network will have these characteris- is to arrange the poles and zeros of the compensation tics: network to meet the requirements for a specific applica- tion. The SC4620 has an internal error amplifier and requires s s 1+ 1+ the compensation network to connect among the COMP w w w I Z1 Z2 G (s) = ⋅ ⋅ COMP pin and FB pin, GND, and the output as shown in Figure s s s 1+ ⋅1+ 17. The compensation network includes C1, C2, R1, R7, w w P1 P2 R8 and C8. R9 is used to program the output voltage ac- cording to:  2008 Semtech Corp. www.semtech.com 14 SC4620 POWER MANAGEMENT Operation Application Inf Application Information (Cont.) ormation (Cont.) The design guidelines for the SC4620 applications are as where follows: 1 ω = I 1. Set the loop gain crossover corner frequency w for R ⋅(C+C ) 7 1 2 C given switching corner frequency w = 2pfs, S 2. Place an integrator at the origin to increase DC and 1 ω = Z1 low frequency gains. R ⋅C 1 2 3. Select w and w such that they are placed near w Z1 Z2 O 1 to damp the peaking and the loop gain has a -20dB/ ω = Z2 dec rate to go across the 0dB line for obtaining a wide (R +R )⋅C 7 8 8 bandwidth. 4. Cancel the zero from C4’s ESR by a compensator pole C+C 1 2 w (w = w = 1/(R C )). ω = P1 P1 P1 ESR C 4 R ⋅C⋅C 1 1 2 5. Place a high frequency compensator pole w (w = P2 P2 pfs) to get the maximum attenuation of the switch- ing ripple and high frequency noise with the adequate 1 ω = P2 phase lag at w . R ⋅C 8 89 C The compensated loop gain will be as given as show in After the compensation, the converter will have the Figure 18. following loop gain: s 1+ 1 s s 1 ⋅ w ⋅ V 1+ 1+ I I V w w R ⋅C M Z1 Z2 C 4 T(s) = G ⋅G (s) ⋅G (s) = ⋅ ⋅ ⋅ PWM COMP VD s s L s 2 1 1+ ⋅1+ 1+ s + s L C 1 w w R P1 P2 s 1+ 1 1 s s ⋅ w ⋅ V 1+ 1+ I I V w w R ⋅C M Z1 Z2 C 4 T(s) = G ⋅G (s) ⋅G (s) = ⋅ ⋅ ⋅ PWM COMP VD = s s L s 2 1 1+ ⋅1+ 1+ s + s L C 1 w w R P1 P2 where G = PWM gain. PWM V = 1.0V, ramp peak to valley voltage of SC4620. M Figure 18. Asymptotic Diagrams of Power Stage and Loop Gain  2008 Semtech Corp. www.semtech.com 15 SC4620 POWER MANAGEMENT Operation Application Inf Application Information (Cont.) ormation (Cont.) Layout Guidelines the big vias to the bottom layer during the re-flow In order to achieve optimal thermal and noise immunity process. for high frequency converters, special attention must be paid to the PCB layout. The goal of layout optimization is to minimize the high di/dt loops and reduce ground bounce. Output voltage setting, line regulation, stability , switching frequency and OCP trip point shifted are affected by a poor layout. The following guidelines should be used to ensure proper functions of the converters. 1. Both Power ground (PGND) and signal ground (AGND) are separated. 2. A ground plane is recommended to minimize noise and copper losses, and maximize heat dissipation. 3. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. 4. Minimize all high di/dt loops. These loops pass high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. Ground bounce happen to magnetic flux changed and it is proportional to a magnetic filed which goes through high di/dt loops. 5. The input ceramic capacitor (C ) should be close to IN PV pins and PGND pins. IN 6. Both input ceramic capacitor gnd and output ceramic capacitor gnd are at same port. 7. A RC snubber circuit between PV and PH pins is IN helpful for stability operation. Be careful with power derating of snubber circuit. 8. The V bypass capacitor should be placed next to the CC V and AGND pins. CC 9. The OCP setting resistor (R ) and filter capacitor ISET (C ) should be placed next to the ISET and AGND ISET pins. 10. Feedback divider connects to output connector by Kelvin connection and far away from the noise sources such as switching node and switching components. 11. A multilayer chip beads between AGND and PGND will reduce the ground bounce injected to the “quiet” circuit. It’s helpful for stability operation. 12. A large copper area underneath the SC4624 IC is necessary for heat sinking purpose. And multiple layers of large copper area connected through vias can be used for better thermal performance. The size of the vias as the connection between multiple layers should not be too large or solder may seep through  2008 Semtech Corp. www.semtech.com 16 SC4620 POWER MANAGEMENT Operation Application Inf Application Information (Cont.) ormation (Cont.) 5 4 3 2 1 5V , 1V , 2.5A, all ceramic capacitors ( application circuit #1 ) IN OUT 5Vin D D R R5 5 R R6 6 R R2 2 10R 10R 10k 10k 10k 10k U U1 1 C C6 6 C C3 3 R R10 10 1nF 1nF 1uF 1uF 7 12 VCC VCC 0R 0R 6 13 PGOOD AGND 47.5k 47.5k R R11 11 9 5 SYNC/EN FS 47nF 47nF C C7 7 C C1 1 2.2pF 2.2pF 8 4 C C NC SS R R1 1 C C2 2 10 20 COMP NC opt opt C C5 5 20k 20k 390pF 390pF R R3 3 11 3 FB ISET 41k 41k 1Vout@2.5A L1 L1 1.8uH 1.8uH 16 1 PH PVIN C C8 8 17 2 PH PVIN 270pF 270pF R R7 7 28.7k 28.7k C C9 9 18 15 R R8 8 PH PGND C C4 4 2.32k 2.32k 22uF 22uF 22uF 22uF 19 14 NC PGND B B R R9 9 S SC C4 46 62 20 0 28.7k 28.7k (2) R R12 12 M MLB LB- -160808- 160808-0600R 0600R- -S S2 2 C C11 11 R R4 4 opt opt opt opt VIN=5V (1) Vout=1V/2.5A Note: (1,2) Option for stability Switching Frequency=550kHz L1: TOKO D104C(919AS-1R8N) A A R12: Multilayer chip inductors; MLB-160808-0600R-S2 Input/Output Capacitors: Panasonic ECJ33YBOJ226M(22uF/6.3V) 5 4 3 2 1  2008 Semtech Corp. www.semtech.com 17 PAD SC4620 POWER MANAGEMENT Operation PCB La PCB Lay yout out Component Side (TOP) (TOP layer) (Bottom layer) (IN1 layer) (IN2 layer)  2008 Semtech Corp. www.semtech.com 18 SC4620 POWER MANAGEMENT Outline Drawing - MLPQ - 20 B DIMENSIONS A D INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX .031 A .035 .039 0.80 0.90 1.00 A1 .000 .001 .002 0.00 0.02 0.05 A2 - (.008) - - (0.20) - b .007 .010 .012 0.18 0.25 0.30 PIN 1 E D .154 .157 .161 3.90 4.00 4.10 INDICATOR D1 .100 .106 .110 2.55 2.70 2.80 (LASER MARK) E .154 .157 .161 3.90 4.00 4.10 E1 .100 .106 .110 2.55 2.70 2.80 e .020 BSC 0.50 BSC L .012 .016 .020 0.30 0.40 0.50 N 20 20 aaa .004 0.10 bbb .004 0.10 A2 A SEATING PLANE aaa C A1 C D1 LxN E/2 E1 2 1 N bxN bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Land Pattern - MLPQ - 20 K DIMENSIONS DIM INCHES MILLIMETERS (.156) (3.95) C G .122 3.10 Z H .106 2.70 G (C) H K .106 2.70 .020 0.50 P X .010 0.25 Y .033 0.85 Y Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com  2008 Semtech Corp. www.semtech.com 19