SEMTECH SC4608

SC4608 High Efficiency Synchronous Step Down Controller POWER MANAGEMENT Description Features The SC4608 is a voltage mode step down (buck) regula- ‹ Asynchronous start up tor controller that provides accurate high efficiency power ‹ Programmable switching frequency up to 1MHz conversion from an input supply range of 2.7V to 5.5V. A ‹ BiCMOS voltage mode PWM controller high level of integration reduces external component ‹ 2.7V to 5.5V input voltage range count, and makes it suitable for low voltage applications ‹ Output voltage as low as 0.5V where cost, size and efficiency are critical. The SC4608 ‹ +/-1% reference accuracy is capable of producing an output voltage as low as 0.5V. ‹ Sleep mode (Icc = 1µA max) It’s frequency of operation is programmable to 1MHz. ‹ Adjustable lossless short circuit current limiting ‹ Combination pulse by pulse & hiccup mode The SC4608 drives external, N-channel MOSFETs with a current limit peak gate current of 1A. A non-overlap protection is pro- ‹ High efficiency synchronous switching vided for the gate drive signals to prevent shoot through ‹ 1A peak current driver of the MOSFET pair. The SC4608 features lossless cur- rent sensing of the voltage drop across the drain to ‹ External soft start source resistance of the high side MOSFET during its ‹ Power good signal conduction period. ‹ 16-pin MLP Lead-free package. This product is fully WEEE and RoHS compliant The quiescent supply current in sleep mode is typically Applications lower than 1µA. A external soft start is provided to pre- vent output voltage overshoot during start-up. ‹ Distributed power architecture ‹ Servers/workstations The SC4608 is an ideal choice for converting 3.3V, 5V or ‹ Local microprocessor core power supplies other low input supply voltages. It’s available in 16 pin ‹ DSP and I/O power supplies MLP package. ‹ Battery-powered applications ‹ Telecommunications equipment ‹ Data processing applications Typical Application Circuit V V =3V =3V – – 3 3..6 6V V in in C1 C10 0 C1 C13 3 C1 C14 4 D2 D2 220u 220u 22u 22u 22u 22u R1 R13 3 R3 R3 1 1 S SC C460 4608 8 M1 M11 1 16 16 15 15 PVD PVDD D BST BST R6 R6 C3 C3 1 1 13 13 AVD AVDD D DRV DRVH H 1u 1u 1 1 2 2 C1 C17 7 I ISET SET L1 L1 1u 1u V V = 0. = 0.5V 5V / / 12 12A A 3 3 12 12 out out COM COMP P PHAS PHASE E 1.8u 1.8u R5 R5 C1 C16 6 M2 M2 4 4 11 11 C6 C6 C5 C5 C4 C4 C9 C9 F FSET SET DRVL DRVL 1 1 5 5 10 10 R7 R7 560pF 560pF 330u 330u 22u 22u 22u 22u EN EN PG PGND ND 4.7n 4.7n 10k 10k C C2 2 2.2n 2.2n R2 R2 6 6 9 9 C1 C1 P PGOOD GOOD AG AGND ND 10k 10k 7 7 8 8 180p 180p R1 R1 SS SS VSEN VSENSE SE R8 R8 Css Css 14.3k 14.3k 200 200 22n 22n Revision: October 26, 2007 1 www.semtech.com SC4608 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit Analog Supply Voltage (AV)6 , PGOOD V DD Power Supply Voltage (PV)V A+V /- 0.3 DD DD PGND ±V 0.3 Output Drivers (DRVH, DRVL) Currents ±A 0.25 Continuous ±A 1.00 Peak Inputs (VSENSE, COMP, FSET, ISET, SS) -0.3 to AV+V 0.3 DD BST PV+V 6 DD PHASE -0.3 to PV+V 0.3 DD PHASE Pulse tpulse < 50ns -2 to PV+V 1 DD ST torage Temperature Range -C 65 to +150 ° STG MT aximum Junction Temperature +C 150 ° J PT eak IR Reflow Temperature, 10 - 40s 2C 60 ° PKG ED SD Rating (Human Body Model) E2 S kV All voltages with respect to AGND. Currents are positive into, negative out of the specified terminal. Electrical Characteristics Unless otherwise specified, AV = 3.3V, AV = PV , CT = 270pF, T = -40°C to 85°C, T =T DD DD DD A A J Ps arameter Tn est Condition Mp i Tx y Mt a Uni Overall Supply Voltage 5V .5 SV upply Current, Sleep E1 N = 0 01 . µA SV upply Current, Operating A =V52 .5 3A .75 m DD AVTT urn-on Threshold=7 -40°C to 85°C 2V . DD A AVT5 urn-off Hysteresis 20 7 35 5 4V 2 m DD Error Amplifier FB Voltage AV = 2.7V to 5.5V, 05 .49 01 . 0.5 DD (Internal Reference) T = -40°C to 85°C V A AV = 2.7V to 5.5V, T=3 25°C05 .49 07 . 0.50 DD A T=2 -40°C to 85°C 05 .49 08 . 0.50 A T=5 25°C 05 .49 05 . 0.50 A VV SENSE Bias Current =0 0.5V 2A 0 n SENSE (1) Open Loop Gain V=0 0.5 to 2.5V 9B d COMP (1) Unity Gain Bandwidth 8z MH  2007 Semtech Corp. 2 www.semtech.com SC4608 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, AV = 3.3V, AV = PV , CT = 270pF, T = -40°C to 85°C, T =T DD DD DD A A J Ps arameter Tn est Condition Mp i Tx y Mt a Uni Error Amplifier (Cont.) (1) Slew Rate 2s .4 V/µ AV-V 0.5 A - 0.3 VI OUT High = -5.5mA V DD DD COMP VI OUT Low =3 5.5mA 05 . 0.4 COMP Oscillator IT nitial Accuracy =5 25°C 55 2 55 7 6z 2 kH A OT SC Line Regulation = 25°C, AV=1 2.7V to 5.5V 2V .5 %/ A DD TT emperature Coefficient =2 -40°C to 85°C 0C .0 %/° A (1) Minimum Operation Frequency 5z 0 kH (1) Maximum Operation Frequency 1z M H Ramp Peak to Valley 1V Ramp Peak Voltage 1V .3 Ramp Valley Voltage 0V .3 Soft Start, Current Limit (1) Programmable Soft Start Time C2 = 22nF ms ST oft Start Charge Current =4 25°C -5-5 5.2 -A 6. µ A IT SET Bias Current =5 25°C -0 4 -5 5 -A 5 µ J Temperature Coefficient of ISET 0C .3 %/° (1) Current Limit Blank Time 1s 30 n Gate Drive (1) DRVH Minimum OFF Time T=0 25°C 1s 6 n A PI eak Source (DRVH) Vgs = 3.3V,=5 100mA 36 . Ω SOURCE PI eak Sink (DRVH) Vgs = 3.3V,=3 100mA 5 Ω SINK (1) Peak Source (DRVL) Vgs = 3.3V, I=2 100mA 2. Ω SOURCE PI eak Sink (DRVL) Vgs = 3.3V,=2 100mA 4 Ω SINK OC utput Rise Time Vgs = 3.3V,=5 4.7nF 3s n OUT OC utput Fall Time Vgs = 3.3V,=7 4.7nF 2s n OUT (1) Minimum Non-Overlap 4s 0 n  2007 Semtech Corp. 3 www.semtech.com SC4608 POWER MANAGEMENT Electrical Characteristics Unless otherwise specified, AV = 3.3V, AV = PV , CT = 270pF, T = -40°C to 85°C, T =T DD DD DD A A J Ps arameter Tn est Condition Mp i Tx y Mt a Uni Power Good PI GOOD Voltage Low = 1mA, AV=5 5.5V 03 .1 0V . PGOOD DD PV GOOD Leakage Current A=1 5.5V µA DD PGOOD Upper Threshold 75 .5 15 1. 1% 5. PGOOD Lower Threshold -5 14.5 -5 10. -% 6. PGOOD Delay 1s 4 m Enable High Level Threshold 0.7 * AV V DD 0.3 * AV Low Level Threshold V DD EV N Input Bias Current V0 EN = 0 -A 1 n Note: (1). Guaranteed by design.  2007 Semtech Corp. 4 www.semtech.com SC4608 POWER MANAGEMENT Pin Configuration Ordering Information (1) TOP VIEW Pe art Number Devic (2) SC4608MLTRT MLP-16 Sd C4608EVB Evaluation Boar Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (16 Pin MLP) Pin Descriptions Pe in #Pn in Nam Pin Functio 1DA. VD Power supply voltage for the analog section of the controller 2T ISE The ISET pin is used to limit current in the high side MOSFET. The SC4608 uses the voltage across the V and ISET pins in order to set the current limit. The current limit IN threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the V and PHASE pin. IN 3P COM This is the output of the voltage error amplifier. The voltage at this output is inverted internally and connected to the non-inverting input of the PWM comparator. A lead-lag network from the COMP pin to the VSENSE pin compensates for the two pole LC filter characteristics inherent to voltage mode control. The lead-lag network is required in order to optimize the dynamic performance of the voltage mode control loop. 4T FSE The FSET pin is used to sets the PWM oscillator frequency through an external timing capacitor that is connected from the FSET pin to the GND pin. The SC4608 can be operated in synchronous mode by placing a resistor in series between the timing capacitor and ground. The other terminal of the timing capacitor will remain connected to the FSET pin. 5N E The oscillator frequency of the SC4608 is set by FSET when EN is pulled and held above 0.7 * AV . Its shutdown mode is invoked if EN is pulled and held below 0.3 * AV DD DD.  2007 Semtech Corp. 5 www.semtech.com SC4608 POWER MANAGEMENT Pin Descriptions (Cont.) Pe in #Pn in Nam Pin Functio 6D PGOO Power good open drain output. Low when the output is below the power good threshold level. 7S S Soft start. A capacitor to ground sets the soft start time. The soft start time is independent of switching frequency and is defined as SS = 0.09 • C. Where C is the external capacitor in nF and SS is the soft start time in ms. 8E VSENS This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. VSENSE is compared to an internal reference value of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired. For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical Application Circuit Diagram). 9DA. GN Analog ground 1D 0P. GN Power ground 1L 1 DRV DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output drivers are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics. 1E 2 PHAS The PHASE pin is used to limit current in the high side MOSFET. The SC4608 uses the voltage across the V and ISET pin in order to set the current limit. The current limit IN threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the V and PHASE pin. IN 1H 3 DRV DRVH drives the gate of the high side (main switch) MOSFET. The output drivers are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics. 1C 4N. No connection 1T 5 BS This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a sufficient gate-to-source voltage level for driving the gate of the high side MOSFET. 1D 6P. VD Power supply voltage for low side MOSFET Thermal Pad Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.  2007 Semtech Corp. 6 www.semtech.com SC4608 POWER MANAGEMENT Block Diagram  2007 Semtech Corp. 7 www.semtech.com SC4608 POWER MANAGEMENT The maximum frequency of the external clock signal can Application Information be higher than the natural switching frequency by about Enable 10%. The SC4608 is enabled by applying a voltage greater than 2.7 volts to the AV pin. The SC4608 is disabled when DD FS FSE ET T AV falls below 2.35 volts or when sleep mode opera- C C DD FS FSE ET T C C S SC C4608 4608 Ex Extte er rnal nal R R tion is invoked by clamping the EN pin to a voltage below Cl Clo oc ck k AA Si Sign gnal al 0.3*AV . 0.1µA is the typical current drawn through the 1k 1k DD 56p 56pF F AV pin during sleep mode. During the sleep mode, the R R D D SYNC SYNC DD high side and low side MOSFETs are turned off and the 100 100 internal soft start voltage is held low. Oscillator Figure 1 The FSET pin is used to set the PWM oscillator frequency UVLO through an external timing capacitor that is connected from the FSET pin to the GND pin. The resulting ramp When the EN pin is not pulled and held below 0.3*AV , DD waveform ion the FSET pin is a triangle at the PWM fre- the voltage on the AV pin determines the operation of DD quency with a peak voltage of 1.3V and a valley voltage the SC4608. As AV increases during start up, the UVLO DD of 0.3V. 160ns minimum OFF time for the top switch block senses AV and keeps the high side and low side DD allows the bootstrap capacitor to be charged during each MOSFETs off and the internal soft start voltage low until cycle. The capacitor tolerance adds to the accuracy of AV reaches 2.7V. If no faults are present, the SC4608 DD the oscillator frequency. The approximate operating fre- will initiate a soft start when AV exceeds 2.7V. A hyster- DD quency and soft start time are both determined by the esis (350mV) in the UVLO comparator provides noise im- value of the external timing capacitor as shown in Table munity during its start up. 1. Power Good Indicator External Timing Frequency (kHz) Capacitor Value (pF) The PGOOD pin is the open-drain output of the power good comparators. These comparators are incorporated 10 20 100 with small amount of hysteresis. A pull-up resistor from 25 70 57 the PGOOD pin to the input supply or the output sets the logic high level of the PGOOD signal. The VSENSE low-to- 40 70 35 high trip voltage of the power good comparator is 89% of the final regulation voltage. The power good compara- 55 60 29 tor output becomes valid provided that V is within about O ±11% of the programmed output voltage. In shutdown Table 1. Operating Frequency value Based on the mode the power good output is actively pulled low. The Value of the External Timing Capacitor Placed Across PGOOD signal delay depends on its operating frequency the FSET and GND Pins fs, for example, about 14ms@ fs=575kHz and 24ms @ fs=330kHz. Synchronous mode operation is invoked by using a sig- nal from an external clock. A low value resistor (100Ω Soft Start typical) must be inserted in series with the timing capaci- tor between the timing capacitor and the GND pin. The The soft start function is required for step down control- other terminal of the timing capacitor will remain con- lers to prevent excess inrush current through the DC bus nected to the FSET pin. The transformed external clock during start up. Generally this can be done by sourcing a signal is then connected to the junction of the external controlled current into a timing capacitor and then using timing capacitor and the added resistor R as shown SYNC the voltage across this capacitor to slowly ramp up the in Figure 1. error amp reference. The closed loop creates narrow  2007 Semtech Corp. 8 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) width driver pulses while the output voltage is low and When the converter detects an over current condition allows these pulses to increase to their steady state duty (I > I ) as shown in Figure 2, the first action the SC4608 MAX cycle as the output voltage reaches its regulated value. takes is to enter the cycle by cycle protection mode (Point With this, the inrush current from the input side is con- B to Point C), which responds to minor over current cases. trolled. The duration of the soft start in the SC4608 is Then the output voltage is monitored. If the over current controlled by an external capacitor. SS, the start-up time and low output voltage (set at 70% of nominal output is defined as: voltage) occur at the same time, the Hiccup mode op- eration (Point C to Point D) of the SC4608 is invoked and the internal soft start capacitor is discharged. This is SS = 0.09 • C like a typical soft start cycle: where, C is the value of the external capacitor in nF, and Figure 2. Over current protection characteristic of SS is the start-up time in ms. SC4608 Over Current Protection The SC4608 detects over current conditions by sensing the voltage across the drain-to-source of the high side A A A A MOSFET. The SC4608 determines the high side MOS- B B B B V V V V O O O O − − − −nom nom nom nom FET current level by sensing the drain-to-source conduc- tion voltage across the high side MOSFET via the V (see in the Typical Application Circuit on page 1) and PHASE pin ⋅⋅⋅⋅ 0 0 0 0....6 7 6 7 V V V V C C C C O O O O − − − −nom nom nom nom during the high side MOSFETs conduction period. This voltage value is then compared internally to a user pro- V V V V O O O O grammed current limit threshold. Note that user should place Kelvin sensing connections directly from the high D D D D IIII MA MA MA MAX X X X side MOSFET source to the PHASE pin. IIII O O O O The current limit threshold is programmed by the user based on the RDS(on) of the high side MOSFET and the Power MOSFET Drivers value of the external set resistor RSET (where RSET is represented by R3 in the applications schematics of this The SC4608 has two drivers which are optimized for driv- document). The SC4608 uses an internal current source ing external power N-Channel MOSFETs. The driver block to pull a 50µA current from the input voltage to the ISET consists two 1 Amp drivers. DRVH drives the high side pin through external resistor RSET. N-MOSFET (main switch), and DRVL drives the low side The current limit threshold resistor (RSET) value is calcu- N-MOSFET (synchronous rectifier transistor). lated using the following equation: The output drivers also have gate drive non-overlap I ⋅R MAX DS(ON) mechanism that provides a dead time between DRVH R = SET 50µA and DRVL transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, the SC4608 is The R sensing used in the SC4608 has an addi- DS(ON) tional feature that enhances the performance of the over capable of driving a converter with up to 12A of output current protection. Because the R has a positive current. As shown in Figure 3, td1 the delay from the DS(ON) , temperature coefficient, the 50µA current source has a top MOSFET off to the bottom MOSFET on is adaptive by positive coefficient of about 0.3%/C° providing first or- detecting the voltage of the phase node. td2, the delay der correction for current sensing vs temperature. This from the bottom MOSFET off to the top MOSFET on is compensation depends on the high amount of thermal fixed, is 40ns for the SC4608. This control scheme guar- transferring that typically exists between the high side N- antees avoidance of cross conduction or shoot through MOSFET and the SC4608 due to the compact layout of the power supply.  2007 Semtech Corp. 9 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) must be able to handle the peak inductor current I PEAK without saturation and produce low core loss during the between the upper and lower MOSFETs and also mini- high frequency operation is: mizes the conduction loss in the body diode of the bot- tom MOSFET for high efficiency applications. I p−p I = I + PEAK OMAX 2 T TO OP M P MO OSFET SFET G Ga atte e Dr Driv ive e The power loss for the inductor includes its core loss and B BO OT TT TOM M OM MO OS SF FE ET T Ga Gate D te Dr rive ive copper loss. If possible, the winding resistance should be minimized to reduce inductor’s copper loss. The core Gro Ground und P Ph ha as se no e node de loss can be found in the manufacturer’s datasheet. The inductor’ copper loss can be estimated as follows: tt tt d1 d1 d2 d2 2 P = I LRMS ⋅R COPPER WINDING Where: Figure 3. Timing Waveforms for Gate Drives and Phase I is the RMS current in the inductor. This current can LRMS Node be calculated as follow is: Inductor Selection 1 2 I = I ⋅ 1+ ⋅ ΔI LRMS OMAX 3 The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4608 applica- Output Capacitor Selection tion, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the in- Basically there are two major factors to consider in se- ductor value will decrease the ripple level of the output lecting the type and quantity of the output capacitors. voltage while the output transient response will be de- The first one is the required ESR (Equivalent Series Re- graded. Low value inductors offer small size and fast tran- sistance) which should be low enough to reduce the volt- sient responses while they cause large ripple currents, age deviation from its nominal one during its load changes. poor efficiencies and more output capacitance to smooth The second one is the required capacitance, which should out the large ripple currents. The inductor should be able be high enough to hold up the output voltage. Before the to handle the peak current without saturating and its SC4608 regulates the inductor current to a new value copper resistance in the winding should be as low as during a load transient, the output capacitor delivers all possible to minimize its resistive power loss. A good trade- the additional current needed by the load. The ESR and off among its size, loss and cost is to set the inductor ESL of the output capacitor, the loop parasitic inductance ripple current to be within 15% to 30% of the maximum between the output capacitor and the load combined output current. with inductor ripple current are all major contributors to The inductor value can be determined according to its the output voltage ripple. Surface mount speciality poly- operating point and the switching frequency as follows: mer aluminum electrolytic chip capacitors in UE series V ⋅(V − V ) from Panasonic provide low ESR and reduce the total OUT IN OUT L = V ⋅ f ⋅ ΔI⋅I capacitance required for a fast transient response. IN s OMAX POSCAP from Sanyo is a solid electrolytic chip capacitor Where: that has a low ESR and good performance for high fre- f = switching frequency and s quency with a low profile and high capacitance. Above ΔI = ratio of the peak to peak inductor current to the mentioned capacitors are recommended to use in maximum output load current. SC4608 application. The peak to peak inductor current is: Input Capacitor Selection I = ΔI•I p−p OMAX The input capacitor selection is based on its ripple cur- After the required inductor value is selected, the proper rent level, required capacitance and voltage rating. This selection of the core material is based on the peak in- capacitor must be able to provide the ripple current by ductor current and efficiency requirements. The core the switching actions. For the continuous conduction  2007 Semtech Corp. 10 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) Where: mode, the RMS value of the input capacitor can be cal- I = the boost current and culated from: B V = discharge ripple voltage. D V ⋅(V − V ) OUT IN OUT I = I ⋅ CIN(RMS) OMAX 2 V IN With f = 300kH, V =0.3V and IB = 50mA, the required s D capacitance for the boost capacitor is: This current gives the capacitor’s power loss as follows: I 1 0.05 1 B C = ⋅ ⋅D = ⋅ ⋅0.95 = 528nF 2 boost max P = I ⋅R CIN(RMS) V f 0.3 300k CIN CIN(ESR) D s This capacitor’s RMS loss can be a significant part of the Power MOSFET Selection total loss in the converter and reduce the overall con- verter efficiency. The input ripple voltage mainly depends The SC4608 can drive an N-MOSFET at the high side on the input capacitor’s ESR and its capacitance for a and an N-MOSFET synchronous rectifier at the low side. given load, input voltage and output voltage. Assuming The use of the high side N-MOSFET will significantly re- that the input current of the converter is constant, the duce its conduction loss for high current. For the top required input capacitance for a given voltage ripple can MOSFET, its total power loss includes its conduction loss, be calculated by: switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bot- D ⋅(1− D) C = I ⋅ IN OMAX tom diode, shown as follows: fs ⋅(ΔV −I ⋅R ) I OMAX CIN(ESR) Where: I ⋅ V ⋅ f 2 TOP _PEAK I s D = V /V , duty ratio and O I P = I TOP _RMS ⋅R + ⋅ TOP _ TOTAL TOP _ ON V ΔV = the given input voltage ripple. GATE I R G (Q + Q ) + Q ⋅ V ⋅ f + (Q + Q ) ⋅ V ⋅ f Because the input capacitor is exposed to the large surge GD GS2 GT GATE s OSS rr I s current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge Where: ratings are not exceeded. For generic tantalum capaci- R = gate drive resistor, G tors, it is wise to derate their voltage ratings at a ratio of Q = the gate to drain charge of the top MOSFET, GD 2 to protect these input capacitors. Q = the gate to source charge of the top MOSFET, GS2 Q = the total gate charge of the top MOSFET, GT Boost Capacitor Selection Q = the output charge of the top MOSFET and OSS Q = the reverse recovery charge of the bottom diode. rr The boost capacitor selection is based on its discharge ripple voltage, worst case conduction time and boost For the top MOSFET, it experiences high current and high current. The worst case conduction time T can be esti- w voltage overlap during each on/off transition. But for the mated as follows: bottom MOSFET, its switching voltage is the bottom diode’s forward drop during its on/off transition. So the 1 Tw = ⋅D max switching loss for the bottom MOSFET is negligible. Its f s total power loss can be determined by: Where: 2 P = I BOT _RMS ⋅R + Q ⋅ V ⋅ f + I _ ⋅ V f = the switching frequency and BOT _ TOTAL BOT _ ON GB GATE s D AVG F s Dmax = maximum duty ratio. Where: The required minimum capacitance for boost capacitor Q = the total gate charge of the bottom MOSFET and GB will be: V = the forward voltage drop of the bottom diode. F I B C = ⋅ T boost W V D  2007 Semtech Corp. 11 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) For a low voltage and high output current application such as the 3.3V/1.5V@12A case, the conduction loss is of- L1 L1 ten dominant and selecting low R MOSFETs will no- VV out out DS(ON) PH PHAS ASE E ticeably improve the efficiency of the converter even though they give higher switching losses. CO COMP MP C9 C9 C4 C4 C1 C1 C2 C2 VS VSEN ENSE SE R7 R7 R R The gate charge loss portion of the top/bottom MOSFET’s SSCC4608 4608 R8 R8 total power loss is derived from the SC4608. This gate R1 R1 charge loss is based on certain operating conditions (f , s V , and I ). GATE O R9 R9 The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their Figure 4. Compensation network provides 3 poles and total power losses P , ambient temperature T and their TOTAL A 2 zeros. RθJA as follows: thermal resistance For voltage mode step down applications as shown in P TOTAL T < T + J(max) A Figure 4, the power stage transfer function is: R θJA s 1+ Loop Compensation Design 1 ⋅ R C C 4 G (s) = V VD I For a DC/DC converter, it is usually required that the L 1 2 1+ s + s L C 1 4 converter has a loop gain of a high cross-over frequency R for fast load response, high DC and low frequency gain Where: for low steady state error, and enough phase margin for R = load resistance and its operating stability. Often one can not have all these R = C ’s ESR. C 4 properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the The compensation network will have the characteristic compensation network to meet the requirements for a as follows: specific application. s s + + 1 1 The SC4608 has an internal error amplifier and requires ω ω ω I Z1 Z2 G (s) = ⋅ ⋅ COMP the compensation network to connect among the COMP s s s 1+ ⋅1+ pin and VSENSE pin, GND, and the output as shown in ω ω P1 P2 Figure 4. The compensation network includes C1, C2, Where R1, R7, R8 and C9. R9 is used to program the output voltage according to: 1 R 7 ω = I V = 0.5 ⋅(1+ ) O R ⋅(C + C ) 7 1 2 R 9 1 ω = Z1 R ⋅ C 1 2 1 ω = Z2 (R + R ) ⋅C 7 8 9 C + C 1 2 ω = P1 R ⋅C ⋅C 1 1 2  2007 Semtech Corp. 12 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) 1 Layout Guidelines ω = P2 ⋅ R C 8 9 In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special at- After the compensation, the converter will have the fol- tention must be paid to the PCB layouts. The goal of lay- lowing loop gain: out optimization is to identify the high di/dt loops and s 1+ minimize them. The following guideline should be used to 1 s s 1 ⋅ ω ⋅ V 1+ 1+ I I V ω ω R ⋅C ensure proper functions of the converters. M Z1 Z2 C 4 T(s) = G ⋅ G (s) ⋅ G (s) = ⋅ ⋅ ⋅ PWM COMP VD s s L s 2 1 1+ ⋅1+ 1+ s + s L C 1 ω ω R P1 P2 1. A ground plane is recommended to minimize noises Where: and copper losses, and maximize heat dissipation. G = PWM gain 2. Start the PCB layout by placing the power compo- PWM V = 1.0V, ramp peak to valley voltage of SC4608 nents first. Arrange the power circuit to achieve a M clean power flow route. Put all the connections on The design guidelines for the SC4608 applications are one side of the PCB with wide copper filled areas if as following: possible. 3. The AV bypass capacitor should be placed next to DD 1. Set the loop gain crossover corner frequency ω the AV and AGND pins. C DD for given switching corner frequency ω = 2πfs, 4. The trace connecting the feedback resistors to the S 2. Place an integrator at the origin to increase DC output should be short, direct and far away from the and low frequency gains. noise sources such as switching node and switching 3. Select ω and ω such that they are placed near components. Z1 Z2 ω to damp the peaking and the loop gain has a 5. Minimize the traces between DRVH/DRVL and the O -20dB/dec rate to go across the 0dB line for gates of the MOSFETs to reduce their impedance to obtaining a wide bandwidth. drive the MOSFETs. 4. Cancel the zero from C ’s ESR by a compensator 6. Minimize the loop including input capacitors, top/bot- 4 pole ω (ω = ω = 1/( R C )). tom MOSFETs. This loop passes high di/dt current. P1 P1 ESR C 4 5. Place a high frequency compensator pole ωp (ωp Make sure the trace width is wide enough to reduce 2 2 = πf ) to get the maximum attenuation of the switch- copper losses in this loop. s ing ripple and high frequency noise with the adequate 7. ISET and PHASE connections to the top MOSFET for phase lag at ω . current sensing must use Kelvin connections. C 8. Maximize the trace width of the loop connecting the The compensated loop gain will be as given in Figure 5: inductor, bottom MOSFET and the output capacitors. T 9. Connect the ground of the feedback divider and the ω Z1 Loop gain ω o compensation components directly to the AGND pin ω Z2 - of the SC4608 by using a separate ground trace. Gvd c ω 0dB Then connect this pin to the ground of the output ωp1 capacitor as close as possible ωp2 Power stage ω ESR - Figure 5. Asymptotic diagrams of power stage and its loop gain  2007 Semtech Corp. 13 www.semtech.com SC4608 POWER MANAGEMENT Application Information (Cont.) Design Example 1. 3V to1.5V @10A application with SC4608 V V =3V =3V - - 5 5..5 5V V in in C1 C10 0 C1 C13 3 C1 C14 4 D2 D2 22u 22u 220u 220u 22u 22u R1 R13 3 R3 R3 1 1 S SC C460 4608 8 M1 M11 1 16 16 15 15 PVD PVDD D BST BST R6 R6 C3 C3 1 1 13 13 AVD AVDD D DRV DRVH H 1u 1u 0 0 2 2 C1 C17 7 I ISET SET L1 L1 1u 1u V V = =1 1.5 .5V/ 1 V/ 10 0A A out out 3 3 12 12 COM COMP P PHAS PHASE E R5 R5 2.3u 2.3u C1 C16 6 M2 M2 4 4 11 11 C7 C7 C5 C5 C4 C4 C9 C9 F FSET SET DRVL DRVL 0 0 5 5 10 10 R7 R7 470pF 470pF 330u 330u 22u 22u 22u 22u EN EN PG PGND ND 8.2n 8.2n 5.76k 5.76k C C2 2 2.2n 2.2n R2 R2 6 6 9 9 C1 C1 P PGOOD GOOD AG AGND ND 10k 10k 7 7 8 8 1.8n 1.8n R1 R1 SS SS VSEN VSENSE SE R8 R8 Css Css 14.3k 14.3k 107 107 22n 22n R9 R9 2.87k 2.87k  2007 Semtech Corp. 14 www.semtech.com SC4608 POWER MANAGEMENT Bill of Materials Iy temQe tRe eferenc Vr alu Part No./Manufacture 11CF 1 1.8n 21CF 2 2.2n 31CF 17 1u 44C6 4,C5, C13, C142M 2uF, 120 TDK P/N: C3225X5R0J226 51C0 7 3L 30uF, 287 Sanyo P/N: 6TPB330M 61CF 9 8.2n 71CF 16 470p 81D1 2 M1 BR0520LT ON Semi P/N: MBR0520LT Cooper Electronic 91LH 1 2.3u P/N: HC1-2R3 12 0M8 1, M2 PP owerpack, SO- Vishay P/N: Si7882D 11 1RK 1 14.3 11 2RK 3 1.33 11 3RK 7 5.76 11 4R7 8 10 11 5RK 9 2.87 11 6R1 13 11 7C5 3 1uF, 080 11 8C0 10 2L 20uF, 287 Sanyo P/N: 6TPB220M 11 9CF ss 22n 21 0U8 1 ST C460 Semtech P/N: SC4608IMLTR 21 1Rk 2 10 Unless specified, all resistors have 1% precision with 0603 package. Resistors are +/-1% and all capacitors are +/-20%  2007 Semtech Corp. 15 www.semtech.com SC4608 POWER MANAGEMENT PCB Layout COMPONENT SIDE (TOP) COMPONENT SIDE (BOTTOM)  2007 Semtech Corp. 16 www.semtech.com SC4608 POWER MANAGEMENT PCB Layout (Cont.) (BOTTOM) (TOP) (INTER LAYER 2) (INTER LAYER 1)  2007 Semtech Corp. 17 www.semtech.com SC4608 POWER MANAGEMENT Outline Drawing - MLP-16 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A D A .031 - .040 0.80 - 1.00 B - - A1 .000 .002 0.00 0.05 - (.008) - - (0.20) - A2 b .010 .012 .014 0.25 0.30 0.35 D .153 .157 .161 3.90 4.00 4.10 PIN 1 D1 .100 .106 .110 2.55 2.70 2.80 INDICATOR E E .153 .157 .161 3.90 4.00 4.10 (LASER MARK) E1 .100 .106 .110 2.55 2.70 2.80 e .026 BSC 0.65 BSC L .012 .016 .020 0.30 0.40 0.50 N 16 16 aaa .003 0.08 bbb .004 0.10 A2 A SEATING aaa C PLANE A1 C D1 e/2 LxN E/2 E1 2 1 N e bxN bbb C A B D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.  2007 Semtech Corp. 18 www.semtech.com SC4608 POWER MANAGEMENT Land Pattern - MLP-16 K DIMENSIONS DIM INCHES MILLIMETERS (.156) (3.95) C G .122 3.10 2x Z H 2x G 2x (C) H .106 2.70 K .106 2.70 P .026 0.65 X .016 0.40 Y Y .033 0.85 Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2007 Semtech Corp. 19 www.semtech.com