SEMTECH SC4603

SC4603 Very Low Input, MHz Operation, High Efficiency Synchronous Buck POWER MANAGEMENT Description Features The SC4603 is a voltage mode step down (buck) regula- ‹ BICMOS voltage mode PWM controller tor controller that provides accurate high efficiency power ‹ 2.25V to 5.5V Input voltage range conversion from input supply range 2.25V to 5.5V. A high ‹ Output voltages as low as 0.5V level of integration reduces external component count ‹ Sleep mode (Icc = 10µA typ) and makes it suitable for low voltage applications where ‹ Lossless adjustable overcurrent protection cost, size and efficiency are critical. ‹ Combination pulse by pulse & hiccup mode current limit The SC4603 drives external complementary power ‹ High efficiency synchronous switching MOSFETs; P-channel on the high side and N-channel on ‹ 0% to 100% Duty cycle range the low side. The use of high side P-channel MOSFETs ‹ Synchronization to external clock eliminates the need for an external charge pump and ‹ Asynchronous start-up simplifies the high side gate driver. Non-overlap protec- tion is provided for the gate drive signals to prevent shoot ‹ 1MHz frequency of operation through of the MOSFET pair. The voltage drop across the ‹ 10-Pin MSOP surface mount package. Lead free P-channel MOSFET during its conduction is sensed for product. This product is fully WEEE and RoHS lossless short circuit current limiting. compliant Applications A low power sleep mode can be achieved by forcing the SYNC/SLEEP pin below 0.8V. A synchronous mode of op- ‹ Distributed power architecture eration is activated as the SYNC/SLEEP pin is driven by ‹ Servers/workstations an external clock. The quiescent supply current in sleep ‹ Local microprocessor core power supplies mode is typically lower than 10µA. A 1.7ms soft start is ‹ DSP and I/O power supplies internally provided to prevent output voltage overshoot ‹ Battery powered applications during start-up. A 100% maximum duty cycle allows the ‹ Telecommunication equipment SC4603 to operate as a low dropout regulator in the ‹ Data processing applications event of a low battery condition. The SC4603 is an ideal choice for 3.3V, 5V or other low input supply systems. It’s available in 10 pin MSOP package. Typical Application Circuit R1 R15 5 V Vi in n = = 2. 2.25V 25V ~ ~ 5. 5.5 5V V 1 1 C1 C14 4 C1 C10 0 C1 C11 1 C1 C12 2 C1 C13 3 R3 R3 M1 M1 33n 33n 22u 22u 22u 22u 22u 22u 22u 22u U1 U1 R RT T 34. 34.8k 8k 5 5 6 6 FS FS IS ISE ET T R6 R6 4. 4.7u 7u C3 C3 1 1 10 10 VC VCC C PD PDR RV V L1 L1 1. 1.0 0 V Vo out ut = = 1. 1.5V 5V ( (a as l s lo ow a w as s 0. 0.5V 5V * * ) ) / /6 6A A 2 2 7 7 SY SYN NC C PH PHASE ASE 2. 2.3u 3u 3 3 9 9 CO COMP MP N NDRV DRV C9 C9 C1 C1 150p 150p 4 4 8 8 M2 M2 C7 C7 C4 C4 VS VSEN ENSE SE GN GND D 1. 1.2n 2n R1 R1 C2 C2 R5 R5 22u 22u R7 R7 150u 150u 14k 14k S SC C4603 4603 R8 R8 20k 20k 1n 1n 1. 1.0 0 806 806 R9 R9 6. 6.98k 98k * * Ex Exte ter rn nal al c comp ompo on nen ents ts c ca an n be be m mo od di if fi ie ed d to to pro prov vi id de e a a Vo Vout ut as as low low a as s 0. 0.5V. 5V. Revision: May 16, 2008 1 www.semtech.com SC4603 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit Supply Voltage (V)6V CC Output Drivers (PDRV, NDRV) Currents Continuous ±A 0.25 Inputs (VSENSE, COMP, SYNC/SLEEP, FS, ISET) 6V Phase -V 0.3 to 5.5 Phase Pulse tpulse < 50ns -V 2 to 6 OT perating Ambient Temperature Range -C 40 to +85 ° A ST torage Temperature Range -C 65 to +150 ° STG JT unction Temperature Range -C 55 to +150 ° J Thermal Impedance Junction to Case θ 4W 1.9 °C/ JC Thermal Impedance Junction to Ambient θ 1W 13.1 °C/ JA LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD ED SD Rating (Human Body Model) E2 S kV All voltages are with respect to GND. Currents are positive into, Electrical Characteristics negative out of the specified terminal. Unless otherwise specified, V = 3.3V, R = 21Kohm, T = -40°C to 85°C, T = T CC T A A J. Ps arameter Tn est Condition Mp i Tx y Mt a Uni Overall Supply Voltage 25 .25 5V . SV upply Current, Sleep =0 0V 151A µ SYNC/SLEEP Supply Current, Operating 23 mA V Turn-on Threshold 252V .2 CC V Turn-off Hysteresis 1V 00 m CC Error Amplifier IV nternal Reference = 3.3V, T=5 25°C 40 9 55 0 5V 0 m CC A V = 3.3V, T=2 -40°C to 85°C48 9 5V 0 m CC A IV nternal Reference Change = 2.25V to 3.3V, T=5 25°C -1 0.1 05 . 0V .3 %/ CC A V = 3.3V to 5.5V, T=4 25°C -2 0. -0 0. %/V CC A VSENSE Bias Current 2A 00 n (1) (1) Open Loop Gain V=0 0.5V to 2.5V 89B 0 d COMP (1) Unity Gain Bandwidth 8z MH (1) Slew Rate 2s .4 V/µ  2008 Semtech Corp. 2 www.semtech.com SC4603 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = 3.3V, R = 21Kohm, T = -40°C to 85°C, T = T CC T A A J. Ps arameter Tn est Condition Mp i Tx y Mt a Uni Error Amplifier (Cont.) VI COMP High =V -5.5mA -V 0.6-V 0.4 COMP CC CC VI COMP Low =5 5.5mA 05 .3 0V .52 COMP Oscillator IT nitial Accuracy = 25°C, V=0 HIGH 50 4 60 0 6z 6 kH A SYNC/SLEEP VT oltage Stability = 25°C, V=1 2.25V to 5.5V %/V A CC TT emperature Coefficient =1 -40°C to 85°C 0C .0 %/° A Synchronization Frequency 1z MH SYNC Low Threshold 0V .8 SYNC High Threshold 2V .0 (1) Ramp Peak to Valley 1V (1) Ramp Peak Voltage 1V .25 (1) Ramp Valley Voltage 0V .25 Sleep, Soft Start, Current Limit SV leep Threshold Measured at 0V .8 SYNC/SLEEP LOGIC LOW Measured at V 2V .0 SYNC/SLEEP LOGIC HIGH (2) Sleep Input Bias Current V=0 0V -A 5 n SYNC/SLEEP (1) Soft Start Time F=7 600kHz 1s . m SW (2) Current Limit Threshold Bias Current, T=3 25°C -0 4 -7 5 -A 5 µ J T3 emperature Coefficient +C 0. %/° (1) Current Limit Blank Time 1s 50 n N-Channel and P-Channel Driver Outputs (2) Pull Up Resistance (PDRV) Vcc = 3.3V, I=4 -100mA (source) 3s . ohm OUT (2) Pull Down Resistance (PDRV) Vcc = 3.3V, I=3 100mA (sink) ohms OUT (1) Pull Up Resistance (NDRV) Vcc = 3.3V, I=4 -100mA (source) 3s . ohm OUT (2) Pull Down Resistance (NDRV) Vcc = 3.3V, I=5 100mA (sink) 1s . ohm OUT (2) PDRV Output Rise Time Vgs = 3.3V, C=8 1.0nF ns OUT (2) PDRV Output Fall Time Vgs = 3.3V, C=7 1.0nF ns OUT  2008 Semtech Corp. 3 www.semtech.com SC4603 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, V = 3.3V, R = 21Kohm, T = -40°C to 85°C, T = T CC T A A J. Ps arameter Tn est Condition Mp i Tx y Mt a Uni N-channel and P-Channel Driver Outputs (Cont.) (1) NDRV Output Rise Time Vgs = 3.3V, C=8 1nF ns COMP (2) NDRV Output Fall Time Vgs = 3.3V, C=3 1nF ns COMP Deadtime Delay adaptive (3) (PDRV high to NDRV high) Deadtime Delay 30 05s n (1) (NDRV low to PDRV low) Notes: (1). Guaranteed by design. (2). Guaranteed by characterization. (3). Dead time delay from PDRV high to NDRV high is adaptive. As the phase node voltage drops below 600mV due to PDRV high, NDRV will start to turn high.  2008 Semtech Corp. 4 www.semtech.com SC4603 POWER MANAGEMENT Pin Configuration Ordering Information (1) Top View Part Number Device (2) SC4603IMSTRT MSOP-10 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (10 Pin MSOP) Pin Descriptions VCC: Positive supply rail for the IC. Bypass this pin to PHASE, ISET: PHASE input is connected to the junction GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci- between the two external power MOSFET transistors. The tor. voltage drop across the upper P-channel device is moni- tored by PHASE and ISET during PFET conduction and GND: All voltages are measured with respect to this pin. forms the current limit comparator and logic that sets All bypass and timing capacitors connected to GND should the PWM latch and terminates the PFET output pulse have leads as short and direct as possible. once excessive voltage drop across the PFET is detected. The controller stops switching and goes through a soft FS: An external resistor connected with FS pin sets the start sequence once the converter output voltage drops clock frequency. below 70% its nominal voltage. This prevents excess power dissipation in the PMOSFET during a short circuit. SYNC/SLEEP: The oscillator frequency of SC4603 is The current limit threshold is set by the external resistor set by FS when SYNC/SLEEP is pulled and held above between VCC and ISET. The internal 50µA current source 2V. Its synchronous mode operation is activated as the has a positive temperature coefficient that can compen- SYNC/SLEEP is driven by an external clock. The oscilla- sate PMOSFET Rdson variation due to its junction tem- tor and PWM are designed to provide practical operation perature change. to 1MHz when synchronized. Sleep mode is invoked if SYNC/SLEEP is pulled and held below 0.8V which can be PDRV, NDRV: The PWM circuitry provides complemen- accomplished by an external gate or transistor. The tary drive signals to the output stages. The Cross con- Sleepmode supply current is 10µA typical. duction of the external MOSFETs is prevented by moni- toring the voltage on the P-channel and N-channel driver VSENSE: This pin is the inverting input of the voltage pins in conjunction with a time delay optimized for FET amplifier and serves as the output voltage feedback point turn-off characteristics. for the Buck converter. It senses the output voltage through an external divider. COMP: This is the output of the voltage amplifier. The voltage at this output is connected to the inverting input of the PWM comparator. A lead-lag network around the voltage amplifier compensates for the two pole LC filter characteristic inherent to voltage mode control and is required in order to optimize the dynamic performance of the voltage mode control loop.  2008 Semtech Corp. 5 www.semtech.com SC4603 POWER MANAGEMENT Typical Characteristics Oscillator Internal Accuracy Oscillator Internal Accuracy vs vs Input Voltage Temperature 602.0 600 Vcc = 3.3V 600.0 595 598.0 590 596.0 585 TA = 25°C 594.0 580 592.0 22.5 33.5 44.555.5 -40 -20 0 204060 80 Vcc (V) Temperature (°C) Sense Voltage Sense Voltage vs vs Input Voltage Temperature 501.0 501.0 500.5 500.5 500.0 500.0 499.5 499.0 499.5 498.5 499.0 498.0 Vcc = 3.3V TA = 25°C 498.5 497.5 22.5 33.5 44.5 55.5 -40 -20 0 204060 80 Vcc (V) Temperature (°C) Current Limit Bias Current Current Limit Bias Current vs vs Input Voltage Temperature 53 60 Vcc = 3.3V A T = 25°C 58 56 52 54 52 52 50 48 51 46 44 51 42 40 50 38 22.533.5 44.555.5 -40 -20 0 20406080 Vcc (V) Temperature (°C)  2008 Semtech Corp. 6 www.semtech.com Internal Accuracy (kHz) Current Limit Bias Sense Voltage (mV) Current (uA) Internal Accuracy (kHz) Current Limit Bias Sense Voltage (mV) Current (uA) SC4603 POWER MANAGEMENT Block Diagram Applications Information Enable 8 126 •10 f = S R T Pulling and holding the SYNC/SLEEP pin below 0.8V ini- tializes the SLEEP mode of the SC4603 with its typical SLEEP mode supply current of 10uA. During the SLEEP An external clock connected to the SYNC/SLEEP acti- mode, the high side and low side MOSFETs are turned vates its synchronous mode and the frequency of the off and the internal soft start voltage is held low. clock can be up to 1MHz. Oscillator UVLO The oscillator uses an external resistor to set the oscilla- When the SYNC/SLEEP pin is pulled and held above 2V, tion frequency when the SYNC/SLEEP pin is pulled and the voltage on the VCC pin determines the operation of held above 2V. The ramp waveform is a triangle at the the SC4603. As V increases during start up, the UVLO CC PWM frequency with a peak voltage of 1.25V and a val- block senses V and keeps the high side and low side CC ley voltage of 0.25V. A 100% maximum duty cycle allows MOSFETs off and the internal soft start voltage low until the SC4603 to operate as a low dropout regulator in the V reaches 2.25V. If no faults are present, the SC4603 CC event of a low battery condition. The resistor tolerance will initiate a soft start when V exceeds 2.25V. A CC adds to the accuracy of the oscillator frequency. The ex- hysteresis (100mV) in the UVLO comparator provides ternal resistor connected to the FS pin, as shown below noise immunity during its start up. determines the approximate operating frequency:  2008 Semtech Corp. 7 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) I and the internal 50µA pull down current available on Soft Start MAX the I pin based on the following expression: SET The soft start function is required for step down control- lers to prevent excess inrush current through the DC bus I • R MAX DS(ON) R = SET during start up. Generally this can be done by sourcing a 50µA controlled current into a timing capacitor and then using Kelvin sensing connections should be used at the drain the voltage across this capacitor to slowly ramp up the and source of P-MOSFET. error amp reference. The closed loop creates narrow width driver pulses while the output voltage is low and The R sensing used in the SC4603 has an addi- DS(ON) allows these pulses to increase to their steady state duty tional feature that enhances the performance of the over cycle as the output voltage reaches its regulated value. current protection. Because the R has a positive DS(ON) With this, the inrush current from the input side is con- temperature coefficient, the 50µA current source has a trolled. The duration of the soft start in the SC4603 is positive coefficient of about 0.3%/C° providing first or- controlled by an internal timing circuit which is used dur- der correction for current sensing vs temperature. This ing start up and over current to set the hiccup time. The compensation depends on the high amount of thermal soft start time can be calculated by: transferring that typically exists between the high side P- MOSFET and the SC4603 due to the compact layout of 1020 the power supply. T = SOFT _ START f S When the converter detects an over current condition (I > I ) as shown in Figure 1, the first action the SC4603 As can be seen here, the soft start time is switching MAX takes is to enter cycle by cycle protection mode (Point B frequency dependant. For example, if f = 600kHz, s to Point C), which responds to minor over current cases. T _ = 1020/600k = 1.7ms. But if f = 1MHz, SOFT START s Then the output voltage is monitored. If the over current T _ = 1020/1M = 1.02ms. SOFT START and low output voltage (set at 70% of nominal output voltage) occur at the same time, the Hiccup mode op- The SC4603 implements its soft start by ramping up the eration (Point C to Point D) of the SC4603 is invoked error amplifier reference voltage providing a controlled and the internal soft start capacitor is discharged. This is slew rate of the output voltage, then preventing over- like a typical soft start cycle. .. shoot and limiting inrush current during its start up... Over Current Protection A Over current protection for the SC4603 is implemented B V O−nom by detecting the voltage drop of the high side P-MOSFET during conduction, also known as high side R detec- DS(ON) tion. This loss-less detection eliminates the sense resis- 0.6875⋅V 0.7 C tor and its loss. The overall efficiency is improved and O−nom the number of components and cost of the converter V are reduced. R sensing is by default inaccurate and O DS(ON) is mainly used to protect the power supply during a fault I MA D case. The over current trigger point will vary from unit to I O unit as the R of P-MOSFET varies. Even for the same DS(ON) unit, the over current trigger point will vary as the junc- tion temperature of P-MOSFET varies. The SC4603 pro- vides a built-in 50µA current source, which is combined with R (connected between V and I ) to determine SET CC SET Figure 1. Over current protection characteristic of the current limit threshold. The value of R can be prop- SET SC4603 erly selected according to the desired current limit point  2008 Semtech Corp. 8 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) ripple current to be within 15% to 30% of the maximum Power MOSFET Drivers output current. The inductor value can be determined according to its The SC4603 has two drivers for external complemen- tary power MOSFETs. The driver block consists of one operating point and the switching frequency as follows: high side P-MOSFET driver, PDRV, and one low side N- V ⋅(V − V ) out in out L = MOSFET driver, NDRV, which are optimized for driving V ⋅ f ⋅ ΔI⋅I in s OMAX external power MOSFETs in a synchronous buck con- Where: verter. The output drivers also have gate drive non-over- f = switching frequency and lap mechanism that gives a dead time between PDRV s ΔI = ratio of the peak to peak inductor current to the and NDRV transitions to avoid potential shoot through maximum output load current. problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, a 6A converter can The peak to peak inductor current is: be achieved. As shown in Figure 2, t the delay from d1, I = ΔI•I the P-MOSFET off to the N-MOSFET on is adaptive by p−p OMAX detecting the voltage of the phase node. t , the delay d2 from the N-MOSFET off to the P-MOSFET on is fixed, is After the required inductor value is selected, the proper 50ns for the SC4603. This control scheme guarantees selection of the core material is based on the peak in- avoiding the cross conduction or shoot through between ductor current and efficiency requirements. The core two MOSFETs and minimizes the conduction loss in the must be able to handle the peak inductor current I PEAK bottom diode for high efficiency applications. without saturation and produce low core loss during the high frequency operation. I PMOSFET Gate Drive p−p I = I + PEAK OMAX 2 NMOSFET Gate Drive The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should Ground Phase node be minimized to reduce inductor’s copper loss. The core loss can be found in the manufacturer’s datasheet. The t t d2 d1 inductor’s copper loss can be estimated as follows: 2 P = I ⋅R LRMS COPPER WINDING Figure 2. Timing Waveforms for Gate Drives and Phase Node Where: I is the RMS current in the inductor. This current can LRMS Inductor Selection be calculated as follows: The factors for selecting the inductor include its cost, 1 efficiency, size and EMI. For a typical SC4603 applica- 2 I = I ⋅ 1+ ⋅ ΔI LRMS OMAX 3 tion, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the in- ductor value will decrease the ripple level of the output Output Capacitor Selection voltage while the output transient response will be de- graded. Low value inductors offer small size and fast tran- Basically there are two major factors to consider in se- sient responses while they cause large ripple currents, lecting the type and quantity of the output capacitors. poor efficiencies and more output capacitance to smooth The first one is the required ESR (Equivalent Series Re- out the large ripple currents. The inductor should be able sistance) which should be low enough to reduce the volt- to handle the peak current without saturating and its age deviation from its nominal one during its load changes. copper resistance in the winding should be as low as The second one is the required capacitance, which should possible to minimize its resistive power loss. A good trade- be high enough to hold up the output voltage. Before the off among its size, loss and cost is to set the inductor SC4603 regulates the inductor current to a new value  2008 Semtech Corp. 9 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) during a load transient, the output capacitor delivers all Because the input capacitor is exposed to the large surge the additional current needed by the load. The ESR and current, attention is needed for the input capacitor. If ESL of the output capacitor, the loop parasitic inductance tantalum capacitors are used at the input side of the between the output capacitor and the load combined converter, one needs to ensure that the RMS and surge with inductor ripple current are all major contributors to ratings are not exceeded. For generic tantalum capaci- the output voltage ripple. Surface mount speciality poly- tors, it is wise to derate their voltage ratings at a ratio of mer aluminum electrolytic chip capacitors in UE series 2 to protect these input capacitors. from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. Power MOSFET Selection POSCAP from Sanyo is a solid electrolytic chip capacitor which has a low ESR and good performance for high fre- The SC4603 can drive a P-MOSFET at the high side and quency with a low profile and high capacitance. Above an N-MOSFET synchronous rectifier at the low side. The mentioned capacitors are recommended to use in use of the high side P-MOSFET eliminates the need for SC4603 applications. an external charge pump and simplifies the high side gate driver circuit. Input Capacitor Selection For the top MOSFET, its total power loss includes its con- duction loss, switching loss, gate charge loss, output ca- The input capacitor selection is based on its ripple cur- pacitance loss and the loss related to the reverse rent level, required capacitance and voltage rating. This recovery of the bottom diode, shown as follows: capacitor must be able to provide the ripple current by I ⋅ V ⋅ f 2 TOP _PEAK I s the switching actions. For the continuous conduction P = I TOP _RMS ⋅R + ⋅ TOP _ TOTAL TOP _ ON V GATE mode, the RMS value of the input capacitor can be cal- R G culated from: (Q + Q ) + Q ⋅ V ⋅ f + (Q + Q ) ⋅ V ⋅ f GD GS2 GT GATE s OSS rr I s V ⋅(V − V ) out in out I = I ⋅ CIN OMAX (RMS) 2 V in Where: R = gate drive resistor, G Q = the gate to drain charge of the top MOSFET, This current gives the capacitor’s power loss as follows: GD Q = the gate to source charge of the top MOSFET, 2 GS2 P = I ⋅R CIN(RMS) CIN CIN(ESR) Q = the total gate charge of the top MOSFET, GT Q = the output charge of the top MOSFET, and OSS This capacitor’s RMS loss can be a significant part of the Q = the reverse recovery charge of the bottom diode. rr total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly de- For the top MOSFET, it experiences high current and high pends on the input capacitor’s ESR and its capacitance voltage overlap during each on/off transition. But for the for a given load, input voltage and output voltage. As- bottom MOSFET, its switching voltage is the bottom suming that the input current of the converter is con- diode’s forward drop during its on/off transition. So the stant, the required input capacitance for a given voltage switching loss for the bottom MOSFET is negligible. Its ripple can be calculated by: total power loss can be determined by: 2 D ⋅(1− D) P = I ⋅R + Q ⋅ V ⋅ f + I _ ⋅ V BOT _RMS C = I ⋅ BOT _ TOTAL BOT _ ON GB GATE s D AVG F IN OMAX fs ⋅(ΔV −I ⋅R ) I OMAX CIN(ESR) Where: Where: Q = the total gate charge of the bottom MOSFET and GB D = V /V , duty ratio and V = the forward voltage drop of the bottom diode. O I F ΔV = the given input voltage ripple. I  2008 Semtech Corp. 10 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) For example, if V = 2.25V, the reference voltage, For a low voltage and high output current application such CC as the 3.3V/1.5V@6A case, the conduction loss is often V @2.25V = REF dominant and selecting low R MOSFETs will notice- DS(ON) ably improve the efficiency of the converter even though Vref @3.3V they give higher switching losses. + • V @ 3.3V Internal Reference REF 100 The gate charge loss portion of the top/bottom MOSFET’s Change @2.25V • V − 3.3V = CC total power loss is derived from the SC4603. This gate charge loss is based on certain operating conditions 500 (f , V , and I ). s GATE O 500 + • 0.1• 2.25 − 3.3 = 500.5(mV) 100 The thermal estimations have to be done for both 5 6 FS ISET MOSFETs to make sure that their junction temperatures 1 10 VCC PDRV L1 do not exceed their thermal ratings according to their Vout 2 7 SYNC PHASE total power losses P , ambient temperature T and their 3 9 COMP NDRV TOTAL A C9 4 8 VSENSE GND thermal resistances R as follows: θJA C2 C4 R C1 R7 SC4603 R8 R1 P TOTAL T < T + J(max) A R θJA R9 Loop Compensation Design: For a DC/DC converter, it is usually required that the Figure 3. Compensation network provides 3 poles and converter has a loop gain of a high cross-over frequency 2 zeros. for fast load response, high DC and low frequency gain For voltage mode step down applications as shown in for low steady state error, and enough phase margin for its operating stability. Often one can not have all these Figure 3, the power stage transfer function is: properties at the same time. The purpose of the loop s compensation is to arrange the poles and zeros of the 1+ 1 compensation network to meet the requirements for a R ⋅C C 4 specific application. G (s) = V VD IN L 2 1 1+ s + s L C 1 4 R The SC4603 has an internal error amplifier and requires the compensation network to connect among the COMP Where: pin and VSENSE pin, GND, and the output as shown in R = load resistance and R = C ’s ESR. Figure 3. The compensation network includes C1, C2, C 4 R1, R7, R8 and C9. R9 is used to program the output voltage according to: The compensation network will have the characteristic as follows: R 7 s s V = 0.5 ⋅(1+ ) OUT 1+ 1+ R 9 ω ω ω I Z1 Z2 G (s) = ⋅ ⋅ COMP s s As indicated in Internal Reference Change section, the s 1+ ⋅1+ ω ω internal reference voltage (measured at VSENSE pin) P1 P2 changes slightly if the input voltage of the SC4603 is away from 3.3V.  2008 Semtech Corp. 11 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) The compensated loop gain will be as given in Figure 4: Where 1 T ω = I ω R ⋅(C + C ) Z1 Loop gain T(s) ωo 7 1 2 ω Z2 -20dB/dec Gd 1 c ω ω = Z1 0dB R ⋅ C 1 2 p1 ω ωp2 1 ω = Z2 (R + R ) ⋅C 7 8 9 Power stage G (s) VD ω ESR C + C 1 2 -40dB/dec ω = P1 R ⋅C ⋅ C 1 1 2 1 ω = P2 R ⋅C 8 9 Figure 4. Asymptotic diagrams of power stage and its loop gain. After the compensation, the converter will have the following loop gain: Layout Guidelines T(s) = G ⋅G (s)⋅ G (s) = PWM COMP VD s In order to achieve optimal electrical, thermal and noise 1+ 1 s s 1 performance for high frequency converters, special at- ⋅ ω ⋅ V 1+ 1+ I IN V R ⋅C tention must be paid to the PCB layouts. The goal of lay- ω ω M Z1 Z2 C 4 ⋅ ⋅ ⋅ s s L out optimization is to identify the high di/dt loops and s 2 1+ ⋅1+ 1+ s + s LC ω ω R minimize them. The following guideline should be used to P1 P2 ensure proper functions of the converters. Where: G = PWM gain and PWM 1. A ground plane is recommended to minimize noises V = 1.0V, ramp peak to valley voltage of SC4603. M and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power compo- The design guidelines for the SC4603 applications are nents first. Arrange the power circuit to achieve a as following: clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if 1. Set the loop gain crossover corner frequency possible. ω for given switching corner frequency C 3. The V bypass capacitor should be placed next to CC ω =2 πf , S s the VCC and GND pins. 2. Place an integrator at the origin to increase DC 4. The trace connecting the feedback resistors to the and low frequency gains. output should be short, direct and far away from the 3. Select ω and ω such that they are placed Z1 Z2 noise sources such as switching node and switching near ω to damp the peaking and the loop gain O components. has a -20dB/dec rate to go across the 0dB 5. Minimize the traces between PDRV/NDRV and the line for obtaining a wide bandwidth. gates of the MOSFETs to reduce their impedance to 4. Cancel the zero from C ’s ESR by a compensa- 4 drive the MOSFETs. tor pole ω (ω = ω = 1/( R C )), P1 P1 ESR C 4 6. Minimize the loop including input capacitors, top/bot- 5. Place a high frequency compensator pole ωp 2 tom MOSFETs. This loop passes high di/dt current. (ωp = πpf ) to get the maximum attenuation of 2 s Make sure the trace width is wide enough to reduce the switching ripple and high frequency noise copper losses in this loop. with the adequate phase lag at ω . C 7. ISET and PHASE connections to P-MOSFET for cur- rent sensing must use Kelvin connections.  2008 Semtech Corp. 12 www.semtech.com SC4603 POWER MANAGEMENT Applications Information - (Cont.) Layout Guidelines (Cont.) 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the GND pin of the SC4603 by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible. Design Example 1: 3.3V to 1.5V @ 5A application with SC4603 (NH020 footprint). R15 Vin = 3.3V 1 R3 C14 C10 C11 M1 33n 22u 22u U1 RT 21k 5 6 FS ISET R6 4.7u C3 1 10 VCC PDRV L1 R2 1.0 Vo = 1.5V/5A 2 7 SYNC/SLEEPPHASE 1.1u 3.32k 3 9 COMP NDRV C9 C1 150p M2 C7 C4 4 8 VSENSE GND 820p R1 C2 R5 150u 22u R7 13k SC4603 R8 20k 820p 1.0 604 R9 6.49k Figure 5. Schematic for 3.3V/1.5V @ 5A application  2008 Semtech Corp. 13 www.semtech.com SC4603 POWER MANAGEMENT Bill of Materials - 3.3V to 1.5V @ 5A Iy temQe tRe eferenc Vr alu Part No./Manufacture 11CF 1 150p 21CF 2 820p 31CF 3 4.7u 41CF 7 1P 50u Panasonic. P/N: 6.3V, S 51CF 9 820p 63C0 10,C11,C42M 2uF, 121 TDK P/N: C3225X5R0J226 71CF 14 33n 81LH 1 1.1u 91M8 1 M5 OSFET P, S0- Fairchild P/N: FDS 637 11 0M8 2 MA OSFET N, S0- Fairchild P/N: FDS 6680 11 1Rk T 21 11 2Rk 1 20 11 3Rk 2 3.32 11 4Rk 7 13 11 5R4 8 60 12 6R1 5,R6 11 7R1 15 11 8Rk 3 2.94 11 9Rk 9 6.49 21 0U3 1 ST C460 Semtech P/N: SC4603IMSTR Key components: U1: SC4603, Semtech M1: FDS 6375, SO-8, Fairchild M2: FDS 6680A, SO-8, Fairchild L1: SMT power inductor, 1.1uH ETQP6F1R1H, Panasonic. Unless specified, all resistors and capacitors are in SMD 0603 package. Resistors are +/-1% and all capacitors are +/-20%  2008 Semtech Corp. 14 www.semtech.com SC4603 POWER MANAGEMENT PCB Layout - 3.3V to 1.5V @ 6A Top Bottom Top Bottom  2008 Semtech Corp. 15 www.semtech.com SC4603 POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS e INCHES MILLIMETERS DIM A MIN NOM MAX MIN NOM MAX D A - - .043 - - 1.10 N - - A1 .000 .006 0.00 0.15 - - A2 .030 .037 0.75 0.95 - - b .007 .011 0.17 0.27 2X E/2 c - - .003 .009 0.08 0.23 D .114 .118 .122 2.90 3.00 3.10 E1 E E1 .114 .118 .122 2.90 3.00 3.10 PIN 1 E .193 BSC 4.90 BSC INDICATOR e .020 BSC 0.50 BSC .016 .024 .032 0.40 0.60 0.80 L ccc C 12 (.037) (.95) L1 10 10 N 2X N/2 TIPS B - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .003 0.08 ccc .010 0.25 D aaa C H A2 A SEATING PLANE c A1 GAGE C PLANE bxN bbb C A-B D 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIMENSIONS DIM INCHES MILLIMETERS (.161) (4.10) C (C) G .098 2.50 G Z P .020 0.50 X .011 0.30 Y .063 1.60 Z .224 5.70 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2008 Semtech Corp. 16 www.semtech.com