SEMTECH SC4510

SC4510 High Performance Synchronous Buck Controller With Reference Tracking POWER MANAGEMENT Features Description The SC4510 can be configured as a synchronous buck u Synchronous buck operation with current sink or convertor capable of sourcing and sinking current from load source without loss of regulation without losing output regulation. The output can be set to u Output can track internal or external reference track an internal reference or an external voltage. The u Buffered reference output from external reference actual reference used by the error amplifier is buffered u Combi-Sense mode lossless current sensing and brought out as a reference. It is the ideal choice for u 2.5V to 16V operation with 4.75V minimum V CC externally referenced or tracking buck convertors such as u Direct drive for high side N-channel MOSFETs with those for DDR memory applications. diode and capacitor bootstrap The controller is also designed for point of use DC-DC u Undervoltage lockout, Soft Start, Enable and Power convertors with 2.5-16V power sources with a Vcc of 4.5V Good functions or higher. Soft start, current limit, programmable oscillator u Fast transient response with external compensation and external compensation functions are provided to u Current mode control with transconductance error ensure high degree of integration and low external amplifier component count. Semetch’s patented Combi-Sense™ u Programmable oscillator frequency with external sync technique is utilised for lossless current sening and maximising efficiency. Both high and low side MOSFET Applications drivers are built in and rated for substantial peak currents to minimise switching losses. The SC4510 is offered in a u Externally referenced buck convertors space saving TSSOP-20 package. u DDR memory terminators u Point of use power supplies Typical Application Circuit VIN 15V MAX Q1 C1 C2 D1 R1 RTN L1 VOUT C3 0.5V MIN Q2 C4 C5 R2 R3 C6 R4 C7 SYNC RTN R5 U1 SC4510 C8 R6 R7 PGOOD INT REF IN+ C9 REFOUT EXT REF C10 C11 C12 C13 United States Patent #6,441,597 www.semtech.com Revision: Jan 07, 2005 1 1 20 REF AGND 2 19 REFIN SYNC 3 18 REFOUT COMP 4 17 CS+ IN- 5 16 CS- ROSC 6 15 PGOOD SS/EN 7 14 AVCC VIN 8 13 PVCC VPN 9 12 GDL BST 10 11 PGND GDH SC4510 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Parameter Symbol Maximum Units BST, GDH to PGND -0.3 to 32 (steady state) V -0.3 to 40 (for < 10ns @ freq. < 500kHz) PVCC, AVCC, VIN, VPN, GDL to PGND -0.3 to 16 V PGND to AGND ±0.3 V CS+ to AGND -0.3 to AVCC V COMP, IN-, REFIN, REFOUT, ROSC, SS/EN to AGND -0.3 to 6 V REFIN and REFOUT to AGND 0 to 3.0 V GDH Source or Sink Current A + 0.75 GDL Source or Sink Current A + 1 Storage Temperature Range -60 to +150 °C Junction Temperature -40 to +125 °C Lead Temperature ( Soldering ) 10 Sec. 260 °C ESD Rating ( Human Body Model ) 2 kV Electrical Characteristics Unless specified: T = T = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V A J Parameter Symbol Test Conditions Min Typ Max Unit Power Supply Operating Current No load on GDL and GDH 8 12 mA Analog Supply Input AVCC VIN > 2.5V 4.75 16 V Drive Supply Input PVCC VIN > 2.5V 4.75 16 V Convertor Power Input VIN 2.5 16 V Undervoltage Lockout Start Threshold 4.2 4.5 4.7 V AVCC MIN UVLO Hysteresis 0.2 V AVCC HYST Soft Start and Shudown Charge Current 2 µA I SSCHG Discharge Current 1 µA I SSDIS Output Enable Threshold 2.0 V V ENTH Shutdown Threshold 0.6 V V SSTH ã 2004 Semtech Corp. 2 www.semtech.com SC4510 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = T = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V A J Parameter Symbol Test Conditions Min Typ Max Unit Error Amplifier Input Bias Current 0.4 0.7 mA Input Offset Voltage 2.5 mV Transconductance Gain -1 Output Source Mode 275 G mW M Output Sink Mode 375 (1) Unity Gain Bandwidth 3 MHz Output Sink/Source Current 15 mA V = 2.5V COMP Buffered Reference Internal reference -40C to +85C 0.49 0.5 0.51 V V REF Line regulation 5V < AVCC < 15V 0.02 %/V External reference input range 0.3 3.0 V V REFIN Tracking accuracy % + 0.5 V With respect to V REFOUT REFIN mV +10.0 (Greater of the two) Reference output current 5 mA I REFOUT Oscillator and Synchronisation Frequency range Fosc 0.1 1 MHz Frequency setting Fosc ROSC = 221K 270 300 330 KHz Sync input High voltage 1.5 V Sync input Low voltage 0.5 V Duty Cycle Maximum Duty Cycle Fosc = 1 MHz 70 % Fosc = 300 kHz 90 % Minimum Duty Cycle Fosc = 100 kHz 5 % Minimum pulse width Fosc = 0.1 to 1 MHz 250 nS Current Limit Current limit sense threshold Output source mode 60 75 90 mV V CSLIM Output sink mode -85 -110 -130 mV (1) Delay to Output 10 mV Overdrive 50 nS t CSDLY ã 2004 Semtech Corp. 3 www.semtech.com SC4510 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = T = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V A J Parameter Symbol Test Conditions Min Typ Max Unit Power Good Output Overvoltage sense threshold REFIN = 2.5V 2.8 V V OVTH Undervoltage sense threshold REFIN = 2.5V 2.2 V V UVTH Power Good voltage 1.5 V V I = 5 mA PG PG 0.4 V I = 2.5 mA PG Output under fault Output Drive High Side Gate Drive Source or sink 1 A I GDH Low Side Gate Drive Source or sink 1 A I GDL Dead Time Between Drives 60 90 120 nS Rise Time C = 1000 pF 20 nS OUT Fall Time C = 1000 pF 20 nS OUT Note: (1) Guaranteed by design. Not tested in production. Ordering Information Pin Configuration (1) Part Number Package Temp. Range (T ) J TOP VIEW SC4510ITSTR TSSOP-20 -40°C to +85°C (2) REF 1 20 AGND SC4510ITSTRT REFIN 2 19 SYNC Notes: REFOUT 3 18 COMP (1) Only available in tape and reel packaging. A reel contains 2500 devices. CS+ 4 17 IN- (2) Lead free product. This product is fully WEEE and RoHS CS- 5 16 ROSC compliant. PGOOD 6 15 SS/EN AVCC 7 14 VIN PVCC 8 13 VPN GDL 9 12 BST PGND 10 11 GDH (20 Pin TSSOP) ã 2004 Semtech Corp. 4 www.semtech.com SC4510 POWER MANAGEMENT Pin Descriptions Pin # Pin Name Pin Function 1 REF Internal 0.5V bandgap reference 2 REFIN Non inverting input of the error amplifier. Can be connected to REF pin or an external voltage such as VDDQ/2. Maximum input range is 3V 3 REFOUT Buffered reference output fro external use. Tracks the REFIN voltage 4 CS+ Current sense input +ve 5 CS- Current sense input -ve. Typically connected to the VOUT end of the output inductor. 6 PGOOD Power Good output signal. Open collector output goes low under fault and sinks up to 5 mA. 12% with respect to REFIN voltage. Monitors the output at thresholds of + 7 AVCC Supply voltage for internal analog circuits. 8 PVCC Supply voltage for output drivers. Bypass with a large ceramic capacitor to PGND. 9 GDL Gate drive output for the low side N-Channel MOSFET. 10 PGND Power ground for returning the drive currents. 11 GDH Gate drive output for the high side N-Channel MOSFET. 12 BST Boost capacitor connection for the high side gate drive. Connect an external capacitor and a diode as shown in the Typical Application Circuit. 13 VPN Virtual Phase Node. Auxiliary pin used for virtual current sense.Connect an RC between this pin and the VOUT end of the output inductor to sense the integrated current feedback signal. 14 VIN Input supply for the virtual current sense circuit. This should be at the same potential as the drain of the high side power MOSFET. 15 SS/EN Soft Start and Enable pin. Grounding the pin shuts down the controller. Connect a capacitor to soft start the output.The output will start switching when the SS pin voltage goes above 0.5V. 16 ROSC Connect a resistor to AGND to program the oscillator frequency. 17 IN- Inverting feedback input for the error amplifier. Follows the reference input provided at the REFIN pin. Maximum voltage range is 3V. 18 COMP Error amplifier output for compensation. 19 SYNC Pin for external synchronisation signal input 20 AGND Analog signal ground. Return the ground connections of noise sensitive components such as ROSC, soft start capacitor, sync signal, feedback resistor chain and feedback compensation components separately to this pin. ã 2004 Semtech Corp. 5 www.semtech.com SC4510 POWER MANAGEMENT Characteristic Curves AVCC vs Bias Current Operating Frequency vs ROSC 12 1000 11.5 900 800 11 700 10.5 600 10 500 9.5 400 9 300 8.5 200 8 100 4.5 5 6 7 8 9 10 11 12 13 14 15 0 100 200 300 400 500 600 700 ROSC in kOhm AVCC Typical Dmax vs Operating Frequency 100 95 90 85 80 75 70 100 250 400 550 700 850 1000 Operating Frequency kHz ã 2004 Semtech Corp. 6 www.semtech.com Ibias mA Typical Dmax % Freq in kHz SC4510 POWER MANAGEMENT Characteristic Curves Internal Reference vs Temperature Current Limit vs Temperature 500.50 74.50 74.00 500.00 73.50 499.50 73.00 72.50 499.00 72.00 498.50 71.50 498.00 71.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Temperature (°C) Frequency vs Temperature Max Duty Cycle vs Temperature @ ROSC = 220K @ ROSC = 220K 94.30 300.50 94.25 300.00 94.20 94.15 299.50 94.10 299.00 94.05 94.00 298.50 93.95 298.00 93.90 93.85 297.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Temperature (°C) ã 2004 Semtech Corp. 7 www.semtech.com Internal Ref. (mV) Max Duty Cycle (%) Frequency in kHz Current Limit (mV) SC4510 POWER MANAGEMENT Block Diagram  2004 Semtech Corp. 8 www.semtech.com SC4510 POWER MANAGEMENT Application Schematic ã 2004 Semtech Corp. 9 www.semtech.com SC4510 POWER MANAGEMENT Functional Description INTRODUCTION In tracking applications such as DDR memories an external reference may be brought in and applied at REFIN pin. The The SC4510 is designed to control and drive N-Channel range of applicable external voltage is up to 3V. The UV MOSFET synchronous rectified buck convertors. It has and OV sensing thresholds for PGOOD output are centered additional features such as reference tracking, buffered +12% around REFIN voltage. REFOUT that make it particularly attractive for tracking output applications such as DDR memories. It can operate The voltage at REFIN pin is buffered and put out as REFOUT. the convertor in both the source and sink modes. The This output tracks REFIN accurately within + 10 mV offset switching frequency is programmable to optimize design. or 0.5% of REFIN, whichever is higher. It can also source The current mode switching regulator section features up to 5 mA current. The REFOUT output is particularly useful Semtech’s patented Combi Sense technique for lossless in DDR memory termination applications. current sensing and provides a hiccup mode overcurrent OSCILLATOR protection. The switching frequency F of the SC4510 is set by an POWERING THE CONTROLLER OSC external resistor using the following formula: Supplies VIN, PVCC and AVCC from the input source are used to power the SC4510. The AVCC and PVCC can be R = 66,000 / F OSC OSC tied to VIN supply or can be from separate source to optimise efficiency. The AVCC supply provides the bias for R is in kW and F is in kHz. The nominal range for the the oscillator, PWM switcher, voltage feedback, current OSC OSC oscillator frequency is from 100 kHz to 1 MHz. The sense and the Power OK circuitry. PVCC is used to drive maximum duty cycle available at any given frequency is the low and high side MOSFET gates. Minimum operating limited by minimum pulse width requirement which is limit for VIN is 2.5V typical. However, PVCC and AVCC have typically 250 nS. This gives a typical Dmax of 70% at the higher UVLO limits as explained below. Maximum range highest frequency of 1 MHz or about 90% at 300 kHz. for all of the input and supply voltages is 16V. The oscillator can be synchronised to an external clock that STARTUP AND ENABLE is nominally faster than the internal frequency set by R OSC. Startup is inhibited until AVCC input reaches its UVLO The synchronising signal should be TTL compatible, with threshold . The UVLO limit is 4.5V typical. When AVCC is transitions above 2.0V and below 0.6V. The external voltage below the UVLO threshold, the soft start pin is pulled low level applied should be lower than AVCC of the device. and output drivers are turned off. The power up sequence GATE DRIVERS is initiated by a 2 uA current source charging the soft start capacitor connected to the SS pin. When the SS pin reaches The low side gate driver is supplied from PVCC and provides 0.5V, the convertor will start switching. The reference input a peak source/sink current of 1A. The high side gate drive of the error amplifier is ramped up with the soft-start signal. is capable of sourcing and sinking peak currents of 0.75A. The soft start duration is controlled by the value of the SS Protection logic provides a typical dead time of 90 nS to cap. The soft start pin also functions as an enabler with ensure both the upper and lower MOSFETs will not turn on TTL compatible input thresholds. If the SS/EN pin is pulled simultaneously and cause a shoot through condition. below 0.6V, the SC4510 is disabled and draws very low current. The high side Mosfet gate drive can be derived from the PVCC supply using the classical bootstrap technique as REFERENCE INPUT AND BUFFERED OUTPUT illustrated in the applications circuits. A bootstrap capacitor is connected from BST to the Phase node while PVCC is The SC4510 comes with a low level built in reference of connected through a low V Schottky or an ultrafast diode 0.5V. The non inverting input of the error amplifier is F to the BST. This will provide a gate to source voltage brought out to provide additional flexibility and output approximately equal to the (VCC - Vfwd). tracking functions. In the basic operation, the REF and REFIN pins may be shorted together and the output voltage feedback is provided at IN- pin. ã 2004 Semtech Corp. 10 www.semtech.com SC4510 POWER MANAGEMENT Functional Description Alternately if an external 12V supply is available it can be directly connected between BST and GND. The actual gate to source voltage of the upper Mosfet will then be approximately be equal to (12V - VIN). This technique is useful if the input voltage is 5V but a 12V supply is also available in the system. POWER GOOD MONITOR The PGOOD circuitry monitors the FB input of the convertor error amplifier. If the voltage on this input goes above +12% or below -12% of the REFIN voltage the PGOOD pin is pulled low. The PGOOD is an open drain output and can sink up to 5 mA. The PGOOD pin is held low during the startup sequence. ERROR AMPLIFIER The SC4510 is a current mode controller and operates by matching the peak of the sensed inductor current to the output of the voltage error amplifier. The error amplifier is transconductance type and should be compensated -1 accordingly. It has a transconductance gain of 275 mW in the source mode. Current is sensed losslessly by taking the weighted average of both the MOSFET drops and adding it to the DC voltage drop across the inductor. More information on this patented Combi Sense technique is provided in the next section. Current mode controllers are inherently unstable at duty ratios above 50% and need some form of slope compensation to operate correctly. This slope compensation is built into the architecture of SC4510 where a portion of the ramp is internally added to the current sense signal. The amount of added ramp is optimised and varies with the operating duty cycle. Larger duty ratios result in larger ramps being added to the current sense signal. Note that the uncorrected current signal is used for overcurrent comparator. The current limit point is unaffected by the slope compensation. ã 2004 Semtech Corp. 11 www.semtech.com SC4510 POWER MANAGEMENT Application Information COMBI-SENSE OPERATION AND CURRENT LIMIT When Q1/Q3 turn OFF and Q2/Q4 turn ON, the equivalent circuit of Fig.1 becomes the sub-circuit as shown in Fig. Effective current sensing is important for the current mode 2b). Where Rds2 is the channel resistance of the bottom control of power convertors. Instead of using the traditional MOSFET. In this case, the branch {R ,C } is in parallel with s s lossy resistive current sense scheme, a novel lossless {(Rds2+RL), L} and V =(Rds2+RL)I . Cs o Combi-Sense technique is used in SC4510. This SEMTECH proprietary technology has the advantages of 1) lossless current sensing, Vin Rds1 2) bigger signal-to-noise ratio, and iL(t) L RL 3) thermal run-away prevention. PN Cin Rs Cs The basic structure of the Combi-Sense is shown in Fig.1. Where R is the equivalent resistance of the output inductor. Vo L VPN Cout Rload The added R and C form the RC branch in “parallel” with s s vC(t) the output inductor for inductor current sensing. This branch works with a small signal totem pole (Q3 and Q4) integrated in SC4510 in order to improve the signal-to-noise ratio. The base signals Vbe3 and Vbe4 are designed to Fig.2 a) Equivalent sub-circuit. closely follow the gate signals Vgs1 and Vgs2, respectively. Ideally, the leading and falling edges of the Virtual Phase When averaged over a complete cycle, Node (VPN) follow that of the Phase Node (PH) when Q1~Q4 V = [D(Rds1+RL)+(1-D)(Rds2+RL)] I switch in perfect synchronism. Cs o = [D Rds1+(1-D)Rds2+RL]I o Vin = R I . eq o Q1 Vgs1 D is the operating duty ratio. It is noted that the average iL(t) L RL PN DC value in V is independent of the value of L, R and C . Cin Cs s s Rs Cs If only the average load current information is needed (such Vo Q2 Cout Rload as in average current mode control), this current sensing vC(t) Vgs2 method is effective without further requirements. Vbe3 Q3 VPN Vin Q4 Vbe4 iL(t) L RL PN Cin Rs Cs Fig.1 The Basic Structure of Combi-Sense. Vo VPN Rds2 Cout Rload When Q1/Q3 turn ON and Q2/Q4 turn OFF, the equivalent vC(t) circuit of Fig.1 is shown in Fig. 2a). Where, Rds1 is the on- resistance of the top MOSFET. The two branches, consisting of {(Rds1+RL), L} and {R , C }, are in parallel. The DC voltage s S drop (Rds1+RL)I equals V . In this way, the output current o Cs is sensed from V when (Rds1+RL) is known. Cs Fig.2 b) Equivalent sub-circuit. ã 2004 Semtech Corp. 12 www.semtech.com SC4510 POWER MANAGEMENT Application Information (Contd.) In peak current mode control as in SC4510, the voltage In the application circuit, R =5.6 mW. However the peak eq ripple on C is critical for PWM operation. In fact, the peak- value of the sensed current is not exact for a number of s to-peak value of the voltage ripple across V (denoted as reasons. Though the Phase Node PH and Virtual Phase Cs DV ) directly affects the signal-to-noise ratio of the PWM Cs Node VPN voltages are assumed to be identical, there will operation. In general, smaller DV leads to small signal-to- Cs be some offset between them which adds to the average noise ratio and more noise sensitive operation. Larger DV Cs value of the current feedback signal. This is particularly leads to more circuit (power stage) parameter sensitive true during the switching transitions where rise and fall operation. A good engineering compromise is to make times of the true Phase Node are dependent on the power MOSFET characteristics. The peak value of the signal also DV ~R D I . Cs eq o includes the ripple current D I riding on the output DC o current. In addition, the signal level is subject to variations Where D I is the peak to peak ripple current in the inductor. o with respect to input and PVCC voltages. The difference The prerequisite for such relation is the so called time between sensed current magnitude and the actual current constant matching condition gets more pronounced for low output voltages where the L operating duty is also low. » R C . s s R eq Given these differences, some amount of scaling the current sense signal is required to adjust the current limit When Rds1 = Rds2, the above approximations become in most applications. This can be accomplished easily by precise equalities. For the example in the Application Circuit simple resistor networks and the possible configurations shown on p9 the inductor value is 1 uH, are shown in Fig.3. RL= 1.4 mW , Rds1 = 11 mW and Rds2 = 3 mW a) When the required current limit value I is greater than LM I , remove R and solve for for R = R and Since the operating duty ratio is very small the effective LMcp s3 s2 seq Rds is determined mostly by Rds2. The time constant R C s s L should be set close to 0.2 mS. Since the effective value of R C = seq s R R is 20 kW // 18 kW = 9.5 kW, C = 22 nF was chosen . eq s s R is the parallel combination of R and R as shown in CURRENT LIMIT SCALING seq s s1 Fig 3). R helps to reduce the offset at the input of current s2 In SC4510, the current limiting is performed on cycle-by- sense amplifier inside SC4510. cycle basis. When the voltage difference between CS+ and CS- exceeds 65 mV, the top MOSFET duty ratio is clipped Vin in order to limit the output source current. Similarly, when Q1 Vgs1 the voltage difference between CS- and CS+ exceeds 113 iL(t) L RL PN mV, the bottom MOSFET duty ratio is clipped in order to Cin Rs Rs1 Vo limit the sink current. For the configuration in Fig.1, the Q2 Cs Cout Rload convertor output current limit is set around Vgs2 vC(t) 75 mV I = , Vbe3 Q3 LMcp R VPN eq Vbe4 Q4 for the current sourcing mode and 1 + Rs2 110 mV 2 - ISEN I = - LMcn Rs3 R eq for the current sinking mode. Fig.3 Current limit scaling. ã 2004 Semtech Corp. 13 www.semtech.com SC4510 POWER MANAGEMENT Application Information (Contd.) For simplicity R can be omitted and the current limit can a) The time it takes to discharge the capacitor from 3.4V to s2 be estimated from 0.4V R + R s s1 I R = 75 mV ´ (3.4 - 0.4)V LM eq R t = C ´ . s1 ssf SS 1mA In the application circuit the current feedback signal had to be halved to account for variations explained above and ensure that the current limit is at least 20% above nominal In the application circuit, C = 47 nF and t is calculated SS ssf at minimum input. as 140 mS. b) The time interval of the soft start process from 0.4V to b) When the required current limit value I is less than LM 3.4V I remove R solve LMcp s1 (3.4 - 0.4) V t = C ´ . L ssr SS R C = 2 mA s s R eq for R and solve s When C = 47 nF, t is calculated as 70 mS. SS ssr R s I R + V = 75 mV LM eq o Notice that during the soft start process, the convertor only R s3 starts switching when the voltage at SS/EN exceeds 1.3V. to set the current limit. Then, Similar steps and equations apply to the current limit setting c) The effective operation time interval and scaling for current sinking mode. (3.4 - 1.3) V OVERCURRENT PROTECTION AND HICCUP MODE t = C ´ . sso SS 2 mA In addition to the current limit capabilty, SC4510 provides overcurrent protection in case the convertor output is shorted to ground. If this fault condition happens, the This is the interval where the gate drive outputs are active controller senses the output voltage via voltage feedback and current builds up in the inductor. pin IN-. When the sensed voltage is below 70% of the The effective inductor current is then normal feedback voltage, the controller shuts down both top and bottom MOSFETs. At the same time, a current sink t of 1 mA discharges the soft start capacitor C connected sso SS I = I . Leff LMcp to the SS/EN pin. t + t ssf ssr When the capacitor is discharged until its voltage reaches 0.4V, the controller initiates the soft start process. If the It turns out that ILeff is independent of the soft start short circuit fault persists, the controller shuts down the capacitor value and is determined as 0.3I . This should LMcp convertor again when the voltage across the soft start lead to a reasonable thermal condition in the convertor capacitor reaches 3.4V. This hiccup process repeats until hiccup operation. Note that ILeff calculated is not the true the fault condition is removed. Under this situation, it is average value of the inductor current since the convertor important to make sure that the convertor does not fail. is still in the soft start mode during the tsso interval. One important parameter is the convertor thermal condition which is directly related to the effective inductor and MOSFETs current. The effective currents in inductor and MOSFETs can be estimated using the following equations. ã 2004 Semtech Corp. 14 www.semtech.com SC4510 POWER MANAGEMENT Application Information (Contd.) PCB LAYOUT FOR SC4510 5) The SC4510 is best placed over a quiet ground plane area. Avoid pulse currents of the Cin, Q , Q loop flowing in T B Careful attention to layout requirements is necessary for this area. This analog ground plane should be connected successful implementation of the SC4510 PWM controller. to the power ground plane at a “quiet” point near the input High switching currents with fast rise and fall times are capacitor. Under no circumstance should it be returned to present in the application and their effect on ground plane a point inside the Cin, Q , Q , Cout power ground loops. T B voltage differentials must be understood and minimized. A good layout with minimum parasitic loop areas will 6) The SC4510 AGND pin is connected to the separate analog ground plane with minimum lead length . All analog a) reduce EMI grounding paths including decoupling capacitors, feedback resistors, compensation components, soft start capacitor, b) lower ground injection currents, resulting in electrically frequency and current-limit setting resistors should be “cleaner” grounds for the rest of the system and connected to the same plane. c) minimize source ringing, resulting in more reliable gate 7) Locate the critical filtering capacitors as close as possible switching signals. to their respective device. This is particularly true for the LAYOUT GUIDELINES current feedback filtering capacitor connected between CS+ and CS-. A high value ceramic capacitor is also In the following Q and Q denote the high side and low T B recommended between PVCC and PGND pins close to the side MOSFETs respectively. device. 1) A ground plane should be used. The number and position of ground plane interruptions should be minimised so as not to compromise ground plane integrity. Isolated or semi- isolated areas of the ground plane may be deliberately introduced to constrain ground currents into particular paths, such as the output capacitor or the Q source. B 2) The high power, high current parts of the circuit should be laid out first. The on time loop formed by the input capacitor Cin, the high side FET Q the output inductor and T, the output capacitor bank Cout must be kept as small as possible. Another loop area to minimise is formed by low side FET Q the output inductor and the output capacitor B, bank Cout during the off period. These loops contain all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. 3) The connection between the junction of Q , Q and the T B output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. The top FET gate charge currents flow in this trace. 4) The output capacitor Cout should be located as close to the load terminals as possible. Fast transient load currents are supplied by Cout and connections between Cout and the load must be kept short with wide copper areas to minimize inductance and resistance. This will improve the transient response to step loads. ã 2004 Semtech Corp. 15 www.semtech.com SC4510 POWER MANAGEMENT Outline Drawing - TSSOP-20 DIMENSIONS A INCHES MILLIMETERS DIM D e MIN NOM MAX MIN NOM MAX A - - .047 - - 1.20 N - - A1 .002 .006 0.05 0.15 A2 .031 - .042 0.80 - 1.05 2X E/2 - - b .007 .012 0.19 0.30 c - - .003 .007 0.09 0.20 D .251 .255 .259 6.40 6.50 6.60 E1 E E1 .169 .173 .177 4.30 4.40 4.50 PIN 1 E .252 BSC 6.40 BSC INDICATOR e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 ccc C 1 2 3 L1 (.039) (1.0) e/2 N 20 20 2X N/2 TIPS - - 01 0° 8° 0° 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AC. Land Pattern - TSSOP-20 X DIMENSIONS DIM INCHES MILLIMETERS (.222) (5.65) C G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 ã 2004 Semtech Corp. 16 www.semtech.com