SEMTECH SC4508A

SC4508A Buck or Buck-Boost (Inverting) Current Mode Controller POWER MANAGEMENT Features Description The SC4508A is a low voltage current mode switching ‹ Wide input voltage range 2.7V to 15V regulator controller that drives a P-channel power ‹ Programmable output voltage MOSFET with programmable switching frequency. It can ‹ Programmable switching frequency up to 1.5MHz be configured in either buck or buck boost (inverting) con- ‹ Buck or buck boost (inverting) configuration verters. The converters can be operated from 2.7V to ‹ Current mode control with slope compensation 15V input voltage range. The typical operating supply ‹ Very low quiescent current in shutdown mode current is 3mA and a shutdown pin allows the user to ‹ Accessible reference voltage turn the controller off reducing it to less than 200µA. ‹ Hiccup mode after 32 cycle-by-cycle OCP The output voltage can adjusted by external resistor di- ‹ 4mm x 4mm MLPQ-12 lead free package. This vider. The switching frequency is programmable up to product is fully WEEE and RoHS compliant 1.5MHz, allowing small inductor and capacitor values to minimize PCB space. The operating current level is pro- Applications grammable via an external sense resistor. Accessible ref- erence voltage allows users to make output voltage as ‹ Low power point of use converters low as they want. ‹ Single or multiple output low power converters ‹ Positive and/or negative output voltage ‹ DSL cards ‹ Graphic cards ‹ I/O cards ‹ Negative bias supplies Typical Application Circuits Vin Vin V+ V+ VREF VREF FB+ CS SC4508A FB- CS FB+ SC4508A OUT FB- COMP OUT COMP Vout Vout SS/EN GND OSC SS/EN GND OSC 1 www.semtech.com Revision: July 25, 2007 SC4508A POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit VDD to GND -V 0.3 to 16 (1) SS/EN to GND 3V .2 FB+, FB-, COMP, OSC to GND 5V VREF Current 1A m Thermal Resistance, Junction to Ambient 4W 8 °C/ θ JA Thermal Resistance, Junction to Case θ 3W °C/ JC ST torage Temperature Range -C 60 to +150 ° STG JT unction Temperature Range -C 40 to +150 ° J PT eak IR Reflow Temperature 10 - 40s 2C 60 ° PKG Note: (1) Voltage from internal circuitry could be higher than 3.2V. See Application Information, Soft-Start section. Electrical Characteristics Unless specified: V = 12V, V = V , V = 0, OUT = open, C = 1uF, C = 0.1uF, C = 330pF. T = T = -40°C to 125°C DD FB+ REF FB- VDD SS/EN OSC A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni PowerSupply Input Voltage Range 25 .7 1V Qw uiescent Current S0 S/EN = lo 20 0 5A 0 µ Od perating CurrentS3 S/EN = high, No loa mA Undervoltage Lockout SV tart Threshold r5 ising 25 .3 25 . 2V .5 DD UVLO Hysteresis 1V 00 m Oscillator Frequency Range 10 00 1z 50 KH Frequency 40 50 50 0 5z 5 KH Charge Current 1A 00 µ ErrorAmplifier Feedback Input Voltage -7 0.2 0V . Offset Voltage 2V m Input Bias Current 10 00 3A 0 n Transconductance 5S m Output Source or Sink Current 50 01A 0 µ www.semtech.com  2007 Semtech Corp. 2 SC4508A POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 12V, V = V , V = 0, OUT = open, C = 1uF, C = 0.1uF, C = 330pF. T = T = -40°C to 125°C DD FB+ REF FB- VDD SS/EN OSC A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni PWMComparator Mz aximum Duty CycleC7 = 1.5nF, 100kH 9% C5 = 100pF, 1.5MHz 9% Minimum On Time 2S 00 n Slope Compensation 6s 3 mV/T Delay to Output 5s 0 n VREF Reference Output Voltage 05 .4925 05 . 0V .507 OT utput Voltage = 25°C, V=6 5V 05 .49 04 . 0V .50 A DD Output Current 1A m LV ine Regulation = 2.7 to 15V, I=5 1mA 1V0 m DD VREF LV oad Regulation = 5V, I=2 0 to 1mA 4 mV DD VREF SoftStart/Enable/Shutdown CV harge Current >0 0.9V 2A µ SS/EN V<0 0.9V 1 SS/EN Discharge Current 1A 2 m Enable Logic Voltage 2V SHDN Logic Voltage 0V .35 CurrentLimit CV ycle by Cycle Threshold =0 5V 9010 1 1V 3 m DD Consecutive Overcurrent 32 Clock Cycles before Auto Restart Shutdown Delay to Output 5S 0 n Output Gate Drive On-Resistance(H) 8m Oh Gate Drive On-Resistance(L) 8m Oh GV ate Drive On-Resistance(H) =5 5V 1m Oh DD GV ate Drive On-Resistance(L) =5 5V 1m Oh DD RC ise Time =0 1000pF 2S n OUT FC all Time =0 1000pF 2S n OUT  2007 Semtech Corp. 3 www.semtech.com SC4508A POWER MANAGEMENT Pin Configuration Ordering Information (1) Pe artNumber Packag TOP VIEW (2) SC4508AMLTRT MLPQ -12 VDD OSC COMP Sd C4508ABUCKEVB Evaluation Boar Sd C4508ABUCK-BOOSTEVB Evaluation Boar 12 11 10 Notes: OUT 1 9 FB+ (1) Only available in tape and reel packaging. A reel contains 3000 devices. CS 2 8 FB- (2) Lead free product. This product is fully WEEE and RoHS compliant. SS/EN 3 7 PGND 4 5 6 VREF NC AGND (MLPQ - 12, 4mm x 4mm) Pin Descriptions Pe in # Pn in Nam Pin Functio 1T OU Gate driver output for external P-MOSFET. OUT swings from VDD to PGND. 2S C Current sense input pin. Connect a current sense resistor between VDD and CS. 3N SS/E Soft start pin. Connects an external capacitor between this pin and AGND. The ramp up time is defined by the capacitor. The device goes into shutdown when VSS/EN is pulled below 0.25V. 4F VRE 0.5V reference output. VREF can source up to 1mA. Bypass with a 0.1uF ceramic capacitor from VREF to AGND. 5CN. No connection 6DA. GN Analog ground 7DP. GN Power ground 8-F. B Error amplifier inverting input 9+F. B Error amplifier non-inverting input 1P 0 COM Compensation pin for internal transconductance error amplifier. Connect loop compensation network from COMP to AGND. 1C 1 OS Oscillator frequency set input. Connect a ceramic capacitor from OSC to AGND to set the internal oscillator frequency from 100KHz to 1.5MHz. Use equation to set the 100µA f = oscillator frequency. C is the capacitor from OSC to AGND. C • 0.65 1D 2 VD Supply voltage. Bypass a 1uF ceramic capacitor from VDD to PGND. THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected PAD internally. www.semtech.com  2007 Semtech Corp. 4 SC4508A POWER MANAGEMENT Block Diagram Marking Information Top View yyww = Date Code (Example: 0012)  2007 Semtech Corp. 5 www.semtech.com SC4508A POWER MANAGEMENT Application Information operating up to 1.5 MHz. It is necessary to consider the The SC4508A is designed to control buck (step down) or operating duty-ratio before deciding the switching buck-boost (inverting) converter with P-channel MOSFET frequency. as a switch using current mode, programmable switching frequency architecture. During steady state operation, Minimum Switch On Time Consideration the switch is turned on each cycle and turned off when the voltage across current sense resistor exceeds the In the SC4508A the falling edge of the clock turns on voltage level at COMP pin set by voltage loop error the MOSFET. The inductor current and the sensed voltage amplifier. A fixed 0.5V artificial ramp is added internally ramp up. After the sensed voltage crosses a threshold to the amplified current signal for operations when duty- determined by the error amplifier output, the MOSFET is cycle is larger than 50%. In over load or output shortage turned off. The propagation delay time from the turn-on condition, if the sensed current signal reaches typical of the controlling MOSFET to its turn-off is the minimum 100mV, the switch is turned off immediately in the same switch on time. The SC4508A has a minimum on time of cycle. If the sensed current signal continues up to 32 about 180ns at room temperature. This is the shortest cycles, not only the switch is turned off but also the soft on interval of the controlling PFET. The controller either start capacitor is discharged by a internal MOSFET to does not turn on the MOSFET at all or turns it on for at ground then charging back to threshold 1.4V during which least 80ns. the switch is held off. With the “hiccup” mode over For a buck converter, the operating duty cycle is V /V . O IN current protection, the thermal stress is reduced in the So the required on time for the MOSFET is V /(V fs). If O IN faulty conditions. the frequency is set such that the required pulse width is less than 180ns, then the converter will start skipping Frequency Setting cycles. Due to minimum on time limitation, simultaneously operating at very high switching frequency and very short The switching frequency in the SC4508A is user- duty cycle is not practical. If the voltage conversion ratio programmable. The advantages of using constant V /V and hence the required duty cycle is higher, the frequency operation are simple passive component O IN switching frequency can be increased to reduce the sizes selection and ease of feedback compensation. Before of passive components. setting the operating frequency, the following trade-offs There will not be enough modulation headroom if the on should be considered. time is simply made equal to the minimum on time of the SC4508A. For ease of control, we recommend the 1) Passive component size required pulse width to be at least 1.5 times the minimum 2) Circuitry efficiency on time. 3) EMI condition 4) Minimum switch on time and Current Sense and Current Limit 5) Maximum duty ratio The SC4508A senses peak inductor current by a current For a given output power, the sizes of the passive sense resistor. The sensed voltage is referenced to VDD components are inversely proportional to the switching and the typical current limit threshold is 100mV. The frequency, whereas MOSFET’s/Diodes switching losses current sense resistor can be calculated by the following are proportional to the operating frequency. Other issues equation assuming the current limit is 20% above peak such as heat dissipation, packaging and the cost issues incuctor current: are also to be considered. The frequency bands for signal transmission should be avoided because of EM 100mV Rs = interference. 120% •I (pk) L The free-running frequency of the internal oscillator can be programmed with an external capacitor from the OSC 1 V − V V + V IN O O D I + ( ) I (pk) = O for Buck pin to the ground. The SC4508A controller is capable of L 2 f •L V + V s IN D www.semtech.com  2007 Semtech Corp. 6 SC4508A POWER MANAGEMENT Application Information (Cont.) undergoes soft-start. If overload persists, the SC4508A will undergo repetitive auto-shutdown-restart hiccup mode. V + V + V V + V 1 V IN O D O D IN I (pk) = I + ( ) L O V 2 f •L V + V + V IN s IN O D In normal operation, the VREF voltage follows the SS/ for Buck − Boost EN voltage from 0 to 0.5V as the SS/EN voltage ramps up from 1.4V to 1.9V. After the SS/EN voltage rises I - full load current above 1.9V, it settles at final value depending upon VDD. O V - output voltage If VDD higher than 7V, it is clamped around 6.8V. In the O V - input voltage worst case, the clamped voltage is about 10V. Therefore, IN V - diode forward voltage drop the external soft-start capacitor should be rated at least D f - switching frequency 16V. S L - inductor The SS/EN pin can also be used as the enable input. The Error Amplifier MOSFET will be turned off if the SS/EN pin is pulled below 0.5V. The error amplifier in the SC4508A is a transconductance error amplifier, which is easily configured as a type two Converter Specifications compensator by connecting compensation network from the COMP pin to AGND. The output voltage of the error Buck or buck-boost converter design includes the amplifier is compared to the sensed current signal following specifications: (amplified by gain 8) plus internal 500mV ramp to generate Input voltage range: ∈ V [V ,V ] in in,min in,max duty cycle. Input voltage ripple (peak-to-peak): DV in Both the non-inverting and the inverting inputs of the Output voltage: V o error amplifier are brought out as device pins so that a Output voltage accuracy: e Output voltage ripple (peak-to-peak): DV converter can be configured as either buck or buck-boost o converter. Nominal output (load) current: I o Maximum output current limit: I o,max Soft-Start and Overload Protection Output (load) current transient slew rate: dI (A/s) o Circuit efficiency: h The undervoltage lockout circuit discharges the SS/EN capacitors. After V rises above 2.5V, the SS/EN Selection criteria and design procedures for the DD capacitors are slowly charged by internal 10uA current following are described. source. As the SS/EN capacitor continues to be charged, 1) output inductor (L) type and value the VREF and the COMP voltage follows. The converter 2) output capacitor (C ) type and value o 3) input capacitor (C ) type and value gradually delivers increasing power to the output. The in inductor current follows the COMP voltage envelope until 4) power MOSFETs the output goes into regulation. 5) current sensing and limiting circuit 6) voltage sensing circuit After the SS/EN capacitor is charged above 1.4V (high 7) loop compensation network enough for the error amplifier to provide full load current), the overload detection circuit is activated. If the CS pin Inductor (L) and Ripple Current senses 32 consective switching cycles of over current, the SC4508A will shut down and hold off the MOSFET The output inductor selection/design is based on the while discharging the soft-start capacitor. The SS/EN output DC and transient requirements. Both output capacitor is discharged with an internal 12mA current current and voltage ripples are reduced with larger sink. The overload latch is reset when the SS/EN capacitor inductors but it takes longer to change the inductor is discharged below 0.5V. The SS/EN capacitor is then current during load transients. Conversely smaller recharged with the 10µA current source and the converter inductors results in lower DC copper losses but the AC  2007 Semtech Corp. 7 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) Co core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple- Lesl current is 20% to 30% of the rated output load current or the inductor DC current. Assuming that the inductor current ripple (peak-to-peak) value is ΔI = *Idc, the δ L Resr inductance value will then be: V − V V + V IN O O D for Buck L = ( ) Figure 1. An equivalent circuit of C o f • ΔI V + V s L IN D If the current through the branch is i (t), the voltage b V + V across the terminals will then be: V O D IN for Buck-Boost L = ( ) f • ΔI V + V + V t s L IN O D 1 di (t) b v (t) = V + i (t)dt + L + R i (t) o o b esl esr b ∫ C dt o 0 The peak current in the inductor becomes (1+δ/2)*Idc and the RMS current is: This basic equation illustrates the effect of ESR, ESL and C on the output voltage. 2 o δ I = I 1+ L,rms dc 12 The first term is the DC voltage across C at time t=0. o The second term is the voltage variation caused by the The Idc is the inductor average or DC current. charge balance between the load and the converter The following are to be considered when choosing output. The third term is voltage ripple due to ESL and inductors: the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the a) Inductor core material: For high efficiency applications last three terms. above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores Since the inductor current is a triangular waveform in can be used for cost sensitive-applications below 350KHz buck configuration with peak-to-peak value δ*I , the o but with attendant higher core losses. ripple-voltage caused by inductor current ripples is: b) Select inductance value: Sometimes the calculated δI o inductance value is not available off-the-shelf. The Δv ≈ C 8C f o s designer can choose the adjacent (larger) standard the ripple-voltage due to ESL is: inductance value. The inductance varies with temperature and DC current. It is a good engineering δ I o Δv = L f ESL esl s practice to re-evaluate the resultant current ripple at D the rated DC output current. c) Current rating: The saturation current of the inductor and the ESR ripple-voltage is: should be at least 1.5 times of the peak inductor current under all conditions. Δv = R δI ESR esr o Output Capacitor (C ) and V Ripple o out Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low The output capacitor provides output current filtering in ESL’s. The ESR has the dominant effect on the output steady state and serves as a reservoir during load ripple voltage. It is therefore very important to minimize transient. The output capacitor can be modeled as an the ESR. ideal capacitor in series with its parasitic ESR (R ) and esr ESL (L ) (Figure 1). esl www.semtech.com  2007 Semtech Corp. 8 SC4508A POWER MANAGEMENT the following remarks are made to clarify some practical Application Information (Cont.) issues. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be Remark 1: High frequency ceramic capacitors may not considered. To keep the steady state output ripple-voltage carry most of the ripple current. It also depends on the < ΔV , the ESR should satisfy: o capacitor value. Only when the capacitor value is set ΔV o properly, the effect of ceramic capacitor low ESR starts R < esr1 δI to be significant. o For example, if a 10µF, 4mΩ ceramic capacitor is To limit the dynamic output voltage overshoot/ connected in parallel with 2x1500µF, 90mΩ electrolytic undershoot within α (say 3%) of the steady state output capacitors, the ripple current in the ceramic capacitor is voltage) from no load to full load, the ESR value should only about 42% of the current in the electrolytic satisfy: capacitors at the ripple frequency. If a 100µF, 2mΩ αV o R < ceramic capacitor is used, the ripple current in the esr2 I o ceramic capacitor will be about 4.2 times of that in the Then, the required ESR value of the output capacitors electrolytic capacitors. When two 100µF, 2mΩ ceramic should be: capacitors are used, the current ratio increases to 8.3. R = min{R ,R } In this case most of the ripple current flows in the esr esr1 esr2 ceramic decoupling capacitor. The ESR of the ceramic The voltage rating of aluminum capacitors should be at capacitors will then determine the output ripple-voltage. least 1.5V . The RMS current ripple rating should also o be greater than: Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. δI o The total equivalent ESR is not simply the parallel 2 3 combination of all the individual ESRs either. Instead they Usually it is necessary to have several capacitors of the should be calculated using the following formulae. same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/ 2 2 2 2 2 (R + R ) ω C C + (C + C ) discharge should be an order of magnitude smaller than 1a 1b 1a 1b 1a 1b C (ω) := eq 2 2 2 the voltage ripple caused by the ESR. To guarantee this, (R C + R C )ω C C + (C + C ) 1a 1a 1b 1b 1a 1b 1a 1b the capacitance should satisfy: 10 2 2 2 2 2 C > R R (R + R )ω C C + (R C + R C ) o 1a 1b 1a 1b 1a 1b 1b 1b 1a 1a R (ω) := 2πf R s esr eq 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b Buck-boost converter has higher ripple current than buck in output. The RMS value is the most important factor to where R and C are the ESR and capacitance of 1a 1a consider. It has to be less than the output capacitor ripple electrolytic capacitors, and R and C are the ESR and 1b 1b current rating. capacitance of the ceramic capacitors respectively. The buck-boost output capacitor RMS current is: (Figure 2) V + V O d I ≈ I RMS _ CAP O V IN Δv = R ⋅I ESR esr d C1a C1b Ceq where, V and I are rectifier forward voltage and current. d d R1a R1b Req In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, Figure 2. Equivalent RC branch.  2007 Semtech Corp. 9 www.semtech.com SC4508A POWER MANAGEMENT It can be seen that the current in the input capacitor Application Information (Cont.) pulses with high di/dt. Capacitors with low ESL should be Req and Ceq are both functions of frequency. For rigorous used. It is also important to place the input capacitor design, the equivalent ESR should be evaluated at the close to the MOSFETs on the PC board to reduce trace ripple frequency for voltage ripple calculation when both inductances around the pulse current loop. ceramic and electrolytic capacitors are used. If R = R 1a 1b = R and C = C = C , then R and C will be frequency- 1 1a 1b 1 eq eq The RMS value of the capacitor current is approximately independent and 2 R = 1/2 R and C = 2C δ D D 2 eq 1 eq 1 I = I D[(1+ )(1− ) + (1− D)] Cin o 2 12 η η Input Capacitor (C ) in The power dissipated in the input capacitors is then: The input supply to the converter usually comes from a 2 P = I R Cin Cin esr pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the For reliable operation, the maximum power dissipation switching frequency. A simple buck converter is shown in o in the capacitors should not result in more than 10 C of Figure 3. temperature rise. Many manufacturers specify the maximum allowable ripple current (RMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is: Figure 3. A simple model for the converter input δ Δv = R (1+ )I ESR esr dc 2 In Figure 3 the DC input voltage source has an internal The peak-to-peak input voltage ripple due to the capacitor impedance R and the input capacitor C has an ESR of is: in in R . MOSFET and input capacitor current waveforms, ESR esr DI dc voltage ripple and input voltage ripple are shown in Figure Δv ≈ C C f in s 4. From these two expressions, C can be found to meet IN the input voltage ripple specification. Power MOSFETs Selection Main considerations in selecting the MOSFETs are power dissipation, cost and packaging. Switching losses and conduction losses of the MOSFETs are directly related to the total gate charge (C ) and channel on-resistance g (R ). In order to judge the performance of MOSFETs, ds(on) the product of the total gate charge and on-resistance is used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 5. Figure 4. Typical waveforms at converter input. www.semtech.com  2007 Semtech Corp. 10 SC4508A POWER MANAGEMENT Application Information (Cont.) manufacturers’ data sheet. From the FDS6675 datasheet, R is less than 14mΩ when V is greater ds(on) gs 50 than 10V. However R increases by 30% as the ds(on) 40 o o junction temperature increases from 25 C to 110 C. Cg() 100, Rds Cg() 200, Rds The switching losses can be estimated using the simple 20 Cg() 500, Rds formula: 1 δ P = (t + t )(1+ )I V f ts r f dc in s 2 2 1 0 0 5 10 15 20 where t is the rise time and t is the fall time of the r f 1 Rds 20 switching process. Different manufacturers have On-resistance (mOhm) different definitions and test conditions for t and t . To FOM:100*10^{-12} r f FOM:200*10^{-12} clarify these, we sketch the typical MOSFET switching FOM:500*10^{-12} characteristics under clamped inductive mode in Figure 6. Figure 5. Figure of Merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFETs with both low C and low R . Usually a trade-off between R and g ds(on ds(on C has to be made. g MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For buck and buck- boost converters with high input to output voltage ratios, the MOSFET is hard switched but conducts with very low Figure 6. MOSFET switching characteristics duty cycle. For such applications, MOSFETs with low C g should be used. In Figure 6, Q is the gate charge needed to bring the gate-to-source gs1 MOSFET power dissipation consists of: voltage V to the threshold voltage V , a) conduction loss due to the channel resistance R , gs gs_th ds(on) Q is the additional gate charge required for the switch gs2 b) switching loss due to the switch rise time t and fall r current to reach its full-scale value I and ds time t, and . f Q is the charge needed to charge gate-to-drain (Miller) gd c) the gate loss due to the gate resistance R . G capacitance when V is falling. ds Switching losses occur during the time interval [t , t ]. The RMS value of the MOSFET switch current is calculated 1 3 Defining t = t -t and t can be approximated as: r 3 1 r as: (Q + Q )R 2 gs2 gd gt δ I = I D(1+ ) t = Qrms dc 12 r V − V cc gsp The conduction losses are then where R is the total resistance from the driver supply gt rail to the gate of the MOSFET. It includes the gate driver 2 P = I R tc Qrms ds(on) internal impedance R , external resistance R and the gi ge gate resistance R within the MOSFET i.e. g Idc is average inductor current. In buck converter, it is also load current. In buck-boost, it is load current divided R = R +R +R gt gi ge g by 1-D. V is the Miller plateau voltage shown in Figure 11. R varies with temperature and gate-source voltage. gsp ds(on) Similarly an approximate expression for t is: f Curves showing R variations can be found in ds(on)  2007 Semtech Corp. 11 www.semtech.com Gate Charge (nC) SC4508A POWER MANAGEMENT o (T , usually 125 C) is not exceeded under the worst- Application Information (Cont.) j,max case condition. The equivalent thermal impedance from (Q + Q )R junction to ambient (θ ) should satisfy: gs2 gd gt ja t = f V gsp T − T j,max a,max θ ≤ ja P loss Only a portion of the total losses (P = Q V f ) is dissipated g g cc s θ depends on the die to substrate bonding, packaging ja in the MOSFET package. Here Qg is the total gate charge material, the thermal contact surface, thermal compound specified in the datasheet. The power dissipated within property, the available effective heat sink area and the the MOSFET package is: air flow condition (free or forced convection). Actual temperature measurement of the prototype should be R g P = Q V f tg g cc s carried out to verify the thermal design. R gt The total power loss of the top switch is then: Overload Protection and Hiccup P = P +P +P t tc ts tg During start-up, the capacitor from the SS/EN pin to If the input supply of the power converter varies over a ground functions as a soft-start capacitor. After the wide range, then it will be necessary to weigh the relative converter starts and enters regulation, the same importance of conduction and switching losses. This is capacitor operates as an overload shutoff timing because conduction losses are inversely proportional to capacitor. As the load current increases, the cycle-by- the input voltage. Switching loss however increases with cycle current-limit comparator will first limit the inductor the input voltage. The total power loss of MOSFET should current. If the over-current persists for more than 32 be calculated and compared for high-line and low-line consecutive switching cycles, the controller will shut off cases. The worst case is then used for thermal design. the MOSFETs. Meanwhile an internal 12mA current source discharges the soft-start capacitor C connected SS Freewheeling Diode Selection to the SS/EN pin. The Schottky diode is recommended as freewheeling When the capacitor is discharged to 0.5V, a 10µA current diode in the both Buck and Buck-Boost applications. The source recharges the SS/EN capacitor to 0.9V and driver diode conducts during the off-time. The diode voltage stage is enabled. Then a 20uA current source continues and current ratings are selected based on the peak to charge the soft-start capacitor. As the soft-start reverse voltage, the peak current and average power capacitor reaches 1.4V, VREF will start to follow the soft- dissipation. The following could be used to determine the start capacitor voltage until VREF=0.5V. If overload diode reversed voltage: persists, the controller will shut down the converter when Δ V − V I the soft-start capacitor voltage exceeds 1.4V. The L IN O V = V , I = I + ,I = I for Buck D(REV) IN D(PEAK ) O D(AVG) O converter will repeatedly start and shut off until it is no 2 V + V IN D longer overloaded. This hiccup mode of overload V + V + V ΔI protection is a form of foldback current limiting. The IN O D L V = V + V , I = I ( ) + ,I = I D(REV) IN O D(PEAK) O D(AVG) O V 2 following calculations estimate the average inductor IN current when the converter output is shorted to the for Buck − Boost ground. The most stressful condition for the diode occurs when a) The time taken to charge the capacitor from 0.5V to the output is shorted. Under this condition, due to the 0.9V V = 0, the diode conducts at close to 100% duty cycle. OUT Therefore, attention should be paid to the thermal (0.9 − 0.5)V t = C ssr1 SS condition when laying out a board. 10uA If C = 0.1µF, t is calculated as 4ms. SS ssr1 Once the power losses (P ) for the MOSFET and loss b) The time to charge the capacitor from 0.9V to 1.4V freewheeling diode are known, thermal and package (driver is enabled but output duty cycle is 0) design at component and system level should be done to verify that the maximum die junction temperature www.semtech.com  2007 Semtech Corp. 12 SC4508A POWER MANAGEMENT Application Information (Cont.) Vo (V) 0.6 0.9 15 .2 1. 15 .8 23 . 3. (1.4 − 0.9)V t = C ssr2 SS 20µA (1-h)/h 0.2 0.8 12 .4 24 .6 5.6 When C = 0.1µF, t is calculated as 2.5ms. Note that SS ssr2 Ro1 (Ohm) 200 806 1K .4K 22K .61K4K .02 5.62 during this period, the converter does not start switching until SS/EN reaches 1.4V. Ro2 (Ohm) 1K 1K 1K K 1 1K K 1K 1 c) The effective start-up time is: Only the voltages in boldface can be precisely set with 32 t = sse standard 1% resistors. 200KHz From this table, one may also observe that when the value Assuming inductor current hitting current limit for 32 − 1− h V 0.5 cycles after SS/EN reaches 1.4V and fs=200KHz. The o = h 0.5 average inductor current is then: and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value t sse I = I Leff LIM resistors to exactly set up the required output voltage t + t ssr1 ssr2 value. I ≈ 0.025 I and is independent of the soft start In buck-boost converter, output voltage is set by Leff LIM capacitor value. The converter will not overheat in hiccup. 0.5 R = R o2 o1 V O Setting the Output Voltage The non-inverting input of the error amplifier is brought The input bias current of the error amplifier also causes out as a device pin (Pin 9) to which the user can connect an error in setting the output voltage. The inverting input Pin 4 or an external voltage reference. A simple voltage bias currents of error amplifiers is -100nA. Since the non-inverting input is biased to 0.5V in buck converter, divider (R at top and R at bottom) sets the converter o1 o2 the percentage error in the second output voltage will be output voltage. In buck converter, the voltage feedback gain (h=0.5/V ) is related to the divider resistors value o –100% · (0.1µA) · R R /[0.5 · (R +R ) ]. To keep o1 o2 o1 o2 as: this error below 0.2%, R //R < 10kΩ. o1 o2 h R = R o2 o1 1− h Loop Compensation Once either R or R is chosen, the other can be o1 o2 SC4508A is a current-mode controller. Current-mode calculated for the desired output voltage V . Since the o control is a dual-loop control system in which the inductor number of standard resistance values is limited, the peak current is loosely controlled by the inner current- calculated resistance may not be available as a standard loop. The higher gain outer loop regulates the output value resistor. As a result, there will be a set error in the voltage. Since the current loop makes the inductor appear converter output voltage. This non-random error is as a current source, the complex high-Q poles of the caused by the feedback voltage divider ratio. It cannot output LC networks is split into a dominant pole be corrected by the feedback loop. determined by the output capacitor and the load The following table lists a few standard resistor resistance and a high frequency pole. This pole-splitting combinations for realizing some commonly used output property of current-mode control greatly simplifies loop voltages. compensation.  2007 Semtech Corp. 13 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) 0.5 h = V The inner current-loop is unstable (sub-harmonic o oscillation) unless the inductor current up-slope is steeper For the rated output current I , the current sensing gain o than the inductor current down-slope. For stable k is fixed as: operation above 50% duty-cycle, a compensation ramp 1 is added to the sensed-current. In the SC4508A the k = 8 ⋅R S compensation ramp is made switching frequency dependent. The slope of the compensation ramp is: From Figure 7, the transfer function from the voltage S = 500 * f mV e s error amplifier output (v ) to the converter output (v )is: c o s The slope of the internal compensation ramp is above 1+ V (s) s the minimal slope requirement for current loop stability o z1 := G (s) = kR vc o s and is sufficient for all the applications. With the inner V (s) c 1+ current loop stable, the output voltage is then regulated s p1 with the outer voltage feedback loop. A simplified where, the single dominant pole is: equivalent circuit model of the buck converter with 1 current mode control is shown in Figure 7. s = p1 (R + R )C o oesr o and the zero due to the output capacitor ESR is: 1 s = z1 R C oesr o The dominant pole moves as output load varies. The controller transfer function (from the converter output (v ) to the voltage error amplifier output (v ) is: o c k s 1+ g s m z2 G (s) = c s s(C + C ) 2 3 1+ s p2 where 1 s = z2 R C 2 2 and Figure 7. A simple model of buck converter with current 1 mode control. s = p2 C C 2 3 R 2 C + C 2 3 The transconductance error amplifier (in the SC4508A) has a gain (g ) of 100µA/V. The target of the m compensation design is to select the compensation The loop transfer function is then: network consisting of C , C and R , along with the 2 3 2 feedback resistors R , R and the current sensing gain, T(s)=G (s)G (s)h o1 o2 vc C such that the converter output voltage is regulated with satisfactory dynamic performance. To simplify design, we assume that C <