SEMTECH SC424

SC414/SC424 6A Integrated FET Regulator with 5V LDO POWER MANAGEMENT Features Description „ Input voltage — 3V to 28V The SC414/SC424 is a stand-alone synchronous buck regu- „ Internal power MOSFETs — 6A lated power supply. It features integrated power MOSFETs, „ Integrated bootstrap switch a bootstrap switch, and a 5V LDO in a space-saving MLPQ- „ Smart power-save protection 4x4mm 28-pin package. The device is highly effi cient and „ Integrated 5V, 150mA LDO with bypass capability uses minimal PCB area. It uses pseudo-fi xed frequency „ TC compensated R sensed current limit adaptive on-time operation to provide fast transient DS(ON) „ Pseudo-fi xed frequency adaptive on-time control response. „ Designed for use with ceramic capacitors The SC414/SC424 supports using standard capacitor types „ Programmable V UVLO threshold IN such as electrolytic or special polymer, in addition to „ Independent enable for switcher and LDO ceramic, at switching frequencies up to 1MHz. The pro- „ Selectable ultrasonic power-save (SC414) grammable frequency, synchronous operation, and select- „ Selectable power-save (SC424) able power-save provide high effi ciency operation over a „ Internal soft-start and soft-shutdown at output wide load range. „ Internal reference — 1% tolerance „ Over-voltage and under-voltage fault protection Additional features include cycle-by-cycle current limit, „ Power good output TM soft-start, under and over-voltage protection, program- „ SmartDrive mable over-current protection, soft shutdown, and select- „ Lead-free 4x4mm, 28 Pin MLPQ package able power-save. The device also provides separate enable „ Fully WEEE and RoHS compliant, and halogen free inputs for the PWM controller and LDO as well as a power Applications good output for the PWM controller. „ Notebook, desktop, tablet, and server computers The input voltage can range from 3V to 28V. The wide „ Networking and telecommunication equipment input voltage range, programmable frequency, and 5V „ Printers, DSL, and STB applications LDO make the device extremely fl exible and easy to use in „ Embedded applications a broad range of applications. It can be used for single cell „ Power supply modules or multi-cell battery systems in addition to traditional DC „ Point of load power supplies power supply applications. The 5V LDO or an external 3.3V to 5V supply can be used to provide the bias voltage for the SC414/SC424. When the SC414/SC424 is used as a 5V output switching regula- tor, the 5V LDO can be used as an initial bias supply for the device. Once the switch regulator output is in the switch over range, the LDO will be bypassed by the switcher output for optimum effi ciency. © 2009 Semtech Corporation September 11, 2009 1 SC414/SC424 Typical Application Circuit ENABLE LDO ENABLE PSAVE V5V RTON RPGOOD 154KΩ RILIM 10KΩ 9.09KΩ PGOOD 28 27 26 25 24 23 22 PAD 2 PAD 1 VIN AGND FB V5V 1 21 FB LX 2 20 V5V LX 3 19 C1 AGND PGND C2 VOUT 1μF 4 18 1μF SC414/SC424 VOUT PGND 5 17 VIN PGND 6 16 VLDO PGND 7 15 BST LX C3 100nF PAD 3 LX CBST 8 9 10 11 12 13 14 1μF VIN +12V CIN CIN 10μF 10μF RGND 0 VOUT L1 1.5μH VOUT 1V @ 6A, 250kHz + COUT RFB1 C4 220μF 10nF 10KΩ FB RFB2 30KΩ Key Components Component Value Manufacturer Part Number Web CIN 10μF/25V Murata GRM32DR71E106KA12L www.murata.com COUT 220μF/15mΩ/6.3V Panasonic EEFUE0J221R www.panasonic.com www.vishay.com L1 1.5μH/9A Vishay IHLP2525CZER1R5M01 All other small signal components (resistors and capacitors) are standard SMT devices. 2 VIN ENL VIN TON VIN AGND VIN EN/PSV LXBST LXS PGND ILIM PGND PGOOD SC414/SC424 Pin Confi guration Ordering Information Device Package (1)(2) SC414MLTRT MLPQ-28 4x4 (1)(2) SC424MLTRT MLPQ-28 4x4 SC414EVB Evaluation Board 28 27 26 25 24 23 22 1 Top View FB 21 LX SC424EVB Evaluation Board V5V 2 20 LX Notes: AGND 3 AGND 19 PGND PAD 1 1) Available in tape and reel only. A reel contains 3000 devices. LX 4 VOUT 18 PGND 2) Lead-free packaging only. Device is WEEE and RoHS compliant, PAD 3 and halogen free. 5 VIN 17 PGND VIN VLDO 6 16 PGND PAD 2 BST 7 15 LX 8 9 10 11 12 13 14 SC414 and SC424 MLPQ-28; 4x4, 28 LEAD Marking Information SC414 SC424 yyww yyww xxxxx xxxxx xxxxx xxxxx yyww = Date Code yyww = Date Code xxxxx = Semtech Lot Number xxxxx = Semtech Lot Number 3 VIN ENL VIN TON VIN AGND VIN EN/PSV LXBST LXS PGND ILIM PGND PGOOD SC414/SC424 Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30 V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 to 5.5 EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(V5V + 0.3) Thermal Information VOUT, VLDO, FB, to GND (V) . . . . . . . . . . . -0.3 to +(V5V + 0.3) Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150 V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150 TON to PGND (V) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5) Operating Junction Temperature (°C) . . . . . . . .-40 to +125 ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V IN (2) Thermal resistance, junction to ambient (°C/W) BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 (1) PWM controller and LDO thermal resistance . . . . . 40 ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Peak IR Refl ow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260 Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specifi ed: V =12V, T = +25°C for Typical, -40 to +85 °C for Min. and Max., T < 125°C, V5V = +5V, Typical Application Circuit IN A J Parameter Conditions Min Typ Max Units Input Supplies Sensed at ENL pin, rising edge 2.40 2.60 2.95 (1) VIN UVLO Threshold V (not available for V5V < 4.5V) Sensed at ENL pin, falling edge 2.235 2.40 2.565 VIN UVLO Hysteresis EN/PSV = High 0.2 V Measured at V5V pin, rising edge 2.50 2.9 3.0 V5V UVLO Threshold V Measured at V5V pin, falling edge 2.40 2.7 2.90 V5V UVLO Hysteresis 0.2 V ENL, EN/PSV = 0V, V = 28V 8.5 20 IN VIN Supply Current μA Standby mode; ENL=V5V, EN/PSV = 0V 130 4 SC414/SC424 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) ENL, EN/PSV = 0V , V5V = 5V 3 7 μA ENL, EN/PSV = 0V , V5V = 3V 2 SC414, EN/PSV = V5V, no load (f = 25kHz), SW 1 (2) V > 750mV FB V5V Supply Current (2) SC424, EN/PSV = V5V, no load, V > 750mV 0.4 FB mA (2) V5V = 5V, f = 250kHz, EN/PSV = fl oating, no load 4 SW (2) V5V = 3V, f = 250kHz, EN/PSV = fl oating, no load 2.5 SW Static V and load, 0 to +85 °C, V5V = 3V or 5V 0.744 0.750 0.756 V IN FB Comparator Threshold Static V and load, -40 to +85 °C, V5V = 3V or 5V 0.7425 0.7575 V IN Continuous mode operation 1000 Frequency Range kHz Minimum f , (SC414 only), EN/PSV = V5V, no load 25 SW Bootstrap Switch Resistance 10 Ω Timing Continuous mode operation, 1350 1500 1650 ns V = 15V, V = 3V, R = 300kΩ IN OUT TON On-Time (3) V5V < 4.5V (2) Minimum On-Time 80 ns V5V = 5V 320 (2) Minimum Off -Time ns V5V = 3V 390 Soft-Start (2) Soft-Start Ramp Time 1.7 ms Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero-Crossing Detector Threshold LX - PGND, V5V = 3V or 5V -3 0 +3 mV 5 SC414/SC424 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Power Good Upper limit, V > internal 750mV reference +20 % FB Power Good Threshold Lower limit, V < internal 750mV reference -10 % FB V5V = 3V 2 Start-Up Delay Time (Time between EN going ms high and PGOOD going high) V5V = 5V 4 (2) Fault (noise immunity) Delay Time 5μs Leakage 1μA Power Good On-Resistance 10 Ω Fault Protection Valley Current Limit V5V = 5V, R = 5k Ω 3 4 5 A ILIM Valley Current Limit V5V = 3V, R = 5k Ω 3.4 A ILIM I Source Current 8μA LIM I Comparator Off set With respect to AGND -8 0 +8 mV LIM V with respect to internal 750mV reference, FB Output Under-Voltage Fault -25 % 8 consecutive clock cycles (2) Smart Power-save Protection Threshold V with respect to internal 750mV reference +10 % FB Over-Voltage Protection Threshold V with respect to internal 750mV reference +20 % FB (2) Over-Voltage Fault Delay 5μs (2) Over-Temperature Shutdown 10°C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage ENL 1 V Logic Input Low Voltage ENL 0.4 V (2) EN/PSV Input for PSAVE Operation % of V5V 45 100 % (2) EN/PSV Input for Forced Continuous Operation % of V5V 1V 42 % (2) EN/PSV Input for Disabling Switcher 0 0.4 V EN/PSV Input Bias Current EN/PSV= V5V or AGND -10 +10 μA ENL Input Bias Current V = 28V 11 18 μA IN FB Input Bias Current FB = V5V or AGND -1 +1 μA 6 SC414/SC424 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Linear Regulator — LDO (not available for V5V < 5V) VLDO Accuracy VLDO load = 10mA 4.9 5.0 5.1 V Start-up and foldback, V = 12V 85 IN LDO Current Limit mA Operating current limit, V = 12V 135 200 IN (4) VLDO to VOUT Switch-over Threshold -140 +140 mV (4) VLDO to VOUT Non-switch-over Threshold -450 +450 mV VLDO to VOUT Switch-over Resistance V = +5V 2 Ω OUT (5) LDO Drop Out Voltage From V to V , V = +5V, I = 100mA 1.2 V IN VLDO VLDO VLDO Notes: (1) V UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. IN (2) Guaranteed by design. (3) For V5V less than 4.5V, the On-Time may be limited by the V5V supply voltage and by V . See the TON Limitations and V5V Supply Voltage IN section in the applications Information. (4) The switch-over threshold is the maximum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to V . The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that OUT VLDO will not switch-over to V . OUT (5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point. Thermal resistance, junction to ambient — guaranteed by design (°C/W) 7 SC414/SC424 Typical Characteristics Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Effi ciency vs. Load — Forced Continuous Mode V vs. Load — Forced Continuous Mode OUT Internally biased at V = 5V, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT LDO IN OUT 100 1.05 80 1.03 60 1.01 40 0.99 20 0.97 0.95 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 I (A) OUT I (A) OUT Effi ciency vs. Load — Powersave Mode (SC414) Effi ciency vs. Load — Powersave Mode (SC414) Externally biased, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT IN OUT 100 100 3V Bias 80 80 5V Bias 60 60 40 40 20 20 0 0 0.001 0.01 0.1 110 0.001 0.01 0.1 1 10 I (A) OUT I (A) OUT Effi ciency vs. Load — Powersave Mode (SC424) Effi ciency vs. Load — Powersave Mode (SC424) Externally biased, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT IN OUT 100 100 80 80 3V Bias 5V Bias 60 60 40 40 20 20 0 0 0.001 0.01 0.1 110 0.001 0.01 0.1 1 10 I (A) OUT IOUT (A) 8 Efficiency (%) Efficiency (%) Efficiency (%) Output Voltage (V) Efficiency (%) Efficiency (%) SC414/SC424 Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Frequency vs. Load — Forced Continuous Mode V vs. Load — Forced Continuous Mode RIPPLE Internally biased at V = 5V, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT LDO IN OUT 400 100 350 80 300 60 250 40 200 20 150 100 0 0.001 0.01 0.1 1 10 1 0.001 0.01 0.1 10 I (A) OUT I (A) OUT V vs. Load — Powersave Mode (SC414) V vs. Load — Powersave Mode (SC424) OUT OUT Internally biased at V = 5V, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT LDO IN OUT 1.05 1.05 1.03 1.03 1.01 1.01 0.99 0.99 0.97 0.97 0.95 0.95 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 I (A) I (A) OUT OUT V vs. Line — Forced Continuous Mode V vs. Line — Forced Continuous Mode OUT OUT Internally biased at V = 5V, V = 12V, V = 1V Internally biased at V = 5V, V = 12V, V = 1V LDO IN OUT LDO IN OUT 100 1.05 80 1.03 0A 1.5A 6A 1.01 60 3A 0.99 40 3A 6A 20 0.97 0A 1.5A 0 0.95 57 9 11 13 15 17 19 5 7 9 1113 1517 19 21 21 Input Voltage (V) Input Voltage (V) 9 Output Voltage (V) VOUT (V) Frequency (kHz) V (V) OUT V (mV ) RIPPLE P_P V (mV ) RIPPLE P_P SC414/SC424 Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Powersave Mode — No Load (SC424) Ultrasonic Powersave Mode — No Load (SC414) V = 12V, V = 1V, I = 0A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1V, I = 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO 5V IN OUT OUT LDO 5V (50mV/div) (50mV/div) (5V/div) (5V/div) Time (10ms/div) Time (10μs/div) Forced Continuous Mode — No Load Self-Biased Start-Up — Power Good True V = 12V, V = 1V, I = 0A, V = V = ENL = 5V, EN/PSV= fl oat V = 0V to 12V step, V = 1V, I = 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO 5V IN OUT OUT LDO 5V (500mV/div) (50mV/div) (2V/div) (10V/div) (5V/div) (5V/div) Time (10ms/div) Time (2μs/div) Enabled Loaded Output — Power Good True Output Over-current Response — Normal Operation V = 12V, V = 1V, I = 1A, V = V = ENL = 5V. EN/PSV= 5V V = 12V, V = 1V, V = V = ENL = 5V, EN/PSV= fl oating; I ramped to trip point IN OUT OUT LDO 5V IN OUT LDO 5V OUT (500mV/div) (5A/div) (500mV/div) (5V/div) (10V/div) (5V/div) (5V/div) Time (1ms/div) Time (100μs/div) 10 SC414/SC424 Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Transient Response — Load Rising (SC414) Transient Response — Load Falling (SC414) V = 12V, V = 1V, I = 200mA to 6A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1V, I = 6A to 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO 5V IN OUT OUT LDO 5V (50mV/div) (50mV/div) (5A/div) (5A/div) (5V/div) (5V/div) Time (10μs/div) Time (10μs/div) Transient Response — Load Rising (SC424) Transient Response — Load Falling (SC424) V = 12V, V = 1V, I = 0A to 6A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1V, I = 6A to 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO 5V IN OUT OUT LDO 5V (50mV/div) (50mV/div) (10V/div) (10V/div) (5A/div) (5A/div) (5V/div) (5V/div) Time (10μs/div) Time (10μs/div) Shorted Output Response — Normal Operation Shorted Output Response — Power-UP Operation V = 12V, V = 1V, I = 0A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1V, I = 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO 5V IN OUT OUT LDO 5V (500mV/div) (500mV/div) (5A/div) (5A/div) (10V/div) (10V/div) (5V/div) (5V/div) Time (40μs/div) Time (1ms/div) 11 SC414/SC424 Pin Descriptions Pin # Pin Name Pin Function Feedback input for switching regulator used to program the output voltage — connect to an external resis- 1FB tor divider from VOUT to AGND. Bias input for internal analog circuits and gate drives — connect to external 3V or 5V supply or bias connec- 2 V5V tion to VLDO. 3, 26, PAD 1 AGND Analog ground 4 VOUT Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO. 5, 8-11 VIN Input supply voltage PAD 2 6 VLDO 5V LDO output Bootstrap pin — connect a capacitor from BST to LXBST to develop the fl oating supply for the high-side gate 7 BST drive. 12 LXBST LX Boost — connect to the BST capacitor. 15,20, 21, LX Switching (phase) node PAD 3 13, 14, 16-19 PGND Power ground Open-drain power good indicator — high impedance indicates power is good. An external pull-up 22 PGOOD resistor is required. 23 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS. 24 LXS LX sense — connects to RILIM resistor Enable/power save input for the switching regulator — connect to AGND to disable the switching regula- tor. Float to operate in forced continuous mode (power save disabled). For SC414, connect to V5V to operate 25 EN/PSV with ultrasonic power save mode enabled. For SC424, connect to V5V to operate with power save mode enabled with no minimum frequency. 27 TON On-time programming input — set the on-time by connecting through a resistor to AGND Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con- 28 ENL trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND. 12 SC414/SC424 Block Diagram VIN V5V PGOOD EN/PSV 2 22 25 A V5V V IN V5V Bootstrap Switch 7 BST AGND D Control & Status Reference DL Hi-side Soft Start MOSFET B LX Gate Drive On- - time 1 Control FB Generator 12 LXBST V5V FB Comparator 24 LXS DL Lo-side TON 27 MOSFET Zero Cross Detector C PGND 4 VOUT Bypass Compar Bypass Comparat ator or Valley Current Limit 3 ILIM A V IN VLDO 6 Y B LDO VLDO Switchover MUX 28 ENL A = connected to pins 5, 8-11, PAD 2 B = connected to pins 15, 20, 21, PAD 3 C = connected to pins 13, 14, 16-19 D = connect to pins 3, 26, PAD 1 13 SC414/SC424 Applications Information The adaptive on-time is determined by an internal one- Synchronous Buck Converter shot timer. When the one-shot is triggered by the output The SC414/SC424 is a step down synchronous DC-DC buck ripple, the device sends a single on-time pulse to the high- converter with integrated power MOSFETs and a 5V LDO. side MOSFET. The pulse period is determined by V and The device is capable of 6A operation at very high effi - OUT V . The period is proportional to output voltage and ciency. A space saving 4x4 (mm) 28-pin package is used. IN inversely proportional to input voltage. With this adaptive The programmable operating frequency range of 200kHz on-time confi guration, the device automatically antici- to 1MHz enables optimizing the configuration for PCB pates the on-time needed to regulate V for the present area and effi ciency. OUT V condition and at the selected frequency. IN The buck controller uses a pseudo-fi xed frequency adap- The advantages of adaptive on-time control are: tive on-time control. This control method allows fast tran- sient response which permits the use of smaller output • Predictable operating frequency compared to capacitors. other variable frequency methods. • Reduced component count by eliminating the Input Voltage Requirements error amplifi er and compensation components. The SC414/SC424 requires two input supplies for normal • Reduced component count by removing the operation: V and V5V. V operates over the wide range IN IN need to sense and control inductor current. from 3V to 28V. V5V requires a 3.3 or 5V supply input that • Fast transient response — the response time is can be an external source or the internal LDO confi gured controlled by a fast comparator instead of a typi- to supply 5V. If the LDO is enabled, V5V voltage must be cally slow error amplifi er. > 5V. • Reduced output capacitance due to fast tran- sient response Psuedo-fi xed Frequency Adaptive On-time Control The PWM control method used by the SC414/SC424 is One-Shot Timer and Operating Frequency pseudo-fi xed frequency, adaptive on-time, as shown in One-shot timer operation is shown in Figure 2. The FB Figure 1. The ripple voltage generated at the output Comparator output goes high when V is less than the FB capacitor (ESR) is used as a PWM ramp signal. This ripple is internal 750mV reference. This feeds into the gate drive used to trigger the on-time of the controller. and turns on the high-side MOSFET, and starts the one- shot timer. The one-shot timer uses an internal compara- TON V IN tor and a capacitor. One comparator input is connected to V LX V , the other input is connected to the capacitor. When OUT the on-time begins, the internal capacitor charges from C IN Q1 V FB zero volts through a current which is proportional to V . IN FB Threshold When the capacitor voltage reaches V , the on-time is OUT V LX completed and the high-side MOSFET turns off . V OUT L Gate ESR Drives V IN FB Comparator Q2 FB - FB 750mV + Q1 DH + V L OUT V LX C OUT V OUT ESR FB One-Shot Q2 V IN + DL C OUT Timer R TON On-time = K x R x (V /V ) TON OUT IN Figure 1 — PWM Control Method, V Ripple OUT Figure 2 — On-Time Generation 14 SC414/SC424 Applications Information (continued) This method automatically produces an on-time that is 1 (V5V1.6V)u10 R  400:u proportional to V and inversely proportional to V. TON OUT IN 25pFu f V SW OUT Under steady-state conditions, the switching frequency can be determined from the on-time by the following Note that when V > (V5V - 1.6V) x 10 , the actual on-time IN equation. is fi xed and does not vary with V . When operating in this IN condition, the switching frequency will vary inversely with V OUT f SW V rather than approximating a fi xed frequency. IN T u V ON IN The SC414/SC424 uses an external resistor to set the on- V Voltage Selection OUT time which indirectly sets the frequency. The on-time can The switcher output voltage is regulated by comparing be programmed to provide an operating frequency from V as seen through a resistor divider at the FB pin to the OUT 200kHz to 1MHz using a resistor between the TON pin and internal 750mV reference voltage (see Figure 3). ground. The resistor value is selected by the following V To FB pin OUT equation. R 1 1 V IN R  400:u R TON 2 25pFu f V SW OUT The maximum R value allowed is shown by the follow- TON ing equation. Figure 3 — Output Voltage Selection V IN _ MIN Note that this control method regulates the valley of the R TON _ MAX 10u1.5PA output ripple voltage, not the DC value. The DC output voltage V is off set by the output ripple according to the OUT Immediately after the on-time, the DL (drive signal for the following equation. low side FET) output drives high to turn on the low-side MOSFET. DL has a minimum high time of ~320ns, after § · R V § · 1 RIPPLE V 0.75u¨1 ¸ ¨ ¸ OUT ¨ ¸ which DL continues to stay high until one of the following R 2 © ¹ © 2¹ occurs: When a large capacitor is placed in parallel with R1 (C ) TOP V is shown by the following equation. OUT • VFB falls below the 750mV reference • The Zero Cross Detector senses that the voltage 2 § · R V 1 (RZC ) § · 1 RIPPLE 1 TOP on the LX node is below ground. Power Save is V 0.75u¨1 ¸ u ¨ ¸ OUT 2 ¨ ¸ R 2 © ¹ § · © 2¹ R uR activated when a zero crossing is detected. 2 1 1¨ ZC ¸ TOP ¨ ¸ R  R © 2 1 ¹ TON limitations and V5V Supply Voltage Where ω is the angular switching frequency. For V5V below 4.5V, the TON accuracy may be limited by the input voltage. Enable and Power-save Inputs The EN/PSV and ENL inputs are used to enable or disable The original RTON equation is accurate if V satisfi es the IN the switching regulator and the LDO. When EN/PSV is low below relation over the entire V range: IN (grounded), the switching regulator is off and in its lowest power state. When off , the output of the switching regula- V < (V5V - 1.6V) x 10 IN tor soft-discharges the output into a 10Ω internal resistor via the VOUT pin. When EN/PSV is allowed to fl oat, the pin If V exceeds (V5V - 1.6V) x 10, for all or part of the V IN IN voltage will fl oat to 33% of the voltage at V5V. The switch- range, the RTON equation is not accurate. In all cases ing regulator turns on with power-save disabled and all where V > (V5V - 1.6V) x 10, the RTON equation must be IN switching is in forced continuous mode. For V5V < 4.5V, it modifi ed as follows. 15 SC414/SC424 Applications Information (continued) is recommended to force 33% of the V5V voltage on the FB Ripple FB threshold Voltage (V ) EN/PSV pin to operate in forced continuous mode. FB (750mV) When EN/PSV is high (above 45% of the voltage at V5V) for SC414, the switching regulator turns on with ultrasonic power-save enabled. The SC414 ultrasonic power-save Inductor DC Load Current Current operation maintains a minimum switching frequency of 25kHz, for applications with stringent audio requirements. DH on-time is triggered when On-time When EN/PSV is high (above 45% of the voltage at V5V) (T ) V reaches the FB Threshold. ON FB for SC424, the switching regulator turns on with power- save enabled. The SC424 power-save operation is designed DH to maximize effi ciency at light loads with no minimum frequency limits. This makes the SC424 an excellent choice for portable and battery-operated systems. DL The ENL input is used to control the internal LDO. This DL drives high when on-time is completed. input provides a second function by acting as a V ULVO IN DL remains high until V falls to the FB threshold. FB sensor for the switching regulator. When ENL is low (grounded), the LDO is off . When ENL is a logic high but Figure 4 — Forced Continuous Mode Operation below the V UVLO threshold (2.6V typical), then the LDO IN is on and the switcher is off . When ENL is above the V Ultrasonic Power-save Operation (SC414) IN UVLO threshold, the LDO is enabled and the switcher is The SC414 provides ultrasonic power-save operation at also enabled if the EN/PSV pin is not grounded. light loads, with the minimum operating frequency fi xed at slightly under 25kHz. This is accomplished by using an Forced Continuous Mode Operation internal timer that monitors the time between consecu- The SC414/SC424 operates the switcher in Forced tive high-side gate pulses. If the time exceeds 40μs, DL Continuous Mode (FCM) by fl oating the EN/PSV pin (see drives high to turn the low-side MOSFET on. This draws Figure 4). In this mode of operation, the MOSFETs are current from V through the inductor, forcing both V OUT OUT turned on alternately to each other with a short dead time and V to fall. When V drops to the 750mV threshold, the FB FB between them to avoid cross conduction. This feature next DH (the drive signal for the high side FET) on-time is results in uniform frequency across the full load range triggered. After the on-time is completed the high-side with the trade-off being poor effi ciency at light loads due MOSFET is turned off and the low-side MOSFET turns on. to the high-frequency switching of the MOSFETs. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side For V5V < 4.5V, it is recommended to force 33% of the V5V MOSFET is turned off . voltage on the EN/PSV pin to operate in forced continuous mode. 16 SC414/SC424 Applications Information (continued) Because the on-times are forced to occur at intervals no Dead time varies according to load greater than 40μs, the frequency will not fall far below FB Ripple Voltage 25kHz. Figure 5 shows ultrasonic power-save operation. FB threshold (V ) FB (750mV) minimum f ~ 25kHz SW Inductor Zero (0A) FB Ripple Current Voltage (V ) FB FB threshold (750mV) On-time (T ) ON Inductor (0A) DH On-time is triggered when Current V reaches the FB Threshold. FB DH DH On-time is triggered when DL On-time V reaches the FB Threshold FB (T ) ON DH DL drives high when on-time is completed. DL remains high until inductor current reaches zero. 40μs time-out Figure 6 — Power-save Operation DL After the 40μsec time-out, DL drives high if V FB Smart Power-save Protection has not reached the FB threshold. Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with Figure 5 — Ultrasonic Power-save Operation power-save enabled, this can force V to slowly rise and OUT reach the over-voltage threshold, resulting in a hard shut- Power-save Mode Operation (SC424) down. Smart power-save prevents this condition. When The SC424 provides power-save operation at light loads the FB voltage exceeds 10% above nominal (exceeds with no minimum operating frequency. With power-save 825mV), the device immediately disables power-save, and enabled, the internal zero crossing comparator monitors DL drives high to turn on the low-side MOSFET. This draws the inductor current via the voltage across the low-side current from V through the inductor and causes V to MOSFET during the off -time. If the inductor current falls to OUT OUT fall. When V drops back to the 750mV trip point, a normal zero for 8 consecutive switching cycles, the controller FB T switching cycle begins. This method prevents a hard enters power-save operation. It will turn off the low-side ON OVP shutdown and also cycles energy from V back to MOSFET on each subsequent cycle provided that the OUT V . It also minimizes operating power by avoiding forced current crosses zero. At this time both MOSFETs remain IN conduction mode operation. Figure 7 shows typical wave- off until V drops to the 750mV threshold. Because the FB forms for the Smart Power-save feature. MOSFETs are off , the load is supplied by the output capaci- tor. If the inductor current does not reach zero on any TM SmartDrive switching cycle, the controller immediately exits power- For each DH pulse, the DH driver initially turns on the save and returns to forced continuous mode. Figure 6 high-side MOSFET at a slower speed, allowing a softer, shows power-save operation at light loads. smooth turn-off of the low-side diode. Once the DH node is high and the LX voltage has risen 1V above PGND, the SmartDrive circuit automatically drives the high-side MOSFET on at a rapid rate. This technique reduces ringing while maintaining high efficiency and also avoids the need for snubbers or series resistors in the gate drive. 17 SC414/SC424 Applications Information (continued) V drifts up to due to leakage OUT current flowing into C V discharges via inductor I OUT OUT PEAK and low-side MOSFET Smart Power Save I Threshold (825mV) LOAD Normal V ripple OUT FB I LIM threshold DH and DL off High-side Drive (DH) Time Single DH on-time pulse after DL turn-off Figure 8 — Valley Current Limit Low-side Setting the valley current limit to 6A results in a peak Drive (DL) inductor current of 6A plus peak ripple current. In this situ- DL turns on when Smart Normal DL pulse after DH PSAVE threshold is reached on-time pulse ation, the average (load) current through the inductor is DL turns off when FB 6A plus one-half the peak-to-peak ripple current. threshold is reached The internal 8μA current source is temperature compen- Figure 7 — Smart Power-save sated at 4100ppm in order to provide tracking with the RDS . ON Current Limit Protection The device features programmable current limiting, which The R value is calculated by the following equation. ILIM is accomplished by using the RDS of the lower MOSFET ON for current sensing. The current limit is set by R resistor. ILIM R = 1250 x I x [0.088 x (5V - V5V) + 1] ILIM LIM The R resistor connects from the ILIM pin to the LXS pin ILIM which is also the drain of the low-side MOSFET. When the do not exceed the absolute When selecting a value for R ILIM low-side MOSFET is on, an internal ~8μA current flows maximum voltage value for the ILIM pin. Note that because from the ILIM pin and through the R resistor, creating a the low-side MOSFET with low RDS is used for current ILIM ON voltage drop across the resistor. While the low-side sensing, the PCB layout, solder connections, and PCB con- MOSFET is on, the inductor current fl ows through it and nection to the LX node must be done carefully to obtain creates a voltage across the RDS . The voltage across the good results. R should be connected directly to LXS ON ILIM MOSFET is negative with respect to ground. If this MOSFET (pin 24). voltage drop exceeds the voltage across R , the voltage ILIM at the ILIM pin will be negative and current limit will acti- Soft-Start of PWM Regulator vate. The current limit then keeps the low-side MOSFET on Soft-start is achieved in the PWM regulator by using an and will not allow another high-side on-time, until the internal voltage ramp as the reference for the FB compara- current in the low-side MOSFET reduces enough to bring tor. The voltage ramp is generated using an internal the ILIM voltage to zero. This method regulates the induc- charge pump which drives the reference from zero to tor valley current at the level shown by ILIM in Figure 8. 750mV in ~1.8mV increments, using an internal ~500kHz oscillator. When the ramp voltage reaches 750mV, the ramp is ignored and the FB comparator switches over to a fixed 750mV threshold. During soft-start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft-start profi le for a wide range of applications. Typical soft-start ramp time is 1.7ms. 18 Inductor Current SC414/SC424 Applications Information (continued) During soft-start the regulator turns off the low-side then begins a soft-start cycle. The PWM will shut off if V5V MOSFET on any cycle if the inductor current falls to zero. falls below 2.7V. This prevents negative inductor current, allowing the device to start into a pre-biased output. This soft start LDO Regulator operation is implemented even if FCM is selected. FCM The device features an integrated LDO regulator with a operation is allowed only after PGOOD is high. fixed output voltage of 5V. There is also an enable pin (ENL) for the LDO that provides independent control. The Power Good Output LDO voltage can also be used to provide the bias voltage The power good (PGOOD) output is an open-drain output for the switching regulator. which requires a pull-up resistor. When the output voltage A minimum capacitance of 1μF referenced to AGND is is 10% below the nominal voltage, PGOOD is pulled low. It normally required at the output of the LDO for stability. If is held low until the output voltage returns to the nominal the LDO is providing bias power to the device, then a voltage. PGOOD is held low during start-up and will not minimum 0.1μF capacitor referenced to AGND is required, be allowed to transition high until soft-start is completed along with a minimum 1μF capacitor referenced to PGND (when V reaches 750mV) and typically 4ms has passed. FB to fi lter the gate drive pulses. Refer to the layout guide- PGOOD will transition low if the V pin exceeds +20% of lines section. FB nominal, which is also the over-voltage shutdown thresh- old (900mV). PGOOD also pulls low if the EN/PSV pin is LDO Start-up low when V5V is present. Before start-up, the LDO checks the status of the following signals to ensure proper operation can be maintained. Output Over-Voltage Protection 1. ENL pin Over-Voltage Protection (OVP) becomes active as soon as 2. VLDO output the device is enabled. The threshold is set at 750mV + 20% 3. V input voltage (900mV). When V exceeds the OVP threshold, DL latches IN FB high and the low-side MOSFET is turned on. DL remains When the ENL pin is high, the LDO will begin start-up, see high and the controller remains off , until the EN/PSV input Figure 10. During the initial phase, when the LDO output is toggled or V5V is cycled. There is a 5μs delay built into voltage is near zero, the LDO initiates a current-limited the OVP detector to prevent false transitions. PGOOD is start-up (typically 85mA) to charge the output capacitor. also low after an OVP event. When V has reached 90% of the fi nal value, the LDO LDO current limit is increased to ~200mA and the LDO output Output Under-Voltage Protection is quickly driven to the nominal value by the internal LDO When V falls to 75% of its nominal voltage (falls to FB regulator. 562.5mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to turn V Final VLDO off the MOSFETs. The controller stays off until EN/PSV is Voltage regulating with toggled or V5V is cycled. ~200mA current limit 90% of V Final VLDO V5V UVLO, and POR Constant current startup Under-Voltage Lock-Out (UVLO) circuitry inhibits switch- ing and tri-states the DH/DL drivers until V5V rises above 2.9V. An internal Power-On Reset (POR) occurs when V5V exceeds 2.9V, which resets the fault latch and soft-start Figure 10 — LDO Start-Up counter to begin the soft-start cycle. The SC414/SC424 19 SC414/SC424 Applications Information (continued) LDO Switch-Over Operation Switch-over MOSFET Parasitic Diodes The SC414/SC424 includes a switch-over function for the The switch-over MOSFET contains parasitic diodes that LDO. The switch-over function is designed to increase are inherent to its construction, as shown in Figure 11. effi ciency by using the more effi cient DC-DC converter to Switchover power the LDO output, avoiding the less efficient LDO Switchover control MOSFET regulator when possible. The switch-over function con- V V LDO OUT nects the VLDO pin directly to the VOUT pin using an internal switch. When the switch-over is complete the LDO is turned off , which results in a power savings and maximizes effi ciency. If the LDO output is used to bias the Parasitic diode Parasitic diode V5V SC414/SC424, then after switch-over the device is self- powered from the switching regulator with the LDO turned off . Figure 11— Switch-over MOSFET Parasitic Diodes The switch-over logic waits for 32 switching cycles before There are some important design rules that must be fol- it starts the switch-over. There are two methods that lowed to prevent forward bias of these diodes. The fol- determine the switch-over of V to V . LDO OUT lowing two conditions need to be satisfi ed in order for the parasitic diodes to stay off . In the fi rst method, the LDO is already in regulation and the DC-DC converter is later enabled. As soon as the • V5V ≥ V LDO PGOOD output goes high, the 32 cycle counter is started. • V5V ≥ V OUT The voltages at the VLDO and VOUT pins are then com- pared; if the two voltages are within ±300mV (typically) of If either V or V is higher than V5V, then the respective LDO OUT each other, within 32 cylces, the VLDO pin connects to the diode will turn on and the SC414/SC424 operating current VOUT pin using an internal switch, and the LDO is turned will flow through this diode. This has the potential of off . damaging the device. In the second method, the DC-DC converter is already ENL pin and V UVLO IN running and the LDO is enabled. In this case the 32 cycles The ENL pin also acts as the switcher under-voltage are started as soon as the LDO reaches 90% of its fi nal lockout for the V supply. The V UVLO voltage is pro- IN IN value. At this time, the VLDO and VOUT pins are compared, grammable via a resistor divider at the VIN, ENL, and AGND and if within ±300mV (typically) the switch-over occurs pins. and the LDO is turned off . ENL is the enable/disable signal for the LDO. In order to Switch-over Limitations on VOUT and VLDO implement the V UVLO there is also a timing requirement IN Because the internal switch-over circuit always compares that needs to be satisfi ed. the VOUT and VLDO pins at start-up, there are voltage limitations on permissible combinations of these pins. If the ENL pin transitions low within 2 switching cycles and Consider the situation where V is programmed to 4.7V. is < 1V, then the LDO will turn off but the switcher remains OUT After start-up, the device would connect VOUT to VLDO on. If ENL goes below the V UVLO threshold and stays IN and disable the LDO, since the two voltage are within the above 1V, then the switcher will turn off but the LDO ±300mV switch-over window. To avoid unwanted switch- remains on. over, the minimum diff erence between the voltages for V and V should be ±500mV. The V UVLO function has a typical threshold of 2.6V on OUT LDO IN the V rising edge. The falling edge threshold is 2.4V. IN 20 SC414/SC424 Applications Information (continued) Note that it is possible to operate the switcher with the signal. If PGOOD is high, then the switcher is already LDO disabled, but the ENL pin must be below the logic running and the LDO will run through the start-up cycle low threshold (0.4V maximum). The table below summa- without aff ecting the switcher. If PGOOD is low, then the rizes the function of the ENL and EN pins, with respect to LDO will not allow any PWM switching until the LDO the rising edge of ENL. output has reached 90% of it’s fi nal value. Using the On-chip LDO to Bias the SC414/SC424 ENL LDO status Switcher status EN The following steps must be followed when using the low low, < 0.4V off off internal LDO to bias the device. high low, < 0.4V off on low high, < 2.6V on off • Connect V5V to VLDO before enabling the LDO. high high, < 2.6V on off • Any external load on VLDO should not exceed 40mA until the LDO voltage has reached 90% of low high, > 2.6V on off fi nal value. high high, > 2.6V on on • Do not connect the EN pin directly to the V5V or any other supply voltage if Vout is greater than Figure 12 below shows the ENL voltage thresholds and or equal to 4.5V their eff ect on LDO and Switcher operation. Many applications connect the EN pin to V5V and control ENL voltage the on/off of the LDO and PWM simultaneously with the ENL pin. This allows one signal to control both the bias LDO on and power output of the SC414. When V > 4.5V this OUT Switcher on if EN = high configuration can cause problems due to the parasitic 2.6V diodes in the LDO switchover circuitry. After the Vout > V UVLO hysteresis IN 4.5V PWM output is up and running the switchover diodes 2.4V can hold up V5V > UVLO even if the ENL pin is grounded, LDO on turning off the LDO. Operating in this way can potentially Switcher off by V UVLO IN damage the part. ENL low threshold (min 0.4V) LDO off Design Procedure Switcher on if EN = high When designing a switch mode supply the input voltage AGND range, load current, switching frequency, and inductor ripple current must be specifi ed. Figure 12 — ENL Thresholds ENL Logic Control of PWM Operation The maximum input voltage (V ) is the highest speci- INMAX When the ENL input is driven above 2.6V, it is impossible to fi ed input voltage. The minimum input voltage ( V ) is INMIN determine if the LDO output is going to be used to power determined by the lowest input voltage after evaluating the device or not. In self-powered operation where the the voltage drops due to connectors, fuses, switches, and LDO will power the device, it is necessary during the LDO PCB traces. start-up to hold the PWM switching off until the LDO has The following parameters defi ne the design. reached 90% of the fi nal value. This prevents overloading the current-limited LDO output during the LDO start-up. • Nominal output voltage (V ) However, if the switcher was previously operating (with OUT • Static or DC output tolerance EN/PSV high but ENL at ground, and V5V supplied exter- • Transient response nally), then it is undesirable to shut down the switcher. To • Maximum load current (I ) prevent this, when the ENL input is above 2.6V (above the OUT V UVLO threshold), the internal logic checks the PGOOD IN 21 SC414/SC424 Applications Information (continued) There are two values of load current to evaluate — con- effi cient. However, larger inductance translates directly tinuous load current and peak load current. Continuous into larger packages and higher cost. Cost, size, output load current relates to thermal stresses which drive the ripple, and effi ciency are all used in the selection process. selection of the inductor and input capacitors. Peak load The ripple current will also set the boundary for power- current determines instantaneous component stresses and save operation. The switching will typically enter power- fi ltering requirements such as inductor saturation, output save mode when the load current decreases to 1/2 of the capacitors, and design of the current limit circuit. ripple current. For example, if ripple current is 4A then The following values are used in this design. Power-save operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, • V = 12V + 10% then power-save will start for loads less than 20% of IN • V = 1V + 4% maximum current. OUT • f = 250kHz SW The inductor value is typically selected to provide a ripple • Load = 6A maximum current that is between 25% to 50% of the maximum load Frequency Selection current. This provides an optimal trade-off between cost, Selection of the switching frequency requires making a effi ciency, and transient performance. trade-off between the size and cost of the external fi lter components (inductor and output capacitor) and the During the DH on-time, voltage across the inductor is power conversion effi ciency. (V - V ). The equation for determining inductance is IN OUT shown next. The desired switching frequency is 250kHz which results from using components selected for optimum size and (V  V )u T IN OUT ON L cost . I RIPPLE A resistor (R ) is used to program the on-time (indirectly Example TON setting the frequency) using the following equation. In this example, the inductor ripple current is set equal to 50% of the maximum load current. Therefore ripple 1 V IN current will be 50% x 6A or 3A. To find the minimum R  400:u TON 25pFu f V SW OUT inductance needed, use the V and T values that corre- IN ON spond to V . To select R , use the maximum value for V , and for T INMAX TON IN ON use the value associated with maximum V . IN (13.2V1V)u318ns L 1.26PH V 3A OUT T ON V u f INMAX SW A slightly larger value of 1.5μH is selected. This will decrease the maximum I to 2.53A. RIPPLE T = 303 ns at 13.2V , 1V , 250kHz ON IN OUT Note that the inductor must be rated for the maximum DC Substituting for R results in the following solution. TON load current plus 1/2 of the ripple current. R = 130.9kΩ, use R = 130kΩ TON TON The ripple current under minimum V conditions is also IN checked using the following equations. Inductor Selection In order to determine the inductance, the ripple current 25pFuR u V must fi rst be defi ned. Low inductor values result in smaller TON OUT T 10ns 311ns ON _ VINMIN V size but create higher ripple current which can reduce INMIN effi ciency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more 22 SC414/SC424 Applications Information (continued) Assuming a peak voltage V of 1.150 (100mV rise upon PEAK (V  V )u T IN OUT ON I load release), and a 6A load release, the required capaci- RIPPLE L tance is shown by the next equation. (10.81V)u311ns I 2.03A RIPPLE _ VINMIN 2 1 § · 1.5PH 1.5PH 6A u 2.53A ¨ ¸ 2 © ¹ COUT MIN 2 2 Capacitor Selection  1.05V 1V The output capacitors are chosen based on required ESR COUT = 772μF and capacitance. The maximum ESR requirement is con- MIN trolled by the output ripple requirement and the DC toler- If the load release is relatively slow, the output capacitance ance. The output voltage has a DC value that is equal to can be reduced. At heavy loads during normal switching, the valley of the output ripple plus 1/2 of the peak-to-peak when the FB pin is above the 750mV reference, the DL ripple. Change in the output ripple voltage will lead to a output is high and the low-side MOSFET is on. During this change in DC voltage at the output. time, the voltage across the inductor is approximately -V . This causes a down-slope or falling di/dt in the The design goal is for the output voltage regulation to be OUT inductor. If the load di/dt is not much faster than the ±4% under static conditions. The internal 750mV refer- -di/dt in the inductor, then the inductor current will tend ence tolerance is 1%. Assuming a 1% tolerance from the to track the falling load current. This will reduce the excess FB resistor divider, this allows 2% tolerance due to V OUT inductive energy that must be absorbed by the output ripple. Since this 2% error comes from 1/2 of the ripple capacitor, therefore a smaller capacitance can be used. voltage, the allowable ripple is 4%, or 40mV for a 1V output. The following can be used to calculate the needed capaci- tance for a given dI /dt. Peak inductor current is shown The maximum ripple current of 2.53A creates a ripple LOAD by the next equation. voltage across the ESR. The maximum ESR value allowed is shown by the following equations. I = I + 1/2 x I LPK MAX RIPPLEMAX V 40mV RIPPLE ESR I = 6A + 1/2 x 2.53A = 7.26A MAX LPK I 2.53A RIPPLEMAX dl LOAD ESR = 15.8 mΩ Rate of change of Load Current MAX dt The output capacitance is chosen to meet transient I = maximum load release = 6A MAX requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor I I LPK MAX Lu  u dt current is at the peak, determines the required capaci- V dl OUT LOAD C I u OUT LPK tance. If the load release is instantaneous (load changes 2 V  V PK OUT from maximum to zero in < 1μs), the output capacitor Example must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the dl 1.25A LOAD following equation. dt 1Ps 2 1 § · L I  uI ¨ ¸ OUT RIPPLEMAX 2 © ¹ COUT MIN 2 2  V V PEAK OUT 23 SC414/SC424 Applications Information (continued) This causes the output current to move from 6A to 0A in C TOP 4.8μs, giving the minimum output capacitance require- ment shown in the following equation. 7.26A 6A To FB pin V R1 OUT 1.5PHu  u1Ps 1V 1.25A C 7.26Au R2 OUT 2 1.05V1V C 443PF OUT Note that C is much smaller in this example, 443μF OUT Figure 13 — Capacitor Coupling to FB Pin compared to 772μF based on a worst-case load release. To meet the two design criteria of minimum 443μF and ESR loop instability is caused by insufficient ESR. The maximum 15mΩ ESR, select two capacitors rated at 220μF details of this stability issue are discussed in the ESR and 15mΩ ESR or less. Requirements section. The best method for checking sta- bility is to apply a zero-to-full load transient and observe It is recommended that an additional small capacitor be the output voltage ripple envelope for overshoot and placed in parallel with C in order to fi lter high frequency OUT ringing. Ringing for more than one cycle after the initial switching noise. step is an indication that the ESR should be increased. Stability Considerations One simple way to solve this problem is to add trace resis- Unstable operation is possible with adaptive on-time con- tance in the high current output path. A side eff ect of trollers, and usually takes the form of double-pulsing or adding trace resistance is a decrease in load regulation. ESR loop instability. ESR Requirements Double-pulsing occurs due to switching noise seen at the A minimum ESR is required for two reasons. One reason is FB input or because the FB ripple voltage is too low. This to generate enough output ripple voltage to provide causes the FB comparator to trigger prematurely after the 10mVp-p at the FB pin (after the resistor divider) to avoid minimum off -time has expired. In extreme cases the noise double-pulsing. can cause three or more successive on-times. Double- pulsing will result in higher ripple voltage at the output, The second reason is to prevent instability due to insuffi - but in most applications it will not aff ect operation. This cient ESR. The on-time control regulates the valley of the form of instability can usually be avoided by providing the output ripple voltage. This ripple voltage is the sum of the FB pin with a smooth, clean ripple signal that is at least two voltages. One is the ripple generated by the ESR, the 10mVp-p, which may dictate the need to increase the ESR other is the ripple due to capacitive charging and dis- of the output capacitors. It is also imperative to provide a charging during the switching cycle. For most applica- proper PCB layout as discussed in the Layout Guidelines tions, the total output ripple voltage is dominated by the section. output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be Another way to eliminate doubling-pulsing is to add a lower than approximately one-third the switching fre- small (~ 10pF) capacitor across the upper feedback resis- quency. The formula for minimum ESR is shown by the tor, as shown in Figure 13. This capacitor should be left following equation. unpopulated unless it can be confirmed that double- pulsing exists. Adding the C capacitor will couple more TOP 3 ripple into FB to help eliminate the problem. An optional ESR MIN 2uSuC u f connection on the PCB should be available for this OUT sw capacitor. 24 SC414/SC424 Applications Information (continued) comparator off set is trimmed so that under static condi- Using Ceramic Output Capacitors tions it trips when the feedback pin is 750mV, 1%. When applications use ceramic output capacitors, the ESR is normally too small to meet the previously stated ESR The on-time pulse from the SC414/SC424 in the design criteria. In these applications it is necessary to add a small example is calculated to give a pseudo-fi xed frequency of virtual ESR network composed of two capacitors and one 250kHz. Some frequency variation with line and load is resistor, as shown in Figure 14. This network creates a expected. This variation changes the output ripple ramp voltage across C , analogous to the ramp voltage L voltage. Because constant on-time converters regulate to generated across the ESR of a standard capacitor. This the valley of the output ripple, ½ of the output ripple ramp is then capacitively coupled into the FB pin via appears as a DC regulation error. For example, if the capacitor C . C output ripple is 50mV with V = 6 volts, then the measured IN DC output will be 25mV above the comparator trip point. L If the ripple increases to 80mV with V = 25V, then the IN High- measured DC output will be 40mV above the comparator side trip. The best way to minimize this eff ect is to minimize C R L L the output ripple. R1 C C C To compensate for valley regulation, it may be desirable to Low- OUT use passive droop. Take the feedback directly from the side R2 output side of the inductor and place a small amount of FB trace resistance between the inductor and output capaci- pin tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- Figure 14 — Virtual ESR Ramp Current tance because the voltage excursions due to load steps are reduced as seen at the load. Output Voltage Dropout The output voltage adjustable range for continuous-con- The use of 1% feedback resistors may result in up to an duction operation is limited by the fi xed 320ns (typical) additional 1% error. If tighter DC accuracy is required, minimum off -time. When working with low input volt- resistors with lower tolerances should be used. ages, the duty-factor limit must be calculated using worst- case values for on and off times. The output inductor value may change with current. This will change the output ripple and therefore will have a The duty-factor limitation is shown by the next equation. minor eff ect on the DC output voltage. The output ESR also aff ects the output ripple and thus has a minor eff ect T on the DC output voltage. ON(MIN) DUTY T  T ON(MIN) OFF(MIN) Switching Frequency Variations The inductor resistance and MOSFET on-state voltage The switching frequency will vary depending on line and drops must be included when performing worst-case load conditions. The line variations are a result of fi xed dropout duty-factor calculations. propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As System DC Accuracy — V Controller V increases, these factors make the actual DH on-time OUT IN Three factors aff ect V accuracy: the trip point of the FB slightly longer than the ideal on-time. The net eff ect is OUT error comparator, the ripple voltage variation with line that frequency tends to falls slightly with increasing input and load, and the external resistor tolerance. The error voltage. 25 CBST SC414/SC424 Applications Information (continued) The switching frequency also varies with load current as a lator with a maximum current of 6A. The total PCB area is result of the power losses in the MOSFETs and the induc- approximately 20 x 25 mm. tor. For a conventional PWM constant-frequency con- Critical Layout Guidelines verter, as load increases the duty cycle also increases The following critical layout guidelines must be followed slightly to compensate for IR and switching losses in the to ensure proper performance of the device. MOSFETs and inductor. A constant on-time converter must also compensate for the same losses by increasing • IC Decoupling capacitors the effective duty cycle (more time is spent drawing • PGND plane energy from V as losses increase). The on-time is essen- IN • AGND island tially constant for a given V and V combination, to OUT IN • FB, VOUT, and other analog control signals off set the losses the off -time will tend to reduce slightly as • BST, ILIM, and LX load increases. The net eff ect is that switching frequency • Capacitors and Current Loops increases slightly with increasing load. IC Decoupling Capacitors PCB Layout Guidelines • A 0.1 μF capacitor must be located as close as The optimum layout for the SC414/SC424 is shown in possible to the IC and directly connected to pins Figure 15. This layout shows an integrated FET buck regu- 2 (V5V) and 3 (AGND). RES_GND — AGND connects AGND plane on to PGND close to SC414/SC424 inner layer Pin 1 marking RILIM SC414/SC424 with All components RFB1 RFB2 vias for LX, AGND, shown Top Side CFF VIN C IN V plane on inner IN or bottom layer PGND C OUT VOUT Plane PGND on inner on Top layer or bottom layer L LX plane on inner or bottom layer Note: This figure is not to scale Figure 15 — PCB Layout 26 SC414/SC424 Applications Information (continued) • All other decoupling capacitors must be located • R should be close to the IC and connected to ILIM as close as possible to the IC. LXS with a Kelvin trace to pin 24 on the IC. This will be a suffi cient connection and will prevent PGND Plane the need to connect the resistor further into the • PGND requires its own copper plane with no LX plane. other signal traces routed on it. • The feedback components for the switcher need • Copper planes, multiple vias, and wide traces are to be as close to the FB pin of the IC as possible needed to connect PGND to input capacitors, to reduce the possibility of noise corrupting output capacitors, and the PGND pins on the IC. these analog signals. • The PGND copper area between the input capacitors, output capacitors, and PGND pins BST, ILIM and LX must be as small as and as compact as possible • LX and BST are very noisy nodes and must be to reduce the area of the PCB that is exposed to carefully routed to minimized the PCB area that noise due to current fl ow on this node. is exposed to these signals. • Connect PGND to AGND with a short trace or • The connections for the boost capacitor 0Ω resistor. This connection should be as close between the IC and LX must be short and directly to the IC as possible. connected to the LXBST (pin 12). • The connections for the current limit resistor AGND Island between the ILIM pin and LX must be as short as • AGND should have its own island of copper with possible and directly connected to pin 24 (LXS). no other signal traces routed on this layer that • The LX node between the IC and the inductor connects the AGND pins and pad of the IC to the should be wide enough to handle the inductor analog control components. current and short enough to eliminate the pos- • All of the components for the analog control cir- sibility of LX noise corrupting other signals. cuitry should be located so that the connections • Multiple vias should be used to provide a good to AGND are done by wide copper traces or vias connection to LX between the IC and the down to AGND. inductor. • Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to Capacitors and Current Loops the IC as possible. • The current loops between the input capacitors, the IC, the inductor, and the output capacitors FB, VOUT, and Other Analog Control Signals must be as close as possible to each other to • The connection from the V power to the OUT reduce IR drop across the copper. analog control circuitry must be routed from the • All bypass and output capacitors must be con- output capacitors and located on a quiet layer. nected as close as possible to the respective pin • The traces between VOUT and the analog control on the IC. circuitry (VOUT, and FB pins) must be short and routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. • ILIM and TON nodes must be as short as possible to ensure the best accuracy in current limit and on time. 27 SC414/SC424 Outline Drawing — MLPQ-4x4-28 B AD DIMENSIONS MILLIMETERS DIM MIN NOM MAX - A 0.80 1.00 - A1 0.00 0.05 - - A2 (0.20) PIN 1 b 0.17 0.23 0.29 E INDICATOR D 3.90 4.00 4.10 (LASER MARK) D1 0.96 1.06 1.16 E 3.90 4.00 4.10 E1 2.48 2.58 2.68 e 0.45 BSC L 0.30 0.40 0.50 N 28 A1 aaa 0.08 A2 bbb 0.10 A SEATING PLANE aaa C C 2.58 1.29 D1 LxN e 0.73±0.10 1.29 E1 1.45±0.10 2 E/2 1 N bxN R 0.20 D1 bbb C A B PIN 1 IDENTIFICATION D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 28 SC414/SC424 Land Pattern — MLPQ-4x4-28 1.29 K X DIMENSIONS DIM MILLIMETERS (3.95) C G 3.20 1.29 H2 2.58 H G (C) Z H H1 0.73 H2 1.45 H1 K 1.06 P 0.45 Y X 0.30 0.75 Y P Z 4.70 K 2.58 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 29