SEMTECH SC403B

SC403B ® 6A EcoSpeed Integrated FET Regulator with Programmable LDO POWER MANAGEMENT Features Description  Power System: ® The SC403B is a stand-alone synchronous EcoSpeed buck • Input voltage — 3V to 28V power supply which incorporates Semtech’s advanced • Internal or external bias voltage — 3V to 5.5V patented adaptive on-time control architecture. It pro- • Reference Voltage — 600mV vides excellent light-load efficiency and fast transient • Integrated bootstrap switch response. It features integrated power MOSFETs, a boot- • Programmable LDO output — 200mA strap switch, and a programmable LDO in a 5x5mm • 1% reference tolerance -40 to +85 °C package. The device is highly efficient and uses minimal ® • EcoSpeed architecture with pseudo-fixed fre- PCB area. quency adaptive on-time control The SC403B supports using standard capacitor types such  Logic Input/Output Control: as electrolytic or special polymer, in addition to ceramic, at • Independent control EN for LDO and switcher switching frequencies up to 1MHz. The programmable • Programmable V UVLO threshold IN frequency, synchronous operation, and selectable power- • Power good output save provide high efficiency operation over a wide load • Selectable power save mode range. • Programmable soft start time  Protections: Additional features include a programmable soft-start, • Over-voltage and under-voltage programmable cycle-by-cycle over-current limit protec- • TC compensated R sensed current limit DS(ON) tion, under and over-voltage protections, soft shutdown, • Thermal shutdown and selectable power-save. The device also provides sep-  Any ESR — SP, POSCAP, OSCON, and ceramic capacitors arate enable inputs for the PWM controller and LDO as  Package: well as a power good output for the PWM controller. • Lead-free package — 5x5mm, 32-pin MLPQ • Fully RoHS/WEEE compliant and halogen-free The wide input and bias voltage ranges, programmable Applications frequency, and programmable LDO make the device extremely flexible and easy to use in a broad range of  Office automation and computing applications. The SC403B can be used in server computers  Networking and telecommunication equipment and single cell or multi-cell battery systems in addition to  Point of load power supplies and module replacement traditional DC power supply applications. Typical Application Circuit ENABLE/PSAVE RILIM ENABLE LDO ENL LXS RTON TON PGOOD PGOOD VOUT 10Ω VDD VEXT/LDO L1 VOUT LX SC403B 1µF CSOFT COUT + SS RFB1 BST FB RFB2 VIN VIN CIN CBST US Patent: 2010/0033215A1 © 2011 Semtech Corporation Rev. 2.1 1 LXBST EN/PSV AGND ILIM PGND SC403B Pin Configuration Ordering Information Device Package (1)(2) SC403BMLTRT MLPQ-32 5X5 32 31 30 29 28 27 26 25 SC403BEVB Evaluation Board Top View 1 24 FB LX 23 VOUT 2 LX AGND PAD 1 VDD 3 22 PGND Notes: AGND 4 21 PGND 1) Available in tape and reel only. A reel contains 3000 devices. LX PAD 3 2) Lead-free package only. Device is RoHS/WEEE compliant and FBL 5 20 PGND halogen-free. 6 19 PGND VIN VIN PAD 2 7 18 SS PGND 8 17 BST PGND 9 10 11 12 13 14 15 16 SC403B MLPQ-32; 5x5, 32 LEAD Marking Information SC403B yyww xxxxxx xxxxxx yyww = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number 2 VIN ENL VIN TON VIN AGND NC EN/PSV LXBST LXS NC ILIM PGND PGOOD PGND LX SC403B Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30 VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5 EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(V + 0.3) DD Thermal Information SS, VOUT, FB, FBL, to GND (V) . . . . . . . . . -0.3 to +(V + 0.3) DD Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150 VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150 TON to AGND (V). . . . . . . . . . . . . . . . . . . . . -0.3 to +(VDD - 1.5) Operating Junction Temperature (°C) . . . . . . -40 to +125 ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V IN (2) Thermal resistance, junction to ambient (°C/W) BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 (1) PWM controller and LDO thermal resistance . . . . . 36 ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specified: V =12V, T = +25°C for Typ, -40 to +85 °C for Min and Max, T < 125°C, V = +5V, per applicable Detailed Application Circuit IN A J DD Parameter Conditions Min Typ Max Units Input Supplies Sensed at ENL pin, rising edge 2.40 2.60 2.95 ) VIN UVLO Threshold V Sensed at ENL pin, falling edge 2.235 2.40 2.565 VIN UVLO Hysteresis EN/PSV = High 0.2 V Measured at VDD pin, rising edge 2.5 3.0 VDD UVLO Threshold V Measured at VDD pin, falling edge 2.4 2.9 VDD UVLO Hysteresis 0.2 V ENL , EN/PSV = 0V, V = 28V 8.5 20 IN VIN Supply Current μA Standby mode; ENL=V , EN/PSV = 0V 130 DD 3 SC403B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) ENL , EN/PSV = 0V, V from external source 190 300 DD (2) EN/PSV = V , no load, V > 600mV 0.7 DD FB V = 5V, f = 250kHz, EN/PSV = floating , no load 4 mA DD SW V = 3V, f = 250kHz, EN/PSV = floating , no load 2.5 DD SW Static V and load, 0 to +85 °C 0.595 0.600 0.605 V IN FB On-Time Threshold Static V and load, -40 to +85 °C 0.594 0.606 V IN Continuous mode operation 1000 Frequency Range kHz Minimum f , EN/PSV = V , no load 25 SW DD Bootstrap Switch Resistance 10 Ω Switching MOSFET Resistance High Side FET 30 R mΩ DSON Low Side FET 10 Timing Continuous mode operation, 2386 2650 2915 V = 15V, V = 5V, f = kHz, R = 300kΩ IN OUT SW TON On-Time ns (3) 3V < V < 4.5V DD Minimum On-Time 80 ns V = 5V 250 DD Minimum Off-Time ns V = 3V 370 DD Soft-Start Soft-Start Current 3 μA Soft-Start Voltage When V reaches regulation 1.5 V OUT Analog Inputs/Outputs VOUT Input Resistance 500 kΩ 4 SC403B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Current Sense Zero-Crossing Detector Threshold LX - PGND -3 0 +3 mV Power Good Upper limit, V > internal reference +20 % FB Power Good Threshold Lower limit, V < internal reference -10 % FB V = 3V, C = 10nF 7 DD SS Start-Up Delay Time (between PWM enable and ms PGOOD going high) V = 5V, C = 10nF 12 DD SS Soft Start Threshold When PGOOD logic switches high 64 % Fault (noise immunity) Delay Time 5 µs Leakage 1 µA Power Good On-Resistance 10 Ω Fault Protection V = 5V,R = 7.06k Ω 4.8 6 7.2 DD ILIM Valley Current Limit A V = 3V,R = 7.06k Ω 5.1 DD ILIM V with respect to internal reference, FB Output Under-Voltage Fault -25 % 8 consecutive switching cycles Smart Power-save Protection Threshold V with respect to internal reference +10 % FB Over-Voltage Protection Threshold V with respect to internal reference +20 % FB Over-Voltage Fault Delay 5 μs Over-Temperature Shutdown 10°C hysteresis 155 °C Logic Inputs/Outputs Logic Input High Voltage ENL, minimum level 1 V Logic Input Low Voltage ENL, maximum level 0.4 V Maximum level expressed in % of V 100 DD EN/PSV Input for PSAVE Operation % Minimum level expressed in % of V 45 DD 5 SC403B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Logic Inputs/Outputs (continued) Maximum level expressed in % of V 42 % DD EN/PSV Input for Forced Continuous Operation Minimum level 1 V Maximum level 0.4 EN/PSV Input for Disabling Switcher V Minimum level 0 EN/PSV Input Bias Current EN/PSV= VDD or AGND -10 +10 μA ENL Input Bias Current V = 16V 11 18 μA IN FBL, FB Input Bias Current FBL, FB = VDD or AGND -1 +1 μA Linear Regulator (The LDO is shorted to the VDD pin internally.) FBL Accuracy LDO load = 10mA 0.735 0.75 0.765 V Short-circuit protection, V = 12V, V < 0.75V 65 IN DD Start-up and foldback, V = 12V, IN 115 LDO Current Limit mA 0.75 < V < 90% of final V value DD DD Operating current limit, V = 12V, V > 90% of final IN DD 135 200 V value DD (4) LDO to VOUT Switch-over Threshold -140 +140 mV (4) LDO to VOUT Non-switch-over Threshold -450 +450 mV LDO to VOUT Switch-over Resistance V = +5V 2 Ω OUT (5) LDO Drop Out Voltage From V to V , V = +5V, I = 100mA 1.2 V IN DD DD LDO Notes: (1) V UVLO is programmable using a resistor divider from VIN to ENL to AGND pins. The ENL voltage is compared to an internal reference. IN (2) For V > 0.750V for the SC403 and V > 0.600V FB FB (3) For VDD less than 4.5V, the on-time may be limited by the VDD supply voltage and by the V . See the TON limitation and VDD supply voltage IN section in the applications Information. (4) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that LDO will internally switch- over to VOUT. The non-switch-over threshold is the minimum voltage differential between the LDO and VOUT pins which ensures that LDO will not switch-over to VOUT. (5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the no load regulation value. 6 SC403B Detailed Application Circuit — 1 Internal LDO Used as Bias ENABLE ENABLE/ LDO PSAVE PGOOD RILIM 8.06KΩ RTON 32 31 30 29 28 27 26 25 130KΩ PAD 1 AGND 1 24 FB LX 2 23 LX VOUT 3 22 VDD PGND 4 21 AGND PGND 5 20 RLDO1 SC403B FBL PGND 425KΩ 6 19 VIN PGND 7 18 SS PGND 8 17 BST PGND RLDO2 1µF 3.3nF 1µF PAD 3 75KΩ LX CBST PAD 2 9 10 14 15 16 11 12 13 1µF VIN CIN +12V 2 x 10µF RGND (see note) 0 1.2V @ 6A, 300kHz L1 1.5µH COUT + VOUT 330µF 10nF 9mΩ RFB1 10KΩ RFB2 10KΩ Key Components Component Value Manufacturer Part Number Web CIN 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com Panasonic EEF-SX0E331ER www.panasonic.com COUT 330µF/9mΩ L1 Cyntec PCMB065T-1R5MS www.cyntec.com 1.5µH/6.7mΩ 7 VIN VIN ENL VIN TON VIN AGND NC EN/PSV LXBST LXS NC ILIM PGND PGOOD PGND LX SC403B Detailed Application Circuit — 2 External 5V Used as Bias ENABLE/ PSAVE PGOOD RILIM 8.06KΩ RTON 32 31 30 29 28 27 26 25 130KΩ PAD 1 AGND 24 1 FB LX 2 23 5V LX VOUT 3 22 VDD PGND 4 21 10Ω AGND PGND 5 20 SC403B FBL PGND 6 19 VIN PGND 7 18 SS PGND 8 17 BST PGND 1µF 3.3nF 1µF PAD 3 LX CBST PAD 2 9 12 13 15 16 10 11 14 1µF VIN CIN +12V 2 x 10µF RGND (see note) 0 1.2V @ 6A, 300kHz L1 COUT 1.5µH + VOUT 330µF 15mΩ 10nF RFB1 10KΩ RFB2 10KΩ Key Components Component Value Manufacturer Part Number Web CIN 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com COUT 330µF/9mΩ Panasonic EEF-SX0E331ER www.panasonic.com L1 1.5µH/6.7mΩ Cyntec PCMB065T-1R5MS www.cyntec.com 8 VIN VIN ENL VIN TON VIN AGND NC EN/PSV LXBST LXS NC ILIM PGND PGOOD PGND LX SC403B Typical Characteristics Characteristics in this section are based on using the applicable Detailed Application Circuit — 2. Efficiency vs. Load — Forced Continuous Mode V vs. Load — Forced Continuous Mode OUT V = 1.2V, V = 5V, EN/PSV is floating, external bias V = 1.2V, V = 5V, EN/PSV is floating, external bias OUT DD OUT DD 100% 2.5 1.26 0.15 VIN = 12V 1.24 0.125 80% 2 Efficiency Regulation V = 20V IN VIN = 12V 1.22 0.1 60% 1.5 VIN = 6V V = 20V IN 1.20 0.075 V = 6V IN 40% 1 PLOSS 1.18 0.05 V = 12V IN VIN = 20V VIN = 12V 20% 0.5 V = 20V IN 1.16 0.025 V PEAK VIN = 6V V = 6V IN 1.14 0 0% 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 I (A ) IOUT (ADC) OUT DC V vs. Load — PSAVE Mode Efficiency vs. Load — PSAVE Mode OUT V = 1.2V, V = 5V = EN/PSV, external bias V = 1.2V, V = 5V, = EN/PSV, external bias OUT DD OUT DD 100 2.5 1.26 0.12 Efficiency 1.24 0.1 80 2 V = 6V IN Regulation V = 12V IN V = 12V IN 1.22 0.08 60 1.5 V = 20V IN VIN = 20V 1.20 0.06 V = 6V IN VIN = 20V 40 1 1.18 0.04 VIN = 12V V = 20V IN 20 0.5 1.16 0.02 VIN = 12V V = 6V IN PLOSS VPEAK V = 6V IN 0 0 1.14 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 IOUT (ADC) IOUT (ADC) Efficiency vs. Load — PSAVE Mode V vs. Load — PSAVE Mode OUT V = 1.2V, V = 12V, EN/PSV = V , external bias V = 1.2V, V = 12V, EN/PSV = V , external bias OUT IN DD OUT IN DD 100 2.5 1.26 0.12 V = 5V DD 1.24 0.1 80 2 Regulation Efficiency V = 3.3V DD 1.22 0.08 VDD = 3.3V 60 1.5 1.20 0.06 V = 5V DD 40 1 VDD = 3.3V PLOSS 1.18 0.04 20 0.5 1.16 0.02 V = 5V DD V = 5V DD V PEAK V = 3.3V DD 0 0 1.14 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 I (A ) IOUT (ADC) OUT DC 9 Eff (%) Eff (%) Eff (%) PLOSS (W) PLOSS (W) PLOSS (W) VOUT (VDC) VOUT (VDC) VOUT (VDC) Vpeak (Vrms) Vpeak (Vrms) Vpeak (Vrms) SC403B Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit — 2. Frequency vs. Load — PSAVE Mode Frequency vs. Load — Forced Continuous Mode V = 1.2V, V = 5V, EN/PSV is floating, external bias V = 1.2V, V = EN/PSV = 5V, external bias OUT DD OUT DD 400 400 350 350 V = 12V IN 300 300 V = 6V IN 250 250 V = 20V IN VIN = 20V V = 12V IN 200 200 V = 6V IN 150 150 100 100 50 50 0 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 I (A ) OUT DC IOUT (ADC) Frequency vs. Line — FCM Mode V vs. Line — Forced Continuous Mode OUT V = 1.5V, V = V = ENL = 5V, EN/PSV is floating V = 1.5V, V = V = ENL = 5V, EN/PSV is floating OUT LDO DD OUT LDO DD 400 1.575 150 350 1.550 125 300 1.525 100 250 V OUT 1.500 75 200 150 1.475 50 VPKPK 100 1.450 25 50 1.425 0 0 6.0 8.8 11.5 14.3 17.0 19.8 22.5 25.3 6.0 8.8 11.5 14.3 17.0 19.8 22.5 25.3 28.0 28.0 V (V ) V (V ) IN DC IN DC On Time vs. Line V = 1.5V, V = V = ENL = 5V, I = 0A OUT LDO DD OUT 1200 1000 800 600 3.3V 400 5V 200 0 6.0 8.8 11.5 14.3 17.0 19.8 22.5 25.3 28.0 Input Voltage (V) 10 V (V ) OUT DC fSW (kHz) On-Time (ns) VPK_PK (mV ) RMS fSW (kHz) Frequency (HZ) SC403B Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit — 2. Powersave Mode — No Load Forced Continuous Mode — No Load V = 12V, V = 1.2V, I = 0A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1.5V, I = 0A, V = V = ENL = 3.3V, EN/PSV= floating IN OUT OUT LDO DD IN OUT OUT LDO DD (20mV/div) (20mV/div) (10V/div) (10V/div) Time (10µs s/div) /div) /div) Time (10µs s/div) /div) /div) Self-Biased Start-Up — Power Good True Enabled Loaded Output V = 0V to 12V step, V = 1.2V, I = 0A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1.2V, I = 1A, V = V = ENL = EN/PSV= 5V IN OUT OUT LDO DD IN OUT OUT LDO DD (10V/div) (10V/div) (500mV/div) (500mV/div) (5V/div) (5V/div) (5V/div) Time (1ms s/div) /div) /div) Time (1ms s/div) /div) /div) Self-Biased Start-Up — Power Good True Self-Biased Start-Up — Power Good True V = 12V step, V = 1.2V, I = 0A, external V = EN/PSV= 5V V = 12V step, V = 1.2V, I = 300mA, external V = EN/PSV= 5V IN OUT OUT DD IN OUT OUT DD (20mV/div) (20mV/div) (10V/div) (10V/div) Time (4ms s/div) /div) /div) Time (4µs s/div) /div) /div) 11 SC403B Typical Characteristics (continued) Characteristics in this section are based on using the applicable Detailed Application Circuit — 2. Output Under-voltage Response — Normal Operation Output Over-current Response — Normal Operation V = 12V, V = 1.5V, I = 0A, V = V = ENL = 3.3V, floating EN/PSV V = 12V, V = 1.5V, V = V = ENL = 3.3V, EN/PSV= floating; I ramped to trip point IN OUT OUT LDO DD IN OUT LDO DD OUT (500mV/div) (10V/div) (500mV/div) (5A/div) (10V/div) (5V/div) (5V/div) Time (100µs s/div) /div) /div) Time (100µs s/div) /div) /div) Shorted Output Response — Normal Operation Shorted Output Response — Soft-start Operation V = 12V, V = 1.5V, V = V = ENL = 3.3V, EN/P5V is floating V = 12V, V = 1.5V, I = 0A, V = V = EN/PSV= ENL = 3.3V IN OUT LDO DD IN OUT OUT LDO DD (1V/div) (1V/div) (10A/div) (10A/div) (10V/div) (5V/div) (5V/div) (5V/div) Time (40µs s/div) /div) /div) Time (400µs s/div) /div) /div) Transient Response Transient Response V = 12V, V = 1.2V, I = 0A to 6A, V = V = EN/PSV= ENL = 5V V = 12V, V = 1.2V, I = 6A to 0A, V = V = EN/PSV= ENL = 5V IN OUT OUT LDO DD IN OUT OUT LDO DD (50mV/div) (50mV/div) (10V/div) (10V/div) Time (40µs s/div) /div) /div) Time (40µs s/div) /div) /div) 12 SC403B Pin Descriptions Pin # Pin Name Pin Function Feedback input for switching regulator used to program the output voltage — connect to an external resis- 1 FB tor divider from VOUT to AGND. Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO. 2 VOUT The voltage at this pin must be less than or equal to the voltage at the VDD pin. Bias supply for the IC — when using the internal LDO as a bias power supply, the VDD is the LDO output. 3 VDD When using an external power supply to bias the IC, the LDO output should be disabled. 4, 30, PAD 1 AGND Analog ground Feedback input for the internal LDO — connect to an external resistor divider from VDD to AGND to pro- 5 FBL gram the LDO output. 6, 9-11, VIN Input supply voltage PAD 2 7 SS The soft start time is programmed by an internal current source charging a capacitor on this pin. Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the 8 BST high-side gate drive. 12 NC No connection 13 LXBST LX Boost — connect to the BST capacitor. 23-25, PAD 3 LX Switching (phase) node 14 NC No connection 15-22 PGND Power ground Open-drain power good indicator — high impedance indicates power is good. An external pull-up 26 PGOOD resistor is required. 27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS. 28 LXS LX sense — connects to R . ILIM Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator. 29 EN/PSV Float to operate in forced continuous mode (PSAVE disabled). Connect to VDD to operate with PSAVE mode enabled. 31 TON On-time programming input — set the on-time by connecting through a resistor to AGND. Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic con- 32 ENL trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND pins. 13 SC403B Block Diagram PGOOD EN/PSV VIN 26 29 A V IN VDD VDD Bootstrap Switch 8 BST AGND D Reference Control & Status VDD DL 12 NC Hi-side SS 7 Soft Start MOSFET B LX Gate Drive On- - time Control FB 1 Generator 13 LXBST VDD FB Comparator 28 LXS DL Lo-side TON 31 MOSFET Zero Cross Detector C PGND 2 VOUT B By yp pa as ss s C Co om mp pa ar ra atto or r Valley Current Limit 27 ILIM VDD A V IN 3 VDD Y B LDO 14 NC VLDO Switchover MUX FBL 5 32 ENL A = connected to pins 6, 9-11, PAD 2 B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 14 SC403B Applications Information Synchronous Buck Converter Psuedo-fixed Frequency Adaptive On-time Control The SC403B is a step down synchronous DC-DC buck The PWM control method used by the SC403B is pseudo- converter with integrated power MOSFETs and a 200mA fixed frequency, adaptive on-time, as shown in Figure 1. programmable LDO. The device operates at a current up The ripple voltage generated at the output capacitor ESR to 6A at very high efficiency. A space saving 5x5 (mm) 32- is used as a PWM ramp signal. This ripple is used to trigger pin package is used. The programmable operating fre- the controller on-time. quency of up to 1MHz enables optimizing the TON configuration for PCB area and efficiency. V IN V LX The buck controller uses a pseudo-fixed frequency adap- C IN tive on-time control. This control method allows fast tran- Q1 V FB FB Threshold sient response which permits the use of smaller output V LX capacitors. V OUT L In addition to the following information, the user can ESR Q2 click on the applicable link to go to the SC403B online FB C-SIM design and simulation tool, which will lead the + C OUT user through the design process. Input Voltage Requirements The SC403B requires two input supplies for normal opera- tion: V and V . V operates over a wide range from 3V to IN DD IN Figure 1 — PWM Control Method, V Ripple OUT 28V. VDD requires a supply voltage between 3V to 5V that The adaptive on-time is determined by an internal one- can be an external source or the internal LDO from V . IN shot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- Power Up Sequence side MOSFET. The pulse period is determined by V and OUT The SC403B initiates a start up when VIN, VDD, and EN/ V . The period is proportional to output voltage and IN PSV pins are above the applicable thresholds. When using inversely proportional to input voltage. With this adaptive an external bias supply for the V voltage, it is recom- DD on-time arrangement, the device automatically antici- mended that the V is applied to the device only after DD pates the on-time needed to regulate V for the present OUT the V voltage is present because V cannot exceed V IN DD IN V condition and at the selected frequency. IN at any time. A 10Ω resistor must be placed between the external V supply and the VDD pin to avoid damage to DD The advantages of adaptive on-time control are: the device during power-up and or shutdown situations where V could exceed V unexpectedly. DD IN • Predictable operating frequency compared to other variable frequency methods. Shutdown • Reduced component count by eliminating the The SC403B can be shutdown by pulling either VDD or error amplifier and compensation components. EN/PSV pin below its threshold. When using an external • Reduced component count by removing the supply voltage for V , the VDD pin must be deactivated DD need to sense and control inductor current. while the V voltage is still present. A 10Ω resistor must IN • Fast transient response — the response time is be placed between the external V supply and the VDD DD controlled by a fast comparator instead of a typi- pin to avoid damage to the device. cally slow error amplifier. • Reduced output capacitance due to fast tran- When the VDD pin is active and EN/PSV is at low logic level, sient response the output voltage discharges through an internal FET. 15 SC403B Applications Information (continued) Immediately after the on-time, the DL (drive signal for the One-Shot Timer and Operating Frequency low side FET) output drives high to turn on the low-side One-shot timer operation is shown in Figure 2. The FB MOSFET. DL has a minimum high time of ~320ns, after Comparator output goes high when V is less than the FB which DL continues to stay high until one of the following internal reference. This feeds into the gate drive and turns occurs: on the high-side MOSFET, and starts the one-shot timer. The one-shot timer uses an internal comparator and a • VFB falls below the reference capacitor. One comparator input is connected to V , the OUT • The zero cross detector senses that the voltage other input is connected to the capacitor. When the on- on the LX node is below ground. Power save is time begins, the internal capacitor charges from zero volts activated eight switching cycles after a zero through a current which is proportional to V . When the IN capacitor voltage reaches V , the on-time is completed crossing is detected. OUT and the high-side MOSFET turns off. TON Limitations and V Supply Voltage DD Gate For V below 4.5V, the TON accuracy may be limited by V Drives DD IN FB Comparator the input voltage. - FB + Q1 DH V L OUT V LX The original R equation is accurate if V satisfies the TON IN relationship over the entire V range, as follows. V OUT ESR IN FB One-Shot Q2 V IN + DL C OUT Timer V < (V - 1.6V) x 10 IN DD R TON On-time = K x R x (V /V ) TON OUT IN If V exceeds (V - 1.6V) x 10, for all or part of the V IN DD IN range, the R equation is not accurate. In all cases where Figure 2 — On-Time Generation TON V > (V - 1.6V) x 10, the R equation must be modified, IN DD TON This method automatically produces an on-time that is as follows. proportional to V and inversely proportional to V . OUT IN Under steady-state conditions, the switching frequency (T 10ns)u(V 1.6V)u10 ON DD can be determined from the on-time by the following R TON 25pFuV OUT equation. V Note that when V > (V - 1.6V) x 10 , the actual on-time OUT IN DD f SW T uV is fixed and does not vary with V . When operating in this ON IN IN condition, the switching frequency will vary inversely with The SC403B uses an external resistor to set the on-time V rather than approximating a fixed frequency. IN which indirectly sets the frequency. The on-time can be programmed to provide an operating frequency from V Voltage Selection OUT 200kHz to 1MHz using a resistor between the TON pin and The switcher output voltage is regulated by comparing ground. The resistor value is selected by the following V as seen through a resistor divider at the FB pin to the OUT equation. internal reference voltage, see Figure 3. (t 10ns)uV ON IN R TON 25pFuV OUT To FB pin V OUT R 1 The maximum R value allowed is shown by the follow- R TON 2 ing equation. V IN_MIN R TON_MAX 10u1.5PA Figure 3 — Output Voltage Selection 16 SC403B Applications Information (continued) Note that this control method regulates the valley of the FB Ripple FB threshold Voltage (V ) output ripple voltage, not the DC value. The DC output FB voltage V is offset by the output ripple according to the OUT following equation. § · R § V · 1 RIPPLE Inductor DC Load Current V V u¨1 ¸ ¨ ¸ OUT FB ¨ ¸ R 2 Current © ¹ © 2 ¹ When a large capacitor is placed in parallel with R1 (C ) TOP V is shown by the following equation. OUT DH on-time is triggered when On-time 2 V reaches the FB Threshold. § R · V 1(RZC ) (T ) § · ON FB 1 RIPPLE 1 TOP ¨ ¸ V V u 1 ¨ ¸u OUT FB ¨ ¸ 2 R 2 © ¹ © 2¹ §R uR · 2 1 ¨ ¸ 1 ZC TOP ¨ ¸ R R DH © 2 1 ¹ Enable and Power Save Input DL The EN/PSV input is used to enable or disable the switch- ing regulator. When EN/PSV is low (grounded), the switch- ing regulator is off and in its lowest power state. When off, DL drives high when on-time is completed. the output of the switching regulator soft-discharges the DL remains high until V falls to the FB threshold. FB output into a 15Ω internal resistor via the V pin. When OUT Figure 4 — Forced Continuous Mode Operation EN/PSV is allowed to float, the pin voltage will float to 33% of the voltage at VDD. The switching regulator turns on Power-save Operation with PSAVE (power save) disabled and all switching is in The SC403B provides power-save operation at light loads forced continuous mode. with no minimum operating frequency. With power-save enabled, the internal zero crossing comparator monitors When EN/PSV is high (above 45% of the voltage at VDD), the inductor current via the voltage across the low-side the switching regulator turns on with power-save MOSFET during the off-time. If the inductor current falls to enabled. zero for 8 consecutive switching cycles, the controller enters power-save operation. It will turn off the low-side Forced Continuous Mode Operation MOSFET on each subsequent cycle provided that the current crosses zero. At this time both MOSFETs remain off The SC403B operates the switcher in FCM (Forced until V drops to the 600mV threshold. Because the FB Continuous Mode) by floating the EN/PSV pin (see Figure MOSFETs are off, the load is supplied by the output 4). In this mode one of the power MOSFETs is always on, capacitor. with no intentional dead time other than to avoid cross- conduction. This feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switch- ing of the MOSFETs. DH is the gate signal driving the upper MOSFET. DL is the lower gate signal driving the lower MOSFET. 17 SC403B Applications Information (continued) If the inductor current does not reach zero on any switch- V drifts up to due to leakage OUT current flowing into C V discharges via inductor OUT OUT ing cycle, the controller immediately exits power-save and and low-side MOSFET Smart Power Save returns to forced continuous mode. Threshold Normal V ripple OUT FB threshold Figure 5 shows power-save operation at light loads. DH and DL off Dead time varies High-side according to load Drive (DH) FB Ripple Voltage Single DH on-time pulse FB threshold (V ) FB after DL turn-off Low-side Drive (DL) Inductor Zero (0A) DL turns on when Smart Normal DL pulse after DH Current PSAVE threshold is reached on-time pulse DL turns off when FB threshold is reached On-time (T ) ON Figure 6 — Smart PSAVE DH On-time is triggered when V reaches the FB Threshold. FB DH TM SmartDrive For each DH pulse the DH driver initially turns on the high- DL side MOSFET at a lower speed, allowing a softer, smooth turn-off of the low-side diode. Once the diode is off and the LX voltage has risen 1V above PGND, the SmartDrive DL drives high when on-time is completed. DL remains high until inductor current reaches zero. circuit automatically drives the high-side MOSFET on at a rapid rate. This technique reduces switching power loss Figure 5 — PSAVE Operation while maintaining high efficiency and also avoids the Smart PSAVE Protection need for snubbers or series resistors in the gate drive. Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with Current Limit Protection PSAVE enabled, this can force V to slowly rise and reach Programmable current limiting is accomplished by using OUT the over-voltage threshold, resulting in a hard shutdown. the RDS of the lower MOSFET for current sensing. The ON Smart PSAVE prevents this condition. When the FB voltage current limit is set by the R resistor. The R resistor con- ILIM ILIM exceeds 10% above nominal, the device immediately dis- nects from the ILIM pin to the LXS pin which is also the drain ables PSAVE, and DL drives high to turn on the low-side of the low-side MOSFET. When the low-side MOSFET is on, MOSFET. This draws current from V through the induc- an internal ~10μA current flows from the ILIM pin and OUT tor and causes V to fall. When V drops back to the through the R resistor, creating a voltage drop across the OUT FB ILIM internal reference trip point, a normal t switching cycle resistor. While the low-side MOSFET is on, the inductor ON begins. This method prevents a hard OVP shutdown and current flows through it and creates a voltage across the also cycles energy from V back to V . It also minimizes RDS . The voltage across the MOSFET is negative with OUT IN ON operating power by avoiding forced conduction mode respect to ground. If this MOSFET voltage drop exceeds the operation. Figure 6 shows typical waveforms for the Smart voltage across R , the voltage at the ILIM pin will be nega- ILIM PSAVE feature. tive and current limit will activate. The current limit then keeps the low-side MOSFET on and will not allow another high-side on-time, until the current in the low-side MOSFET reduces enough to bring the ILIM voltage back up to zero. This method regulates the inductor valley current at the level shown by ILIM in Figure 7. 18 SC403B Applications Information (continued) is the soft start time (t ). The calculation for the soft-start SS I PEAK time is shown by the following equation. I LOAD 1.5V t C u I LIM SS SS 3PA The voltage at the SS pin continues to ramp up and eventu- ally is equal to 64% of V . After soft start completes, the FB DD Time pin voltage is compared to the internal reference. The delay time between the V regulation point and PGOOD going Figure 7 — Valley Current Limit OUT high is shown by the following equation. Setting the valley current limit to 6A results in a peak induc- tor current of 6A plus the peak-to-peak ripple current. In CSSu(0.64uV 1.5V) DD t PGOOD-DELAY this situation, the average (load) current through the induc- 3PA tor is 6A plus one-half the peak-to-peak ripple current. The internal 10μA current source is temperature compen- sated at 4100ppm in order to provide tracking with the (10mV/div) RDS . ON The R value is calculated by the following equation. ILIM (500mV/div) R = 1176 x I x [0.088 x (5V - V ) + 1] (Ω) (2V/div) ILIM LIM DD where I is in Amps. LIM (5V/div) Time (400µs/div) /div)s/div) When selecting a value for R do not exceed the absolute ILIM maximum voltage value for the ILIM pin. Note that because Figure 8 — Soft-start Timing Diagram the low-side MOSFET with low RDS is used for current ON Pre-Bias Startup sensing, the PCB layout, solder connections, and PCB connec- SC403B can start up as if in a soft-start condition with an tion to the LX node must be done carefully to optimize opera- existing output voltage level. The soft start time is still the tion. R should be connected directly to LXS (pin 28). ILIM same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up when Soft-Start of PWM Regulator 40% of the voltage at SS pin meets the pre-charge FB SC403B has a programmable soft-start time that is con- voltage level. Pre-bias startup is achieved by turning off trolled by an external capacitor at the SS pin. After the the lower gate when the inductor current falls below zero. controller meets both UVLO and EN/PSV thresholds, the This method prevents the output voltage from controller has an internal current source of 3µA flowing decreasing. through the SS pin to charge the capacitor. During the start up process (Figure 8), a percentage of the voltage at Power Good Output the SS pin is used as the reference for the FB comparator. The PGOOD (power good) output is an open-drain output The percentage is 50% for the SC403 and 40% for the which requires a pull-up resistor. When the voltage at the SC403B. The PWM comparator issues an on-time pulse FB pin is 10% below the nominal voltage, PGOOD is pulled when the voltage at the FB pin is less than 50% (or 40%) of low. It is held low until the output voltage returns above the SS pin. As result, the output voltage follows the SS 92% of nominal. start voltage. The output voltage reaches and maintains regulation when the soft start voltage is > 1.5V. The time between the first LX pulse and when V meets regulation OUT 19 Inductor Current SC403B Applications Information (continued) PGOOD will transition low if the V pin exceeds +20% of The LDO output voltage is set by the following equation. FB nominal, which is also the over-voltage shutdown thresh- old. PGOOD also pulls low if the EN/PSV pin is low when § · R LDO1 ¨ ¸ VLDO 750mVu 1 ¨ ¸ V voltage is present. R LDO2 © ¹ DD A minimum 1μF capacitor referenced to AGND is required Output Over-Voltage Protection along with a minimum 1.0μF capacitor referenced to Over-voltage protection becomes active as soon as the PGND to filter the gate drive pulses. The capacitance to device is enabled. The threshold is set at 20% above the PGND will need to increase to 10uF if VLDO is set to a feedback reference voltage. When V exceeds the OVP FB voltage lower than 4.5V. Refer to the layout guidelines threshold, DL latches high and the low-side MOSFET is section for component placement suggestions. turned on. DL remains high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is LDO ENL Functions a 5μs delay built into the OVP detector to prevent false The ENL input is used to control the internal LDO. When transitions. PGOOD is also low after an OVP event. ENL is low (grounded), the LDO is off. When ENL is above the V UVLO threshold, the LDO is enabled and the IN Output Under-Voltage Protection switcher is also enabled if EN/PSV and VDD meet the When V falls 25% below its nominal voltage for eight FB thresholds. consecutive switching cycles, the switcher is shut off and the DH and DL drives are pulled low to tri-state the The ENL pin also acts as the switcher UVLO (under-voltage MOSFETs. The controller stays off until EN/PSV is toggled lockout) for the V supply. The V UVLO voltage is pro- IN IN or VDD is cycled. grammable via a resistor divider at the VIN, ENL and AGND pins. VDD UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switch- If the ENL pin transitions from high to low within 2 switch- ing and tri-states the DH/DL drivers until V rises above DD ing cycles and is less than 1V, then the LDO will turn off 3.0V. An internal POR (Power-On Reset) occurs when V DD but the switcher remains on. If the ENL goes below the V IN exceeds 3.0V, which resets the fault latch and soft-start UVLO threshold and stays above 1V, then the switcher will counter to prepare for soft-start. The SC403B then begins turn off but the LDO remains on. The V UVLO function IN a soft-start cycle. The PWM will shut off if VDD falls below has a typical threshold of 2.6V on the V rising edge. The IN 2.4V. falling edge threshold is 2.4V. LDO Regulator Note that it is possible to operate the switcher with the SC403B has an option to bias the switcher by using an inter- LDO disabled, but the ENL pin must be below the logic nal LDO from V . The LDO output is connected to VDD IN low threshold (0.4V maximum). In this case, the UVLO internally. The output of the LDO is programmable by using function for the input voltage cannot be used. The table external resistors from the VDD pin to AGND. The feedback below summarizes the function of the ENL and EN pins, pin (FBL) for the LDO is regulated to 750mV (see Figure 9). with respect to the rising edge of ENL. VDD To FBL pin ENL LDO status Switcher status EN R LDO1 low low, < 0.4V off off R LDO2 high low, < 0.4V off on low high, < 2.6V on off high high, < 2.6V on off Figure 9 — LDO Voltage Divider low high, > 2.6V on off high high, > 2.6V on on 20 SC403B Applications Information (continued) Figure 10 shows the ENL voltage thresholds and their V Final VLDO effect on LDO and switcher operation. Voltage regulating with ~ 200mA 90% of current limit ENL voltage V Final VLDO LDO on Constant current Switcher on if EN = high startup @ ~ 115mA 0.7V Short-circuit Protection @ ~ 65mA 2.6V V UVLO hysteresis IN 2.4V Figure 11 — LDO Start-Up LDO on Switcher off by V UVLO IN LDO Switch-Over Operation ENL low The switch-over function is provided to increase efficiency threshold by using the more efficient DC-DC converter to power the (min 0.4V) LDO off LDO output, avoiding the less efficient LDO regulator Switcher on if EN = high AGND when possible. The switch-over function connects the VDD pin directly to the VOUT pin using an internal switch. Figure 10 — ENL Threshold When the switch-over is complete the LDO is turned off, which results in power savings and maximizes efficiency. Before start-up, the LDO checks the status of the following If the LDO output is used to bias the SC403B, then after signals to ensure proper operation can be maintained. switch-over the device is self-powered from the switching regulator with the LDO turned off. 1. ENL pin 2. V input voltage IN The switch-over logic waits for 32 switching cycles before it starts the switch-over. When the LDO is already in regu- When the ENL pin is high and V is above the UVLO point, IN lation and the DC-DC converter is later enabled, as soon as the LDO will begin start-up. During the initial phase, when the PGOOD output goes high, the 32 cycles are started. the V voltage (which is the LDO output voltage) is less DD The voltages at the VDD and VOUT pins are then com- than 0.75V, the LDO initiates a current-limited start-up pared; if the two voltages are within ±300mV of each (typically 65mA) to charge the output capacitors while other, the VDD pin connects to the VOUT pin using an protecting from a short circuit event. When V is greater DD internal switch, and the LDO is turned off. than 0.75V but still less than 90% of its final value (as sensed at the FBL pin), the LDO current limit is increased Switch-over Limitations on VOUT, ENL, and VDD to ~115mA. When V has reached 90% of the final value DD Because the internal switch-over circuit always compares (as sensed at the FBL pin), the LDO current limit is increased the VOUT and VDD pins at start-up, there are limitations to ~200mA and the LDO output is quickly driven to the on permissible combinations of these pins. Consider the nominal value by the internal LDO regulator. It is recom- case where V is programmed to 3.0V and V is pro- mended that during LDO start-up to hold the PWM OUT LDO grammed to 3.3V. After start-up, the device would connect switching off until the LDO has reached 90% of the final VOUT to VDD and disable the LDO, since the two voltages value. This prevents overloading the current-limited LDO are within the ±300mV switch-over window. To avoid output during the LDO start-up. unwanted switch-over, the minimum difference between Due to the initial current limitations on the LDO during the voltages for V and V should be ±500mV. OUT LDO power up (Figure 11), any external load attached to the VDD pin must be limited to 20mA before the LDO has reached 90% of it final regulation value. 21 SC403B Applications Information (continued) In many applications, the EN/PSV pin will be pulled high to the bias and power output of the SC403B. When V > OUT the VDD node to allow control of the PWM and LDO ENL 3.0V this configuration can cause problems due to the pin. If the switch over feature is used, this circuit must be parasitic diodes in the LDO switchover circuitry. After the implemented with caution or the circuit may be damaged. V > 3.0V PWM output is up and running the switchover OUT In the case where the ENL pin is being controlled by a GPIO diodes can hold up V5V > UVLO even if the ENL pin is signal or is tied directly to the input voltage, the ENL pin can grounded, turning off the LDO. Operating in this way can be pulled low while the PWM is still generating an output potentially damage the part. voltage that is seen across one of the switch-over diodes. This may result in the VDD node being held above its UVLO Design Procedure threshold while the LDO is deactivated. This type of opera- When designing a switch mode supply the input voltage tion can potentially damage the part. range, load current, switching frequency, and inductor ripple current must be specified. In the case where the ENL pin is used to control the input UVLO, it is acceptable to connect EN/PSV directly to the The maximum input voltage (V ) is the highest speci- INMAX VDD node. fied input voltage. The minimum input voltage ( V ) is INMIN determined by the lowest input voltage after evaluating It is not recommended to use the switch-over feature for the voltage drops due to connectors, fuses, switches, and an output voltage less than 3V since this does not provide PCB traces. sufficient voltage for the gate-source drive to the internal p-channel switch-over MOSFET. The following parameters define the design. Switch-over MOSFET Parasitic Diode • Nominal output voltage (V ) OUT The switch-over MOSFET contains a parasitic diode that is • Static or DC output tolerance inherent to its construction, as shown in Figure 12. • Transient response • Maximum load current (I ) OUT Switchover Switchover control MOSFET There are two values of load current to evaluate — con- LDO V OUT tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and Parasitic diode filtering requirements such as inductor saturation, output VDD capacitors, and design of the current limit circuit. The following values are used in this design. Figure 12— Switch-over MOSFET Parasitic Diodes • V = 12V + 10% If V is higher than VDD, then the diode will turn on and IN OUT • V = 1.5V + 4% the SC403B operating current will flow through this diode. OUT • f = 300kHz This has the potential of damaging the device. SW • Load = 6A maximum • V = 600mV There are some important design rules that must be fol- FB lowed to prevent forward bias of this diode. The following condition, V ≥ V needs to be satisfied in order for the DD OUT parasitic diode to stay off and prevent damaging the device. Many applications connect the EN pin to V5V and control the on/off of the LDO and PWM simultaneously with the ENL pin. This allows one signal to control both 22 SC403B Applications Information (continued) Frequency Selection current. This provides an optimal trade-off between cost, Selection of the switching frequency requires making a efficiency, and transient performance. trade-off between the size and cost of the external filter During the DH on-time, voltage across the inductor is components (inductor and output capacitor) and the (V - V ). The equation for determining inductance is power conversion efficiency. IN OUT shown next. The desired switching frequency is 300kHz which results (V V )ut from using components selected for optimum size and IN OUT ON L I cost. RIPPLE Example A resistor (R ) is used to program the on-time (indirectly TON In this example, the inductor ripple current is set equal to setting the frequency) using the following equation. 50% of the maximum load current. Therefore ripple current will be 50% x 6A or 3A. To find the minimum (t 10ns)uV ON IN R TON inductance needed, use the V and t values that corre- 25pFuV OUT IN ON spond to V . INMAX To select R , use the maximum value for V , and for t TON IN ON use the value associated with maximum V . IN (13.21.5)u379ns L 1.48PH 3A V OUT t ON V uf INMAX SW A slightly larger value of 1.5µH is selected. This will t = 379 ns at 13.2V , 1.5V , 300kHz decrease the typical I to 2.7A. ON IN OUT RIPPLE Note that the inductor must be rated for the maximum DC Substituting for R results in the following solution. TON load current plus 1/2 of the ripple current. R = 129.9kΩ, use R = 130kΩ TON TON The ripple current under minimum V conditions is also IN Inductor Selection checked using the following equations. In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller 25pFuR uV TON OUT t 10ns 461ns ON_VINMIN size but create higher ripple current which can reduce effi- V INMIN ciency. Higher inductor values will reduce the ripple current and ripple voltage and for a given DC resistance are more (V V )ut IN OUT ON I efficient. However, larger inductance translates directly into RIPPLE L larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. (10.81.5)u461ns I 2.38A RIPPLE_MIN 1.5PHu(10.2) The ripple current will also set the boundary for PSAVE operation. The switching will typically enter PSAVE mode (10.81.5)u379ns when the load current decreases to 1/2 of the ripple I 3.7A RIPPLE_MAX 1.5PHu(10.2) current. For example, if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple The value of L has been adjusted by +20% for the equa- current is set at 40% of maximum load current, then PSAVE tions above assuming an inductor tolerance of +20%. will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load 23 SC403B Applications Information (continued) Output Capacitor Selection If the load release is relatively slow, the output capacitance The output capacitors are chosen based upon required can be reduced. At heavy loads during normal switching, ESR and capacitance. The maximum ESR requirement is when the FB pin is above the reference, the DL output is controlled by the output ripple requirement and the DC high and the low-side MOSFET is on. During this time, the tolerance. The output voltage has a DC value that is equal voltage across the inductor is approximately to the valley of the output ripple plus 1/2 of the peak-to- -V . This causes a down-slope or falling di/dt in the OUT peak ripple. A change in the output ripple voltage will inductor. If the load di/dt is not much faster than the lead to a change in DC voltage at the output. -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess The design goal is that the output voltage regulation be inductive energy that must be absorbed by the output ±4% under static conditions. The internal reference toler- capacitor, therefore a smaller capacitance can be used. ance is ±1%. Allowing ±1% tolerance from the FB resistor divider, this allows 2% tolerance due to V ripple. Since The following can be used to calculate the needed capaci- OUT this 2% error comes from 1/2 of the ripple voltage, the tance for a given dI /dt. LOAD allowable ripple is 4%, or 60mV for a 1.5V output. Peak inductor current is shown by the next equation. The maximum ripple current of 3.7A creates a ripple I = I + 1/2 x I voltage across the ESR. The maximum ESR value allowed LPK MAX RIPPLEMAX is shown by the following equations. I = 6 + 1/2 x 3.7 = 7.9A LPK V 60mV RIPPLE ESR MAX dl I 3.7A LOAD RIPPLEMAX RateofchangeofLoadCurrent dt ESR = 16.2 mΩ MAX I = maximum load release = 6A MAX The output capacitance is usually chosen to meet tran- sient requirements. A worst-case load release, from I I LPK MAX Lu  u dt maximum load to no load at the exact moment when the V dl OUT LOAD C I u OUT LPK inductor current is at the peak, determines the required 2V  V  PK OUT capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output Example capacitor must absorb all the inductor’s stored energy. dl This will cause a peak voltage on the capacitor requiring a 2A LOAD capacitance provided by the following equation. dt 1Ps This would cause the output current to move from 6A to 2 1 § · L I  uI ¨ ¸ OUT RIPPLEMAX 0A in 3.0µs, giving the minimum output capacitance 2 © ¹ COUT MIN requirement shown in the following equation. 2 2 V  V  PEAK OUT 7.9 6 Assuming a peak voltage V of 1.6V (100mV rise upon 1.5PHu  u1Ps PEAK 1.5 2 load release), and a 6A load release, the required capaci- C 7.9Au OUT 21.6V1.5V tance is shown by the next equation. C = 194 µF 2 OUT 1 § · 1.5PH 6A u 3.7A ¨ ¸ 2 © ¹ COUT Note that C is much smaller in this example, 194µF MIN 2 2 OUT 1.6V 1.5V compared to 298µF based on a worst-case load release. To meet the maximum design criteria of minimum 298µF COUT = 298µF MIN 24 SC403B Applications Information (continued) and maximum 16mΩ ESR, select one capacitor rated at unpopulated until it can be confirmed that double-pulsing 330µF and 9mΩ ESR. exists. Adding the C capacitor will couple more ripple TOP into FB to help eliminate the problem. An optional con- It is recommended that an additional small capacitor be nection on the PCB should be available for this capacitor. placed in parallel with C in order to filter high frequency OUT C switching noise. TOP Soft Start Capacitor Selection For a soft-start time (t ) of approximately 3ms, solve the SS following equation for C . To FB pin V R1 OUT SS R2 3PA C t SS SS 1.5V C 6nF SS Figure 13 — Capacitor Coupling to FB Pin If C is selected as 4.7 nF, then t will be 2.4 ms. SS SS ESR loop instability is caused by insufficient ESR. The Then the PGOOD delay, the time from V regulation to OUT details of this stability issue are discussed in the ESR PGOOD signal high is shown by the following equation. Requirements section. The best method for checking sta- 4.7nFu(0.64V 1.5V) DD bility is to apply a zero-to-full load transient and observe t PGOOD-DELAY 3PA the output voltage ripple envelope for overshoot and ringing. Ringing for more than one switching cycle after At V = 5V, the PGOOD delay will be 2.7ms. DD the initial step is an indication that the ESR should be increased. Stability Considerations Unstable operation is possible with adaptive on-time con- One simple way to solve this problem is to add trace resis- trollers, and usually takes the form of double-pulsing or tance in the high current output path. A side effect of ESR loop instability. adding trace resistance is a decrease in load regulation performance. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This ESR Requirements causes the FB comparator to trigger prematurely after the A minimum ESR is required for two reasons. One reason is 250ns minimum off-time has expired. In extreme cases to generate enough output ripple voltage to provide the noise can cause three or more successive on-times. 10mVp-p at the FB pin (after the resistor divider) to avoid Double-pulsing will result in higher ripple voltage at the double-pulsing. output, but in most applications it will not affect opera- tion. This form of instability can usually be avoided by The second reason is to prevent instability due to insuffi- providing the FB pin with a smooth, clean ripple signal cient ESR. The on-time control regulates the valley of the that is at least 10mVp-p, which may dictate the need to output ripple voltage. This ripple voltage is the sum of the increase the ESR of the output capacitors. It is also impera- two voltages. One is the ripple generated by the ESR, the tive to provide a proper PCB layout as discussed in the other is the ripple due to capacitive charging and dis- Layout Guidelines section. charging during the switching cycle. For most applica- tions the minimum ESR ripple voltage is dominated by the Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis- tor, as shown in Figure 13. This capacitor should be left 25 SC403B Applications Information (continued) output capacitors, typically SP or POSCAP devices. For t ON(MIN) stability the ESR zero of the output capacitor should be DUTY t t ON(MIN) OFF(MAX) lower than approximately one-third the switching fre- quency. The formula for minimum ESR is shown by the The inductor resistance and MOSFET on-state voltage following equation. drops must be included when performing worst-case dropout duty-factor calculations. 3 ESR MIN 2uSuC uf OUT sw System DC Accuracy (V Controller) OUT Three factors affect V accuracy: the trip point of the FB Using Ceramic Output Capacitors OUT error comparator, the ripple voltage variation with line For applications using ceramic output capacitors, the ESR and load, and the external resistor tolerance. The error is normally too small to meet the above ESR criteria. In comparator offset is trimmed so that under static condi- these applications it is necessary to add a small virtual ESR tions it trips when the feedback pin is within +1% of the network composed of two capacitors and one resistor, as reference voltage. shown in Figure 14. This network creates a ramp voltage across C , analogous to the ramp voltage generated across L The on-time pulse from the SC403B in the design example the ESR of a standard capacitor. This ramp is then capaci- is calculated to give a pseudo-fixed frequency of 300kHz. tively coupled into the FB pin via capacitor C . C Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the L output ripple, ½ of the output ripple appears as a DC regu- High- lation error. For example, if the output ripple is 50mV with side C R L L V = 6 volts, then the measured DC output will be 25mV IN above the comparator trip point. If the ripple increases to R1 C 80mV with V = 25V, then the measured DC output will be C C IN Low- OUT 40mV above the comparator trip. The best way to mini- Virtual side ESR mize this effect is to minimize the output ripple. R2 Network FB To compensate for valley regulation, it may be desirable to pin use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- Figure 14 — Virtual ESR Ramp Circuit tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation Dropout Performance limit. Passive droop minimizes the required output capaci- The output voltage adjust range for continuous-conduc- tance because the voltage excursions due to load steps tion operation is limited by the fixed 80ns (typical) are reduced as seen at the load. minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calcu- The use of 1% feedback resistors may result in up to 1% lated using worst-case values for on and off times. error. If tighter DC accuracy is required, 0.1% resistors should be used. The duty-factor limitation is shown by the next equation. 26 SC403B Applications Information (continued) The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency will vary depending upon line and load conditions. The line variation is a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As V increases, these factors make the actual DH on-time IN slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the induc- tor. For a conventional PWM constant-frequency con- verter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V as losses increase). The on-time is essen- IN tially constant for a given V /V combination, to offset OUT IN the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. 27 CBST VDD SC403B Applications Information (continued) • All other decoupling capacitors must be located PCB Layout Guidelines as close as possible to the IC. The optimum layout for the SC403B is shown in Figure 15. This layout shows an integrated FET buck regulator with a PGND Plane maximum current of 6A. The total PCB area is approxi- • PGND requires its own copper plane with no mately 25 x 29 mm. other signal traces routed on it. • Copper planes, multiple vias and wide traces are Critical Layout Guidelines needed to connect PGND to input capacitors, The following critical layout guidelines must be followed output capacitors, and the PGND pins on the to ensure proper performance of the device. device. • The PGND copper area between the input • IC decoupling capacitors capacitors, output capacitors, and PGND pins • PGND plane must be as tight and compact as possible to • AGND island reduce the area of the PCB that is exposed to • FB, VOUT, and other analog control signals noise due to current flow on this node. • BST, ILIM, and LX • Connect PGND to AGND with a short trace or • CIN and COUT placement and current loops 0Ω resistor. This connection should be as close to the device as possible. IC Decoupling Capacitors • A 0.1 μF capacitor must be located as close as possible to the IC and directly connected to pins 3 (VDD) and 4 (AGND). All components shown Top Side IC with vias for VDD Decoupling Capacitor LX, AGND, VIN Pin 1 marking AGND plane on inner layer LX plane on top and RFB2 RFB1 bottom layer L CTOP Vout sense trace VOUT Plane on top on inner layer C IN and bottom layer C IN SP or C OUT POSCAP PGND on inner Cer. or bottom layer V plane on RGND — AGND connects to IN PGND on top top and/or PGND close to IC layer bottom layer Figure 15 — PCB Layout 28 Css RTON RILIM SC403B Applications Information (continued) AGND Island BST, ILIM, and LX • AGND should have its own island of copper with • LX and BST are very noisy nodes and must be no other signal traces routed on this layer that routed to minimized the PCB area that is exposed connects the AGND pins and pad of the device to these signals. to the analog control components. • The connections for the boost capacitor • All of the components for the analog control cir- between the device and LX must be short and cuitry should be located so that the connections directly connected to the LXBST (pin 13). to AGND are done by wide copper traces or vias • The connections for the current limit resistor down to AGND. between the ILIM pin and LX must be as short as • Connect PGND to AGND with a short trace or 0Ω possible and directly connected to pin 28 (LXS). resistor. This connection should be as close to • The LX node between the IC and the inductor the device as possible. should be wide enough to handle the inductor current and short enough to eliminate the pos- FB, VOUT, and Other Analog Control Signals sibility of LX noise corrupting other signals. • The connection from the V power to the • Multiple vias should be used to provide a good OUT analog control circuitry must be routed from the connection to LX between the device and the output capacitors and located on a quiet layer. inductor. • The traces between VOUT and the analog control circuitry (VOUT, and FB pins) must be short and Capacitors and Current Loops routed away from noise sources, such as BST, LX, • The current loops between the input capacitors, VIN, and PGND between the input capacitors, the device, the inductor, and the output capaci- output capacitors, and the device. tors must be as close as possible to each other to • ILIM and TON nodes must be as short as possible reduce IR drop across the copper. to ensure the best accuracy in current limit and • All bypass and output capacitors must be con- on time. nected as close as possible to the pin on the • The R resistor should be close to the device device. ILIM and connected to LX with a Kelvin trace to pin Soft-Start Capacitor 28 on the device. All of the LX pins are connected • The capacitor used for soft-start should be to the LX PAD on the device, which should be a located away from the BST pin and its capacitor. sufficient connection and will prevent the need • If possible locate the boost capacitor on the to connect the resistor further into the LX opposite side of the board form the IC and soft- plane. start capacitor. • The feedback components for the switcher and the LDO need to be as close to the FB and FBL pins of the device as possible to reduce the pos- sibility of noise corrupting these analog signals. 29 SC403B Outline Drawing — MLPQ-5x5-32 DIMENSIONS B A D INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .031 .039 0.80 1.00 - - A1 .000 .002 0.00 0.05 - (.008) - - (0.20) - A2 b .007 .010 0.25 0.30 PIN 1 .012 0.18 E INDICATOR D .193 .197 .201 4.90 5.00 5.10 (LASER MARK) .076 .078 1.92 1.97 D1 .080 2.02 E .193 .197 .201 4.90 5.00 5.10 E1 .135 .137 .139 3.43 3.48 3.53 e .020 BSC 0.50 BSC L .012 .016 .020 0.30 0.40 0.50 A2 N 32 32 aaa .003 0.08 bbb .004 0.10 A SEATING PLANE aaa C C A1 3.48 D1 0.76 1.05 LxN 1.49 3.61 E1 1.66 2 1 0.76 N R0.20 bxN PIN 1 IDENTIFICATION e bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 30 SC403B Land Pattern — MLPQ-5x5-32 3.48 K1 K DIMENSIONS 1.74 DIM INCHES MILLIMETERS (.195) (4.95) C G .165 4.20 H .137 3.48 H2 1.74 H1 .059 1.49 (C) G H 3.61 H2 .065 1.66 Z K .078 1.97 H1 K1 .041 1.05 P .020 0.50 Y X .012 0.30 Y .030 0.75 X Z .224 5.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. 31 SC403B © Semtech 2011 All rights reserved. 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