SEMTECH SC402B

SC402B ® 10A EcoSpeed Integrated FET Regulator with Programmable LDO POWER MANAGEMENT Features Description ®  Power System The SC402B is a stand-alone synchronous EcoSpeed buck • Input voltage — 3V to 28V power supply which incorporates Semtech’s advanced • Bias voltage — 3V to 5.5V LDO or external patented adaptive on-time control architecture. This pro- • Up to 96% peak efficiency vides excellent light-load efficiency and fast transient • Integrated bootstrap switch response. It features integrated power MOSFETs, a boot- • Programmable LDO output — 200mA strap switch, and a programmable LDO in a 5x5mm • Reference tolerance — 1% T = -40 to +125 °C J package. The device is highly efficient and uses minimal • Programmable soft start time PCB area. The SC402B has the same package and pin con-  Logic Input/Output Control figuration as the entire SC40x series for compatibility. • Independent EN controls for LDO and switcher • Programmable V UVLO threshold The SC402B supports using standard capacitor types such IN • Power good output as electrolytic or specialty polymer, in addition to ceramic, • Selectable PSAVE or FCM mode at switching frequencies up to 1MHz. The programmable  Protection frequency, synchronous operation, and selectable power- • Over-voltage and under-voltage save provide high efficiency operation over a wide load • TC compensated R sensed current limit range. DS(ON) • Thermal Shutdown  Output Capacitor Types Additional features include a programmable soft-start, • High ESR — SP, POSCAP, OSCON programmable cycle-by-cycle over-current limit protec- • Ceramic capacitors tion, under-voltage and over-voltage protection, soft  Package shutdown, and selectable power-save operation. The • Lead-free package — 5x5mm, 32-Pin MLPQ device also provides separate enable inputs for the PWM • RoHS/WEEE compliant and Halogen free controller and LDO as well as a power good output for the PWM controller. Applications The wide input and programmable frequency make the  Networking and telecommunication equipment device extremely flexible and easy to use in a broad range  Printers, DSL, and STB applications of applications.  Embedded systems and power supply modules  Point of load power supplies Typical Application Circuit ENABLE/PSAVE EN/PSV ILIM RILIM LXS ENABLE LDO ENL RTON PGOOD PGOOD TON VOUT L1 10Ω VDD SC402B VEXT/LDO VOUT LX 1µF CSOFT COUT SS + RFB1 BST FB VIN VIN RFB2 CIN CBST © 2011 Semtech Corporation Rev. 2.1 1 LXBST AGND PGND SC402B Pin Configuration Ordering Information Device Package (1)(2) SC402BMLTRT MLPQ-32 5X5 32 31 30 29 28 27 26 25 SC402BEVB Evaluation Board Top View 1 24 LX FB Notes: 23 VOUT 2 LX 1) Available in tape and reel only. A reel contains 3000 devices. AGND PAD 1 3 22 VDD PGND 2) Lead-free, Halogen free, and RoHS/WEEE compliant 4 21 AGND PGND LX PAD 3 FBL 5 20 PGND VIN 6 19 PGND VIN PAD 2 7 18 SS PGND 8 17 PGND BST 9 10 11 12 13 14 15 16 SC402B MLPQ-32; 5x5, 32 LEAD Marking Information SC402B yyww xxxxxx xxxxxx yyww = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number 2 VIN ENL VIN TON VIN AGND DH EN/PSV LXBST LXS DL ILIM PGND PGOOD PGND LX SC402B Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28 LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30 VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5 VIN to VDD (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 Thermal Information EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(VDD + 0.3) Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150 SS, VOUT, FB, FBL, to GND (V) . . . . . . . . . -0.3 to +(VDD + 0.3) Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150 VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 Operating Junction Temperature (°C) . . . . . . -40 to +125 TON to PGND (V) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(VDD - 1.5) (2) Thermal resistance, junction to ambient (°C/W) ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V IN High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DH, BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DH, BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 PWM controller and LDO thermal resistance . . . . . 50 DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260 AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 (1) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specified: V =12V, T = +25°C for Typ, -40 to +85 °C for Min and Max, T < 125°C, VDD = +5V, Typical Application Circuit IN A J Parameter Conditions Min Typ Max Units Input Supplies Input Supply Voltage V > VDD 3 28 V IN VDD Voltage 3 5.5 V Sensed at ENL pin, rising edge 2.40 2.60 2.95 (1) VIN UVLO Threshold V Sensed at ENL pin, falling edge 2.23 2.40 2.57 VIN UVLO Hysteresis EN/PSV = High 0.25 V Measured at VDD pin, rising edge 2.5 3.0 VDD UVLO Threshold V Measured at VDD pin, falling edge 2.4 2.9 VDD UVLO Hysteresis 0.2 V ENL , EN/PSV = 0V, V = 28V 10 20 IN VIN Supply Current μA Standby mode; ENL=VDD, EN/PSV = 0V 130 3 SC402B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) ENL , EN/PSV = 0V, no external 5V VDD 3 7 μA ENL , EN/PSV = 0V, external 5V VDD supply 190 300 VDD Supply Current EN/PSV = VDD (PSAVE), No load, VFB > 600mV 0.7 (2) VDD = 5V, f = 250kHz, EN/PSV = floating , no load 8 mA SW (2) VDD = 3V, f = 250kHz, EN/PSV = floating , no load 5 SW Static V and load, T = 0 to +125 °C 0.595 0.6 0.605 V IN J FB On-Time Threshold Static V and load, T = 40 to +125 °C 0.594 0.6 0.606 V IN J Frequency Range Continuous mode operation (FCM) 1000 kHz Bootstrap Switch Resistance 10 Ω Timing Continuous mode operation, On-Time 999 1110 1220 ns V = 12V, V = 5V, f = 300kHz, R = 133kΩ IN OUT SW TON (2) Minimum On-Time 80 ns VDD = 5V 250 (2) Minimum Off-Time ns VDD = 3V 370 Soft-Start Soft-Start Current 3.0 µA (2) Soft-Start Voltage When V reaches regulation 1.5 V OUT Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero-Crossing Detector Threshold LX - PGND -3 0 +3 mV Power Good Upper limit, V > internal 600mV reference +20 % FB Power Good Threshold Lower limit, V < internal 600mV reference -10 % FB VDD = 5V, C = 10nF 12 SS Start-Up Delay Time ms (between PWM enable and PGOOD high) VDD = 3V, C = 10nF 7 SS 4 SC402B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Power Good (continued) Power Good start-up Delay Threshold on SS pin SS voltage when PGOOD goes high 64 %VDD (2) Fault (noise immunity) Delay Time 5 µs Leakage 1 µA Power Good On-Resistance 10 Ω Fault Protection VDD = 5V, R = 6810, T = 0 to +125 °C 8.5 10 11.5 ILIM J (3) Valley Current Limit A VDD = 3V, R = 6810 9 ILIM I Source Current 10 μA LIM I Comparator Offset With respect to AGND -10 0 +10 mV LIM V with respect to internal 600mV reference, FB Output Under-Voltage Fault -25 % 8 consecutive clocks (2) Smart Power-save Protection Threshold V with respect to internal 600mV reference +10 % FB Over-Voltage Protection Threshold V with respect to internal 600mV reference +20 % FB (2) Over-Voltage Fault Delay 5 μs (2) Over-Temperature Shutdown 10°C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage ENL 1.0 V Logic Input Low Voltage ENL 0.4 V (2) EN/PSV Input for PSAVE Operation VDD = 5V 2.2 5 V (2) EN/PSV Input for Forced Continuous Operation 1 2 V EN/PSV Input for Disabling Switcher 0 0.4 V EN/PSV Input Bias Current EN/PSV= VDD or AGND -10 +10 μA ENL Input Bias Current ENL = V = 28V 10 18 μA IN FBL, FB Input Bias Current FBL, FB = VDD or AGND -1 +1 μA 5 SC402B Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Linear Regulator (LDO) FBL Accuracy VLDO load = 5mA 0.728 0.75 0.773 V Short-circuit protection, V = 12V, V < 0.75V 65 IN DD Start-up and foldback, V = 12V, IN 115 LDO Current Limit mA 0.75 < V < 90% of final V value DD DD Operating current limit, V = 12V, IN 135 200 V > 90% of final V value DD DD (4) VLDO to VOUT Switch-over Threshold -130 +130 mV (4) VLDO to VOUT Non-switch-over Threshold -500 +500 mV VLDO to VOUT Switch-over Resistance V = +5V 2 Ω OUT (5) LDO Drop Out Voltage From V to V , V = +5V, I = 100mA 1.2 V IN DD DD VLDO Notes: (1) V UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. IN (2) Typical value measured on standard evaluation board. (3) SC402B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout. (4) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. (5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point. 6 SC402B Detailed Application Circuit — 1 Internal LDO Used as Bias ENABLE/PSAVE PGOOD RILIM ENABLE LDO 7.68KΩ RTON 130KΩ PAD 1 AGND 24 1 FB LX 2 23 LX VOUT 3 22 VDD PGND 4 21 AGND PGND 5 RLDO1 20 SC402B FBL PGND 422KΩ 6 19 VIN PGND 7 18 SS PGND 8 17 BST PGND RLDO2 1µF 3.3nF 1µF PAD 3 75KΩ LX RBST 0Ω VIN CIN +12V 2 x 10µF RGND CBST (see note) 1µF 0 1.5V @ 10A, 300kHz L1 1µH + COUT VOUT 330µF 22µF 9mΩ CFF RFB1 100pF 10KΩ RFB2 6.65KΩ Key Components Component Value Manufacturer Part Number Web CIN (see note) 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com COUT 330µF/9mΩ Panasonic EEF-SX0E331ER www.panasonic.com L1 1.0µH/3mΩ Cyntec PIMB104T-1R0MS www.cyntec.com NOTE: The quantity of 10µF input capacitors required varies with the application requirements. 7 PAD 2 VIN 9 VIN 32 ENL 10 31 VIN TON 11 30 VIN AGND 29 12 DH EN/PSV 13 28 LXBST LXS 27 14 DL ILIM 15 26 PGND PGOOD 16 25 PGND LX SC402B Detailed Application Circuit — 2 External 3.3V - 5V Used as Bias ENABLE/PSAVE PGOOD RILIM 7.68KΩ RTON 130KΩ PAD 1 AGND 24 1 FB LX 5V 2 23 LX VOUT 3 22 VDD PGND 4 21 10Ω AGND PGND 5 20 SC402B FBL PGND 6 19 VIN PGND 7 18 SS PGND 8 17 BST PGND 1µF 3.3nF 1µF PAD 3 LX RBST 0Ω VIN CIN +12V 2 x 10µF RGND (see note) CBST 0 1µF L1 1.5V @ 10A, 300kHz 1µH + COUT VOUT 330µF 22µF 9mΩ CFF RFB1 100pF 10KΩ RFB2 6.65KΩ Key Components Component Value Manufacturer Part Number Web CIN (see note) 2 x 10µF/25V Murata www.murata.com GRM32DR71E106KA12L 330µF/9mΩ Panasonic EEF-SX0E331ER www.panasonic.com COUT L1 1.0µH/3mΩ Cyntec PIMB104T-1R0MS www.cyntec.com NOTE: The quantity of 10µF input capacitors required varies with the application requirements. 8 PAD 2 VIN 9 VIN 32 ENL 10 31 VIN TON 11 30 VIN AGND 29 12 DH EN/PSV 28 13 LXBST LXS 14 27 DL ILIM 15 26 PGND PGOOD 16 25 PGND LX SC402B Typical Characteristics Characteristics in this section are based on using the Typical Application Circuit on page 8. Efficiency/Power Loss — PSAVE vs. FCM Efficiency/Power Loss vs. Load — PSAVE Mode VDD = 3.3V, V = 1.5V VDD = 3.3V, V = 1.5V, V = 12V OUT IN OUT 5.0 100 100 0.3000 V = 5V IN 95 95 0.2675 PSAVE Efficiency 90 4.0 90 0.2350 V = 12V IN FCM 85 85 0.2025 80 3.0 80 0.1700 75 75 0.1375 70 2.0 70 0.1050 65 65 0.0725 V = 12V P IN LOSS 60 1.0 60 0.0400 FCM minus PSM 55 55 0.0075 V = 5V IN 50 0.0 50 -0.0250 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) I (A) OUT Efficiency/Power Loss — PSAVE vs. FCM Efficiency/Power Loss vs. Load — PSAVE Mode VDD = 5V, V = 1.5V VDD = 5V, V = 1.5V, V = 12V OUT OUT IN 100 5.0 0.3000 100 V = 12V IN 95 V = 5V Efficiency IN 95 0.2675 PSAVE 90 4.0 90 0.2350 V = 18V IN FCM 85 85 0.2025 80 3.0 80 0.1700 75 75 0.1375 70 2.0 70 0.1050 V = 12V IN 65 65 0.0725 V = 18V IN 60 1.0 60 0.0400 FCM minus PSM P LOSS 55 55 0.0075 V = 5V IN 0.0 -0.0250 50 50 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) OUT I (A) OUT Efficiency/Power Loss vs. Load — FCM Efficiency/Power Loss — PSAVE VDD = 5V, V = 1.5V V = 1.5V, V = 12V OUT OUT IN 100 5.0 100 0.35 V = 12V IN 95 V = 5V Efficiency IN 95 0.30 3.3V Bias 90 4.0 90 0.25 5V Bias 85 V = 18V IN 85 0.20 80 3.0 80 0.15 75 75 0.10 70 2.0 70 0.05 V = 12V IN 3.3V minus 5V 65 65 0.00 V = 18V IN 60 1.0 60 -0.05 PLOSS 55 55 -0.10 VIN = 5V 50 0.0 50 -0.15 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) I (A) OUT OUT 9 Efficiency (%) Efficiency (%) Efficiency (%) PLoss (W) Power Loss (W) PLOSS (W) Efficiency (%) Efficiency (%) Efficiency (%) PLOSS (W) P (W) PLOSS (W) LOSS SC402B Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Load Regulation — FCM Load Regulation — FCM VDD = 5V, V = 1.5V VDD = 3.3V, V = 1.5V OUT OUT 1.525 1.525 1.520 1.520 V = 18V IN 1.515 1.515 V = 12V IN 1.510 1.510 V = 12V IN VIN = 5V V = 5V IN 1.505 1.505 1.500 1.500 1.495 1.495 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) OUT I (A) OUT Load Regulation — PSAVE Load Regulation — PSAVE Mode VDD = 3.3V, V = 1.5V VDD = 5V, V = 1.5V OUT OUT 1.525 1.525 1.520 1.520 V = 18V IN 1.515 1.515 V = 12V IN 1.510 1.510 V = 12V IN V = 5V IN V = 5V IN 1.505 1.505 1.500 1.500 1.495 1.495 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) OUT I (A) OUT Switching Frequency — PSAVE Mode vs. FCM Switching Frequency — PSAVE Mode vs. FCM VDD = 5V, V = 1.5V, V = 12V VDD = 3.3V, V = 1.5V OUT OUT IN 350 350 300 300 FCM FCM 250 250 200 200 PSAVE PSAVE 150 150 100 100 50 50 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) OUT I (A) OUT 10 Vout (V) Vout (V) Switching Frequency (kHz) Vout (V) Vout (V) Switching Frequency (kHz) SC402B Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Load Regulation vs. Temperature — FCM Load Regulation vs. Temperature — FCM VDD = 5V, V = 1.5V VDD = 3.3V, V = 1.5V OUT OUT 1.525 1.525 V = 18V T = 25°C IN A V = 12V TA = 25°C 1.520 1.520 IN T = 85°C VIN = 12V A V = 18V T = 85°C IN A 1.515 1.515 V = 12V T = 85°C IN A V = 12V T = 25°C IN A V = 18V IN T = -40°C A T = 85°C V = 5V A IN 1.510 1.510 T = 85°C VIN = 5V A V = 12V T = -40°C IN A V = 5V T = 25°C IN A 1.505 1.505 V = 5V T = 25°C IN A T = -40°C VIN = 12V A 1.500 V = 5V T = -40°C IN A 1.500 T = -40°C VIN = 5V A 1.495 1.495 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) I (A) OUT OUT Load Regulation vs. Temperature — PSAVE Load Regulation vs. Temperature — PSAVE VDD = 5V, V = 1.5V VDD = 5V, V = 1.5V OUT OUT 1.525 1.525 V = 18V TA = 25°C IN V = 12V T = 25°C IN A 1.520 1.520 T = 85°C V = 12V A IN T = 85°C VIN = 18V A V = 12V TA = 85°C IN 1.515 1.515 T = 25°C VIN = 12V A V = 5V T = 85°C T = 85°C IN A VIN = 5V A 1.510 1.510 V = 18V T = -40°C IN A V = 12V T = -40°C A IN V = 5V TA = 25°C IN 1.505 1.505 V = 5V T = 25°C IN A V = 12VT = -40°C IN A 1.500 V = 5V T = -40°C 1.500 IN A T = -40°C VIN = 5V A 1.495 1.495 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 I (A) I (A) OUT OUT Efficiency/Power Loss vs. Load — PSAVE Mode Efficiency Variation with V — PSAVE OUT VDD = 5V, V = 12V, L = 2.2uH (4.6m Ω) for V = 2.5V, 3.3V and 5V IN OUT VDD = 5V, V = 12V, V = 1.5V IN OUT 100 100 0.350 V = 5V V = 2.5V OUT OUT V = 3.3V OUT 95 External 0.315 Bias 95 90 0.280 V = 1.5V OUT 85 0.245 90 80 0.210 V = 1V OUT LDO 75 Bias 0.175 85 70 0.140 65 0.105 80 60 0.070 55 0.035 LDO minus External 75 0.000 50 0 1 2 3 4 5 6 7 8 9 10 0.000 0.001 0.010 0.100 1.000 10.000 I (A) OUT I (A) OUT 11 Vout (V) Vout (V) Efficiency (%) Vout (V) Vout (V) Efficiency (%) PLOSS (W) SC402B Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Start-up — EN/PSV Shutdown — EN/PSV VDD = 5V, V = 12V, V = 1.5V, I = 0A VDD = 5V, V = 12V, V = 1.5V, I = 0A IN OUT OUT IN OUT OUT (5V/div) (500mV/div) (5V/div) 2.2ms (500mV/div) (1V/div) (1V/div) (5V/div) (5V/div) Time (1ms s/div) /div) /div) Time (2ms s/div) /div) /div) Start-up (Pre-Bias) — EN/PSV Power Save Mode VDD = 5V, V = 12V, V = 1.5V, I = 0A VDD = 5V, V = 12V, V = 1.5V, I = 0A IN OUT OUT IN OUT OUT (5V/div) (500mV/div) (50mV/div) 27ms (1V/div) (5V/div) (5V/div) Time (2 ms s/div) /div) /div) Time (5ms s/div) /div) /div) Over Current Protection — Under-Voltage Protection Forced Continuous Mode V = 12V, V = 1.5V, I = OC regulated at 10.15A VDD = 5V, V = 12V, V = 1.5V, I = 10A IN OUT OUT IN OUT OUT (5V/div) (500mV/div) (50mV/div) 15.10A (5A/div) 10.15A (10V/div) (5V/div) Time (100μs s/div) /div) /div) Time (2μs s/div) /div) /div) 12 SC402B Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Rising Edge Dead-time — LX Falling Edge Dead-time — LX VDD = 5V, V = 12V, V = 1.5V, I = 10A VDD = 5V, V = 12V, V = 1.5V, I = 10A IN OUT OUT IN OUT OUT (1V/div) (1V/div) (1V/div) (1V/div) 12ns 16ns Time (10ns s/div) /div) /div) Time (10ns s/div) /div) /div) Transient Response — PSAVE Load Rising Transient Response — PSAVE Load Falling VDD = 5V, V = 12V, V = 1.5V, I = 0.5A to 8.5A, di/dt = 1A/μs s VDD = 5V, V = 12V, V = 1.5V, I = 8.5A to 0.5A, di/dt = 1A/μs s IN OUT OUT IN OUT OUT 811kHz (50mV/div) (50mV/div) (5A/div) 74mV (5A/div) (10V/div) (10V/div) Time (10μs s/div) /div) /div) Time (10μs s/div) /div) /div) º Transient Response — FCM Over Temperature Shutdown — 159 C V = 12V, V = 1.5V, I = 0A, LDO mode VDD = 5V, V = 12V, V = 1.5V, I = 2.5A to 10A, di/dt = 1A/μs s IN OUT OUT IN OUT OUT (2V/div) (50mV/div) 74mV (5A/div) (10V/div) (10V/div) Time (20μs s/div) /div) /div) Time (500μs s/div) /div) /div) 13 SC402B Pin Descriptions Pin # Pin Name Pin Function Feedback input for switching regulator used to program the output voltage — connect to an external resis- 1 FB tor divider from VOUT to AGND. Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO. 2 VOUT The voltage at this pin must be less than or equal to the voltage at the VDD pin. Bias supply for the IC — when using the internal LDO as a bias power supply, VDD is the LDO output. When 3 VDD using an external power supply as the bias for the IC, the LDO output should be disabled. 4, 30, PAD 1 AGND Analog ground Feedback input for the internal LDO — used to program the LDO output. Connect to an external resistor 5 FBL divider from VDD to AGND. 6, 9-11, VIN Input supply voltage PAD 2 7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin. Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the 8 BST high-side gate drive. 12 DH High-side gate drive 13 LXBST LX Boost — connect to the BST capacitor. 23-25, PAD 3 LX Switching (phase) node 14 DL Low-side gate drive 15-22 PGND Power ground Open-drain power good indicator — high impedance indicates power is good. An external pull-up 26 PGOOD resistor is required. 27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS. 28 LXS LX sense — connects to R ILIM Enable/power save input for the switching regulator — connect to AGND to disable the switching regulator, 29 EN/PSV connect to VDD to operate with power save mode and float to operate in forced continuous mode. 31 TON On-time programming input — set the on-time by connecting through a resistor to AGND Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic con- 32 ENL trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND. 14 SC402B Block Diagram VIN PGOOD EN/PSV 26 29 A V IN VDD VDD Bootstrap Switch 8 BST AGND D Control & Status Reference VDD DL 12 DH Hi-side SS 7 Soft Start MOSFET B LX Gate Drive On- - time 1 Control FB Generator 13 LXBST VDD FB Comparator 28 LXS DL Lo-side 31 TON MOSFET Zero Cross Detector C PGND 2 VOUT B By yp pa as ss s C Co om mp pa ar ra atto or r Valley Current Limit 27 ILIM VDD A V IN VDD 3 Y B LDO 14 DL VLDO Switchover MUX FBL 5 32 A = connected to pins 6, 9-11, PAD 2 ENL B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 15 SC402B Applications Information Synchronous Buck Converter Psuedo-fixed Frequency Adaptive On-time Control The SC402B is a step down synchronous DC-DC buck The PWM control method used by the SC402B is pseudo- converter with integrated power MOSFETs and a 200mA fixed frequency, adaptive on-time, as shown in Figure 1. capable programmable LDO. The device is capable of 10A The ripple voltage generated at the output capacitor ESR operation at very high efficiency. A space saving 5x5 (mm) is used as a PWM ramp signal. This ripple is used to trigger 32-pin package is used. The programmable operating the on-time of the controller. frequency of up to 1MHz enables optimizing the configu- ration for PCB area and efficiency. TON V IN V LX The buck controller uses a pseudo-fixed frequency adap- tive on-time control. This control method allows fast tran- C IN Q1 V FB sient response which permits the use of smaller output FB Threshold capacitors. V LX V OUT L In addition to the following information, the user can click on the applicable link to go to the SC402B online ESR Q2 C-SIM design and simulation tool, which will lead the FB user through the design process. + C OUT Input Voltage Requirements The SC402B requires two input supplies for normal opera- tion: V and VDD. V operates over a wide range from 3V IN IN to 28V. VDD requires a 3V to 5.5V supply input that can be an external source or the internal LDO configured to Figure 1 — PWM Control Method, V Ripple OUT supply 3V to 5.5V from V . IN The adaptive on-time is determined by an internal one- shot timer. When the one-shot is triggered by the output Power Up Sequence ripple, the device sends a single on-time pulse to the high- When the SC402B uses an external power source at the side MOSFET. The pulse period is determined by V and OUT VDD pin, the switching regulator initiates the start up V ; the period is proportional to output voltage and IN when V , VDD and EN/PSV are above their respective IN inversely proportional to input voltage. With this adaptive thresholds. When EN/PSV is at a logic high, VDD needs to on-time arrangement, the device automatically antici- be applied after V rises. It is also recommended to use IN pates the on-time needed to regulate V for the present OUT a10Ω resistor between an external power source and the V condition and at the selected frequency. IN VDD pin. To start up by using the EN/PSV pin when both VDD and V are above their respective thresholds, apply The advantages of adaptive on-time control are: IN EN/PSV to enable the start-up process. For SC402B in self- • Predictable operating frequency compared to biased mode, refer to the LDO section for a full other variable frequency methods description. • Reduced component count by eliminating the error amplifier and compensation components Shutdown • Reduced component count by removing the The SC402B can be shutdown by pulling either VDD or need to sense and control inductor current EN/PSV below its threshold. When using an external • Fast transient response — the response time is power source, it is recommended that the VDD voltage controlled by a fast comparator instead of a typi- ramps down before the V voltage. When VDD is active IN cally slow error amplifier. and EN/PSV at low logic, the output voltage discharges • Reduced output capacitance due to fast tran- into the VOUT pin through an internal FET. sient response 16 SC402B Applications Information (continued) The maximum R value allowed is shown by the follow- One-Shot Timer and Operating Frequency TON ing equation. The one-shot timer operates as shown in Figure 2. The FB Comparator output goes high when V is less than the FB V internal 600mV reference. This feeds into the gate drive IN_MIN R TON_MAX 15PA and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal com- V Voltage Selection parator and a capacitor. One comparator input is con- OUT The switcher output voltage is regulated by comparing nected to V , the other input is connected to the OUT V as seen through a resistor divider at the FB pin to the capacitor. When the on-time begins, the internal capaci- OUT internal 600mV reference voltage, see Figure 3. tor charges from zero volts through a current which is proportional to V . When the capacitor voltage reaches IN V To FB pin V , the on-time is completed and the high-side MOSFET OUT OUT R 1 turns off. R 2 Gate V Drives IN FB Comparator FB - V REF + Q1 DH Figure 3 — Output Voltage Selection V L OUT V LX Note that this control method regulates the valley of the V OUT ESR FB output ripple voltage, not the DC value. The DC output One-Shot Q2 V IN + DL C OUT Timer voltage V is offset by the output ripple according to the OUT following equation. R TON On-time = K x R x (V /V ) TON OUT IN § R · V § · 1 RIPPLE V 0.6u¨1 ¸ Figure 2 — On-Time Generation ¨ ¸ OUT ¨ ¸ R 2 © ¹ © 2 ¹ This method automatically produces an on-time that is When a large capacitor is placed in parallel with R (C ) 1 TOP proportional to V and inversely proportional to V . OUT IN V is shown by the following equation. OUT Under steady-state conditions, the switching frequency can be determined from the on-time by the following 2 § R · V 1(RZC ) § · 1 RIPPLE 1 TOP ¨ ¸ V 0.6u 1 ¨ ¸u equation. OUT ¨ ¸ 2 R 2 © ¹ © 2¹ §R uR · 2 1 ¨ ¸ 1 ZC V TOP ¨ ¸ OUT R R f © 2 1 ¹ SW T uV ON IN The SC402B uses an external resistor to set the on-time Enable and Power-save Inputs which indirectly sets the frequency. The on-time can be The EN/PSV input is used to enable or disable the switch- programmed to provide an operating frequency up to ing regulator. When EN/PSV is low (grounded), the switch- 1MHz using a resistor between the TON pin and ground. ing regulator is off and in its lowest power state. When off, The resistor value is selected by the following equation. the output of the switching regulator soft-discharges the output into a 15Ω internal resistor via the VOUT pin. When k R TON EN/PSV is allowed to float, the pin voltage will float to 33% 25pFuf SW of the voltage at VDD. The switching regulator turns on with power-save disabled and all switching is in forced The constant, k, equals 1 when VDD is greater than 3.6V. If continuous mode. VDD is less than 3.6V and V is greater than (VDD -1.75) x 10, IN k is shown by the following equation. When EN/PSV is high (above 44% of the voltage at VDD), VDD1.75u10 k the switching regulator turns on with power save enabled. V IN 17 SC402B Applications Information (continued) The SC402B PSAVE operation reduces the switching fre- current crosses zero. At this time both MOSFETs remain off quency according to the load for increased efficiency at until V drops to the 600mV threshold. Because the FB light load conditions. MOSFETs are off, the load is supplied by the output capacitor. Forced Continuous Mode Operation If the inductor current does not reach zero on any switch- The SC402B operates the switcher in FCM (Forced ing cycle, the controller immediately exits power-save and Continuous Mode) by floating the EN/PSV pin (see Figure returns to forced continuous mode. 4). In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid cross- Figure 5 shows power-save operation at light loads. conduction. This feature results in uniform frequency across the full load range with the trade-off being poor Dead time varies efficiency at light loads due to the high-frequency switch- according to load FB Ripple ing of the MOSFETs. DH is gate signal to drive upper Voltage MOSFET. DL is lower gate signal to drive lower MOSFET. FB threshold (V ) FB FB Ripple FB threshold Voltage (V ) FB Inductor Zero (0A) Current On-time (T ) ON DC Load Current Inductor Current DH On-time is triggered when V reaches the FB Threshold. FB DH DH on-time is triggered when On-time DL (T ) V reaches the FB Threshold. FB ON DL drives high when on-time is completed. DH DL remains high until inductor current reaches zero. Figure 5 — Power-save Operation DL DL drives high when on-time is completed. Smart Power-save Protection DL remains high until V falls to the FB threshold. FB Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with Figure 4 — Forced Continuous Mode Operation power-save enabled, this can force V to slowly rise and OUT reach the over-voltage threshold, resulting in a hard shut- Power-save Operation down. Smart power save prevents this condition. When The SC402B provides power-save operation at light loads the FB voltage exceeds 10% above nominal, the device with no minimum operating frequency. With power-save immediately disables power save, and DL drives high to enabled, the internal zero crossing comparator monitors turn on the low-side MOSFET. This draws current from the inductor current via the voltage across the low-side V through the inductor and causes V to fall. When V OUT OUT FB MOSFET during the off-time. If the inductor current falls to drops back to the 600mV trip point, a normal T switch- ON zero for 8 consecutive switching cycles, the controller ing cycle begins. This method prevents a hard OVP shut- enters power-save operation. It will turn off the low-side down and also cycles energy from V back to V . It also OUT IN MOSFET on each subsequent cycle provided that the minimizes operating power by avoiding forced conduc- 18 SC402B Applications Information (continued) tion mode operation. Figure 6 shows typical waveforms vate. The current limit then keeps the low-side MOSFET on for the Smart Power Save feature. and will not allow another high-side on-time, until the current in the low-side MOSFET reduces enough to bring V drifts up to due to leakage OUT the ILIM voltage back up to zero. This method regulates current flowing into C V discharges via inductor OUT OUT and low-side MOSFET the inductor valley current at the level shown by ILIM in Smart Power Save Threshold Figure 7. Normal V ripple OUT FB threshold DH and DL off High-side Drive (DH) I PEAK Single DH on-time pulse I LOAD after DL turn-off I LIM Low-side Drive (DL) DL turns on when Smart Normal DL pulse after DH PSAVE threshold is reached on-time pulse DL turns off when FB Time threshold is reached Figure 7 — Valley Current Limit Figure 6 — Smart Power Save Setting the valley current limit to 10A results in a peak inductor current of 10A plus peak ripple current. In this TM SmartDrive situation, the average (load) current through the inductor For each DH pulse the DH driver initially turns on the high- is 10A plus one-half the peak-to-peak ripple current. side MOSFET at a lower speed, allowing a softer, smooth turn-off of the low-side diode. Once the diode is off and The internal 10μA current source is temperature compen- the LX voltage has risen 0.5V above PGND, the SmartDrive sated at 4100ppm in order to provide tracking with the circuit automatically drives the high-side MOSFET on at a RDS . ON rapid rate. This technique reduces switching losses while maintaining high efficiency and also avoids the need for The R value is calculated by the following equation. ILIM snubbers for the power MOSFETs. R = 670 x I x [0.0647 x (5V - VDD) +1] ILIM LIM Current Limit Protection The device features programmable current limiting, which When selecting a value for R be sure not to exceed the ILIM is accomplished by using the RDS of the lower MOSFET absolute maximum voltage value for the ILIM pin. Note ON for current sensing. The current limit is set by R resistor. that because the low-side MOSFET with low RDS is used ILIM ON The R resistor connects from the ILIM pin to the LXS pin for current sensing, the PCB layout, solder connections, ILIM which is also the drain of the low-side MOSFET. When the and PCB connection to the LX node must be done care- low-side MOSFET is on, an internal ~10μA current flows fully to obtain good results. R should be connected ILIM from the ILIM pin and through the R resistor, creating a directly to LXS (pin 28). ILIM voltage drop across the resistor. While the low-side MOSFET is on, the inductor current flows through it and Soft-Start of PWM Regulator creates a voltage across the RDS . The voltage across the SC402B has a programmable soft-start time that is con- ON MOSFET is negative with respect to ground. If this MOSFET trolled by an external capacitor at the SS pin. After the voltage drop exceeds the voltage across R , the voltage controller meets both UVLO and EN/PSV thresholds, the ILIM at the ILIM pin will be negative and current limit will acti- controller has an internal current source of 3µA flowing 19 Inductor Current SC402B Applications Information (continued) when 40% of the voltage at SS pin meets the existing FB through the SS pin to charge the capacitor. During the voltage level. Pre-bias startup is achieved by turning off start up process (Figure 8), 50% of the voltage at the SS the lower gate when the inductor current falls below zero. pin is used as the reference for the FB comparator. The This method prevents the output voltage from PWM comparator issues an on-time pulse when the discharging. voltage at the FB pin is less than 40% of the SS pin. As a result, the output voltage follows the SS voltage. The Power Good Output output voltage reaches and maintains regulation when The PGOOD (power good) output is an open-drain output the soft start voltage is > 1.5V. The time between the first which requires a pull-up resistor. When the voltage at the LX pulse and V reaching regulation is the soft-start time OUT FB pin is 10% below the nominal voltage, PGOOD is pulled (t ). The calculation for the soft-start time is shown by the SS low. It is held low until the output voltage returns above following equation. -8% of nominal. 1.5V t C u SS SS PGOOD will transition low if the V pin exceeds +20% of 3PA FB nominal, which is also the over-voltage shutdown thresh- old. PGOOD also pulls low if the EN/PSV pin is low when The voltage at the SS pin continues to ramp up and eventu- VDD is present. ally equals 64% of V . After the soft start completes, the FB DD pin voltage is compared to an internal reference of 0.6V. The Output Over-Voltage Protection delay time between the V regulation point and PGOOD OUT Over-voltage protection becomes active as soon as the going high is shown by the following equation. device is enabled. The threshold is set at 600mV + 20% (720mV). When V exceeds the OVP threshold, DL latches FB CSSu(0.64uV 1.5V) DD t high and the low-side MOSFET is turned on. DL remains PGOOD-DELAY 3PA high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V falls 25% below its nominal voltage (falls to FB 450mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tri- state the MOSFETs. The controller stays off until EN/PSV is toggled or VDD is cycled. VDD UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switching Figure 8 — Soft-start Timing Diagram and tri-states the DH/DL drivers until VDD rises above 3.0V. An internal POR (Power-On Reset) occurs when VDD exceeds 3.0V, which resets the fault latch and a soft-start Pre-Bias Startup counter cycle begins which prepares for soft-start. The The SC402B can start up normally even when there is an SC402B then begins a soft-start cycle. The PWM will shut existing output voltage present. The soft start time is still off if VDD falls below 2.4V. the same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up 20 SC402B Applications Information (continued) The ENL pin also acts as the switcher under-voltage lockout LDO Regulator for the V supply. When SC402B is self-biased from the LDO SC402B has an option to bias the switcher by using an IN and runs from the V power source only, the V UVLO internal LDO from V . The LDO output is connected to IN IN IN feature can be used to prevent false UV faults for the PWM VDD internally. The output of the LDO is programmable output by programming with a resistor divider at the VIN, by using external resistors from the VDD pin to AGND (see ENL and AGND pins. When SC402B has an external bias Figure 9). The feedback pin (FBL) for the LDO is regulated voltage at VDD and the ENL pin is used to program the V to 750mV. IN UVLO feature, the voltage at FBL needs to be higher than 750mV to force the LDO off. To FBL pin VDD R LDO1 Timing is important when driving ENL with logic and not R LDO2 implementing V UVLO. The ENL pin must transition from IN high to low within 2 switching cycles to avoid the PWM output turning off. If ENL goes below the VIN UVLO threshold and stays above 1V, then the switcher will turn Figure 9 — LDO Output Voltage Selection off but the LDO will remain on. The LDO output voltage is set by the following equation. LDO Start-up Before start-up, the LDO checks the status of the following § · R LDO1 ¨ ¸ VLDO 750mVu 1 ¨ ¸ signals to ensure proper operation can be maintained. R LDO2 © ¹ A minimum capacitance of 1μF referenced to AGND is 1. ENL pin normally required at the output of the LDO for stability. 2. V input voltage IN Note that if the LDO voltage is set lower than 4.5V, the When the ENL pin is high and V is above the UVLO point, IN minimum output capacitance for the LDO is 10uF. the LDO will begin start-up. During the initial phase, when the V voltage (which is the LDO output voltage) is less DD LDO ENL Functions than 0.75V, the LDO initiates a current-limited start-up The ENL input is used to enable/disable the internal LDO. (typically 65mA) to charge the output capacitors while When ENL is a logic low, the LDO is off. When ENL is above protecting from a short circuit event. When V is greater DD the V UVLO threshold, the LDO is enabled and the switcher than 0.75V but still less than 90% of its final value (as IN is also enabled if the EN/PSV and VDD are above their sensed at the FBL pin), the LDO current limit is increased threshold. The table below summarizes the function of ENL to ~115mA. When V has reached 90% of the final value DD and EN/PSV pins. (as sensed at the FBL pin), the LDO current limit is increased to ~200mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is recom- ENL LDO Switcher EN/PSV mended that during LDO start-up to hold the PWM Disabled Low, < 0.4V OFF OFF switching off until the LDO has reached 90% of the final Enabled Low, < 0.4V OFF ON value. This prevents overloading the current-limited LDO Disabled 1.0V < High < 2.6V ON OFF output during the LDO start-up. Enabled 1.0V < High < 2.6V ON OFF Disabled High, > 2.6V ON OFF Enabled High, > 2.6V ON ON 21 SC402B Applications Information (continued) Due to the initial current limitations on the LDO during Switch-over MOSFET Parasitic Diodes power up (Figure 10), any external load attached to the The switch-over MOSFET contains parasitic diodes that VDD pin must be limited to less than the start up current are inherent to its construction, as shown in Figure 11. If before the LDO has reached 90% of its final regulation the voltage at the VOUT pin is higher than VDD, then the value. respective diode will turn on and the current will flow through this diode. This has the potential of damaging the device. Therefore, V must be less than VDD to OUT V Final VLDO prevent damaging the device. Voltage regulating with ~ 200mA 90% of current limit V Final VLDO Switchover Switchover control MOSFET Constant current LDO V OUT startup @ ~ 115mA 0.7V Short-circuit Protection @ ~ 65mA Figure 10 — LDO Start-Up Parasitic diode VDD LDO Switch-Over Operation The SC402B includes a switch-over function for the LDO. Figure 11— Switch-over MOSFET Parasitic Diodes The switch-over function is designed to increase efficiency by using the more efficient DC-DC converter to power the Design Procedure LDO output, avoiding the less efficient LDO regulator When designing a switch mode supply the input voltage when possible. The switch-over function connects the range, load current, switching frequency, and inductor VDD pin directly to the VOUT pin using an internal switch. ripple current must be specified. When the switch-over is complete the LDO is turned off, which results in a power savings and maximizes efficiency. The maximum input voltage (V ) is the highest speci- INMAX If the LDO output is used to bias the SC402B, then after fied input voltage. The minimum input voltage ( V ) is INMIN switch-over the device is self-powered from the switching determined by the lowest input voltage after evaluating regulator with the LDO turned off. the voltage drops due to connectors, fuses, switches, and PCB traces. The switch-over starts 32 switching cycles after PGOOD output goes high. The voltages at the VDD and VOUT pins The following parameters define the design. are then compared; if the two voltages are within ±300mV of each other, the VDD pin connects to the VOUT pin using • Nominal output voltage (V ) OUT an internal switch, and the LDO is turned off. To avoid • Static or DC output tolerance unwanted switch-over, the minimum difference between • Transient response the voltages for VOUT and VDD should be ±500mV. • Maximum load current (I ) OUT It is not recommended to use the switch-over feature for an output voltage less than VDD UVLO threshold since the SC402B is not operational below that threshold. 22 SC402B Applications Information (continued) There are two values of load current to evaluate — con- current/voltage and for a given DC resistance are more tinuous load current and peak load current. Continuous efficient. However, larger inductance translates directly load current relates to thermal stresses which drive the into larger packages and higher cost. Cost, size, output selection of the inductor and input capacitors. Peak load ripple, and efficiency are all used in the selection process. current determines instantaneous component stresses The ripple current will also set the boundary for PSAVE and filtering requirements such as inductor saturation, operation. The switching will typically enter PSAVE mode output capacitors, and design of the current limit circuit. when the load current decreases to 1/2 of the ripple The following values are used in this design. current. For example, if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple • V = 12V + 10% current is set at 40% of maximum load current, then PSAVE IN • V = 1.5V + 4% will start for loads less than 20% of maximum current. OUT • f = 300kHz SW • Load = 10A maximum The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load Frequency Selection current. This provides an optimal trade-off between cost, Selection of the switching frequency requires making a efficiency, and transient performance. trade-off between the size and cost of the external filter components (inductor and output capacitor) and the During the on-time, voltage across the inductor is power conversion efficiency. (V - V ). The equation for determining inductance is IN OUT shown next. The desired switching frequency is 300kHz which results from using components selected for optimum size and (V V )uT IN OUT ON L cost. I RIPPLE Example A resistor (R ) is used to program the on-time (indirectly TON In this example, the inductor ripple current is set equal to setting the frequency) using the following equation. 45% of the maximum load current. Therefore ripple k current will be 45% x 10A or 4.5A. To find the minimum R TON 25pFuf SW inductance needed, use the V and T values that corre- IN ON spond to V . To select R , use the maximum value for V , and for T INMAX TON IN ON use the value associated with maximum V . IN (13.21.5)u379ns L 0.99PH V 4.5A OUT T ON V uf INMAX SW A slightly larger value of 1µH is selected. This will decrease the maximum I to 4.43A. RIPPLE T = 379 ns at 13.2V , 1.5V , 300kHz ON IN OUT Note that the inductor must be rated for the maximum DC Substituting for R results in the following solution. TON load current plus 1/2 of the ripple current. R = 133.3kΩ, use R = 130kΩ TON TON Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple 23 SC402B Applications Information (continued) The ripple current under minimum V conditions is also 2 1 IN § · 1PH 10 u 4.43 ¨ ¸ checked using the following equations. 2 © ¹ COUT MIN 2 2 1.65 1.5 25pFuR uV TON OUT T 451ns ON_VINMIN V INMIN COUT = 316µF MIN (V V )uT During the load release time, the voltage cross the induc- IN OUT ON I RIPPLE L tor is approximately -V . This causes a down-slope or OUT falling di/dt in the inductor. If the load di/dt is not much (10.81.5)u451ns I 4.19A RIPPLE_VINMIN faster than the di/dt of the inductor, then the inductor 1PH current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed Capacitor Selection by the output capacitor, therefore a smaller capacitance The output capacitors are chosen based upon required can be used. ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC The following can be used to calculate the needed capaci- tolerance. The output voltage has a DC value that is equal tance for a given dI /dt. to the valley of the output ripple plus 1/2 of the peak-to- LOAD peak ripple. A change in the output ripple voltage will Peak inductor current is shown by the next equation. lead to a change in DC voltage at the output. I = I + 1/2 x I LPK MAX RIPPLEMAX The design goal for output voltage ripple is 3% of 1.5V or 45mV. The maximum ESR value allowed is shown by the I = 10 + 1/2 x 4.43 = 12.215A LPK following equations. dl LOAD RateofchangeofLoadCurrent V 45mV RIPPLE ESR dt MAX I 4.43A RIPPLEMAX I = maximum load release = 10A MAX ESR = 10.2 mΩ MAX I I LPK MAX The output capacitance is usually chosen to meet tran- Lu  u dt V dl OUT LOAD sient requirements. A worst-case load release, from C I u OUT LPK maximum load to no load at the exact moment when 2V  V  PK OUT inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load Example changes from maximum to zero in < 1µs), the output dl 2.5A LOAD capacitor must absorb all the inductor’s stored energy. dt 1Ps This will cause a peak voltage on the capacitor according to the following equation. This would cause the output current to move from 10A to 0A in 4µs, giving the minimum output capacitance 2 1 § · requirement shown in the following equation. L I  uI ¨ ¸ OUT RIPPLEMAX 2 © ¹ COUT MIN 2 2 12.215 10 V  V  PEAK OUT 1PHu  u1Ps 1.5 2.5 C 12.215u OUT Assuming a peak voltage V of 1.65V (150mV rise upon PEAK 21.651.5 load release), and a 10A load release, the required capaci- C = 169 µF OUT tance is shown by the next equation. 24 SC402B Applications Information (continued) Note that C is much smaller in this example, 169µF ESR loop instability is caused by insufficient ESR. The OUT compared to 316µF based on a worst-case load release. To details of this stability issue are discussed in the ESR meet the two design criteria of minimum 316µF and Requirements section. The best method for checking sta- maximum 10.2mΩ ESR, select one capacitor of 330µF and bility is to apply a zero-to-full load transient and observe 9mΩ ESR. the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial It is recommended that an additional small capacitor be step is an indication that the ESR should be increased. placed in parallel with C in order to filter high frequency OUT switching noise. ESR Requirements A minimum ESR is required for two reasons. One reason is Stability Considerations to generate enough output ripple voltage to provide Unstable operation is possible with adaptive on-time con- 10mVp-p at the FB pin (after the resistor divider) to avoid trollers, and usually takes the form of double-pulsing or double-pulsing. ESR loop instability. The second reason is to prevent instability due to insuffi- Double-pulsing occurs due to switching noise seen at the cient ESR. The on-time control regulates the valley of the FB input or because the FB ripple voltage is too low. This output ripple voltage. This ripple voltage is the sum of the causes the FB comparator to trigger prematurely after the two voltages. One is the ripple generated by the ESR, the 250ns minimum off-time has expired. In extreme cases other is the ripple due to capacitive charging and dis- the noise can cause three or more successive on-times. charging during the switching cycle. For most applica- Double-pulsing will result in higher ripple voltage at the tions the minimum ESR ripple voltage is dominated by the output, but in most applications it will not affect opera- output capacitors, typically SP or POSCAP devices. For tion. This form of instability can usually be avoided by stability the ESR zero of the output capacitor should be providing the FB pin with a smooth, clean ripple signal lower than approximately one-third the switching fre- that is at least 10mVp-p, which may dictate the need to quency. The formula for minimum ESR is shown by the increase the ESR of the output capacitors. It is also impera- following equation. tive to provide a proper PCB layout as discussed in the Layout Guidelines section. 3 ESR MIN 2uSuC uf OUT sw Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis- Using Ceramic Output Capacitors tor, as shown in Figure 12. This capacitor should be left When the system is using high ESR value capacitors, the unpopulated until it can be confirmed that double-pulsing feedback voltage ripple lags the phase node voltage by 90 exists. Adding the C capacitor will couple more ripple TOP degrees. Therefore, the converter is easily stabilized. into FB to help eliminate the problem. An optional con- When the system is using ceramic output capacitors, the nection on the PCB should be available for this capacitor. ESR value is normally too small to meet the above ESR cri- teria. As a result, the feedback voltage ripple is 180 C TOP degrees from the phase node and behaves in an unstable manner. In this application it is necessary to add a small To FB pin V R1 OUT R2 Figure 12 — Capacitor Coupling to FB Pin 25 SC402B Applications Information (continued) virtual ESR network that is composed of two capacitors and one resistor, as shown in Figure 13. Figure 15 shows the magnitude of the ripple contribution due to the output voltage ripple at the FB pin. DCR L L DCR C V R L V OUT OUT L V L R L V L R 1 C OUT C C C C L R R 1 C 1 + C D x V C IN - C OUT C R 2 OUT FB R R 2 2 pin FB FB pin pin Figure 13 — Virtual ESR Ramp Circuit Figure 15 — FB Voltage by Output Voltage The ripple voltage at FB is a superposition of two voltage It is shown by the following equation. sources: the voltage across C and output ripple voltage. L They are defined in the following equations. R 2 VFB'V 'V u OUT OUT 1 R1// R ILuDCR(suL/DCR1) 2 Vc SuC C L SuRC 1 L L The purpose of this network is to couple the inductor 'I L current ripple information into the feedback voltage such 'V OUT 8Cuf SW that the feedback voltage has 90 degrees phase lag to the switching node similar to the case of using standard high Figure 14 shows the magnitude of the ripple contribution ESR capacitors. This is illustrated in Figure 16. due to C at the FB pin. L FB contribution by V OUT LX output voltage ripple FB R L L FB contribution C pin C V L by C D x V L IN + - C R R DCR L 1 2 Combined FB I L Figure 16 — FB voltage in Phasor Diagram Figure 14 — FB Voltage by CL Voltage The magnitude of the feedback ripple voltage, which is It is shown by the following equation. dominated by the contribution from C , is controlled by L the value of R , R and C . If the corner frequency of (R // 1 2 C 1 R ) x C is too high, the ripple magnitude at the FB pin will R1//R2uSuC C 2 C VFBc Vc u L L be smaller, which can lead to double-pulsing. Conversely,   R1//R2 uSuC 1 C if the corner frequency of (R // R ) x C is too low, the 1 2 C ripple magnitude at FB pin will be higher. Since the 26 SC402B Applications Information (continued) SC402B regulates to the valley of the ripple voltage at the The on-time pulse from the SC402B in the design example FB pin, a high ripple magnitude is undesirable as it signifi- is calculated to give a pseudo-fixed frequency of 300kHz. cantly impacts the output voltage regulation. As a result, Some frequency variation with line and load is expected. it is desirable to select a corner frequency for (R // R ) x C This variation changes the output ripple voltage. Because 1 2 C to achieve enough, but not excessive, ripple magnitude adaptive on-time converters regulate to the valley of the and phase margin. The component values for R , R , and output ripple, ½ of the output ripple appears as a DC regu- 1 2 C should be calculated using the following procedure. lation error. For example, if the output ripple is 50mV with C V = 6 volts, then the measured DC output will be 25mV IN Select C (typical 10nF) and R to match with L and DCR above the comparator trip point. If the ripple increases to L L time constant using the following equation. 80mV with V = 25V, then the measured DC output will be IN 40mV above the comparator trip. The best way to mini- L R mize this effect is to minimize the output ripple. L DCRuC L The use of 1% feedback resistors may result in up to 1% error. If tighter DC accuracy is required, 0.1% resistors Select C by using the following equation. C should be used. 1 3 C | u C R//R 2uSufsw The output inductor value may change with current. This 1 2 will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR The resistor values (R and R ) in the voltage divider circuit 1 2 also affects the output ripple and thus has a minor effect set the V for the switcher. The typical value for C is OUT C on the DC output voltage. from 10pF to 1nF. Switching Frequency Variation Dropout Performance The switching frequency varies with load current as a The output voltage adjustment range for continuous con- result of the power losses in the MOSFETs and DCR of the duction operation is limited by the fixed 250ns (typical) inductor. For a conventional PWM constant-frequency minimum off-time of the one-shot. When working with converter, as load increases the duty cycle also increases low input voltages, the duty-factor limit must be calcu- slightly to compensate for IR and switching losses in the lated using worst-case values for on and off times. MOSFETs and inductor. An adaptive on-time converter The duty-factor limitation is shown by the next equation. must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V as losses increase). The on-time is essen- T ON(MIN) IN DUTY tially constant for a given V /V combination, to offset T T OUT IN ON(MIN) OFF(MAX) the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency The inductor resistance and MOSFET on-state voltage increases slightly with increasing load. drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (V Controller) OUT Three factors affect V accuracy: the trip point of the FB OUT error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static condi- tions it trips when the feedback pin is 750mV, 1%. 27 CBST VDD SC402B Applications Information (continued) IC Decoupling Capacitors PCB Layout Guidelines • A 1 μF capacitor must be located as close as pos- The optimum layout for the SC402B is shown in Figure 17. sible to the IC and directly connected to pins 3 This layout shows an integrated FET buck regulator with a (VDD) and 4 (AGND). maximum current of 10A. The total PCB area is approxi- • Another 1 μF capacitor must be located as close mately 25 x 29 mm with single side components. as possible to the IC and directly connected to Critical Layout Guidelines pins 3 (VDD) and PGND plane. The following critical layout guidelines must be followed PGND Plane to ensure proper performance of the device. • PGND requires its own copper plane with no other signal traces routed on it. • IC Decoupling capacitors • Copper planes, multiple vias and wide traces are • PGND plane needed to connect PGND to input capacitors, • AGND island output capacitors, and the PGND pins on the IC. • FB, VOUT, and other analog control signals • The PGND copper area between the input • C SS capacitors, output capacitors and PGND pins • BST, ILIM, and LX must be as tight and compact as possible to • C and C placement and Current Loops IN OUT reduce the area of the PCB that is exposed to noise due to current flow on this node. All components shown Top Side VDD Decoupling Capacitor IC with vias for Pin 1 marking LX, AGND, VIN AGND plane on inner layer LX plane on top and RFB2 RFB1 bottom layer L CTOP Vout sense trace VOUT Plane on top on inner layer C IN and bottom layer C IN SP or C OUT POSCAP PGND on inner Cer. or bottom layer V plane on RGND — AGND connects to IN PGND on top top and/or PGND close to IC layer bottom layer Figure 17 — PCB Layout 28 RGND Css RTON RILIM SC402B Applications Information (continued) AGND Island • Multiple vias should be used on the LX PAD to • AGND should have its own island of copper with provide good thermals and connection to an no other signal traces routed on this layer that internal or bottom layer LX plane. connects the AGND pins and pad of the IC to the analog control components. Capacitors and Current Loops • All of the components for the analog control cir- • Figure 17 shows the placement of input/output cuitry should be located so that the connections capacitors and inductor. This placement shows to AGND are done by wide copper traces or vias the smallest current loops between the input/ down to AGND. output capacitors, the SC402B and the inductor • Connect PGND to AGND with a short trace or 0Ω to reduce the IR drop across the copper. resistor. This connection should be as close to the IC as possible. FB, VOUT, and Other Analog Control Signals • The connection from the V power to the OUT analog control circuitry must be routed from the output capacitors and located on a quiet layer. • The traces between Vout and the analog control circuitry (VOUT, and FB pins) must be wide, short and routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. • The feedback components for the switcher and the LDO need to be as close to the FB and FBL pins of the IC as possible to reduce the possibil- ity of noise corrupting these analog signals. BST, ILIM,TON,SS and LX • The connections for the boost capacitor between the BST and LXBST must be short, wide and directly connected. • ILIM and TON nodes must be as short as possible to ensure the best accuracy in current limit and on time. • R should be close to the IC and connected ILIM between LXS (pin 28) and ILIM (pin 27) only. • R should be close to the IC and connected TON between TON (pin 31) and AGND (pin 30). • C should be close to the IC and kept away SOFT from the boost capacitor. Connect the AGND end of C to the AGND plane at pin 4. SOFT • The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos- sibility of LX noise corrupting other signals. 29 SC402B Outline Drawing — MLPQ-5x5-32 DIMENSIONS B A D INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .031 .039 0.80 1.00 - - A1 .000 .002 0.00 0.05 - (.008) - - (0.20) - A2 b .007 .010 0.25 0.30 PIN 1 .012 0.18 E INDICATOR D .193 .197 .201 4.90 5.00 5.10 (LASER MARK) .076 .078 1.92 1.97 D1 .080 2.02 E .193 .197 .201 4.90 5.00 5.10 E1 .135 .137 .139 3.43 3.48 3.53 e .020 BSC 0.50 BSC L .012 .016 .020 0.30 0.40 0.50 A2 N 32 32 aaa .003 0.08 bbb .004 0.10 A SEATING PLANE aaa C C A1 3.48 D1 0.76 1.05 LxN 1.49 3.61 E1 1.66 2 1 0.76 N R0.20 bxN PIN 1 IDENTIFICATION e bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 30 SC402B Land Pattern — MLPQ-5x5-32 3.48 K1 K DIMENSIONS 1.74 DIM INCHES MILLIMETERS (.195) (4.95) C G .165 4.20 H .137 3.48 H2 1.74 H1 .059 1.49 (C) G H 3.61 .065 1.66 Z H2 K .078 1.97 H1 K1 .041 1.05 P .020 0.50 Y X .012 0.30 Y .030 0.75 X Z .224 5.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. 31 SC402B © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse- quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 32