SEMTECH SC339

SC339 Ultra Low Output Voltage Linear FET Controller POWER MANAGEMENT Description Features The SC339 is an ultra-low output voltage, linear power  ± % Voltage Accuracy Over-Temperature supply controller designed to simplify power manage-  Low Shutdown Current ment for notebook PCs. It is part of Semtech’s Smart  Runs Off 5V Supply TM LDO family of products. The SC339 has a user  Ultra-Fast Transient Response adjustable output that can be set anywhere between 0.5V  Enable Control for the Output and 3.3V using two external resistors.  Power Good Monitoring and Signaling for the Output  Gate Drive from Input Supply Enables Use of SC339 features include tight output voltage regulation (± N-Channel MOSFET % over 0°C to +85°C), enable control, open drain power  User Selectable Dropout Voltage good signal, under-voltage protection and soft-start. The enable pin allows the part to enter a very low power standby  Under-Voltage Protection for the Output mode. Pulling it high enables the output. The power good  SOT-23 6-pin Surface Mount Package pin is an open drain and asserts low when the voltage at  Compatible with Ceramic Capacitors the adjust pin is below 88% (typ) of nominal. If the voltage  Low Ripple Output at the adjust pin is below 50% (typ) of nominal, the under-  Internal ms soft-start requires no external compo- voltage protection circuitry will shut down the output. The nents SC339 is available in a tiny SOT-23 6-pin surface mount  Fully WEEE and RoHS compliant package. Applications  Notebook PCs  Desktop Computers  Battery Powered Devices Typical Application Circuit  Portable Instruments 1.2V +/-5% IN IRF7311 C1 or similar V = (1+R1/R2)*0.5 out 1.05V @ 3A C2 5V IN R1 DRV IN GND SC339 ADJ 1.05V EN PGD 1.05V Enable Power Good (1) R3 C4 R2 (1) Notes: C3 (1) Optional Components to use with ceramic output capacitors (C2) Sept , 2006 www.semtech.com  SC339 PRELIMINARY POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. Parameter Symbol Maximum Units Input Supply Voltage V -0.3 to +6 V IN Drive Pin V -0.3 to V + 0.3V V DRV IN Adjust and Power Good Pin V , V -0.3 to V + 0.3V V ADJ PGD IN Enable Pin V -0.3 to V + 0.3V V EN IN Thermal Impedance Junction to Ambient θ 190 °C/W JA Thermal Impedance Junction to Case θ 81 °C/W JC Operating Ambient Temperature Range T -40 to +85 °C A Operating Junction Temperature Range T -40 to +125 °C J Storage Temperature Range T -65 to +150 °C STG Lead Temperature (Soldering) 10 Sec. T 300 °C LEAD ESD Rating (Human Body Model) V 2 kV ESD Electrical Characteristics () Unless specified: T = 25°C, V = V = 5V ± 5%, V = .5V ± 5%, 0A ≤ I ≤ 3A. Values in bold apply over full operating ambient temperature range. A IN EN PWR OUT Parameter Symbol Conditions Min Typ Max Units Supply Voltage V 4.5 5 5.5 V IN Quiescent Current I V = 5V 130 200 µA Q IN Standby Current I EN low 0.1 1.0 µA Q(OFF) Input Under-Voltage Lockout Start Threshold V V rising 4.20 V UVLO IN Hysteresis V V falling 0.10 V HYST IN EN V Output on 2.8 IH Enable Input Threshold V V Output off 1.8 IL Enable Input Bias Current V = V = 5V -1 +1 µA IN EN  2006 Semtech Corp. www.semtech.com 2 SC339 POWER MANAGEMENT Electrical Characteristics Parameter Symbol Conditions Min Typ Max Units ADJ Adjust Input Bias Current I V = 0.5V -100 0 +100 nA ADJ ADJ Reference Voltage V 0°C ≤ T ≤ +85°C -1% 0.500 1% V ADJ A DRV Sourcing 5 20 mA Output Current I DRV Sinking 5 20 mA Output Voltage V Full On, I = 0mA, V = 5V 4.70 4.85 V DRV DRV IN Output Under-Voltage Protection (2) Trip Threshold V Measured at ADJ pin 40 50 60 %V TH(UV) ADJ PGD (3) Power Good Threshold V Measured at ADJ pin -15 -12 -8 %V TH(PGD) ADJ Output Logic Low Voltage V V = 0.4V, I = -1mA 0.4 V PGD ADJ PGD Power Good I V = 0.5V, 0V ≤ V ≤ V -1 0 +1 µA PGD ADJ PGD IN Leakage Current Soft-Start Output Rise Time 10% VOUT From EN rising to t 500 1000 2000 µs r to 90% VOUT, VOUT = 1.05V 99% of V OUT Notes: ) V = input voltage to pass device drain (or source depending upon orientation of FET). PWR 2) If V is exceeded for longer than ms (nom.) the protection circuitry will shut down the output. TH(UV) 3) During start-up only, V is -6% (typical), then switches to -2% (typical). TH(PGD)  2006 Semtech Corp. www.semtech.com 3 SC339 PRELIMINARY POWER MANAGEMENT Pin Configuration Ordering Information Part Number Package Top View SC339SKTRT SOT-23 6 Pin IN DRV 1 6 GND ADJ SC339EVB Evaluation Board 5 2 Notes: EN 4 3 PGD ) Only available in tape and reel packaging. A reel contains 3000 devices. 2) V = 5V IN (SOT-23 6L) 3) V is ± 1% over 0°C ≤ T ≤ +85°C. ADJ A ) Lead-free product. This product is fully WEEE and RoHS compliant. Marking Information Marking for SOT23, 6 lead package: yyww = Datecode (Example: E652) Pin Descriptions Pin Pin Name Pin Function 1 IN 5V supply 2 GND Ground 3 EN Active high enable control - connect to IN if not being used - do not allow to float 4 PGD Power good signal output for V OUT Regulator sense input - used for sensing the output voltage for power good and 5 ADJ under-voltage and to set the output voltage 6 DRV Output of regulator - drives the gate of an N-channel MOSFET to maintain V OUT set by R1 and R2  2006 Semtech Corp. www.semtech.com  SC339 POWER MANAGEMENT Block Diagram IN 0.5V Bandgap Vref Reference ( 0.5V) Shutdown EN Control DRV Vref + - ADJ Error Amplifier 0.5 VBG Under + Voltage Control - Undervoltage Comparator PGD 0.88 VBG + (0.95 VBG At start-up) - GND Power Good Comparator  2006 Semtech Corp. www.semtech.com 5 SC339 PRELIMINARY POWER MANAGEMENT Applications Information Theory Of Operation stabilize. The power-up is very smooth and monotonic. The SC339 linear FET controller provides a simple OCP and Power Supply Sequencing way to drive an N-channel MOSFET to produce tightly regulated output voltages from an available, The SC339 has output under-voltage protection that higher, supply voltage. It takes its power from looks at the output to see if it is: a) less than 50% (typi- the 5V system supply, drawing 30µA (typ) while cal) of its nominal value and, b) V for that output is DRV operating. within 350mV (typical) of maximum. If both of these criteria are met, there is a ms (typical) delay and It contains an internal bandgap reference which is then the output is shut down. This provides inherent compared to the output voltage via a resistor divider. immunity to UV shutdown at start-up (which may occur while The resistor divider is external and user selectable. The the output capacitors are being charged). drive pin (DRV) can pull up to a guaranteed minimum of .7V. Thus, the device can be used to regulate a large At start-up, it is necessary to ensure the power range of output voltages by careful selection of the supplies and enable are sequenced correctly to external MOSFETs (see Component Selection on this avoid erroneous latch-off. For UV latch-off not to oc- page). cur at start-up due to sequencing issues, the volt- age supplied to the MOSFET drain should be greater The SC339 includes an active high enable control (EN). If than the output under-voltage threshold when that this pin is pulled low, the drive pin is pulled low, turning output is enabled. This assumes that the drop through the off the N-channel MOSFET. If the pin is pulled up to 2.8V pass MOSFET is negligible. If not, then this drop needs to ≤ V ≤ V , the drive pin is enabled. This pin should not be taken into account also since: EN IN be allowed to float. V = V - (I x R ) OUT DRAIN OUT DS(ON) The SC339 has a power good output (PGD) which is an open drain output that pulls low if the related output is If the supply to the SC339 IN pin comes up before the below the power good threshold (-2% of the programmed supply to the MOSFET drain, then that output should be output voltage typical). The power good circuitry is active enabled after the supply to the MOSFET drain is applied if the device is enabled, regardless of the state of the - the power good signal for this rail would be ideal. If the over-current latch. power supply to the MOSFET drain comes up before the power supply to the SC339 IN pin, then the output can either An over-current protection circuit monitors the output voltage. be enabled with the supply to the IN pin or afterwards. If the output voltage drops below 50% (typical) of nominal, as would occur during an over-current or short condition, the Please note the following example: device will pull the drive pin low and latch off. Toggle the power supply or enable pin to reset the latch condition. SC339 powered from 5V, the MOSFET (V ) powered from DRAIN .8V, set for .5V . Worst-case: under-voltage threshold is OUT Drive Output 60% (over temperature) of .5V, or 0.9V. The typical enable threshold is ~2.V, see Figure  on Page 7. The drive output is source and sink capable. The drivers both source and sink 20mA of current typically at 5V IN. Component Selection Soft-Start and Power Good Timing Output Capacitors: low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for At start-up, the internal reference is switched from its bulk capacitance, with ceramic bypass capacitors for normal 0.5VDC to a ms (typical) linear ramp. The output decoupling high frequency transients. Ceramic output voltage tracks the ramp until 0.5V is reached. The PWRGD capacitors may be used; however, use of ceramic output signal is held low until the output has been in regulation capacitors requires compensation on the DRV output. approximately 500µsec to allow the output voltage to  2006 Semtech Corp. www.semtech.com 6 SC339 POWER MANAGEMENT Applications Information (Cont.) Note: R must be met at all temperatures and at the mini- Input Capacitors: placement of low ESR capacitors such DS(ON) mum V condition. as Sanyo POSCAPs or Panasonic SP-caps at the input to GS the MOSFET (V ) will help to hold up the power supply DRAIN Setting The Output Voltage: the adjust pin connects during fast load changes, thus improving overall transient directly to the inverting input of the error amplifier, and response. If V is located at the bulk capacitors for DRAIN the output voltage is set using external resistors (please the upstream voltage regulator, additional capacitance refer to the Typical Application Circuit on Page ). may not be required. In this case a 0.µF ceramic capacitor will suffice. The 5V bias supply to the SC339 Using output  as an example, the output voltage can be should be bypassed with a 0.µF ceramic capacitor. calculated as follows: MOSFETs: very low or low threshold N-channel R V = 0.5 • (  + —— ) MOSFETs are required. Select FETs rated for V OUT GS R2 of 2.7V or lower. For the device to work under all operating conditions, a maximum R must be met to DS(ON) The input bias current for the adjust pin is so low that ensure that the output will never go into dropout: it can be safely ignored. To avoid picking up noise, it is recommended that the total resistance of the feedback V V IN(MIN) ― OUT(MAX) chain be less than 00kΩ. With ceramic capacitors, a R = ——————— Ω DSON(MAX) I OUT(MAX) recommended divider current of >00µA is recommended to keep the FET conducting during light load conditions to improve transient response. 2.8V SC339 Supply Comes Up Before MOSFET Drain Supply 2.7V MOSFET Drain Supply Comes Up Before SC339 Supply Power Supply Sequencing  2006 Semtech Corp. www.semtech.com 7 SC339 PRELIMINARY POWER MANAGEMENT Applications Information (Cont.) Table  lists recommended resistor values for some stan- Total DC error = ±2.25% = 23.6mV dard output voltages. All resistors are %, /0W. This leaves ±2.75% = 28.875mV for the load transient ESR The maximum output voltage that can be obtained spike, therefore: from each output is determined by the input supply voltage and the R and gate threshold voltage of the DS(ON) 28.875mV external MOSFET. Assuming that the MOSFET gate R = —————— = .55mΩ ESR(MAX) 2.5A threshold voltage is sufficiently low for the output voltage chosen and the worst-case drive voltage, V OUT(MAX) is given by: Bulk capacitance required is given by: V = V ― I • R dl • τ OUT (MAX) DRAIN(MIN) OUT(MAX) DSON(MAX) C = ——— = µF BULK(MIN) dV V (V) R1 or R3 (kΩ) R2 or R4 (kΩ) OUT Where dI is the maximum load current step, t is the 1.05 11.0 10.0 maximum regulator response time and dV is the 1.2 14.0 10.0 allowable voltage droop. Therefore with dI = 2.5A, t = 1µs, and dV = 28.875mV: 1.5 20.0 10.0 2.5 45.3 11.3 6 3.3 63.4 11.3 2.5 •  • 0¯ C = ———————— = 87µF BULK(MIN) 3 Recommended Resistor Values For SC339 28.875 • 0¯ Design Example So if we use % V set resistors we would select OUT 00µF, 2mΩ POSCAP for output capacitance (which Goal: 1.05V±5% @ up to 2.5A from 1.2V±5% and 5V±5% assumes that local ceramic bypass capacitors will absorb the balance of the (2 - .55)mΩ ESR Solution 1: No Passive Droop requirement - otherwise 0mΩ capacitors should be used). Total window for DC error, ripple and transient is If we use 0.% set resistors, then the total DC error ±52.5mV. becomes ±.35% = ±5.75mV, leaving ±3.65% = 38.33mV for the ESR spike. In this case: Since this device is linear and assuming that it has been designed to not ever enter dropout, there is negligible ripple 38.33mV on the output. R = ———— = 5.33mΩ and, ESR(MAX) 2.5A The DC error for this output is the sum of: 6 2.5 •  • 0¯ = ——————— = 65µF V accuracy = ±% = ±0.5mV C ADJ BULK(MIN) 3 38.33 • 0¯ Feedback chain tolerance = ±% = ±0.5mV So for 0.% resistors we could use  x 00µF, 5mΩ Load regulation = ±0.25% = ±2.6mV POSCAP for output capacitance. Resistors per Table  should be .0kΩ (top) and 0.0kΩ (bottom).  2006 Semtech Corp. www.semtech.com 8 SC339 POWER MANAGEMENT Applications Information (Cont.) This is a very severe example, since the output Solution 2: Using Passive Droop voltage is so low, therefore the allowable window is very small. See Solution 2 for an alternate 1.2V +/-5% IN C1 circuit. For higher output voltages the components 0.1uF required will be less stringent. RDROOP 1.075V 1.05V @ 2.5A Q1 C3 20mOhm The input capacitance needs to be large enough to stop the input supply from collapsing below -5% (i.e., the design minimum) during output load steps. If the input R1 SC339 U1 100uF, 25mOhm POSCAP 11.0k PGD EN 3 4 to the pass MOSFET is not local to the supply bulk 5 2 ADJ GND capacitance then additional bulk capacitance may be 6 IN DRV 1 required. R2 10.0k MOSFET selection: since the input voltage to the SC339 is 5V±5%, the minimum available gate drive is: V = (4.4 ― 1.1025) = 3.3V Passive droop allows us to use almost the full output GS tolerance window for transients, therefore making the output capacitor selection simpler and less So a MOSFET rated for V = 2.7V will be required, with an expensive. The trade-offs are the cost of the droop GS R (over-temperature) given by: resistor versus the reduction in output capacitor cost, DS(ON)(MAX) and the reduction in headroom which impacts MOSFET selection. The top of the feedback chain connects to the V ― V ( ) (1.14 ― 1.05) IN(MIN) OUT R = —————— = —————— = 36mΩ input side of R , and the output is set for .075V. Thus DSON(MAX) DROOP I 2.5 at no load, V will be .075V (or .05V + 2.%) and at I OUT(MAX) OUT OUT = 2.5A, V will be .025V (or .05V - 2.%). OUT MOSFET SELECTION If % set resistors are used, the total DC error will be SO-8 Footprint ±2.25% = 2mV. Thus, at no load, the minimum output Vgs Rds-on Imax voltage will be given by: FDS6682 .7V 9mΩ A IRF756 .5V 6.5mΩ 6A V = 1.075 ― 0.024 = .05V OUT(MIN_NO_LOAD) 206 Footprint This leaves 53.5mV for transient response, giving: Vgs Rds-on Imax Si506DC 0.6V 20mΩ 9.5A 53.5mV and, = 2.mΩ R = ———— ESR(MAX) 2.5A NTHS50 0.6V 25mΩ 7.2A SOT-23 Footprint 6 2.5 •  • 0¯ = 7µF C = ——————— Vgs Rds-on Imax BULK(MIN) 3 53.5 •0¯ IRLMS2002 V 30mΩ 5.2A FDN337N 0.7V 65mΩ 2.2A Instead of 2 x 00µF, 2mΩ capacitors, we can use  x (when Input 7µF, 5mΩ capacitor. is > .2V for .05V output)  2006 Semtech Corp. www.semtech.com 9 SC339 PRELIMINARY POWER MANAGEMENT Applications Information (Cont.) Using Ceramic Capacitors From this response we see that the system is not stable as it has a phase margin of approximately 0 degrees. SC339 is capable of operation using an all-ceramic so- lution, needing only an external R-C compensation. The For stable operation we introduce a low frequency pole Typical Application schematic (R3, C3) from page  is re- and a zero. The low frequency pole is used to roll off the produced here: gain quicker and the zero is used to increase the band- width of the system. 1.2 V +/-5 % IN IRF7311 C1 or similar The Pole-Zero location: V = (1+R1/R2)*0.5 out 1.05V @ 3A C2 Gain (dB) PHASE (deg) 5V IN R1 60 270 IN DRV Pin + Pcomp GND SC339 ADJ 1.05V Ceramic Capacitor EN PGD 1.05V 40 180 Enable Power Good (1) Operation with R 3 Compensation on DRV pin C4 R2 90 20 (1) Notes : C 3 Prout (1) Optional Components to use with ceramic output capacitors (C2) Zin + Zcomp Pcout FREQ (Hz) 0,0 100 1K 10K 100K 1MEG 10MEG Typical Applications Circuit -20 PHASE -90 -40 -180 Typical Frequency Response without Compensation and Ceramic Output Capacitors: -60 -270 Gain (dB) PHASE (deg) Low frequency pole generated internally SC339 Frequency Response with 60 270 Low frequency zero Pin generated internally Ceramic Output Capacitors and R-C Compensation Rout / Cout pole, moves with the load current Prout Zin 40 180 High frequency pole From the above figure we can see that the overall re- generated by ESR 90 20 and Output Capacitor Pcout sponse of the system is stable with a decent phase margin FREQ (Hz) 0,0 100 1K 10K 100K 1MEG 10MEG PHASE It is important to select the external compensation zero -20 -90 to be between  kHz and 5 kHz for optimum bandwidth Ceramic Capacitor operation with very low ESR for the and phase margin. In this example we have selected output capacitor . We get a -180 -40 three pole 1 zero system as zero at approximately 3 kHz. shown above and is unstable without external compensation -60 -270 The compensation values are calculated by the following empirical equation: ½ • � • R3 • C3 = 3kHz SC339 Frequency Response with We chose a low R3 compensation value to roll off gain. Ceramic Output Capacitors and no Compensation R3 = 100 Ω.  2006 Semtech Corp. www.semtech.com 0 SC339 POWER MANAGEMENT Applications Information (Cont.) Now, Layout Guidelines C3 = ½ • � • R3 • 3kHz = 530nF The advantages of using the SC339 to drive external We choose C3 = 70nF as the standard value. MOSFETs are: Soft-Start Behavior a) that the bandgap reference and control circuitry are in a die that does not contain high power dissipating devices At start-up, V first ramps linearly from ground at the rate of OUT ~0.5V/ms (+/- 25%) for about 800us. The linear ramping is and, followed by a phase of smooth settling for about 700us at the end of which the output has fully settled (to better than %). b) that the device itself does not need to be located right next to the power devices. Thus very accurate output The total start-up time of about .5ms is kept within ms voltages can be obtained since changes due to heating - 2ms window, and this is regardless of the loading and effects will be minimal. of the external components connected to the device. The 0.µF bypass capacitor should be located close to the supply (IN) and GND pins, and connected directly to the ground plane. The feedback resistors should be located at the device, with the sense line from the output routed from the load (or top end of the droop resistor if passive droop is being used) directly to the feedback chain. If passive droop is being used, the droop resistor should be located next to the load to avoid adding additional unplanned droop. Sense and drive lines should be routed away from noisy traces or components. For very low input to output voltage differentials, the input to output/load path should be as wide and short as possible. Where greater headroom is available, wide SC339 Start-Up Response traces may suffice. Power dissipation within the device is practically negligible, thus requiring no special consideration dur- ing layout. The MOSFET pass devices should be laid out according to the manufacturer’s guidelines for the power being dissipated within them.  2006 Semtech Corp. www.semtech.com  SC339 PRELIMINARY POWER MANAGEMENT Performance Characteristics Supply Current vs. Supply Voltage Adjust Voltage vs. Output Current V = 4.5V to 5.5V, I = 2.5A, V = 1.5V, V = 5V CC OUT IN EN I = 0A to 3A, V = 1.5V, V = 5.0V, V = 5V OUT IN CC EN 160.0E-6 0.5060 155.0E-6 0.5040 150.0E-6 0.5020 145.0E-6 0.5000 140.0E-6 135.0E-6 0.4980 130.0E-6 0.4960 125.0E-6 0.4940 4.500 4.600 4.700 4.800 4.900 5.000 5.100 5.200 5.300 5.400 5.500 0.000 0.500 1.000 1.500 2.000 2.500 3.000 V (V) CC IOUT (A) Supply Current Adjust Voltage +1% -1% Figure 1: Supply Current v/s Supply Voltage Figure 2: Adjust Voltage v/s Output Current (1% accurate) Figure 3: Soft Start waveform shows the PWRGD delay Figure 4: Input UVLO Test (Rising) Figure 5: Input UVLO Test (Falling) Figure 6: Enable threshold detect (Rising)  2006 Semtech Corp. www.semtech.com 2 I (A) CC VADJ (V) SC339 POWER MANAGEMENT Performance Characteristics Figure 7: Enable threshold detect (Falling) Figure 8: Transient load rising edge Figure 9: Transient load falling edge  2006 Semtech Corp. www.semtech.com 3 SC339 PRELIMINARY POWER MANAGEMENT Outline Drawing - SOT-23 6 DIMENSIONS INCHES MILLIMETERS A DIM MIN NOM MAX MIN NOM MAX - - A .057 0.90 1.45 .035 e1 D A1 .000 - .006 0.00 - 0.15 A2 .035 .045 .051 .90 1.15 1.30 - - N b .010 .020 0.25 0.50 2X E/2 c - - .003 .009 0.08 0.22 EI E D .110 .114 .118 2.80 2.90 3.00 E1 .060 .063 .069 1.50 1.60 1.75 1 2 E .110 BSC 2.80 BSC ccc C e .037 BSC 0.95 BSC e1 .075 BSC 1.90 BSC 2X N/2 TIPS L .012 .018 .024 0.30 0.45 0.60 e (.024) (0.60) L1 B N 6 6 01 - - 0° 10° 0° 10° aaa .004 0.10 bbb .008 0.20 D ccc .008 0.20 aaa C A2 A SEATING H H PLANE A1 C c bxN GAGE PLANE bbb C A-B D 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS - A - AND - B - TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.  2006 Semtech Corp. www.semtech.com  SC339 POWER MANAGEMENT Land Pattern - SOT-23 6 X D DIIM ME EN NSI SION ONS S D DIIM M IIN NC CH HES ES M MIIL LL LIIM ME ET TER ERS S (.098) (2.50) C C G G .055 1.40 (C) G Z P P .037 0.95 X X .024 0.60 Y Y Y .043 1.10 Z Z 3.60 .141 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com  2006 Semtech Corp. www.semtech.com 5