SEMTECH SC284

SC284 Dual Channel 2.5MHz, 1.8A Synchronous Step-Down Regulator POWER MANAGEMENT Features Description  V Range — 2.9 – 5.5V The SC284 is a dual channel .8A synchronous step- IN down regulator designed to operate with an input  V Selectable — 0.8 - 3.3V OUT voltage range of 2.9 to 5.5 Volts. Each channel offers  Up to .8A Output Current for Each Channel fifteen pre-determined output voltages via four control  Ultra-Small Footprint, <mm Height Solution pins programmable from 0.8 to 3.3 Volts. The control pins  Switching Frequency — 2.5MHz allow for on-the-fly voltage changes, enabling system  Efficiency Up to 94% designers to implement dynamic power savings. The  Excellent Light Load Efficiency SC284 is also capable of adjusting the output voltage via  Low Output Noise Across Load Range an external resistor divider.  Excellent Transient Response The device operates with a fixed 2.5MHz oscillator  Start Up into Pre-Bias Output frequency, allowing the use of small surface mount  00% Duty-Cycle Low Dropout Operation external components.  Shutdown Current — <µA  Internal Soft Start Connecting CTL0 — CTL3 to logic low forces the device  Input Under-Voltage Lockout into shutdown mode reducing the supply current to less  Output Over-Voltage, Current Limit Protection than µA. Connecting any of the control pins to logic high enables the converter and sets the output voltage  Over-Temperature Protection according to Table . Other features include under-  Adjustable Output Voltage voltage lockout, soft-start to limit inrush current, and  Package — 3 x 3 x 0.6(mm) UT20 over-temperature protection.  Temperature Range — -40 to +85°C  Lead-free, halogen-free, and RoHS/WEEE compliant The SC284 is available in a 3 x 3 x 0.6 (mm) MLPQ-UT20 package and has a rated temperature range of -40 to Applications +85°C.  Desktop Computing  Set-Top Box  LCD TV  Network Cards  Printer Typical Application Circuit L 2.2µH A V PVINA INA V LXA OUTA R 1Ω AVINA C OUTA C INA VOUTA 22µF 10µF AVINA L 2.2µH B C 10nF AVINA V LXB OUTB AGNDA C OUTB VOUTB 22µF SC284 V PVINB INB RAVINB 1Ω PGNDA C INB 10µF AVINB C 10nF AVINB PGNDB AGNDB CTL0A CTL0A CTL0B CTL0B CTL1A CTL1B CTL1A CTL1B CTL2A CTL2B CTL2A CTL2B CTL3A CTL3B CTL3A CTL3B Revision 2.0  SC284 Pin Configuration Ordering Information Device Package ()(2) SC284ULTRT 3 x 3 x 0.6(mm) MLPQ-UT20 (3) SC284EVB Evaluation Board Notes: () Available in tape and reel only. A reel contains 3,000 devices. 20 19 18 17 16 (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. PVINA 1 15 CTL1B (3) Please specify the default VOUTA & VOUTB when ordering. TOP VIEW AGNDA 14 2 CTL0B AVINA 3 13 AVINB CTL0A 12 AGNDB 4 T PVINB CTL1A 5 11 6 7 8 9 10 Table 1 – Output Voltage Settings CTL3_ CTL2_ CTL1_ CTL0_ Output Voltage 0 0 0 0 Shutdown 3 x 3 x 0.6(mm) MLPQ-UT20 0 0 0  0.80 θ 40°C/W JA 0 0  0 .00 0 0   .025 Marking Information 0  0 0 .05 0  0  .20 0   0 .25 0    .30  0 0 0 .50  0 0  .80 284  0  0 2.20 yyww  0   2.50 xxxx   0 0 2.60   0  2.80    0 3.00     3.30 yyww = Datecode xxxx = Semtech Lot number 2 CTL2A LXA CTL3A PGNDA VOUTB VOUTA PGNDB CTL3B LXB CTL2B SC284 Absolute Maximum Ratings Recommended Operating Conditions VINA and VINB Supply (V) . . . . . . . . . . . . . . . . . . -0.3 to +6.0 VINA and VINB Supply (V) . . . . . . . . . . . . . . . . . . . . 2.9 to 5.5 LXA, LXB (V) . . . . . . . . . . . . . - to VIN+, -3 (20ns Max), 6 Max Maximum Output current each channel (A) . . . . . . . . . . .8 VOUTA, VOUTB (V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN+0.3 Temperature Range (°C) . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85 CTLxA/B pins (V) . . . . . . . . . . . . . . . . . . . . -0.3 to (V + 0.3) OUT Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . . . . . 260 Thermal Information (2) ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . 3KV () Thermal Resistance, Junction to Ambient (°C/W) . . . . . . . . 40 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . . +50 Storage Temperature Range (°C) . . . . . . . . . . . . . . . . . -65 to +50 Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. Notes: () Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. (2) Tested according to JEDEC standard JESD22-A4-B. Electrical Characteristics Unless specified: VINA= VINB= 5.0V, VOUTA= VOUTB=.50V, C =C =0µF, C =C = 22µF, L= 2.2µH, -40°C≤ T ≤ +25 °C. Unless otherwise noted INA INB OA OB J typical values are T = +25 °C. A Parameter Symbol Conditions Min Typ Max Units Rising VINA, VINB 2.65 2.75 2.85 V Under-Voltage Lockout UVLO Hysteresis 240 300 mV () Output Voltage Tolerance ΔV Channel A & B; VIN= 2.9 – 5.5V; I =0A -2.0 +2.0 % OUT OUT Current Limit I Channel A & B; Peak LX current 2.25 3.0 3.75 A LIMIT Supply Current I Channel A & B; No load, Per channel 0 mA Q Shutdown Current I CTL = GND, Per channel  0 µA SHDN 0-3 (2) High Side Switch Resistance R Channel A & B; I = 00mA, T = 25 °C 95 DSON_P LX J mΩ (2) Low Side Switch Resistance R Channel A & B; I = -00mA, T = 25 °C 65 DSON_N LX J Channel A & B; VIN= 5.5V; LX= 0V; CTL = GND  0 0-3 (2) L Leakage Current I µA X LK(LX) Channel A & B; VIN= 5.5V; LX= 5.0V; CTL = GND -0 - 0-3 Load Regulation ΔV Channel A & B; VIN= 5.0V; I =mA – .8A ±0.5 % LOAD-REG OUT Oscillator Frequency f Channel A & B 2.0 2.5 3.0 MHz OSC Soft-Start Time t Channel A & B; I = .8A 850 µs SS OUT 3 SC284 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Average LX Current, VOUT=.5V 240 mA Foldback Holding Current I CL_HOLD Average LX Current, VOUT=3.3V 30 mA (2) CTLx Input Current I Channel A & B; CTL =VIN or GND -2.0 2.0 µA CTL_ 0-3 CTLx Input High Threshold V Channel A & B .2 V CTLx_HI CTLx Input Low Threshold V Channel A & B 0.4 V CTLx_LO V Over Voltage Protection V Channel A & B 5 % OUT OVP (3) Thermal Shutdown Temperature T Channel A & B 60 °C SD (3) Thermal Shutdown Hysteresis T Channel A & B 0 °C SD_HYS Notes: () The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature and the line regulation. (2) The negative current means the current flows into the pin and the positive current means the current flows out from the pin. (3) The thermal shutdown for both Channel A and B is independent from each other. 4 SC284 Typical Characteristics Circuit Conditions: C = 0uF/6.3V; C = 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). IN OUT Efficiency vE s. L fficoad C iency urrent Total Loss (Per Channel) vs. Load Current Total Loss 100% 1000 V =5.0V;V =3.3V IN OUT T =25°C A 95% V =5.0V;V =3.3V IN OUT 800 90% 85% 600 V =3.3V;V =1.5V IN OUT 80% V =3.3V;V =1.5V 400 IN OUT 75% 70% V =5.0V;V =1.5V 200 IN OUT 65% T =25°C A V =5.0V;V =1.5V IN OUT 60% 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.3 0.6 0.9 1.2 1.5 1.8 Output Current (A) Output Current (A) Dropout Voltage in 100% Duty Cycle Operation Load Regulation Load Regulation Dropout Voltage of 100% Duty Cycle Operation 1.0% 500 T = 25°C T =25°C A A 450 0.8% 0.6% 400 L= 1071AS-2R2M V =3.3V;V =1.5V IN OUT 0.4% 350 (DCR= 60m_max) 0.2% 300 V =5.0V;V =1.5V IN OUT 0.0% 250 -0.2% 200 -0.4% 150 -0.6% 100 L= 1127AS-2R2M V =5.0V;V =3.3V (DCR=48m_max) -0.8% IN OUT 50 -1.0% 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.3 0.6 0.9 1.2 1.5 1.8 Output Current (A) Output Current (A) UVLO Hysteresis Variation UVLO Rising Threshold Variation UVLO Hysteresis Variation UVLO Rising Threshold Variation 5% 1.0% 4% 0.8% 3% 0.6% 2% 0.4% 1% 0.2% 0% 0.0% -1% -0.2% -2% -0.4% -3% -0.6% -0.8% -4% I = 0A I = 0A OUT OUT -5% -1.0% -40 -15 10 35 60 85 -40 -15 10 35 60 85 Ambient Temperature (°C) Ambient Temperature (°C) 5 Variation Efficiency (%) Load Regulation Variation Loss (mW) Dropout Voltage (mV) SC284 Typical Characteristics (continued) Circuit Conditions: C = 0uF/6.3V; C = 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). IN OUT RDSON (P & N) Variation Over Temperature R R V Daria SON tion v (P & N) V sa . I rinput ation ov V eoltage r Line R Variation vs. Temperature DS(ON) DS(ON) 20% 30% V = 5.0V IN 15% 25% I = ±100mA LX P-Channel 10% 20% 5% 15% N-Channel 0% 10% -5% 5% -10% 0% I = ±100mA LX N-Channel P-Channel -15% -5% T = 25°C A -20% -10% -40 -15 10 35 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Input Voltage (V) Switching Frequency Variation vs. Temperature Switching F Switcr hequenc ing Freque y nc V yaria Varia tion v tion ove sr. I Lnput ine Voltage Switching Frequency Variation 5% 1.0% 4% 0.8% V = 3.3V OUT 3% 0.6% 2% 0.4% 1% 0.2% 0% 0.0% -1% -0.2% -2% V = 1.5V -0.4% OUT -3% -0.6% I = 0A OUT V = 5.0V IN T = 25°C -4% A -0.8% I = 0A OUT -5% -1.0% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 Input Voltage (V) Ambient Temperature (°C) Line Regulation Line Regulation vs. Temperature Line Regulation over Temperature Line Regulation ove Line 1.0% 1.0% 0.8% 0.8% 0.6% 0.6% 0.4% V = 1.5V 0.4% OUT 0.2% 0.2% 0.0% 0.0% -0.2% -0.2% -0.4% -0.4% V = 3.3V OUT -0.6% -0.6% V = 1.5V I = 0A OUT OUT -0.8% -0.8% I = 0A T = 25°C OUT A -1.0% -1.0% -40 -15 10 35 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Input Voltage (V) 6 Regulation Variation Variation Regulation Variation Variation SC284 Typical Waveforms Circuit Conditions: C = 0uF/6.3V; C = 22uF/6.3V, L= 2.2uH (TOKO: 27AS-2R2M). IN OUT Output Voltage Ripple (V =1.5V) Output Voltage Ripple (V =1.5V) OUT OUT Output Voltage Ripple (V =1.5V) Output Voltage Ripple (V =1.5V) OUT OUT V V OUT OUT 10mV/div 10mV/div I I LX LX 1A/div 1A/div V V LX LX 2V/div 2V/div V =3.3V V =5.0V IN IN 500ns/div 500ns/div I =1.8A I =1.8A OUT OUT Output Voltage Ripple (V =3.3V) Output Voltage Ripple (V =3.3V) OUT OUT Output Voltage Ripple (V =3.3V) Output Voltage Ripple (V =3.3V) OUT OUT V OUT 10mV/div V OUT 10mV/div I LX 0.5A/div I LX 1A/div V V LX LX 2V/div 2V/div V =5.0V V =5.0V IN IN 500ns/div 500ns/div I =0A I =1.8A OUT OUT Transient Response (V =1.5V) Transient Response (V =3.3V) OUT OUT Transient Response (V =1.5V; 0A to 1A to 0A) Transient Response (V =3.3V; 0A to 1A to 0A) OUT OUT V V OUT OUT 100mV/div 100mV/div I I OUT OUT 1A/div 500mA/div V =5.0V V =5.0V IN IN 50µs/div 50µs/div I =0A to 1A I =0A to 1A OUT OUT 7 SC284 Typical Waveforms (continued) Circuit Conditions: C = 0uF/6.3V; C = 22uF/6.3V, L= 2.2uH (TOKO: 27AS-2R2M). IN OUT Start Up (V =1.5V) Start Up (V =1.5V) OUT OUT Start Up (Enable)(V =1.5V) Start Up (Enable)(V =1.5V) OUT OUT V V IN IN 2V/div 2V/div V V CTLx CTLx 2V/div 2V/div V V OUT OUT 0.5V/div 0.5V/div V =5.0V V =5.0V IN IN 50µs/div 200µs/div R =1k R =0.83 (1.8A) OUT OUT Start Up (V =1.5V), EN=VIN Start Up (V =1.5V), EN=VIN OUT OUT Start Up (Power up V =V ) (V =1.5V) Start Up (Power up V =V ) (V =1.5V) IN CTLx OUT IN CTLx OUT V V IN IN 2V/div 2V/div V V OUT OUT 0.5V/div 0.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1k R =0.83 (1.8A) OUT OUT Start Up (V =3.3V) Start Up (V =3.3V) OUT OUT Start Up (Enable)(V =3.3V) Start Up (Enable)(V =3.3V) OUT OUT V V IN IN 2V/div 2V/div V V CTLx CTLx 2V/div 2V/div V V OUT OUT 1V/div 1V/div V =5.0V V =5.0V IN IN 100µs/div 200µs/div R =1k R =1.83 (1.8A) OUT OUT 8 SC284 Typical Waveforms (continued) Circuit Conditions: C = 0uF/6.3V; C = 22uF/6.3V, L= 2.2uH (TOKO: 27AS-2R2M). IN OUT Start Up (V =3.3V), EN=VIN Start Up (V =3.3V), EN=VIN OUT OUT Start Up (Power up V =V ) (V =3.3V) Start Up (Power up V =V ) (V =3.3V) IN CTLx OUT IN CTLx OUT V V IN IN 2V/div 2V/div V V OUT OUT 1.5V/div 1.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1k R =1.83 (1.8A) OUT OUT Shutdown-Disable (1.5V) Shutdown-Disable (3.3V) Shutdown (Disable)(V =1.5V) Shutdown (Disable)(V =3.3V) OUT OUT V V IN IN 2V/div 2V/div V V CTLx CTLx 2V/div 2V/div V V OUT OUT 1V/div 1.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1.5 R =3.3 OUT OUT 9 SC284 Pin Descriptions Pin # Pin Name Pin Function  PVINA Channel A — Input supply voltage for the converter power stage and internal circuitry. 2 AGNDA Ground connection for internal circuitry — connect directly to PGNDA. 3 AVINA Power supply for internal circuitry — Must be connected to PVINA using an R-C filter of Ω and 0nF. Channel A — Control bit 0, see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This resis- 4 CTL0A tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel A — Control bit , see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This resis- 5 CTLA tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel A — Control bit 2, see Table  for decoding. This pin has a  MΩ internal pulldown resistor. This resis- 6 CTL2A tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel A — Control bit 3, see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This resis- 7 CTL3A tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 8 VOUTB Output voltage sense pin of Channel B 9 PGNDB Channel B — Ground connection for converter power stage and internal circuitry. 0 LXB Switching node of Channel B — connect an inductor between this pin and the output capacitor.  PVINB Channel B — Input supply voltage for the converter power stage and internal circuitry. 2 AGNDB Ground connection for internal circuitry — connect directly to PGNDB. 3 AVINB Power supply for internal circuitry — Must be connected to PVINB using an R-C filter of Ω and 0nF. Channel B — Control bit 0, see Table  for decoding. This pin has a  MΩ internal pulld-own resistor. This resis- 4 CTL0B tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel B — Control bit  - see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This 5 CTLB resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel B — Control bit 2, see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This resis- 6 CTL2B tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. Channel B — Control bit 3, see Table  for decoding. This pin has a  MΩ internal pull-down resistor. This resis- 7 CTL3B tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 8 VOUTA Output voltage sense pin of Channel A 9 PGNDA Channel A — Ground connection for converter power stage and internal circuitry. 20 LXA Switching node of Channel A — connect an inductor between this pin and the output capacitor. 0 SC284 Block Diagram 1 PVINA Current Amp AVINA 3 Plimit Amp Oscillator and Slope Generator Control 20 LXA Logic VOUTA 18 PWM CTL0A 4 Comp Error Amp Voltage 500mV CTL1A 5 Select Ref 19 PGNDA 6 CTL2A CTL3A 7 AGNDA 2 11 PVINB Current Amp AVINB 13 Plimit Amp Oscillator and Slope Generator Control 10 LXB Logic VOUTB 8 PWM Comp CTL0B 14 Error Amp Voltage 500mV CTL1B 15 Select Ref 9 PGNDB 16 CTL2B 17 CTL3B AGNDB 12  SC284 Applications Information in value for the current through the resistor chain to be Detailed Description at least 20µA in order to ignore the VOUT pin current. The SC284 is a two channel synchronous step-down converter. Both channels on this device are designed to V V operate in fixed-frequency PWM mode at 2.5MHz and OUT OSTD R uR FB1 FB2 V provide the same current capacity of up to .8A. The OSTD switching frequency is chosen to minimize the size of the where V is the pre-determined output voltage via the external inductor and capacitors while maintaining high OSTD CTL pins. efficiency. Both channels of SC284 are independent. C is needed to maintain good transient response FF Operation performance. The correct value of C can be found using FF During normal operation, the PMOS MOSFET is activated the following Equation. on each rising edge of the internal oscillator. The voltage feedback loop uses an internal feedback resistor divider. 2 V 0.5 V OUT OSTD The period is set by the internal oscillator. The device C [nF] 2.5u u( ) FF R [k:]uV V  V 0.5 has an internal synchronous NMOS rectifier and does FB1 OUT OSTD OSTD not require a Schottky diode on the LX pin. The device To simplify the design, it is recommended to program the operates as a buck converter in PWM mode with a fixed desired output voltage from a standard .0V as shown in frequency of 2.5MHz. Figure  with the correct C calculated from Equation 2. FF For programming the output voltage from other standard Programmable Output Voltage voltages, R , R and C need to be adjusted to meet Both channels on SC284 have fifteen pre-determined FB FB2 FF Equations  and 2. output voltage values which can be individually selected by programming the CTL input pins (see Table  — Output V INA L V OUTA Voltage Settings). Each CTL pin has an active  MΩ internal PVINA LXA RAVINA 1Ω pull-down resistor. The MΩ resistor is switched in circuit C INA SC284 CFFA COUTA 10µF AVINA R FB1A whenever the CTL input voltage is below the input C AVINA 0.1µF threshold, or when the part is in under-voltage lockout. It is AGNDA VOUTA R FB2A VINB R = (V -1) recommended to tie all high CTL pins together and use an FB1A OUTA 10kΩ PVINB x R FB2A for CTLA = 0010 external pull-up resistor to VIN if there is no enable signal, or R 1Ω X AVINB C INB (1.0V) 10µF AVINB if the enable input is an open drain/collector signal. The CTL L V CAVINB OUTB 0.1µF LXB pins may be driven by a microprocessor to allow dynamic AGNDB C C voltage adjustment for systems that reduce the supply FFB OUTB R FB1B CTL0A Enable A voltage when entering sleep states. Avoid all zeros being CTL1A present on the CTL pins when changing programmable VOUTB CTL2A R FB2B 10kΩ R = (V -1) CTL3A FB1B OUTB output voltages as this would disable the device. x R FB2B for CTLB = 0010 X PGNDA (1.0V) CTL0B Enable B SC284 is also capable of regulating a different (higher) CTL1B output voltage, which is not shown in the Table , via an CTL2B PGNDB CTL3B external resistor divider. There will be a typical 2µA cur- rent flowing into the VOUT pin. The typical schematic for an adjustable output voltage option from the standard Figure 1 — Output Voltage Programming .0V with CTLx=[000], is shown in Figure . RFBA/B and RFB2A/B are used to adjust the desired output volt- age. If the RFB2A/B current is such that the 2µA VOUT pin current can be ignored, then RFBA/B can be found by the next equation. RFB2A/B needs to be low enough 2 SC284 Applications Information (continued) Maximum Power Dissipation Each channel of SC284 has its own Θ of 40°C/W when 2 JA TA = 68°C only one channel is in operation. Since both channels are 1.8 within same package, there is about 50% heat which will be 1.6 T = 75°C A transferred to the adjacent channel. The equivalent total 1.4 T = 85°C A thermal impedance will be higher when the neighboring 1.2 channel is also in operation. To guarantee an operating 1 junction temperature of less than 25°C, Figure 2 shows 0.8 the maximum allowable power loss of each channel. The 0.6 curve is based upon the junction temperature of either 0.4 channel reaching a maximum of 25°C. Each channel of 0.2 SC284 can support up to .8A load current. Figures 3a 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 and 3b show the maximum allowable load current based Load Current Channel A (A) upon the limit of maximum loss for V =3.3V and V =5.0V, IN IN respectively. The curves are drawn for high duty-cycle (a) V = 3.3V, V =2.5V IN OUT operation. If the operating duty-cycle is lower, the loss is lower allowing higher load current. 2 TA < 76°C 1.8 T < 85°C A 2.8 1.6 2.6 1.4 2.4 2.2 1.2 T = 25°C A 2 1 1.8 1.6 0.8 1.4 0.6 1.2 1 0.4 0.8 T = 55°C T = 85°C A A 0.2 0.6 0.4 0 0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 Load Current A (A) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 Loss of Channel A (W) (b) V = 5.0V, V =3.3V IN OUT Figure 2 — Maximum allowable loss for each channel Figure 3 — Maximum allowable Load Current for each for a maximum junction temperature of 125°C channel for a maximum junction temperature of 125°C Protection Features Current Limit and Protection The SC284 provides the following protection features: The internal PMOS power device in the switching stage • Current Limit is protected by a current limit feature. If the inductor • Over-Voltage Protection current is above the PMOS current limit for 6 consecutive • Soft-Start Operation cycles, the part enters foldback current limit mode and • Thermal Shutdown the output current is limited to the current limit holding current (I ) of a few hundred milliampere. Under CL_HOLD this condition, the output voltage will be the product of I and the load resistance. The current limit CL_HOLD holding current will decrease when the output voltage increases. The load presented must fall below the current limit holding current for the part to exit foldback current 3 Loss of Channel B (W) Load Current Channel B (A) Load Current B (A) SC284 Applications Information (continued) limit mode. Figure 4 shows how the typical current limit rail, the SC284 will not discharge the output during the holding current varies with output voltage. The SC284 is soft start interval. capable of sustaining an indefinite short circuit without damage and will resume normal operation when the fault Shut Down is removed. The foldback current limit mode is disabled When all CTL pins of each channel are low, the channel will during soft-start. Current limit functionality is shown in run in shutdown mode, drawing less than μA from the Figure 5 at the end of this section. input power supply. The internal switches and bandgap Current Limit Holding Current over Vout voltage will be immediately turned off. 300 T = 25°C A Thermal Shutdown 250 V = 3.6V IN The device has a thermal shutdown feature to protect V = 5.0V IN 200 the SC284 if the junction temperature exceeds 60°C. During thermal shutdown, the on-chip power devices are 150 disabled, tri-stating the LX output. When the temperature drops by 0°C, it will initiate a soft start cycle to resume 100 normal operation. V = 3.3V IN 50 Inductor Selection 0 The SC284 converter has internal loop compensation. 1.0 1.5 2.0 2.5 3.0 3.5 Output Voltage (V) The compensation is designed to work with an output filter corner frequency of less than 40kHz for a V of 5V IN Figure 4 — Typical Current Limit Holding Current and 50KHz for a V of 3.3V over any operating condition. IN vs. Output Voltage The corner frequency of the output filter is shown in the following equation. Over-Voltage Protection In the event of a 5% over-voltage on the output, the 1 PWM drive is disabled leaving the LX pin floating. f C 2S LuC OUT Soft-Start The soft-start mode is activated after VIN reaches its UVLO and one or more CTL pins are set high to enable the part. Values outside this range may lead to instability, A thermal shutdown event will also activate the soft start malfunction, or out-of-specification performance. sequence. Soft-start mode controls the maximum current during startup thus limiting inrush current. The PMOS In general, the inductance is chosen by making the current limit is stepped through four soft start levels of inductor ripple current to be less than 30% of maximum approximately 20%, 25%, 40%, & 00%. Each step is main- load current. When choosing an inductor, it is important tained for 200μs following an internal reference start up to consider the change in inductance with DC bias duration of 50μs giving a total nominal startup period of current. The inductor saturation current is specified as 850μs. During startup, the chip operates by controlling the current at which the inductance drops a specific the inductor current swings between 0A and current limit. percentage from the nominal value. This is approximately If at any time V reaches 86% of the target or at the end 30%. Except for short-circuit or other fault conditions, OUT of the soft-start period, the SC284 will switch to PWM the peak current must always be less than the saturation mode operation. Figure 6 at the end of this section shows current specified by the manufacturer. The peak current is the typical diagram of soft start operation. the maximum load current plus one half of the inductor ripple current at the maximum input voltage. Load and/or The SC284 is capable of starting up into a pre-biased line transients can cause the peak current to exceed this output. When the output is precharged by another supply level for short durations. Maintaining the peak current 4 Current Limit Holding Current (mA) SC284 Applications Information (continued) below the inductor saturation specification keeps the C Selection OUT inductor ripple current and the output voltage ripple at The internal voltage loop compensation in the SC284 acceptable levels. Manufacturers often provide graphs of limits the minimum output capacitor value to 22µF if actual inductance and saturation characteristics versus using a 2.2µH inductor or 44µF if using a µH inductor. applied inductor current. The saturation characteristics of This is due to its influence on the the loop crossover the inductor can vary significantly with core temperature. frequency, phase margin, and gain margin. Increasing Core and ambient temperatures should be considered the output capacitor above this minimum value will when examining the core saturation characteristics. reduce the crossover frequency and provide greater phase margin. The total output capacitance should not When the inductance has been determined, the DC exceed 50µF to avoid any start-up problems. For most resistance (DCR) must be examined. The efficiency that typical applications it is recommended to use an output can be achieved is dependent on the DCR of the inductor. capacitance of 22µF to 44µF. When choosing the output The lower values give higher efficiency. The RMS DC capacitor’s capacitance, verify the voltage derating effect current rating of the inductor is associated with losses in from the capacitor vendor’s data sheet. the copper windings and the resulting temperature rise of the inductor. This is usually specified as the current which Capacitors with X7R or X5R ceramic dielectric are produces a 40˚C temperature rise. Most copper windings recommended for their low ESR and superior temperature are rated to accommodate this temperature rise above and voltage characteristics. Y5V capacitors should not maximum ambient. be used as their temperature coefficients make them unsuitable for this application. Magnetic fields associated with the output inductor can interfere with nearby circuitry. This can be minimized by The output voltage droop due to a load transient is the use of low noise shielded inductors which use the determined by the capacitance of the ceramic output minimum gap possible to limit the distance that magnetic capacitor. The ceramic capacitor supplies the load current fields can radiate from the inductor. However shielded initially until the loop responds. Within a few switching inductors typically have a higher DCR and are thus less cycles the loop will respond and the inductor current will efficient than a similarly sized non-shielded inductor. increase to match the required load. The output voltage Final inductor selection depends on various design droop during the period prior to the loop responding considerations such as efficiency, EMI, size, and cost. can be related to the choice of output capacitor by the Table 2 lists the manufacturers of recommended inductor relationship from the following equation. options. The saturation characteristics and DC current u', /2$' & 287 ratings are also shown. 9 uI '5223 26& L at Dimen- DCR Rated The output capacitor RMS ripple current may be calculated Manufacturer L Rated sions Max Current (μH) Current LxWxH Part Number from the following equation. (Ω) (A) (μH) (mm) TOKO 9 u9 9  2.20±20% 0.060 .80 .54 2.8x3.0x.5  § · 287 ,10$; 287 1071AS-2R2M ¨ ¸ , &287506 ¨ ¸ /uI u9   © 26& ,1 ¹ TOKO .00±30% 0.040 2.70 0.70 2.8x3.0x.5 1071AS-1R0N TOKO 2.20±20% 0.048 2.50 .54 3.5x3.7x.8 1127AS-2R2M Panasonic .00±23% 0.062 2.20 0.70 3.2x3.2x.5 ELLVGG1R0N Table 2 – Recommended Inductors 5 SC284 Applications Information (continued) Table 3 lists the manufacturers of recommended output The input voltage ripple and RMS current ripple are at capacitor options. a maximum when the input voltage is twice the output voltage or 50% duty cycle. Value Rated Dimensions Manufacturer The input capacitor provides a low impedance loop for Value at Type Voltage LxWxH (μF) 3.3V Part Nunber the edges of pulsed current drawn by the PMOS switch. (VDC) (mm) (μF) Low ESR/ESL X5R ceramic capacitors are recommended Murata 2.0x.25x.25 for this function. To minimise stray inductance ,the 0±0% X5R 6.3 4.74 GRM21BR60J106K (EIA:0805) capacitor should be placed as closely as possible to the Murata 2.0x.25x0.85 0±0% X5R 6.3 4.05 VIN and GND pins of the SC284. GRM219R60J106K (EIA:0805) Murata 2.0x.25x.25 22±20% X5R 6.3 6.57 GRM21BR60J226M (EIA:0805) Murata 3.2x.6x.6 47±20% X5R 6.3 20.3 GRM31CR60J476M (EIA:206) Table 3 – Recommended Capacitors C Selection IN The SC284 source input current is a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 0μF should be used. It is important to consider the DC voltage coefficient charac- teristics when determining the actual required value. It should be noted a 0µF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5µF. To estimate the required input capacitor, determine the acceptable input ripple voltage and calculate the minimum value required for C as shown by the following IN equation. § · 9 9 287 287 ¨ ¸ ¨ ¸ 9 9 ,1 © ,1 ¹ & ,1 § · '9 ¨ ¸ (65 uI 26& ¨ ¸ , 287 © ¹ The input capacitor RMS ripple current varies with the input and output voltage. The maximum input capacitor RMS current is found from the next equation . § · 9 9 287 287 , ¨ ¸ &,1506 ¨ ¸ 9 9 ,1 © ,1 ¹ 6 SC284 Applications Information (continued) 6WDJHV 2SHUDWLRQGHVFULSWLRQ 6RIWVWDUWHQGV K J  1RUPDO3:0RSHUDWLRQ 6WDJH 6WDJH 2YHUORDGSURWHFWLRQLVHQDEOHGDQGSHDNFXUUHQWOLPLWDWOHYHO    &\FOHE\F\FOHSHDNFXUUHQWOLPLW 6WDJH 2&3SURWHFWLRQLVDFWLYDWHG IROGEDFNSHDNFXUUHQWOLPLW M   3:021ZKHQLQGXFWRUFXUUHQWRI$ 3:02))ZKHQLQGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLWRIIROGEDFNPRGH &RQGLWLRQV 2SHUDWLRQGHVFULSWLRQ - ,QGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLW . 3HDNFXUUHQWOLPLWIRUFRQVHFXWLYHF\FOHV L / 9RXW•WDUJHW 0 ,QGXFWRUFXUUHQWGRHVQ WKLWSHDNFXUUHQWOLPLW Figure 5 — Current Limit Protection 6WDJHV 2SHUDWLRQGHVFULSWLRQ  &KLSLV2)) 3HDNFXUUHQWOLPLWDWOHYHO 3:021ZKHQLQGXFWRUFXUUHQWRI$  3:02))ZKHQLQGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLW % 6WDJHGXUDWLRQRI—V 6WDJH 6WDJH 3HDNFXUUHQWOLPLWDWOHYHO $ &   3:021ZKHQLQGXFWRUFXUUHQWRI$  3:02))ZKHQLQGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLW 6WDJH 6WDJHGXUDWLRQRI—V  3HDNFXUUHQWOLPLWDWOHYHO * 3:021ZKHQLQGXFWRUFXUUHQWRIP$  3:02))ZKHQLQGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLW ) 6WDJH + 6WDJHGXUDWLRQRI—V  3HDNFXUUHQWOLPLWDWOHYHO 3:021ZKHQLQGXFWRUFXUUHQWRIP$  3:02))ZKHQLQGXFWRUFXUUHQWKLWVSHDNFXUUHQWOLPLW ' 6WDJHGXUDWLRQRI—V 3HDNFXUUHQWOLPLWDWOHYHO 6WDJH  6ZLWFKWRFORVHGORRS3:0RSHUDWLRQ  6RIW6WDUWHQGV 6WDJH  1RUPDO3:0RSHUDWLRQ  2YHUORDGSURWHFWLRQLVHQDEOHG ( , &RQGLWLRQV 2SHUDWLRQGHVFULSWLRQ 9,1!89/27KUHVKROG $1' $ 2QHRUPRUH&7/SLQLVKLJK 6WDJH $1'  ,QWHUQDOUHIHUHQFHLVUHDG\ % (QGRIVWDJH$1'9RXWRIWDUJHW & (QGRIVWDJH$1'9RXWRIWDUJHW ' (QGRIVWDJH$1'9RXWRIWDUJHW ( (QGRIVWDJH$1'9RXWRIWDUJHW ) 9RXW!RIWDUJHW * 9RXW!RIWDUJHW + 9RXW!RIWDUJHW , (QGRIVRIWVWDUWWLPHRI—V Figure 6 — Soft Start Operation 7 SC284 Applications Information (continued) PCB Layout Considerations The layout diagram in Figure 7 shows a recommended top-layer PCB for the SC284 and supporting components. Figure 8 shows the bottom layer for this PCB. Fundamental layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. The following guidelines are recommended when developing a PCB layout: . The input capacitor, C , should be placed as close to the IN VIN and GND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to connect as closely to the IC as possible. This will minimize EMI and input voltage ripple by localizing Figure 7 — Recommended PCB Layout (Top Layer) the high frequency current pulses. 2. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. C and L should be connected as OUT close as possible between the LX and GND pins, with a direct return to the GND pin from C . OUT 3. Route the output voltage feedback/sense path away from the inductor and LX node to minimize noise and magnetic interference. 4. Use a ground plane referenced to the SC284 GND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 5. If possible, minimize the resistance from the output and GND pin to the load. This will reduce the voltage drop on the ground plane and improve the load regulation. It will also improve the overall efficiency by reducing the copper losses on the output and ground planes. Figure 8 — Bottom Layer Detail 8 SC284 Outline Drawing – 3x3 MLPQ-UT20 Land Pattern – 3x3 MLPQ-UT20 9 SC284 © Semtech 20 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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