SEMTECH SC2688

SC2688 Programmable Synchronous DC/DC Converter, Dual LDO Controller POWER MANAGEMENT Features Description The SC2688 combines a synchronous voltage mode ‹ ·Synchronous design, enables no heatsink solution controller with two low-dropout linear regulators ‹ 95% efficiency (switching section) providing most of the circuitry necessary to implement three ® ‹ Designed for embedded Pentium III requirements DC/DC converters for powering advanced microprocessors ‹ 1.5V, 2.5V short circuit protected linear controllers ® such as Pentium III. The SC2688 switching section features latched drive out- Applications put for enhanced noise immunity, pulse by pulse current ® ‹ Embedded Pentium III microprocessor supplies. limiting and logic compatible shutdown. The SC2688 switching section operates at a fixed frequency of 140kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The SC2688 linear sections are low dropout regulators with short circuit protection, supplying 1.5V for GTL bus and 2.5V for non-GTL I/O. Typical Application Circuit 12V + 0.1uF 5V 47uF + 1500uF 10 11 7 BST CS+ x4 0.1uF 4 6 0.1uF VCC CS- 2R2 5 8 LDOEN DH 0.1uF 1.00k 2.32k 2R2 EN 12 10 EN DL VCC_CORE 16 13 1.9uH AGND FB 5mOhm 14 9 LDOV PGND 15 1 GATE2 GATE1 + 0.1uF 3 2 LDOS2 LDOS1 SC2688S 3.3V 1500uF x6 1k + 1.5V 2.5V 330uF + + 330uF 330uF 1 Revision: March 25, 2004 www.semtech.com SC2688 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit VV CC to AGND -V 0.3 to +7 IN PGND to AGND ±V 1 BST to PGND -V 0.3 to +15 DH to PGND, DL to PGND (Note2) -V 1 to +15 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD Thermal Resistance Junction to Ambient θ 8W 0 °C/ JA Thermal Impedance Junction to Case 2W 5 °C/ θ JC Electrical Characteristics Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; T = 0 to 70°C O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Switching Section OI utput Voltage=8 2A in Application Circuit 10 .2313 .25 1V .26 O SC upply VoltageV5 C 47 . V SV upply CurrentV8 CC = 5.0 1A5 m LI oad Regulation=1 0.8A to 15A % O Line Regulation ±% 0.5 Current Limit Voltage 60 0 758V m Oscillator Frequency 10 20 10 4 1z 6 kH Oscillator Max Duty Cycle 95 09% PV eak DH Sink/Source Current BSTH - DH = 4.5V, DH- PGNDH = 3.3 1 A DH- PGNDH = 1.5V 100 mA PV eak DL Sink/Source Current BSTL - DL = 4.5V, DL - PGNDL= 3.3 1 A DL- PGNDH = 1.5V 100 mA Gain (A)V VOSENSE to 3B 5 d OL O FV B Input current=1 1.25V 2 uA FB Dead Time 40 01s 0 n www.semtech.com  2004 Semtech Corp. 2 SC2688 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; T = 0 to 70°C O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Linear Sections QV uiescent Current L5 DOV = 12 mA Output Voltage LDO1 25 .49326 .52 2V .55 Output Voltage LDO2 15 .49614 .51 1V .53 RA eference Voltage I6 ref < 100u 15 .2414 .26 1V .28 Gain (A))L0 DOS (1,2) to GATE (1,2 9B d OL LI oad Regulation =3 0 to 8A 0% . O Line Regulation 0% .3 OV utput Impedance V1 GATE = 6.5 1k .5 Ω LDOV Undervoltage Lockout 60 .5 80 . 1V LDOEN Threshold 19 .3 1V . LV DOEN Sink Current LDOEN = 3.3 0.01 1.0 µA LDOEN = 0V -200 -300 µA Ot vercurrent Trip Voltage %0 of Vo set poin 20406% Power-up Output Short Circuit Immunity 15 6s 0 m Output Short Circuit Glitch Immunity 04 .5 3s 0 m G; ate Pulldown Impedance GATE (1,2) -AGND 80 0 30 0 7k 5 Ω VCC+BST=0V VOSENSE Impedance 1k 0 Ω Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recomendations.  2004 Semtech Corp. 3 www.semtech.com SC2688 POWER MANAGEMENT Pin Configuration Ordering Information (1) DevicePr ackage Linea Temp TOP VIEW Voltage Range (T ) J S6 C2688STRSV O-11C .5V/2.5 0° to 125° GATE1 1 16 AGND LDOS1 2 15 GATE2 Note: LDOS2 3 14 LDOV (1) Only available in tape and reel packaging. A reel VCC 4 13 FB contains 2500 devices. LDOEN 5 12 EN CS- 6 11 BST CS+ 7 10 DL DH 8 9 PGND (16 Pin SOIC) Pin Descriptions Pe in #Pn in Nam Pin Functio 11G1 ATE Gate Drive Output LDO 21L1 DOS Sense Input for LDO 32L2 DOS Sense Input for LDO 4CVe C Input Voltag 5NL. DOE LDO Supply Monitor 6-C) S Current Sense Input (negative 7+C) S Current Sense Input (positive 8HDt High Side Driver Outpu 9DPd GN Power Groun 1L 0Dt Low Side Driver Outpu 1T 1Bs S Supply for Driver (1) 1N 2 E Logic low shuts down the converter, High or open for normal operation 1B 3Ft Switcher section feedback inpu 1V 4Ln DO +12V for LDO sectio 12 5G2 ATE Gate Drive Output LDO 1D 6Ad GN Small Signal Analog and Digital Groun Note: (1) All logic level inputs and outputs are open collector TTL compatible. www.semtech.com  2004 Semtech Corp. 4 SC2688 POWER MANAGEMENT Block Diagram VCC CS- CS+ EN CURRENT LIMIT BST + 70mV REF - LEVEL SHIFT AND HIGH SIDE DRIVE DH + - - FB + ERROR AMP OSCILLATOR AGND R SHOOT-THRU CONTROL Q S 1.265V REF LDOEN LDOS1 2.5V FET 1.5V FET SYNCHRONOUS DL CONTROLLER CONTROLLER MOSFET DRIVE GATE1 PGND LDOV GATE2 LDOS2  2004 Semtech Corp. 5 www.semtech.com SC2688 POWER MANAGEMENT Layout Guidelines Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and successful implementation of the SC2688 PWM control- as short as possible to minimize loop inductance. Mini- ler. High currents switching at 140kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds entials must be understood and minimized. for the rest of the system and c) minimize source ringing, 1). The high power parts of the circuit should be laid out resulting in more reliable gate switching signals. first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re- to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec- Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out- particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace tom FET ground. or copper area, there are no fast voltage or current transi- 2). The loop formed by the Input Capacitor(s) (Cin), the Top tions in this connection and length is not so important, FET (Q1) and the Bottom FET (Q2) must be kept as small however adding unnecessary impedance will reduce effi- as possible. This loop contains all the high current, fast ciency. 5V 12V IN 10 1 16 2.32k GATE1 AGND 2 15 Q1 LDOS1 GATE2 Cin + 3 14 1.00k LDOS2 LDOV 5mOhm L 4 13 VCC FB Vout 5 12 0.1uF Q2 LDOEN EN 6 11 CS- BST Cout 7 10 CS+ DL 0.1uF 8 9 DH PGND SC2688 Heavy lines indicate Vo Lin1 3.3V high current paths. Q3 Cout Lin1 Cin Lin Layout Diagram SC2688 Vo Lin2 Q4 Cout Lin2 www.semtech.com  2004 Semtech Corp. 6 SC2688 POWER MANAGEMENT Layout Guidelines (Cont.) 4) The Output Capacitor(s) (Cout) should be located as 6) Vcc for the SC2688 should be supplied from the 5V close to the load as possible, fast transient load currents supply through a 10Ω resistor, the Vcc pin should be are supplied by Cout only, and connections between Cout decoupled directly to AGND by a 0.1µF ceramic capacitor, and the load must be short, wide copper areas to mini- trace lengths should be as short as possible. mize inductance and resistance. 7) The Current Sense resistor and the divider across it 5) The SC2688 is best placed over a quiet ground plane should form as small a loop as possible, the traces run- area, avoid pulse currents in the Cin, Q1, Q2 loop flowing ning back to CS+ and CS- on the SC2688 should run par- in this area. PGND should be returned to the ground plane allel and close to each other. The 0.1µF capacitor should close to the package. The AGND pin should be connected be mounted as close to the CS+ and CS- pins as possible. to the ground side of (one of) the output capacitor(s). If 8) Ideally, the grounds for the two LDO sections should be this is not possible, the AGND pin may be connected to returned to the ground side of (one of) the output the ground path between the Output Capacitor(s) and the capacitor(s). Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 5V Currents in Power Section + Vout +  2004 Semtech Corp. 7 www.semtech.com SC2688 POWER MANAGEMENT Component Selection SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most and 0% duty cycle capability, so some allowance must be critical component. Because of fast transient load current made. Choosing an inductor value of 50 to 75% of the requirements in modern microprocessor core supplies, the calculated maximum will guarantee that the inductor cur- output capacitors must supply all transient load current rent will ramp fast enough to reduce the voltage dropped requirements until the current in the output inductor ramps across the ESR at a faster rate than the capacitor sags, up to the new level. Output capacitor ESR is therefore one hence ensuring a good recovery from transient with no of the most important criteria. The maximum ESR can be additional excursions. simply calculated from: We must also be concerned with ripple current in the out- put inductor and a general rule of thumb has been to V t allow 10% of maximum output current as ripple current. R ≤ ESR I t Note that most of the output voltage ripple is produced by Where the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: V = Maximum transient voltage excursion t I = Transient current step V t IN I = L RIPPLE ⋅ ⋅ 4 L f OSC For example, to meet a 100mV transient limit with a 10A Ripple current allowance will define the minimum permit- load step, the output capacitor ESR must be less than ted inductor value. 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. POWER FETS - The FETs are chosen based on several criteria, with probably the most important being power Each Cap. Total dissipation and power handling capability. Qty. Technology C ESR C ESR TOP FET - The power dissipation in the top FET is a com- Rqd. (µF) (mΩ) (µF) (mΩ) bination of conduction losses, switching losses and bot- tom FET body diode recovery losses. L0 ow ESR Tantalum 30 3 6620 000 1 a) Conduction losses are simply calculated as: O0 S-CON 35 3 2393 90 8. 2 P = I ⋅R ⋅ δ COND O DS(on) L0 ow ESR Aluminum14 50 4573 500 8. where V O The choice of which to use is simply a cost/performance δ = duty cycle ≈ V IN issue, with Low ESR Aluminum being the cheapest, but taking up the most space. b) Switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: INDUCTOR - Having decided on a suitable type and value −2 of output capacitor, the maximum allowable value of in- P = I ⋅ V ⋅10 SW O IN ductor can be calculated. Too large an inductor will pro- or more generally, duce a slow current ramp rate and will cause the output I ⋅ V ⋅(t + t ) ⋅ f O IN r f OSC capacitor to supply more of the transient load current for P = SW 4 longer - leading to an output voltage sag below the ESR c) Body diode recovery losses are more difficult to esti- excursion calculated above. mate, but to a first approximation, it is reasonable to as- The maximum inductor value may be calculated from: sume that the stored charge on the bottom FET body di- R C ESR ode will be moved through the top FET as it starts to turn L ≤ ⋅ V A I t on. The resulting power dissipation in the top FET will be: where V is the lesser of V or () V − V A O IN O P = Q ⋅ V ⋅ f RR RR IN OSC The calculated maximum inductor value assumes 100% To a first order approximation, it is convenient to only con- www.semtech.com  2004 Semtech Corp. 8 SC2688 POWER MANAGEMENT Component Selection (Cont.) sider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET INPUT CAPACITORS - since the RMS ripple current in the losses would be: input capacitors may be as high as 50% of the output Using 1.5X Room temp R to allow for temperature rise. current, suitable capacitors must be chosen accordingly. DS(ON) Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy FR ET type (mΩ)P(e W) Packag DS(on) D storage within the converter circuitry, either as extra 2 I5 RL34025191D .6 Pak output capacitance or, more usually, additional input ca- 2 pacitors. Choosing low ESR input capacitors will help maxi- I5 RL220319 0. 1D .1 Pak mize ripple rating for a given size. S0 i44102628 .2 S0- GATE RESISTOR SELECTION - The gate resistors for the BOTTOM FET - Bottom FET losses are almost entirely top and bottom switching FETs limit the peak gate current due to conduction. The body diode is forced into conduc- and hence control the transition time. It is important to tion at the beginning and end of the bottom switch con- control the off time transition of the top FET, it should be duction period, so when the FET turns on and off, there fast to limit switching losses, but not so fast as to cause is very little voltage across it, resulting in low switching excessive phase node oscillation below ground as this can losses. Conduction losses for the FET can be determined lead to current injection in the IC substrate and erratic by: behaviour or latchup. The actual value should be deter- 2 mined in the application, with the final layout and FETs. P = I ⋅R ⋅(1− δ) COND O DS(on) For the example above: SHORT CIRCUIT PROTECTION - LINEARS The Short circuit feature on the linear controllers is imple- FR ET type (mΩ)P(e W) Packag DS(on) D mented by using the Rds(on) of the FETs. As output cur- 2 I5 RL34025131D .3 Pak rent increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, 2 I5 RL220313 0. 0D .9 Pak as the Rds(on) limit is reached, the FET will be unably to turn on more fully, and output voltage will start to fall. S0 i44102718 .7 S0- When the output voltage falls to approximately 40% of Each of the package types has a characteristic thermal nominal, the LDO controller is latched off, setting output impedance. For the surface mount packages on double voltage to 0. Power must be cycled to reset the latch. sided FR4, 2 oz printed circuit board material, thermal To prevent false latching due to capacitor inrush currents o 2 o impedances of 40 C/W for the D PAK and 80 C/W for the or low supply rails, the current limit latch is initially dis- SO-8 are readily achievable. The corresponding tempera- abled. It is enabled at a preset time (nominally 2ms) after ture rise is detailed below: both the LDOV and LDOEN pins rise above their lockout points. To be most effective, the linear FET Rds(on) should not be O Temperature Rise ( C) selected artificially low, the FET should be chosen so that, FT ET typeTT op FE Bottom FE at maximum required current, it is almost fully turned on. If, for example, a linear supply of 1.5V at 4A is required I6 RL3402562 7. 53. from a 3.3V ± 5% rail, max allowable Rds(on) would be. Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ I6 RL2203 42 7. 37. To allow for temperature effects 200mΩ would be a suit- S8 i4410 16 80. 141. able room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time be- It is apparent that single SO-8 Si4410 are not adequate fore shutdown. for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4.  2004 Semtech Corp. 9 www.semtech.com SC2688 POWER MANAGEMENT Theory of Operation (Linear OCP) The Linear controllers in the SC2688 have built in Gate Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on 1.4V/us and the output currrent is R limited, this is detected Vout DS(ON) by the gate voltage going very high while the output volt- 1V/ms age is below approximately 40% of it’s setpoint. To allow for capacitor charging and very short overcurrent dura- Vout/2 tions, the gate voltage is ramped very slowly upwards when- ever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reach- Time ing it’s setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold val- Startup with no short circuit ues are exceeded, ensuring that there is sufficient gate If at some later time, a short circuit is applied to the out- drive capability and sufficient LDO input voltage capabil- put, the GATEx voltage will ramp up quickly as Vout falls to ity. A block diagram of one LDO controller is shown below. try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will con- tinue ramping at the 1V/ms rate. If the short is not re- 12V 3.3V moved before the GATEx output reaches approximately LDOV LDOEN LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO + - 10pF C RAMP Short LDOV LDOV-0.7V applied - 1V/ms - gm GATEx + + Gate VREF 1.3V R2 LDOSx Vout 1.26V SWITCH CLOSED R ON LOW Vout - S1 + + Vout/2 10nA R R1 Time 14uA AGND Short circuit after startup RESET BY S + LDOV LOW Q - If the LDO tries to start into a short, the gate ramps at the R LDOV-0.7V 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low. LDOV-0.7V During a normal start-up, once LDOV and LDOEN have Gate reached their thresholds, the GATEx pin is released and C is charged by 10nA causing the GATEx voltage to RAMP ramp at 10nA/10pF = 1V/ms. Once the GATEx output has 1V/ms ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP thresh- old, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Time Vout, until Vout reaches setpoint and the loop settles into Startup into short circuit steady state regulation. www.semtech.com  2004 Semtech Corp. 10 SC2688 POWER MANAGEMENT Typical Characteristics Typical Ripple, Vo=2.0V, Io=10A Typical Efficiency (Switching section) 96% PIN Descriptions 92% 88% 84% Vo=2.8V 80% Vo=2.0V Vo=2.5V 76% 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 Io (Amps) Transient Response Vo=2.4V, Io=300mA to 15A 2.5V Linear Short circuit output response  2004 Semtech Corp. 11 www.semtech.com Efficiency (%) SC2688 POWER MANAGEMENT Outline Drawing - SO-16 Land Pattern - SO-16 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2004 Semtech Corp. 12