SEMTECH SC2659

SC2659 Programmable Synchronous DC/DC Hysteretic Controller with VRM 8.5 VID Range POWER MANAGEMENT Features Description The SC2659 is a synchronous-buck switch-mode con- ‹ Programmable hysteresis troller designed for use in single ended power supply ap- ‹ 5 bit DAC programmable output (1.050V-1.825V) plications where efficiency is the primary concern. The ‹ On-chip power good and OVP functions controller is a hysteretic type, with a user selectable hys- ‹ Designed to meet latest Intel specifications teresis. The SC2659 is ideal for implementing DC/DC ‹ Up to 95% efficiency converters needed to power advanced microprocessors ‹ VIDs pulled up to +3.3V ® ® such as Pentium llI and Athlon , in both single and mul- tiple processor configurations. Inhibit, under-voltage lock- out and soft-start functions are included for controlled Applications power-up. ‹ Server Systems and Workstations ® ‹ Pentium III Core Supplies SC2659 features include an integrated 5 bit D/A con- ® ‹ AMD Athlon Core Supplies verter, temperature compensated voltage reference, current limit comparator, over-current protection, and an ‹ Multiple Microprocessor Supplies adaptive deadtime circuit to prevent shoot-through of ‹ Voltage Regulator Modules the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-volt- age protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.050V to 1.825V in 25mV increments. The SC2659 high side driver can be configured as either a ground-referenced or as a floating bootstrap driver. The high and low side MOSFET drivers have a peak cur- rent rating of 2 amps. Typical Application Circuit +5V R1 * R10 R9 U1 10k 1k SC2659 R3 PWRGD * 1 28 IOUT PW RGD "POWER GOOD" R2 C6 1k 0.1 2 27 DROOP VID0 R4 INHIB 1k 3 26 OCP VID1 "INHIBIT" C7 R11 4 25 0.1 1k VHYST VID2 R5 * 5 24 L1 VREFB VID3 0.5uH C1 R6 0.1 + 20k 6 23 VSENSE VID25 C2 Cin 0.001 Cin 7 22 HF Vin +5V/12V Bulk AGND INHIBIT 8 21 _ SOFTST IOUTLO C8 C3 0.033 0.1 9 20 N/C LOSENSE +5V 10 19 LODRV HISENSE C4 0.01 Q1 11 18 LOHIB BOOTLO FDB6035AL R12 1.0 12 17 DRVGND HIGHDR L2 13 16 LOW DR BOOT 1.0uH C9 +12V + 1.0 14 15 Q2 DRV VIN12V FDB7030BL R14 1.6 Cout Cout Bulk HF 1.05 to 1.825V C5 C10 _ R7 R8 * 10k *) for the values see specific application circuit somewhere else in the datasheet Revision: December 10, 2003 1 www.semtech.com SC2659 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit VN IN12V VI -V 0.3 to 14 MAX BOOT to DRVGND -V 0.3 to 25 BOOT to BOOTLO -V 0.3 to 15 Digital Inputs -V 0.3 to 7.3 AGND to DRVGND ±V 0.5 LOHIB to AGND -V 0.3 to 14 LOSENSE to AGND -V 0.3 to 14 IOTLO to AGND -V 0.3 to 14 HISENSE to AGND -V 0.3 to 14 VSENSE to AGND -V 0.3 to 5 0 Continuous Power Dissipation, T = 25CP 1W .2 A D 0 Continuous Power Dissipation, T = 25CP 6W .25 C D OT perating Junction Temperature Range 0C to +125 ° J LT ead Temperature (Soldering) 10 Sec. 3C 00 ° L ST torage Temperature -C 65 to 150 ° STG DC Electrical Characteristics Unless specified: 0 < T < 125°C, VIN = 12V J Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit SV upply Voltage RangeV4 IN12 12 1. 131V SI upply Current (Quiescent)qg INH = 5V, Vin above UVLO threshold durin 1A 5 m IN start-up, f = 200 kHz, BOOTLO = 0V, sw C = C = 50pF DH DL High Side Driver Supply Iqd INH = OV or Vin below UVLO threshol 2A m BOOT Current (Quiescent) during start-up, BOOT = 13V, BOOTLO = 0V INH = 5V, VIN above UVLO threshold 5A m during start-up, f = 200kHz, BOOT = 13V, BOOTLO = 0V, sw C = 50pF DH www.semtech.com  2003 Semtech Corp. 2 SC2659 POWER MANAGEMENT DC Electrical Characteristics Unless specified: 0 < T (Cont.) < 125°C, VIN = 12V J Ps arameter Ss ymbolCn ondition Mp i Tx yMs a Unit Reference/Voltage Identification RV eference Voltage Accuracy 11.4V < VIN12V< 12.6V, over full-2 1.2 1% . REF VID range (see Output Voltage Table) VID0 - VID25mV High Threshold V 2V .25 TH(H) Voltage VID0 - VID25mV Low Threshold V 1V TH(L) Voltage Power Good UV ndervoltage Threshold 88 2 8V % TH(PWRGD) REF OV utput Saturation Voltage I=5 5mA 0V . SAT O HV ysteresis 1V 0 m HYS(PWRGD) Over Voltage Protection OV VP Trip Point 15 2 102V % OVP OUT (1) Hysteresis V 1V 0 m HYS(OVP) Soft Start CI harge Current V = 0.5V, resistance from VREFB13 0.4161A 5. µ CHG SS pin to AGND = 20kΩ, V = 1.3V REFB Note: I = (I / 5) CHG VREFB Dg ischarge Current IV disch=1 1V mA (SS) Inhibit Comparator St tart Threshold Vstar 1024 . 2V . (NH) VIN 12V UVLO St tart Threshold Vstar 95 .2515 0.21V 1.2 UVLO Hs ysteresis Vhy 11 .8 24 . 2V . UVLO Hysteretic Comparator Is nput Offset Voltage Vo Vp5 in grounded mV HYSCMP DROOP Is nput Bias Current Ibia 1A u HYSCMP HV ysteresis Accuracy 7V m HYS ACC HV ysteresis Setting 6V 0 m HYS SET  2003 Semtech Corp. 3 www.semtech.com SC2659 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Ps arameter Ss ymbol Cn ondition Mp iTx yMs a Unit Droop Compensation IV nitial Accuracy V=8 50 mV mV DROOP ACC DROOP Overcurrent Protection OV CP Trip Point 01 .0901 . 0V .1 OCP Is nput Bias Current Ibia 1A 00 n OCP High-Side VDS Sensing Gain 2V V/ IV nitial Accuracy V = 12V, V=6 11.9V mV IOUT ACC HISENSE IOUTLO V = 0.5V, V = 12V, IOUT HISENSE Ie OUT Source Isourc 5A 00 µ IOUT V = 11.5V IOUTLO Isink V =0.05V, V = 12V, IOUT IOUT HISENSE IOUT Sink Current 30 85A µ V = 12V IOUTLO V V = 11V, R = 10K Ω 053V .7 IOUT(11) HISENSE IOUT VV IOUT Voltage Swing V = 4.5V, R = 10k Ω 002V . IOUT(4.5V) HISENSE IOUT V V = 3V, R = 10k Ω 001V . IOUT(3V) HISENSE IOUT Lh OSENSE High Level Input Voltage Vi V=5 4.5V (Note 1) 2V .8 LOSENSE HISENSE Ll OSENSE Low Level Input Voltage Vi V=8 4.5V (Note 1) 1V . LOSENSE HISENSE SR ample/Hold Resistance (0 Note 1) 5560 8 Ω S/H Buffered Reference Vg REFB Load Regulation Vldre 10µA < I<2 500µA mV REFB REFB Deadtime Circuit (1) Lh OHIB High Level Voltage Vi 2V LOHIB Ll OHIB Low Level Input Voltage Vi 1V .0 LOHIB Lh OWDR High Level Input Voltage Vi 2V LOWDR Ll OWDR Low Level Input Voltage Vi 1V .0 LOWDR Drive Regulator DV RV Voltage 11.4 < VIN12V < 12.6V, I=7 50mA 9V DRV DRV Lg oad Regulation Vldre 1mA < I<0 50mA 1V 0 m DRV DRV St hort Circuit Current Ishor 1A 00 m DRV www.semtech.com  2003 Semtech Corp. 4 SC2659 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Pl arameter Ss ymbo Cn ondition Mp i Tx yMs a Unit High-Side Output Driver Pc eak Output Current Isr duty cycle < 2%, tpw < 100us, 2 HIGHDR T = 125°C A J Isink V - V = 6.5V, V = 1.5V (src), HIGHDR BOOT BOOTLO HIGHDR or V = 5V (sink) HIGHDR Equivalent Output Rsrc T = 125°C 45 HIGHDR J Resistance V - V = 6.5V, V = 6V Ω BOOT BOOTLO HIGHDR Rsink T = 125°C 5 HIGHDR J V - V = 6.5V, V = 0.5V BOOT BOOTLO HIGHDR Low-Side Output Driver Pc eak Output Current Isr duty cycle < 2%, tpw < 100us, 2 LOWDR T = 125°C A J Isink V = 6.5V, V = 1.5V (src), or LOWDR DRV LOWDR V = 5V (sink) LOWDR Equivalent Output Rsrc T = 125°C 45 LOWDR J Resistance V = 6.5V, V = 6V Ω DRV LOWDR Rsink T = 125°C 5 LOWDR J V = 6.5V, V = 0.5V DRV LOWDR AC Electrical Characteristics (Note 1) Pl arameter Ss ymbo Cn ondition Mp i Tx yMs a Unit Hysteretic Comparators Propagation Delay Time t 10mV overdrive, 10 502s 5 n HCPROP from VSENSE to HIGHDR or 1.3V ≤ Vref ≤ 1.8V LOWDR (excluding deadtime) Output Drivers Hr IGHDR rise/fall time t CI = 9nF, V = 6.5v, V = grounded, 6s 0 n HIGHDR BOOT BOOTLO tr T =125°C HIGHDR J Lr OWDR rise/falltime t CI = 9nF, V = 6.5V, 6s 0 n LOWDR DRV tf T =125°C LOWDR J Overcurrent Protection Comparator Propagation t 1s µ OVPROP Delay Time Deglitch Time (Includes t 25 µs OVDGL comparator propagation delay time)  2003 Semtech Corp. 5 www.semtech.com SC2659 POWER MANAGEMENT AC Electrical Characteristics (Cont.) (Note 1) Ps arameter Ss ymbolCn ondition Mp i Tx yMs a Unit Overvoltage Protection Ct omparator Propagation Delay Time 1s µ OVPROP Deglitch Time (Includes comparator t 13 µs OVDGL protection delay time) High-Side Vds Sensing Rt esponse Time V = 12V, V pulsed VDSRESP HISENSE IOUTLO from 12V to 11.9V, 100ns rise 2s µ and fall times V = 4.5V, V pulsed HISENSE IOUTLO from 4.5V to 4.4V, 100ns rise 3s µ and fall times V = 3V, V pulsed HISENSE IOUTLO from 3.0V to 2.9V, 100ns rise 3s µ and fall times Short Circuit Protection Rising Edge tL0 OSENSE grounded 30 0 5s 0 n VDSRED Delay Sample/Hold Switch turn-on/turn-off 3V < V < 11V HISENSE t 30 0 1s 0 n SWXDLY Delay V = V LOSENSE HISENSE Power Good Ct omparator Propagation Delay 1s µ PWRGD Softstart Ct omparator Propagation Delay o0 verdrive = 10mV 50 6 9s 0 n SLST Deadtime C = 9nF, 10% threshold on LOWDR Dt river Non-overlap Time 30 0 1s 0 n NOL LOWDR LODRV PT ropagation Delay 4s 00 n LODRVDLY Note: (1) Guaranteed, but not tested. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required. www.semtech.com  2003 Semtech Corp. 6 SC2659 POWER MANAGEMENT Test Circuit Timing Diagram Simplified Block Diagram  2003 Semtech Corp. 7 www.semtech.com SC2659 POWER MANAGEMENT Pin Configuration Ordering Information Top View (1) DevicePT ackage Temp Range ( ) J S8 C2659SWTRSC O-2 0° to 125° Sd C2659EVB Evaluation Boar Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (28-Pin SOIC) Pin Descriptions Pe in #Pn in Nam Pin Functio 1T IOU Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RD I S(ON) x LOAD. DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a 2 function of load current. The voltage is set by a resistor divider between IOUT and AGND. 3P OC Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. 4T VHYS Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. 5BV. REF Buffered Reference Voltage (from VID circuitry) 6EV. SENS Output Voltage Sense 7DA. GN Small Signal Analog and Digital Ground 8T SOFTS Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. 9CN. Not connected 1V 0 LODR Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. 1B 1 LOHI Low Side Inhibit. This pin is used to eliminate shoot-thru current. 1D 2 DRVGN Power Ground. Insure output capacitor ground is connected to this pin. 1R 3 LOWD Low Side Driver Output. Connect to gate of low side MOSFET. www.semtech.com  2003 Semtech Corp. 8 SC2659 POWER MANAGEMENT Pin Descriptions (Cont.) Pe in #Pn in Nam Pin Functio 1V 4D. R Drive Regulator for the MOSFET Drivers 1V 5V. IN12 12V Supply. Connect to 12V power rail 1T 6 BOO Bootstrap. This pin is used to generate a floating drive for the high side FET driver. 1R 7 HIGHD High Side Driver Output. Connect to gate of high side MOSFET. 1O 8BV OOTL Bootstrap Low. In applications where ≤ 5V is used as a power source, this pin can IN be connected to DRVGND. 1E 9 HISENS High Current Sense. Connected to the drain of the high side FET,or the input side of a current sense resistor between the input and the high side FET. 2E 0 LOSENS Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. 2O 1 IOUTL This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. 2T 2 INHIBI Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. 25 3V. ID2 Programming Input 23 4V. ID Programming Input 22 5V. ID Programming Input 21 6V. ID Programming Input 20 7V. ID Programming Input 2D 8 PWRG Power Good. This open collector logic output is high if the output voltage is within 15% of the set point.  2003 Semtech Corp. 9 www.semtech.com SC2659 POWER MANAGEMENT Block Diagram www.semtech.com  2003 Semtech Corp. 10 PWRGD IOUT HISENSE IOUTLO LOSENSE SOFTST + + - - 50uA G=2 ANALOG BIAS Vcc VIN12V PREREG I(VREFB) / 5 DRIVE RISING EDGE REGULATOR FAULT DELAY R Q + - DRV BANDGAP + S - HIGHDR SHUTDOWN LOWDR FILTER BOOT 0.85VREF 1.15VREF 0.85VREF UVLO DEGLITCH INH HIGHDR DEGLITCH + +- - + - + + - BOOTLO - 10V VID + DAC FILTER Vcc + VREF - - 1.15VREF FILTER + LOWDR - + - VSENSE DRVGND 2V + - - VREF + 100mV OCP AGND INHIBIT VID0 VID2 VID25 DROOP VSENSE VHYST VREFB LOHIB LODRV VID1 VID3 SC2659 POWER MANAGEMENT Output Voltage Table 0 = GND, 1 = OPEN (2) (1) (1) (1) (1) VID25mV VID3 VID2 VID1 VIDO VDC (V) 00 1 0 0 1.05 10 10 0 1.075 000 11 1.10 10 0 1 1 1.125 000 1 0 1.15 10 0 1 0 1.175 0000 1 1.20 1 000 1 1.225 00000 1.25 1 0000 1.275 0 1111 1.30 11111 1.325 0 111 0 1.35 1111 0 1.375 01 1 0 1 1.40 111 0 1 1.425 01 1 0 0 1.45 111 00 1.475 01 01 1 1.50 11 0 1 1 1.525 01 01 0 1.55 11 0 1 0 1.575 01 0 0 1 1.60 11 00 1 1.625 0 1 000 1.65 11 000 1.675 00 111 1.70 1 0 111 1.725 00 11 0 1.75 10 1 1 0 1.775 00 1 0 1 1.80 10 10 1 1.825 NOTE: (1) VID (3:0) correspond to legacy VRM 8.4 voltage levels for 1.3V - 1.8V. (2) VID 25mV provides a 25mV increment.  2003 Semtech Corp. 11 www.semtech.com SC2659 POWER MANAGEMENT Applications Information - Functional Description configured as a floating driver, the bias voltage to the Reference/Voltage Identification driver is developed from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT The reference/voltage identification (VID) section con- pins, is a Schottky for improved drive efficiency. The sists of a temperature compensated bandgap reference maximum voltage that can be applied between the BOOT and a 5-bit voltage selection network. The 5 VID pins pin and ground is 25V. The driver can be referenced to are TTL compatable inputs to the VID selection network. ground by connecting BOOTLO to PGND, and connecting They are internally pulled up to +3.3V generated from +12V to the BOOT pin. the +12V supply by a resistor divider, and provide pro- grammability of output voltage from 1.050V to 1.825V Deadtime Control in 25mV increments. Refer to the Output Voltage Table for the VID code set- Deadtime control prevents shoot-through current from tings. The output voltage of the VID network, VREF is flowing through the main power FETs during switching within 1% of the nominal setting over the full input and transitions by actively controlling the turn-on times of the output voltage range and junction temperature range. FET drivers. The high side driver is not allowed to turn on The output of the reference/VID network is indirectly until the gate drive voltage to the low-side FET is below 2 brought out through a buffer to the REFB pin. The volt- volts, and the low side driver is not allowed to turn on age on this pin will be within 3mV of VREF. It is not rec- until the voltage at the junction of the 2 FETs (VPHASE) is ommended to drive loads with REFB other than setting below 2 volts. An internal low-pass filter with an 11MHz the hysteresis of the hysteretic comparator, because the pole is located between the output of the low-side driver current drawn from REFB sets the charging current for (DL) and the input of the deadtime circuit that controls the soft start capacitor. Refer to the soft start section the high-side driver, to filter out noise that could appear for additional information. on DL when the high-side driver turns on. Hysteretic Comparator Current Sensing The hysteretic comparator regulates the output voltage Current sensing is achieved by sampling and holding the of the synchronous-buck converter. The hysteresis is voltage across the high side FET while it is turned on. set by connecting the center point of a resistor divider The sampling network consists of an internal 50Ω switch from REFB to AGND to the HYST pin. The hysteresis is and an external 0.033µF hold capacitor. Internal logic set by connecting the center point of a resistor divider controls the turn-on and turn-off of the sample/hold from REFB to AGND to the HYST pin. The hysteresis of switch such that the switch does not turn on until VPHASE tne comparator will be equal to twice the voltage differ- transitions high and turns off when the input to the high ence between REFB and HYST, and has a maximum value side driver goes low. Thus sampling will occur only when of 60mV. The maximum propagation delay from the com- the high side FET is conducting current. The voltage at parator inputs to the driver outputs is 250ns. the IO pin equals 2 times the sensed voltage. In applica- tions where a higher accuracy in current sensing is re- Low Side Driver quired, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor The low side driver is designed to drive a low R N- DS(ON) can be sampled by the current sensing circuit. channel MOSFET, and is rated for 2 amps source and sink. The bias for the low side driver is provided inter- Droop Compensation nally from VDRV. The droop compensation network reduces the load tran- High Side Driver sient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF equal The high side driver is designed to drive a low R N- DS(ON) to VREF • (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an channel MOSFET, and is rated for 2 amps source and external resistor divider from VOUT to the VSENSE pin to sink current. It can be configured either as a ground reduce the undershoot on VOUT during a low to high load referenced driver or as a floating bootstrap driver. When www.semtech.com  2003 Semtech Corp. 12 SC2659 POWER MANAGEMENT Applications Information - Functional Description (Cont.) current transient. The overshoot during a high to low proportional to VREF, the power-up time for VOUT will be load current transient is reduced by subtracting the volt- independent of VREF. Thus, C can remain the same SS age that is on the DROOP pin from VREF. The voltage on value for all VID settings. The soft start charging current the IO pin is divided down with an external resistor di- is determined by the following equation: I = I /5. SS REFB vider, and connected to the DROOP pin. Thus, under Where I is the current flowing out of the REFB pin. It REFB loaded conditions, VOUT is regulated to: is recommended that no additional loads be connected VOUT = VREF • (1+R7/R8) - IOUT • R2/(R1+R2). to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will deter- Inhibit mine the soft start charging current. The maximum cur- rent that can be sourced by REFB is 500µA. The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output Power Good drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the control- The power good circuit monitors for an undervoltage con- ler is in a low I state. When INH goes high, the short dition on VOUT. If VSENSE is 15% (nominal) below VREF, Q across the soft start capacitor is removed, the soft start then the power good pin is pulled low. The PWRGD pin is current source is enabled, and normal converter opera- an open drain output. tion begins. When the system logic supply is connected to INH, it controls power sequencing by locking out con- Overvoltage Protection troller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the The overvoltage protection circuit monitors VOUT for an +12V supply and the system logic supply (either +5V or overvoltage condition. If VSENSE is 15% above VREF, 3.3V) must be above UVLO thresholds before the con- than a fault latch is set and both output drivers are turned troller is allowed to start up. off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is in- VIN cluded for noise immunity. The VIN undervoltage lockout circuit disables the con- Overcurrent Protection troller while the +12V supply is below the 10V start threshold during power-up. While the controller is dis- The overcurrent protection circuit monitors the current abled, the output drivers will be low, the soft start ca- through the high side FET. The overcurrent threshold is pacitor will be shorted and the soft start current is dis- adjustable with an external resistor divider between IO abled and the controller will be in a low I state. When and AGND, with the divider voltage connected to the OCP Q VIN exceeds the start threshold, the short across the pin. If the voltage on the OCP pin exceeds 100mV, then soft start capacitor is removed, the soft start current a fault latch is set and the output drivers are turned off. source is enabled and normal converter operation be- The latch will remain set until VIN goes below the gins. There is a 2V hysteresis in the undervoltage lock- undervoltage lockout value. A 1ms deglitch timer is in- out circuit for noise immunity. cluded for noise immunity. The OCP circuit is also de- signed to protect the high side FET against a short-to- Soft Start ground fault on the terminal common to both power FETs (VPHASE). The soft start circuit controls the rate at which VOUT pow- ers up. A capacitor is connected between SS and AGND Drive Regulator and is charged by an internal current source. The value of the current source is proportional to the reference The drive regulator provides drive voltage to the low side voltage so the charging rate of C is also proportional to driver, and to the high side driver when the high side SS the reference voltage. By making the charging current driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA.  2003 Semtech Corp. 13 www.semtech.com SC2659 POWER MANAGEMENT Application Circuit www.semtech.com  2003 Semtech Corp. 14 +5V R10 R11 U1 10k 1k SC2659 PWRGD +12V 1 28 IOUT PWRGD "POWER GOOD" +12V C9 0.1 J0 R1 R3 2 27 DROOP VID0 GND 4.3k 2k INHIB C1 C2 J1 3 26 OCP VID1 "INHIBIT" 0.001 0.001 C10 R12 J2 R2 R4 0.1 4 25 1k VHYST VID2 1k 1k C3 R5 0.1 J3 150* 5 24 VREFB VID3 POS/IN L1 C4 R6 0.1 J4 + 20k 6 23 VSENSE VID25 0.5uH C15-23 C24-32 7 22 Vin +5V/12V AGND INHIBIT R13 R14,15,16 1.0 820uF 16V C5 0 0 0.001 8 21 _ SOFTST IOUTLO GND/IN C11 R17 0.033 NS C6 9 20 0.1 N/C LOSENSE +5V R19 C12 R7 R18 0 22.0 100 NS 10 19 LODRV HISENSE D1 C7 MBRA130L 0.01 11 18 LOHIB BOOTLO Q1 Q2 R20 FDB6035AL FDB6035AL R21 1.0 1.0 R24,25 12 17 DRVGND HIGHDR 3.3 2pl. C33,34 L2 13 16 LOWDR BOOT 1.0uH@40A POS/OUT 0.0022 C13 +12V 2pl. + 1.0 14 15 DRV VIN12V Q3 Q4 FDB7030BL R22 FDB7030BL R26,27 1.6 3.3 C37-46 R23 C47-58 1.6 1500uF 6.3V 2pl. Vout=1.7Vtyp. 10.0 C35,36 D2(opt) C8 C14 0.0022 MBRB3030CT 2.2 2.2 2pl. _ D(opt) MBRA130L GND/OUT R9 150 R8 C59 10k L1 - #T51-26C, 2ts, 18AWG 1.0 L2 - #77310-A7, 3ts, 4x20AWG SC2659 POWER MANAGEMENT Typical Characteristics V = 5V; I = 0A to 40A IN OUT “Droop” & “Offset” Disabled V = 1.8V OUT 100% 3% 90% 2% 80% 70% 1% 60% 50% 0% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A V = 1.5V OUT 3% 100% 90% 2% 80% 70% 1% 60% 50% 0% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A V = 1.1V OUT 3% 100% 90% 2% 80% 70% 1% 60% 0% 50% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A  2003 Semtech Corp. 15 www.semtech.com Efficiency Efficiency Efficiency Regulation Regulation Regulation SC2659 POWER MANAGEMENT Typical Characteristics (Cont.) V = 12V; I = 0A to 40A IN OUT “Droop” & “Offset” Disabled V = 1.8V OUT 100% 3% 90% 2% 80% 70% 1% 60% 50% 0% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A V = 1.5V OUT 100% 3% 90% 2% 80% 70% 1% 60% 50% 0% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A V = 1.1V OUT 100% 3% 90% 2% 80% 70% 1% 60% 50% 0% 40% -1% 30% 20% -2% 10% 0% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 Current, A Current, A www.semtech.com  2003 Semtech Corp. 16 Efficiency Efficiency Efficiency Regulation Regulation Regulation SC2659 POWER MANAGEMENT Evaluation Board Artwork Top Layer Bottom Layer Mid Layer  2003 Semtech Corp. 17 www.semtech.com SC2659 POWER MANAGEMENT Evaluation Board Artwork (Cont.) Top Overlay Bottom Overlay www.semtech.com  2003 Semtech Corp. 18 SC2659 POWER MANAGEMENT Materials List Qe uantityRn eferenc Pr art/Descriptio Vendo 35CF 1,C2,C 0n .001µ TDK, Murata, Taiyo-Yude 60CF 3,C4,C6,C7,C9,C1 0y .1µ an 11CF 1 0y .033µ an 12CF 1 2y 2µ an 19 1CF 13, C15-C23, C5 1y µ an 24CF 8,C1 2y .2µ an 92CV 24 - C3 8X 20µF, 16 SANYO P/N: 16MV820A 16 0Ce 37 - C4 1X 500µF, 6.3V, thru hol SANYO P/N: 6R3MV1500A 18 2CF 47 - C5 1y 0µ an 46CF 33 - C3 .y 0022µ an 11DyMi BRA130L. Schottk ON Sem 1)DL 2 (optional Mi BRB2515 ON Sem 11Ld0G .5uH, Toroi Micrometals P/N: T51-26C, 18 AW 12Ld1G .0uH, Toroi Magnetics, #77310, 3ts, 4 X 20 AW 22QT 1,Q DL 2Pak, MOSFE Fairchild P/N: FDB6035A 24QT 3,Q DL 2Pak, MOSFE Fairchild P/N: FDB7030B 11Rk2y an 42Rk 2,R4,R11,R1 1y an 13Rk4y .3 an 16Rk2y 0 an 15 R any 150* 17R01y 0 an 20Rk 8,R1 1y 0 an 19R01y 5 an 21R1 20,R2 any 23R6 22,R2 1y . an 47R3 24,R25,R26,R2 3y . an 11URS1 C2659CSW.T Semtech Corp. 805-498-211  2003 Semtech Corp. 19 www.semtech.com SC2659 POWER MANAGEMENT Layout Guidelines (See pg. 1) 1. Locate R8 and C2 close to pins 6 and 7. 10. If Schottky diode used in parallel with a synchronous 2. Locate C1 close to pins 5 and 7. (bottom) FET, to achieve a greater efficiency at lower Vout 3. Components connected to IOUT, DROOP, OCP, VHYST, settings, it needs to be placed next to the aforementioned VREFB, VSENSE, and SOFTST should be referenced to FET in very close proximity. AGND. 11. Since the feedback path relies on the accurate sampling 4. The bypass capacitors C5 and C10 should be placed of the output ripple voltage, the best results can be achieved close to the IC and referenced to DRVGND. by connecting the AGND to the ground side of the bulk 5. Locate bootstrap capacitor C13 close to the IC. output capacitors. 6. Place bypass capacitor close to Drain of the top FET and 12. DRVGND pin should be tight to the main ground plane Source of the bottom FET to be effective. utilizing very low impedance connection, e.g., multiple vias. 7. Route HISENSE and LOSENSE close to each other to 13. In order to prevent substrate glitching, a small (0.5A) minimize induced differential mode noise. Schottky diode should be placed in close proximity to the 8. Bypass a high frequency disturbance with ceramic chip with the cathode connected to BOOTLO and anode capacitor at the point where HISENSE is connected to Vin. connected to DRVGND. 9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. Outline Drawing - SO-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2003 Semtech Corp. 20