SEMTECH SC2616

SC2616 Complete DDR Power Solution POWER MANAGEMENT Description Features The SC2616 is a fully integrated DDR power solution pro- ‹ High efficiency (90%) switcher for VDDQ supplies viding power for the VDDQ and the VTT rails. The SC2616 20 Amps also completely adheres to the ACPI sleep state power ‹ High current gate drives requirements. A synchronous buck controller provides ‹ Single chip solution complies fully with ACPI power the high current of the VDDQ at high efficiency, while a sequencing specifications linear sink/source regulator provides the termination ‹ Internal S3 state LDO supplies high standby VDDQ voltage with 2 Amp Source/Sink capability. This approach current (0.65 Amp Min.) makes the best trade-off between cost and performance. ‹ ACPI sleep state controlled Additional logic and UVLOs complete the functionality of ‹ 2 Amp VTT source/sink capability this single chip DDR power solution in compliance with ‹ UVLO on 5V and 12V SLP_S3 and SLP_S5 motherboard signals. ‹ Indepent thermal shutdown for VDDQSTBY and VTT ‹ Fast transient response The SC2616 is capable of sourcing up to 20A at the ‹ 18 pin MLP package switcher output, and 2A source/sink at the VTT output. The MLP package provides excellent thermal impedance Applications while keeping small footprint. VDDQ current limit as well as 3 independent thermal shutdown circuits assure safe ‹ Power solution for DDR memory per ACPI operation under all fault conditions. motherboard specification ‹ High speed data line termination ‹ Memory cards Typical Application Circuit 5VCC Q1 R1 12VCC 5VSBY R3 R9 Cin Q2 R4 C8 C18 U1 SC2616 VDDQ 9 0 5VCC 16 12VCC 0 15 0 L1 TG Q3 4 14 R7 Cout 5VSBY BG 13 PGND 11 7 SLP_S3# SLP_S3 VDDQSTBY 10 8 SLP_S5# SLP_S5 VDDQIN 0 1 FB 18 2 SS/EN VTTSNS 17 5 COMP VTT R5 6 0 VTT C5 VTT 1k R2 C15 C14 R8 1k C6 0 0 0 0 0 1 October,13, 2003 www.semtech.com 0.1uF 12 AGND 19 PAD 3 LGND SC2616 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit SV upply Voltage, 5VCC to AGND 7V 5VCC SV upply Voltage, 12VCC to AGND 1V 5 12VCC SV tandby Input Voltage 7V 5VSBY IO nputs I3 /5V VSTBY +0.3, AGND -0. AGND to PGND or LGND 0V .3 VI TT Output Current ±A 3 O(VTT) OT perating Ambient Temperature Range 0C to 70 ° A OT perating Junction Temperature 1C 25 ° J Thermal Resistance Junction to Ambient θ 2W 5 °C/ JA Thermal Resistance Junction to Case θ 4W °C/ JC ST torage Temperature -C 65 to 150 ° STG TG/BG DC Voltage 1V 2Vcc + 0.3, AGND -0.5 TG/BG AC Voltage, t ≤10 00ns 1V 2Vcc + 1.0, AGND -2. ED SD Rating (Human Body Model) E2 S kV Electrical Characteristics Unless specified: T = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit 5V V Supply Voltage 45 .5 5V .5 5VCC 1V 2V Supply Voltage 12 0 141V 12VCC 5V V Standby Voltage 45 .5 5V .5 5VSBY S2 0, S5 5A . m QI uiescent Current Q(5VSBY) S8 3, IDDQSTBY = 0 7A . m SLP_S3 Threshold TV TL SLP_S5 Threshold TV TL SI LP_S3/SLP_S5 Input Current 5A 0 µ S3,S5 www.semtech.com © 2003 Semtech Corp. 2 SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit 1O 2VCC Under Voltage Lockout UVL 8290 . 1V 12VCC 5O VCC Under Voltage Lockout UVL 2V .5 5VCC FV eedback Reference 1V .25 REF FI eedback Current V=5 1.25V 0A . µ FB FB SV S/EN Shutdown Threshold 0V .3 EN(TH) TT hermal Shutdown 1C 50 ° J-SHDN Ts hermal ShutdownHT ysteresi 1C 0 ° J-HYST Switcher LI oad Regulation =2 0A to 10A; S0 0% . VDDQ Of scillator Frequency 20 2525 5 2z 7 KH OSC SI oft Start Current 2A 5 µ SS Duty Cycle 059% OV vercurrent Trip Voltage %0 of VDDQ Setpoint 75708% TRIP TG op Gate Rise Time TG5 ate capacitance = 4000pF 2S n R TG op Gate Fall Time TG5 ate capacitance = 4000pF 2S n F BG ottom Gate Rise Time BG5 ate capacitance = 4000pF 3S n R BG ottom Gate Fall Time BG5 ate capacitance = 4000pF 3S n F Dt ead Time 20 05S n d EG rror Amplifier Transconductance 0S .8 m M EA rror Amplifier Gain @ DC R=8 open 3B d EA COMP EG rror Amplifier Bandwidth 5z MH BW Error Amplifier Source/Sink Current ±A 60 µ © 2003 Semtech Corp. 3 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit Switcher (Cont.) PV WM Ramp P5 eak to Peak 0V .5 RAMP STBY LDO OI utput Current D0 C current 60 5 70 5 8A 5 m VDDQSTBY Load Regulation ∆V/∆II=3 0A to 460mA; S3 05 . 0% . VDDQ CI urrent Limit S3 LP_S3 = 0 2A . LIM VTT LDO OT utput Voltage VV T =7 2.500V 10 .2317 .25 1.26 VDDQSTBY V I=5 1.8A to -1.8A 10 .2215 .25 1.27 VTT SI ource and Sink Currents ±2 1.8 ±A VTT Load Regulation ∆VTT/ ∆II=5 +1.8A to -1.8A ±0 0. ±% 1. VTT EA rror Amplifier Gain 7B 5 d EA_VTT S3 LP_S3 = high (sink) CT urrent Limit VT A ILIM S3 LP_S3 = high (source) www.semtech.com © 2003 Semtech Corp. 4 SC2616 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW Pe art Numbers Packag (1) SC2616MLTR MLP-18 FB 1 18 SS/EN VTTSNS 2 17 COMP Note: (1) Only available in tape and reel packaging. A reel LGND 3 16 12VCC contains 3000 devices. 5VSBY 4 15 TG VTT 5 14 BG VTT 6 13 PGND VDDQSTBY 7 12 AGND VDDQIN 8 11 SLP_S3 5VCC 9 10 SLP_S5 (18 Pin MLP) Note: Pin 19 is the thermal Pad on the bottom of the device Pin Descriptions Pe in #Pn in Nam Pin Functio 1BF. Feedback for the STBY LDO and the switcher for VDDQ 2SVT TTSNV. T LDO feedback and remote sense input 3DLT GN VT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2A of current. 4Y5. VSB Bias supply for the chip. Connect to 5V standby 5T , 6 VT VTT output. Connect to point of load. The trace connecting to this pin must be able to carry 2A of current 7Y VDDQSTB S3 VDDQ output. Provision must be made to prevent the VDDQSTBY supply from back feeding the input supply (see typical application schematic). Traces connecting to this pin must be capable of carring 0.85A of current. 8NVT DDQI VDDQ power input to VT LDO. The trace connecting to this pin must be able to carry 2 A of current. 9C5c VC Supply to the lnternal logi 15 0S. LP_S Connect to SLP_S5 signal from motherboard 13 1S. LP_S Connect to SLP_S3 signal from motherboard 1D 2A. GN Analog ground 1D 3P. GN Gate drive return. Keep this pin close to bottom FET source 1G 4B. Bottom gate drive 1G 5T. Top gate drive 1C 61. 2VC Supply to the upper and lower gate drives 1P 7C. OM Compensation pin for the PWM transconductance amplifier 1N 8 SS/E Soft start capacitor to AGND. Pull low to less than 0.3V to disable the controller. 1D 9 TH_PA Copper pad on bottom of chip used for heatsinking. This pin must be connected to ground plane under IC. (See application information). © 2003 Semtech Corp. 5 www.semtech.com SC2616 POWER MANAGEMENT Block Diagram E/A www.semtech.com © 2003 Semtech Corp. 6 SC2616 POWER MANAGEMENT Timing Diagram UVLO 5V,12V Rails SLP_S3 SLP_S5 1.25V 1.0V 0.3V SS/EN Internal PGOOD TG BG VDDQSTBY VTT Vddqsb Vddqsw VDDQ S5 S0 S3 S0 S5 © 2003 Semtech Corp. 7 www.semtech.com SC2616 POWER MANAGEMENT Applications Information supplies(5V and 12V), since both supplies have to be Description higher than their UVLO thresholds for proper start-up. The Semtech SC2616 DDR power supply controller offers Initial Conditions and Event Sequencing a switching and linear regulator combination to provide the necessary functions to comply with S3 and S5 sleep The main switcher will start-up in Asynchronous Mode state signals generated by the Desktop Computer when the voltage on SS/EN pin is greater than ~0.3V. Motherboards. VDDQ supply, and VTT termination voltage The SS/EN will go high only after the 5Vcc and 12Vcc are are supplied to the Memory bus during S0 (normal higher than their respective UVLO thresholds. The switcher operation) state. During S0, VDDQ is supplied via the achieves maximum duty cycle when SS/EN reaches Switching regulator, sourcing high output currents to the 0.8V. When the SS/EN equals 1.25V, the synchronous VDDQ bus as well as supplying the termination supply FET will also be activated. current. The SC2616 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability When the SLP_S5 and SLP_S3 go high for the first time, allows 15-20A DC load on the VDDQ supply. The VTT the VDDQ is supplied by the switcher, thus removing the termination voltage is an internal sink/source linear burden of charging the output capacitors via the linear regulator, which during S0 state receives its power from regulator. An internal latch guarantees that the supply the VDDQ bus. It is capable of sourcing and sinking 2 goes through S0 state for the first time. Amps (max). The current limit on this pin is set to 3 Amps (typical). During a transition from S3 to S0, where the 5V and 12V rails and subsequently the SS/EN pin go high, the internal Output Current and PCB layout VDDQ standby supply will remain ”on” until SS/EN has reached 1V, at which point only the switcher is supplying The current handling capacity of SC2616 depends upon VDDQ , and the internal “power good” indicator goes the amount of heat the PC board can sink from the high. SC2616 thermal pad. (See thermal considerations). The PC board layout must take into consideration the high The “Memory” activity should be slaved off the “Power current paths, and ground returns for both the VDDQ OK” signal from the Silver Box supply, and since the and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND “Power OK” is asserted after all supplies are within close traces must also be routed using wide traces to minimize tolerance of their final values, the VDDQ switcher should power loss and heat in these traces, based on the current have been running for some time before the memory is handling requirements. activated. This is true for typical SS/EN capacitor values (10nf to 220nf). Thus during transitions from S3 to S0, S3 and S5 States the concern that the VDDQ Standby supply may have to provide high currents before the switcher is activated is During S3 and S5 sleep states, the operation of the VDDQ alleviated. and VTT supplies is governed by the internal sequencing logic in strict adherence with motherboard specifications. The logic inputs to SLP_S3 and SLP_S5 pins must be The timing diagram demonstrates the state of the defined before application of power to the SC2616. This controller, and each of the VDDQ and VTT supplies during can be guaranteed by pulling up the SLP_S3 and SLP_S5 S3 and S5 transitions. When SLP_S3 is low, the VDDQ inputs to 5VStandby. If the chipset that asserts these supplies the “Suspend To RAM” current of 650 mA (min) signals is powered after the SC2616 powers up, and to maintain the information in memory while in standby SLP_S3 and SLP_S5 are not pulled up, erroneous startup mode. The VTT termination voltage is not needed during and operation can result. this state, and is thus tri-stated during S3. Once SLP_S3 goes high, the VDDQ switcher recovers and takes control Care must be taken not to exceed the maximum voltage/ of the VDDQ supply voltage. When SLP_S5 and SLP_S3 current specifications of the interface inputs supplying are both pulled low, all supplies shut down. The SS/EN these signals. The pullup voltage and resistor must be pin must be pulled low (<0.3V) and high again to restart chosen such that when high, the S3 and S5 do not “back the SC2616. This can be achieved by cycling the input drive” the interface chipset (Southbridge, etc.) and the www.semtech.com © 2003 Semtech Corp. 8 SC2616 POWER MANAGEMENT Applications Information (Cont.) maximum voltage applied to these pins do not exceed that will give an inductor ripple current of approximately the chipsets specifications. A separate lower pullup supply 20% of max. output current. may be necessary to avoid damage to the chipset. Inductor ripple current is given by:- ⎛ V ⎞ O “Back Feeding” the Input Supply V ⋅⎜1− ⎟ O ⎜ ⎟ V ⎝ IN⎠ I = LRIPPLE L ⋅ f OSC When in S3 state, VDDQ is supplied by the linear regulator and current can flow back from the VDDQ supply through So choose inductor value from:- the body diode of the Top switching MOSFET to the 5V ⎛ V ⎞ O 5 ⋅ V ⋅⎜1− ⎟ supply of the Silver Box, which is off during the S3 state. O ⎜ ⎟ V ⎝ IN⎠ L = This in turn shorts out the VDDQ supply and is not I ⋅ f O OSC acceptable. OUTPUT CAPACITOR(S) - The output capacitors should An addittional MOSFET should be addded to avoid the be selected to meet output ripple and transient response reverse current flow. The MOSFETs should have the drains criteria. Output ripple voltage is caused by the inductor to each other(common- Drain). ripple current flowing in the output capacitor’s ESR (There is also a component due to the inductor ripple current During S0 to S3 transition, As soon as SLP_S3 signal charging and discharging the output capacitor itself, but goes low, BG signal stops chopping. This can prevent the this component is usually small and can often be ignored). inductor to build up its current in the reverse direction. Given a maximum output voltage ripple requirement, ESR is given by:- To avoid the MOSFET damaged by overshoot, the input bulk capacitor must be added to the node of common - L ⋅ f ⋅ V OSC RIPPLE R < ESR Drain. ⎛ V ⎞ O V ⋅⎜1− ⎟ O ⎜ ⎟ V ⎝ IN⎠ Current Limit Output voltage transient excursions are a function of load Current limit is implemented by sensing the VDDQ voltage. current transient levels, input and output voltages and If it falls to 75% off its nominal voltage, as sensed by the inductor and capacitor values. FB pin, the TG and BG pins are latched off and the switcher and the linear converters are shut down. To Capacitance and R values to meet a required tran- ESR recover from the current limit condition, either the power sient condition can be calculated from rails, 5VCC or 12VCC have to be recycled, or the SS/EN pin must be pulled low and released to restart switcher V T operation. R < ESR I T 2 L ⋅I Thermal Shutdown T C > 2 ⋅ V ⋅ V T A There are three independent Thermal Shutdown where protection circuits in the SC2616: the VDDQ linear V = V − V for negative transients (load application) A IN O regulator, the VTT source regulator, and the VTT sink and regulator. If any of the three regulators’ temperature V = V for positive transients (load release) A O rises above the threshold, that regulator will turn off independently, until the temperature falls below the values for positive and negative transients must be cal- thermal shutdown limit. culated seperately and the worst case value chosen. For Capacitor values, the calculated value should be doubled OUTPUT INDUCTOR - A good starting point for output to allow for duty cycle limitation and voltage drop issues. filter component selection is to choose an inductor value © 2003 Semtech Corp. 9 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) The task here is to properly choose the compensation Compensation Components network for a nicely shaped loop-gain Bode plot. The Gpwm following design procedures are recommended to accom- L EA plish the goal: R1 R Rc (1) Calculate the corner frequency of the output filter: Vbg Vin Ro 1 Co C R2 1.25Vdc F := o 2⋅π⋅ LC ⋅ o (2) Calculate the ESR zero frequency of the output filter Fig. 1. SC2616 control model. capacitor: 1 F := The control model of SC2616 can be depicted in Fig. 1. esr 2⋅π⋅R ⋅C c o This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference (3) Check that the ESR zero frequency is not too high. is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive F sw F < esr divider network, R1 and R2. 5 If this condition is not met, the compensation structure The error amplifier is transconductance type with fixed may not provide loop stability. The solution is to add gain of: 0.0008⋅A some electrolytic capacitors to the output capacitor bank G := m V to correct the output filter corner frequency and the ESR The compensation network includes a resistor and a ca- zero frequency. In some cases, the filter inductance may pacitor in series, which terminates from the output of also need to be adjusted to shift the filter corner the error amplifier to the ground. frequency. It is not recommended to use only high fre- quency multi-layer ceramic capacitors for output filter. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is propor- (4) Choose the loop gain cross over frequency (0 dB fre- tional to the input voltage, which results in an excellent quency). It is recommended that the crossover frequency performance to reject input voltage variation. The PWM is always less than one fifth of the switching frequency : gain is inversion of the ramp amplitude, and this gain is given by: F sw F ≤ 1 x_over G 5 pwm V ramp If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one where the ramp amplitude (peak-to-peak) is 0.55 volts tenth of the switching frequency for good noise immunity. when input voltage is 5 volts. The resistor in the compensation network can then be calculated as: The total control loop-gain can then be derived as follows: 2 F F V . . 1 ⎛ esr⎞ ⎛ x_over⎞⎛ o⎞ 1sR C . . 1sR C c o R := ⋅ ⋅ ⋅ ⎜ ⎜ ⎜ . . Ts () T ⋅V ⋅G F F V G o pwm in m o esr bg . . ⎝ ⎠ ⎝ ⎠⎝ ⎠ sR C R L c 2 . . . . . 1s R C s L C 1 c o o R R o o when where V ⎛ bg⎞ F < F < F T := G ⋅G ⋅V ⋅R⋅ o m pwm in ⎜ o esr x_over V o ⎝ ⎠ www.semtech.com © 2003 Semtech Corp. 10 SC2616 F.o F.o POWER MANAGEMENT Applications Information (Cont.) or Step 1. Output filter corner frequency 2 F F V 1 ⎛ o⎞ ⎛ x_over⎞⎛ o⎞ F = 1.13 KHz o R := ⋅ ⋅ ⋅ ⎜ ⎜ ⎜ G ⋅V ⋅G F F V pwm in m esr o bg ⎝ ⎠ ⎝ ⎠⎝ ⎠ Step 2. ESR zero frequency: when F = 4.019 KHz esr F < F < F esr o x_over Step 3. Check the following condition: (5) The compensation capacitor is determined by choos- F sw F < esr ing the compensator zero to be about one fifth of the 5 output filter corner frequency: Which is satisfied in this case. F o F zero Step 4. Choose crossover frequency and calculate 5 compensator R: 1 C . . . F = 50 KHz 2 π R F x_over zero R = 43.197 KΩ (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equa- Step 5. Calculate the compensator C: tions provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this C = 16.287 nF design procedure ensures a healthy phase margin. Step 6. Generate Bode plot and check the phase margin. An example is given below to demonstrate the proce- In this case, the phase margin is about 85°C that en- dure introduced above. The parameters of the power sures the loop stability. Fig. 2 shows the Bode plot of the supply are given as: loop. V := 5 V in V := 2.5 V o I := 20 A o F := 250 KHz sw L := 3 µH C := 6600 µF o R := 0.006 Ω c R := 1.0 KΩ 1 R := 1.0 KΩ 2 © 2003 Semtech Corp. 11 www.semtech.com SC2616 POWER MANAGEMENT Loop Gain Mag (dB) 100 50 mag () i 0 50 3 4 5 6 . . . . 10 100 1 10 1 10 1 10 1 10 F i Loop Gain Phase (Degree) 0 45 phase () i 90 135 180 3 4 5 6 . . . . 10 100 1 10 1 10 1 10 1 10 F i Fig. 2. Bode plot of the loop www.semtech.com © 2003 Semtech Corp. 12 4.7uF /6 .3 V 4.7uF /6 .3 V 3300uF /6 .3 V 4 .7uF /6 .3 V 1500uF /6 .3 V 3300uF /6 .3 V 1500uF /6 .3 V 1500uF /6 .3 V 4.7uF /6 .3 V IP P 06N 03LA IP D 13N 03 L IP D 09N 03LA non pop. 0.1uF 1500uF /6 .3 V 1N 414 8 SC2616 POWER MANAGEMENT Applications Information (Cont.) Evaluation Board Schematic 5VCC 5VCC 5VSBY D1 Q1 R1 C19 12VCC 2R2 R13 0 C13 2.2R 0 1uF C5 C6 15n 12VCC C1 C2 C3 C7 C4 0 U1 1 18 R2 Q2 FB FB SS/EN R3 43K 2R2 2 17 R4 VTTSNS COMP VDDQ C8 0 2R2 3 16 1uF 0 0 LGND 12VCC 4 15 L1 3uH 5VSBY TG R5 VTT Q3 5 14 R6 1k VTT BG C12 2R2 C9 C10 C11 C15 6 13 R7 FB VTT PGND 4.7uF C16 2R2 7 12 1n R8 C14 VDDQSTBY AGND 1k 8 11 0 SLP_S3 VDDQIN SLP_S3 VDDQ 9 10 SLP_S5 5VCC SLP_S5 0 0 C17 SC2616 1uF R9 C18 2R2 1uF 5VCC 0 0 0 Guidelines for Layout of DDR Supply Using SC2616 DDR load point (do not connect to the inductor output at the Controllers on Typical Motherboards VDDQ plane near the controller/FETS. Place the voltage divider at the load point and route the divider center and Signals of arbitrary importance (signals that can be routed the sense ground close together as a differential pair. last, such as SLP_S3, SLP_S5, 5VCC) have been omitted Connect the AGND and the sensed ground and LGND at for simplicity. the chip. 5. The VTTSNS must be connected to a distant load Parameters of importance in the Layout of the DDR power point. section are as follows (in order of importance): 6. Adequate copper area must be allocated to both 1. The VTT decoupling cap,C15, must be placed less than VDDQ and VTT. The copper coverage must be uniform, i. 0.25 inch from Controller. e. it provides low resistance to all areas around the 2. The power rail decoupling cap,C4, must be placed DIMMs. VDDQIN traces (and vias if used to carry current) less than 0.25 inch from Q2 drain. must be adequate for 2.0Amps. 3. The decoupling caps for 5VSBY AND 12Vcc,C13 and 7. Make the phase node area, which connects the C8, must be placed very close to the controller(0.25inch Inductor, Top FET and the Bottom FET, as small as or less) possible to prevent EMI, and ringing. Avoid making this 4. The VDDQ sense lines must be routed from a distant © 2003 Semtech Corp. 13 www.semtech.com 19 PAD SC2616 POWER MANAGEMENT Applications Information (Cont.) connection using Vias, to minimize inductance. 8. Route gate drive traces on the Top layer as much as possible, with traces 25 mil or wider. If Vias are used, use multiple vias. While gate drive resistors are not required, they may be needed to reduce ringing if the traces are long and inductive. 9. Place components R2,C5, C6 and C7 near the controller, preferably on an analog ground island. 10. Keep Input electrolytic capacitors near the FETs, to minimize AC current loops. The traces connecting to pins 9, 10, 11 are not critical, since low currents flow in these paths. Thermal considerations 11. The controller must be placed on a copper land, with at least 0.5” square area. Remove the Soldermask under the IC, as shown in the recommend landing pattern in this datasheet. The Solder-mask cutout area(also referred as stencil aperture) allows the Ground contact at the bottom of the controller (pin 19) to be directly soldered to the PC board for heatsinking to the PC board. There must be at least 5 vias connecting the top and bottom layers on this plane to reduce thermal resistance. These thermal vias must be minimum diameter for the PCB process(12mil drill for 62mil thick PCB). Also it is better to plug the vias by copper plating and solder plating. Making the soldermask cutout area too large will add to the risk of solder flowing near the pins and causing shorted connections. 12. The FETs must be placed on a copper area large enough to adequately transfer heat from the FETs to the PC board. Multiple vias aid in cooling the copper area surrounding the FETs, thus reducing the FETs’ junction to ambient thermal resistance. www.semtech.com © 2003 Semtech Corp. 14 SC2616 POWER MANAGEMENT Outline Drawing - MLP-18 TERMINAL 1 TOP VIEW IDENTIFIER TERMINAL 1 BOTTOM VIEW 1 CONTROLLING DIMENSIONS: MILLIMETERS © 2003 Semtech Corp. 15 www.semtech.com SC2616 POWER MANAGEMENT Recommended Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com © 2003 Semtech Corp. 16