SEMTECH SC2615

SC2615 Complete DDR Power Solution POWER MANAGEMENT Description Features The SC2615 is a fully integrated, Three in One, Linear Linear Linear Linear Linear ‹ Single chip solution adheres to ACPI sleep state DDR power solution providing power for the VDDQ and requirements using BF_CUT the VTT rails. The SC2615 completely adheres to the ‹ UVLO on 3.3V and 12V R ACPI sleep state power requirements per Intel ‹ Internal S3 state LDO for VDDQ supplies 650 mA motherboard specifications. A linear regulator controller ‹ Dual thermal shutdown provides the high current of the VDDQ during S0, via an ‹ Fast transient response external Power MOSFET, while an internal 1.8A (min) sink/ ‹ Internal VTT regulator Sinks and Sources 1.8A source regulator supplies the termination voltage. (Min) ‹ Power good output In addition to these two blocks, an Internal LDO provides ‹ 18 pin MLP package VDDQ power during S3, capable of sourcing 650 mA. R The SC2615 uses Intel defined Latched BF_CUT signal Applications which is also used to drive the external Blocking MOSFET. R ‹ DDR power solution for Intel motherboard Additional logic, two UVLOs and three thermal shutdown circuits assure reliability of this single chip DDR power applications solution. A Power Good Output indicates the rails are in ‹ High speed data line termination regulation. ‹ Graphic cards ‹ Disk drives A Soft Start/Enable pin assures proper startup and allows external shutdown control. The MLP package provides excellent thermal impedance while keeping a small footprint. Typical Application Circuit 12V 5V 5V STBY Cin 1uF SC2615 16 9 VDDQ 12VCC 3.3VCC 4 15 5VSBY TG BF_CUT BF_CUT 11 14 Cout BF_CUT NC PWRGD PWRGD 10 13 PGOOD NC 18 7 SS/EN VDDQSTBY 17 8 NC VDDQIN 12 1 AGND FB 0.1uF 3 6 LGND VTT 2 5 VTT VTTSNS VTT 1 Revision 2, April 2003 www.semtech.com 19 HSINKPAD SC2615 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit IV nput Supply Voltage, 3.3VCC 7V CC3 IV nput Supply Voltage, 12VCC 1V 5 CC12 VI TT Output Current ±A 3 O(VTT) 5V V Standby Input Voltage 7V 5SB IO nputs and Outputs I3 /5V VSTBY +0.3, GND -0. AGND to LGND ±V 0.3 OT perating Ambient Temperature Range A 0C to 70 ° OT perating Junction Temperature J 1C 25 ° (1) Thermal Resistance Junction to Ambient 2W 5 °C/ θJA (1) Thermal Resistance Junction to Case θJC 4W °C/ ST torage Temperature STG -C 65 to 150 ° LT ead Temperature (Soldering) 10seconds LEAD 3C 00 ° ED SD Rating (Human Body Model) E2 S kV Electrical Characteristics Unless specified: T = 0 to 70°C, V = 12V, V = 3.3V, 5VSTBY = 5V. A CC12 CC3 Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit 3V .3V Supply Voltage 33 .0 36 . 3V . CC3.3 1V 2V Supply Voltage 12 0.8121V 3. CC12 5V V Standby Voltage 45 .5 5V .5 5SB 5V STBY Input Quiescent I S4 0 2A . m Q(STBY) Current BF_CUT Threshold TTL 1O 2V Under Voltage Lockout UVL 7280 . 1V 12 3O .3V Under Voltage Lockout UVL 29 .4 20 . 3V . 3.3 FV eedback Reference 1V .25 REF FI eedback Current 2A µ FB 5I V STBY in S3 Current 25 mA Q(STBY) SV S/EN Shutdown Threshold 0V .2 EN(TH) Thermal Shutdown 1C 50 ° www.semtech.com  2003 Semtech Corp. 2 SC2615 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: T = 0 to 70°C, V = 12V, V = 3.3V, 5VSTBY = 5V. A CC12 CC3 Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit VDDQLinear OV utput Voltage D0 DR1 25 .45 20 . 2V .55 OUT D4 DR2 18 .76 16 . 1V .83 SI oft Start Current 2A 5 µ SS OV vercurrent Trip Voltage 50 0 607% TRIP EW rror Amplifier BandwidthB5 MHz LT oad Regulation <2 125°C % jmax EL rror Amplifier GainA5 O 7b d Pk ower Good Low 10 mA sin 504V 0 m PV ower Good High Leakage 5102 . µA STBYLDO O3 utput Current S06A 5 m LT oad Regulation <2 125°C % jmax VTT LDO (2) Source and Sink Currents I 10 .82A . TT Load Regulation 2% .5 EG rror Amplifier Gain 7b 5 d EA Notes: (1) Mounting considerations: The thermal copper pad on bottom of device must be soldered to a solid copper area, of 1 inch * 1 inch (min.) with multiple vias under the device to achieve specified θ and θ , JA JC (See recommended land pattern). (2) This limit indicates that the regulator has a current limit threshold that is greater than the rated Minimum current. The rated current can only be achieved if the Absolute Maximum Junctions temperatures are not violated. The amount of heatsinking determines the maximum usable VTT current.  2003 Semtech Corp. 3 www.semtech.com SC2615 POWER MANAGEMENT Pin Configuration Ordering Information Top View Pe artNumbers Packag (1) SC2615MLTR MLP-18 Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (MLP-18) Pin Descriptions Pe in # Pn in Nam Pin Functio 1BF. Feedback for the VDDQ and standby LDO 2SVV TTSN LDO feedback and remote sense input. TT 3DL. GN VTT regulator ground 4Y5V VSTB ICf. rom 5V standby CC 5T ,6 VT VTT regulator output. A 0.1µF - 1µF ceramic capacitor must be placed less than 0.25 inch from VTT pins to Ground. 7YV. DDQSTB VDDQ "suspend to memory" regulator output 8NVV DDQI VDDQ supply input to regulator. TT 9C3. .3VC Input Power rail 1D 0P. GOO VDDQ regulator power good indicator 1T 1 BF_CU BF_CUT signal from "Glue" chip. Controls the BF_CUT MOSFET during S3. 1D 2A. GN Analog ground 1C 3, 14N. No Connection 1G 5T. Regulator control for VDDQ output MOSFET 1C 61. 2VC Supply for VDDQ control 1C 7 N. No connection 1N 8S. S/E Soft start/Enable control www.semtech.com  2003 Semtech Corp. 4 SC2615 POWER MANAGEMENT Block Diagram  2003 Semtech Corp. 5 www.semtech.com SC2615 POWER MANAGEMENT Timing Diagram www.semtech.com  2003 Semtech Corp. 6 SC2615 POWER MANAGEMENT Applications Information Description regulator supplies the “Suspend To RAM” current of 650 mA (max) to maintain the information in memory while in The Semtech SC2615 DDR power supply controller is standby mode. Since the Memory read/write cycles are the latest and most complete linear regulator, providing suspended during S3, the VTT termination voltage is not the necessary functions to comply with the BF_CUT signal needed and is tri-stated during S3. Once BF_CUT goes R generated by Intel Motherboards. The BF_CUT input low, signifying S0 mode, the VDDQ supply recovers and signal is generated via an External “Glue Chip” and can takes control of the VDDQ bus. be logically defined as : The memory read-write cycles start after the Silver box POWER_OK signal goes high. The Silver-Box supply BF_CUT=S0 .NAND.P_OK POWER_OK signal goes high when all the voltages are within a tight tolerance of the nominal voltage (typically Where S0 is the “Motherboard Active signal”. When S0 with 1-2%). Thus, the transition from S3 to S0 does not is logic “Low”, the motherboard is in S3 mode. The cause a drop out in VDDQ voltage, since the higher VDDQ Latched BF_CUT signal is the input to the SC2615 currents follow the transition of POWER_OK signal from controller, and is generated by using the S5 signal. All the input Silver Box supply. The External VDDQ MOSFET, references made to BF_CUT are referring to the latched which is capable of supplying the higher current, is signal. activated from the UVLO transition of the Input Rails, which occur much earlier. Thus the External MOSFET will The BF_CUT signal is inverted to externally drive a be activated in time for the Memory’s Active state. Back_Feed_Cut MOSEFT, used to prevent current flow from the VDDQ supply back to the 3.3V supply during S3 Initial Conditions state. VDDQ supply and the VTT termination voltages are supplied to the DDR SDRAM databus during S0 When the S5 and S3 go high (BF_CUT goes low) for the (normal operation) state. During S0, VDDQ is supplied first time, the VDDQ is supplied via the external MOSFET, via the an external pass MOSFET from the 3.3V rail , thus removing the burden of charging the output sourcing high output currents to the VDD bus as well as capacitors via the internal linear VDDQ regulator. supplying the termination supply current. The VTT termination voltage is an internal sink/source Reset/restart linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking The SS/EN pin must be pulled low and high again to restart 1.8 Amps (Min) . The current limit on this pin is set to 3 the SC2615. This can be achieved by cycling the input Amps (typical). The current handling capacity of this pin supplies, 3.3VCC/12VCC. There is a 50mV Hysteresis depends upon the amount of heat the PC board can sink on the UVLO threshold. When the rails are near the UVLO from the SC2615 thermal pad. (See mounting thresholds, it is possible for noise to trigger the UVLO. instructions). The PC board layout must take into Since the reference for the UVLO threshold is derived consideration the high current paths, and ground returns from the 5VSBY voltage, sufficient bypassing of the for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 5VSBY improves noise immunity of the UVLO circuit. 3.3VCC traces must also be routed using wide traces to The Short Circuit Protection function is disabled when minimize power loss and heat in these traces, based on any of the input rails are below their respective UVLO the current handling requirements. thresholds. S3 and S5 States Back-feeding the Input Supply The operation of the VDDQ and VTT supplies is governed When in S3 state, VDDQ is supplied by the internal linear by the internal sequencing logic in strict adherence with regulator. Current can flow back from the VDDQ supply TM Intel specifications with regards to the BF_CUT signal. through the body diode of the Top MOSFET to the 3.3V The timing diagram demonstrates the state of the input supply from the Silver Box, which is off during this controller, and each of the VDDQ and VTT supplies during state. This in turn shorts out the VDDQ bus and is not S3 and S5 transitions. When S3 is low, the VDDQ internal  2003 Semtech Corp. 7 www.semtech.com SC2615 POWER MANAGEMENT Applications Information (Cont.) desirable. A MOSFET in series with the top pass MOSFET (See typical application circuit) must block this reverse current during S3. This MOSFET can be driven from the inverted BF_CUT signal. By removing the gate drive for this series MOSFET, the current path from the VDDQ supply back into the input power source is removed. This MOSFET is enhanced during S0 state. Short Circuit Protection Short Circuit Protection is implemented by sensing the VDDQ voltage. If the SS/EN pin has risen above 1.25V (i.e. the controller has completed the startup cycle), and the output falls to 60% of its nominal voltage, as sensed by the FB pin, the TG pin is latched off and the linear controllers shut down. To recover from this condition, either the power rails have to be recycled, or the SS/EN pin must be pulled low and released to restart controller operation. The short circuit protection function is disabled when any of the input rails are below their respective UVLO thresholds. Thermal Shutdown There are three independent Thermal Shutdown protection circuits in the SC2615, the VDDQ linear regulator the VTT source regulator, and the VTT sink regulator. If any of the three regulators’ temperature rises above the threshold, that regulator will turn off independently, until the temperature falls below the thermal shutdown limit. Power Good An open collector output provides indication that the VDDQ is regulating. This is accomplished by monitoring the SS/EN pin. When the voltage on this pin has risen above 1.0V, the PGOOD goes high (open). When BF_CUT goes high (standby), the 5V and 12V rails go low, and the SS/EN also goes low. Subsequently, PWRGD will also go low, and stays low until the 3.3V and/or 12V rails are recycled and rise above their respective UVLO thresh- olds. www.semtech.com  2003 Semtech Corp. 8 SC2615 POWER MANAGEMENT Typical Characteristics SC2615 DDR controller’s timing : BF_CUT generated from S3 and P_OK Ch1: S3 signal to Silverbox Ch2: Power_OK from Silverbox Ch3: BF_CUT(NOT)=S3.AND.P_OK Ch4: SS/EN SC2615 DDR controller’s timing : VDDQ and VTT vs. BF_CUT Ch3: VTT @ 650 mA Ch1: BF_CUT (NOT) Ch4: PGOOD output Ch2: VDDQ with 2.5V offset, @ 650mA  2003 Semtech Corp. 9 www.semtech.com SC2615 POWER MANAGEMENT Typical Characteristics (Cont.) SC2615 DDR controller’s timing : Power Good vs. SS/EN pin Ch1: BF_CUT (NOT) Ch2: VDDQ with 2.5V offset, @ 650mA Ch3: VTT @ 650 mA Ch4: PGOOD output www.semtech.com  2003 Semtech Corp. 10 SC2615 POWER MANAGEMENT Mounting Considerations Description Solder Mask Design the solder mask around all pads on each side, The MLP18 is a leadless package whose electrical i.e. there should be no solder mask between adjacent connections are made by lands on the bottom surface terminal fingers. of the component. These lands are soldered directly to the PC board. The MLP has an exposed die attach pad, Exposed Pad Stencil Design which enhances the thermal and electrical characteristics enabling high power applications. Power handling capability It is good practice to minimize the presence of voids within of the MLP package is typically >2x the power of other the exposed pad inter-connection. Total elimination is SMT packages. In order to take full advantage of this difficult but the design of the exposed pad stencil is feature the exposed pad must be physically connected important, a single slotted rectangular pattern is to the PCB substrate with solder. recommended. (If large exposed pads are screened with excessive solder, the device may “float”, thus causing a Thermal Pad Via Design gap between the MLP terminal and the PCB land metalization.) The proposed stencil designs enables out- Thermal data (θja) for the MLP18 is based on a 4 layer gassing of the solder paste during reflow as well as PCB incorporating vias which act as the thermal path to controlling the finished solder thickness. other layers. (Ref: Jedec Specification JESD 51-5). Based on thermal performance, four-layer PCB’s with vias are recommended to effectively remove heat from the device. Vias should be 0.3mm diameter on a 1.2mm pitch, and should be plugged to prevent voids being formed between the exposed pad and PCB thermal pad due to solder escaping by capillary action. Plugging can be accomplished by “tenting” the via during the solder mask process. The via solder mask diameter should be 100µm larger than the via diameter. Two layer boards have no vias, thus any heat sinking must be accomplished in the same plane as the metal traces. This will typically require an increase in the PC board area.  2003 Semtech Corp. 11 www.semtech.com SC2615 POWER MANAGEMENT Outline Drawing - MLP-18 www.semtech.com  2003 Semtech Corp. 12 SC2615 POWER MANAGEMENT Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2003 Semtech Corp. 13 www.semtech.com