SEMTECH SC2602

SC2602L Synchronous Voltage Mode Controller for Distributed Power Supply POWER MANAGEMENT Description Features The SC2602L is low-cost, full featured, synchronous volt- ‹ Synchronous operation for high efficiency (95%) age-mode controller designed for use in single ended ‹ R current sensing DS(ON) power supply applications where efficiency is of primary ‹ Output voltage can be programmed as low as 0.8V concern. Synchronous operation allows for the elimina- ‹ On-chip power good and OVP functions tion of heat sinks in many applications. The SC2602L is ‹ Small size with minimum external components ideal for implementing DC/DC converters needed to ‹ Soft Start power advanced microprocessors in low cost systems, ‹ Enable function or in distributed power applications where efficiency is ‹ SO-14 package is fully WEEE and RoHS compliant important. Internal level-shift, high-side drive circuitry, and preset shoot-through control, allows the use of inexpen- Applications sive N-channel power MOSFETs. ‹ Microprocessor core supply SC2602L features include temperature compensated ‹ Low cost synchronous applications voltage reference, triangle wave oscillator and current ‹ Voltage Regulator Modules (VRM) sense comparator circuitry. Power good signaling, shut- ‹ DDR termination supplies down, and over voltage protection are also provided. ‹ Networking power supplies ‹ Sequenced power supplies The SC2602L operates at a fixed 200kHz which is for optimum compromise between efficiency, external com- ponent size, and cost. Two SC2602L can be used together to sequence two voltage regulators for power up in telecom systems. The power good of the first SC2602L connected to the en- able of the second SC2602L makes this possible. Typical Application Circuit V_pullup 5V IN R1 R2 R3 C1 + C3 C2 U1 GND C4 C5 C6 1 14 VCC GND SS/SHDN 2 13 PWRGD SS/SHDN 3 12 PWRGD OVP COMP R4 4 11 R5 C7 OCSET SENSE Q1 5 10 L1 OVP 12V IN PHASE BSTH 6 9 DH BSTL C8 Q2 2.5V OUT D1 7 8 R6 PGND DL SC2602L + C10 C9 R7 GND R8 Figure 1. Typical distributed power supply 1 Revision: January 05, 2006 www.semtech.com SC2602L POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Pl arameter Sm ymbo Ms aximu Unit VV CC, BST L to GND -V 1.0 to 16 (20V Surge) IN PGND to GND ±V 0.5 (1) PHASE to GND -V 0.5 to 18 (20V Surge) BST H to PHASE 1V 6 (20V Surge) T hermal Resistance Junction to Case 4W 5 °C/ θ JC T hermal Resistance Junction to Ambient 1W 15 °C/ θ JA OT perating T emperature Range -C 40 to +85 ° A MT aximum Junction T emperature 1C 25 ° J ST torage T emperature Range -C 65 to +150 ° ST G LT ead T emperature (Soldering) 10 Sec. 3C 00 ° LEAD ED SD Rating (Human Body Model) E2 S kV Note: (1) -1.5V to 20V for 25ns repetitive every cycle. Electrical Characteristics o Unless specified: V = 4.75V to 12.6V; GND = PGND = 0V; V = 12V; V = 12V; T = 25 C CC BSTL BSTH-PHASE J Ps arameter Cn ondition Mp i Tx y Ms a Unit Power Supply SV upply Voltage 46 .2 1V 2. CC SV upply Current EN = 601A m CC LV ine Regulation =5 2.5V 0% . O Error Amplifier TG ransconductance 1S .8 m m Gain (AOL) 5B 0 d Input Bias 58 µA Oscillator Oscillator Frequency 2z 00 kH O0 scillator Max Duty Cycle 959% Internal Ramp Peak to Peak 1V MOSFET Drivers D, H Source/Sink BST H - DH = 4.5V1A DH - PHASE = 2V D. L Source/Sink BST L - DL = 4.5V1A DL - PGND. = 2V www.semtech.com  2005 Semtech Corp. 2 SC2602L POWER MANAGEMENT Electrical Characteristics (Cont.) o Unless specified: V = 4.75V to 12.6V; GND = PGND = 0V; V = 12V; V = 12V; T = 25 C CC BSTL BSTH-PHASE J Ps arameter Cn ondition Mp i Tx y Ms a Unit PROTECTION OVP T hreshold Voltage 2% 0 OV VP Source Current =0 3V1A m OVP P8 ower Good T hreshold 821% 1 D5 ead T ime 401S 0 n OV ver Current Set (Isink) 2< .0 V 1.2 * V BG. 4TO. CSE Set the converter over current trip point 5EP. HAS Input from the phase node between the MOSFET s 6HD. High side driver output 7DP. GN Power ground 8LD. Low side driver output 9LB. ST Bootstrap, low side driver 1H 0B. ST Bootstrap, high side driver 1E 1S. ENS Voltage sense input 1P 2C. OM Compensation pin 1N 3 SS/SHD Gate Drive return Ground for the 1.5V GMCH regulator. Connect to Source of bottom FET . 1D 4G. N Signal ground Note: Note: Note: Note: Note: (1) All logic level inputs and outputs are open collector TTL compatible. www.semtech.com  2005 Semtech Corp. 4 SC2602L POWER MANAGEMENT Block Diagram VCC 200uA Vbg Over Current +10% Under Voltage OCSET -10% PWRGD 0.8V +20% VCC One Shot Oscillator OVP Error Amp SENSE PWM Vbg BSTH DR DRVH VH COMP DH S S Cross VCC 0.8V Current PHASE R R Q QB B Control 10uA SS/SHDN Fault BSTL GND 1.5uA DL DR DRVL VL 0.6V PGND Theory of Operation Synchronous Buck Converter The output rail is regulated by a synchronous, voltage- As SENSE increases, the output voltage of the error mode pulse width modulated (PWM) controller. This amplifier decreases. This causes a reduction in the on- section has all the features required to build a high effi- time of the high-side MOSFET connected to DH, hence ciency synchronous buck converter, including “Power lowering the output voltage. Good” flag, shut-down, and cycle-by-cycle current limit. Under Voltage Lockout The output voltage of the synchronous converter is set The under voltage lockout circuit of the SC2602L as- and controlled by the output of the error amplifier. The sures that the high-side MOSFET driver outputs remain external resistive divider reference voltage is derived from in the off state whenever the supply voltage drops below an internal trimmed-bandgap voltage reference (See Fig. set parameters. Lockout occurs if V falls below 4.1V. CC 1). The inverting input of the error amplifier receives its Normal operation resumes once V rises above 4.2V. CC voltage from the SENSE pin. Over-Voltage Protection The internal oscillator uses an on-chip capacitor and The over-voltage protection pin (OVP) is high only when trimmed precision current sources to set the oscillation the voltage at SENSE is 20% higher than the target value frequency to 200kHz. The triangular output of the oscil- programmed by the external resistor divider. The OVP lator sets the reference voltage at the inverting input of pin is internally connected to a PNP’s collector. the comparator. The non-inverting input of the compara- tor receives it’s input voltage from the error amplifier. Power Good When the oscillator output voltage drops below the er- The power good function is to confirm that the regulator ror amplifier output voltage, the comparator output goes outputs are within +/-10% of the programmed level. high. This pulls DL low, turning off the low-side FET, and PWRGD remains high as long as this condition is met. DH is pulled high, turning on the high-side FET (once PWRGD is connected to an internal open collector NPN the cross-current control allows it). When the oscillator transistor. voltage rises back above the error amplifier output volt- age, the comparator output goes low. This pulls DH low, turning off the high-side FET, and DL is pulled high, turn- ing on the low-side FET (once the cross-current control allows it).  2005 Semtech Corp. 5 www.semtech.com SC2602L POWER MANAGEMENT Applications Information (Cont.) Soft Start Initially, SS/SHDN sources 10µA of current to charge an An over-current condition occurs when the high-side drive external capacitor. The outputs of the error amplifiers is turned on, but the PHASE node does not reach the are clamped to a voltage proportional to the voltage on voltage level set at the OCSET pin. The PHASE node is SS/SHDN. This limits the on-time of the high-side sampled only once per cycle during the valley of the tri- MOSFETs, thus leading to a controlled ramp-up of the angular oscillator. Once an over-current occurs, the high- output voltages. side drive is turned off and the low-side drive turns on and the SS/SHDN pin begins to sink 1.5µA. The soft- R Current Limiting start voltage will begin to decrease as the 1.5µA of cur- DS(ON) The current limit threshold is set by connecting an ex- rent discharges the external capacitor. When the soft- ternal resistor from the V supply to OCSET. The volt- start voltage reaches 0.8V, the SS/SHDN pin will begin CC age drop across this resistor is due to the 200µA inter- to source 10µA and begin to charge the external capaci- nal sink sets the voltage at the pin. This voltage is com- tor causing the soft-start voltage to rise again. Again, pared to the voltage at the PHASE node. This compari- when the soft-start voltage reaches the level of the in- son is made only when the high-side drive is high to ternal oscillator, switching will occur. avoid false current limit triggering due to uncontributing measurements from the MOSFETs off-voltage. When If the over-current condition is no longer present, nor- the voltage at PHASE is less than the voltage at OCSET, mal operation will continue. If the over-current condition an overcurrent condition occurs and the soft start cycle is still present, the SS/SHDN pin will again begin to sink is initiated. The synchronous switch turns off and SS/ 1.5µA. This cycle will continue indefinitely until the over- SHDN starts to sink 1.5µA. When SS/SHDN reaches current condition is removed. 0.8V, it then starts to source 10µA and a new cycle be- gins. In conclusion, below is shown a typical “12V Application Circuit” which has a BSTH voltage derived by Hiccup Mode bootstrapping input voltage to the PHASE node through During power up, the SS/SHDN pin is internally pulled diode D1. This circuit is very useful in cases where only low until VCC reaches the undervoltage lockout level of input power of 12V is available. 4.2V. Once V has reached 4.2V, the SS/SHDN pin is CC released and begins to source 10µA of current to the In order to prevent substrate glitching, a small-signal di- external soft-start capacitor. As the soft-start voltage ode should be placed in close proximity to the chip with rises, the output of the internal error amplifier is clamped cathode connected to PHASE and anode connected to to this voltage. When the error signal reaches the level PGND. of the internal triangular oscillator, which swings from 1V to 2V at a fixed frequency of 200kHz, switching oc- curs. As the error signal crosses over the oscillator sig- nal, the duty cycle of the PWM signal continues to in- crease until the output comes into regulation. If an over- current condition has not occurred the soft-start voltage will continue to rise and level off at about 2.2V. www.semtech.com  2005 Semtech Corp. 6 SC2602L POWER MANAGEMENT Application Circuit Typical 12V Application Circuit with Bootstrapped BSTH +5V 12V IN R2 C1 R3 R1 C2 1.74K 0.1u 10 C4 + C3 D1 5K 1.0u 10u 1N1418 C5 C6 C7 U1 GND 0.1u 0.1u 1.0u 1 14 PWRGD VCC GND SS/SHDN 2 13 C8 1.0u PWRGD SS/SHDN R5 C9 3 12 OVP COMP R4 1K 4 11 9.6K 36n OCSET SENSE Q1 OVP 5 10 L1 4uH PHASE BSTH 6 9 DH BSTL D2 Q2 3.3V OUT 7 8 R6 PGND DL 1N4148 C11 + C10 SC2602L 10u R7 GND R8 2.2  2005 Semtech Corp. 7 www.semtech.com 820u/16V 1200u/6.3V SC2602L POWER MANAGEMENT Typical Characteristics Output Ripple Voltage Ch1: Vo_rpl Gate Drive Waveforms Ch1: Top FET 1. V = 5V; V = 3.3V; I = 12A Ch2: Bottom FET IN O OUT PIN Descriptions Ch1: Vo_rpl Ch1: Top FET 2. V = 5V; V = 1.3V; I = 12A IN OUT OUT Ch2: Bottom FET www.semtech.com  2005 Semtech Corp. 8 SC2602L POWER MANAGEMENT Typical Characteristics (Cont.) Ch1: Vo_rpl Ch1: Top FET 2. V = 5V; V = 1.3V; I = 12A Ch2: Bottom FET IN OUT OUT  2005 Semtech Corp. 9 www.semtech.com SC2602L POWER MANAGEMENT Typical Characteristics (Cont.) Hiccup Mode Ch1: Vin Ch2: Vss Ch3: Top Gate Ch4: Vout Vin = 5V Vout = 3.3V Vbst = 12V Iout = S.C. Iout = S.C. Iout = S.C. Iout = S.C. Iout = S.C. Start Up Mode Ch1: Vin Ch2: Vss Ch3: Top Gate Ch4: Vout Vin = 5V Vout = 3.3V Iout = 2A Vbst = 12V www.semtech.com  2005 Semtech Corp. 10 SC2602L POWER MANAGEMENT The task here is to properly choose the compensation Gpwm network for a nicely shaped loop-gain Bode plot. The L EA following design procedures are recommended to ac- R1 complish the goal: R Rc (1) Calculate the corner frequency of the output filter: Vbg Vin Ro Co C R2 1.25Vdc 0.5Vdc 0.8Vdc 1 F := o 2⋅π⋅ LC ⋅ o Fig. 2. SC2602L small signal model. (2) Calculate the ESR zero frequency of the output filter capacitor: The control model of SC2602L control loop small signal 1 can be depicted in Fig. 2. This model can also be used in F := esr SPICE kind of simulator to generate loop gain Bode plots. 2⋅π⋅R ⋅C c o The bandgap reference is 0.8V and trimmed to +/-1% (3) Check that the ESR zero frequency is not too high. accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. F sw F < esr 5 The error amplifier is transconductance type with fixed If this condition is not met, the compensation structure gain of: may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank . 1.8 mA to correct the output filter corner frequency and the ESR G m V zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner The compensation network includes a resistor and a frequency. It is not recommended to use only high fre- capacitor in series, which terminates from the output of quency multi-layer ceramic capacitors for output filter. the error amplifier to the ground. (4) Choose the loop gain cross over frequency (0 dB This device uses voltage mode control with input volt- frequency). It is recommended that the crossover fre- age feed forward. The peak-to-peak ramp voltage is quency is always less than one fifth of the switching proportional to the input voltage, which results in an ex- frequency : F cellent performance to reject input voltage variation. The sw F ≤ x_over PWM gain is inversion of the ramp amplitude, and this 5 gain is given by: 1 G If the transient specification is not stringent, it is better to pwm V ramp choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The where the ramp amplitude (peak-to-peak) is 1.0 volts resistor in the compensation network can then be cal- when input voltage is 12 volts. culated as: The total control loop-gain can then be derived as 2 F F V follows: 1  esr  x_over o R := ⋅ ⋅ ⋅    G ⋅V ⋅G F F V pwm in m o esr bg . .      1sR C . . 1sR C c o . . Ts () T o . . sR C R L c 2 . . . . . 1s R C s L C 1 c o o when R R o o F < F < F o esr x_over V  bg T := G ⋅G ⋅V ⋅R⋅ o m pwm in  V o    2005 Semtech Corp. 11 www.semtech.com SC2602L POWER MANAGEMENT Step 1. Output filter corner frequency Applications Information (Cont.) or F = 2.516 KHz o 2 F F V 1  o  x_over o Step 2. ESR zero frequency: R := ⋅ ⋅ ⋅    G ⋅V ⋅G F F V pwm in m esr o bg      F = 7.958 KHz esr when Step 3. Check the following condition: F < F < F esr o x_over (5) The compensation capacitor is determined by choos- F sw F < esr ing the compensator zero to be about one fifth of the 5 output filter corner frequency: Which is satisfied in this case. F o F zero 5 Step 4. Choose crossover frequency and calculate compensator R: 1 C . . . 2 π R F zero F = 20 KHz x_over (6) The final step is to generate the Bode plot, either by R4 = .8KΩ using the simulation model in Fig. 2 or using the equa- tions provided here with Mathcad. The phase margin Step 5. Calculate the compensator C: can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. C = 65.886 nF (7) An additional capacitor should be reserved at the compensation pin to ground to have another high fre- Step 6. Generate Bode plot and check the phase mar- quency pole. o gin. In this case, the phase margin is about 85 C that An example is given below to demonstrate the proce- ensures the loop stability. dure introduced above. The parameters of the power supply are given as : The parameters of the power supply are given as : . V 12 V in . V 3.3 V o . I 12 A o . F 200 KHz sw . L4 µH . C 1200 µF o . R 0.02 Ω c . V 0.8 V bg . V 1V ramp . 1.8 mA G m V www.semtech.com  2005 Semtech Corp. 12 SC2602L POWER MANAGEMENT Applications Information (Cont.) Loop Gain Mag (dB) 100 50 mag() i 0 50 3 . 0.01 0.1 1 10 100 1 10 F i kHz Loop Gain Phase (Degree) 0 45 phase() i 90 135 180 3 . 0.01 0.1 1 10 100 1 10 F i kHz Bode plot of the control loop  2005 Semtech Corp. 13 www.semtech.com SC2602L POWER MANAGEMENT Outline Drawing - S0-14 DIMENSIONS INCHES MILLIMETERS A DIM MIN NOM MAX MIN NOM MAX D e - - A .053 .069 1.35 1.75 N A1 .004 - .010 0.10 - 0.25 A2 .049 - .065 1.25 - 1.65 2X E/2 b .012 - .020 0.31 - 0.51 - - c .007 .010 0.17 0.25 D .337 .341 .344 8.55 8.65 8.75 E1 E E1 .150 .154 .157 3.80 3.90 4.00 E .236 BSC 6.00 BSC e .050 BSC 1.27 BSC - - h .010 .020 0.25 0.50 12 3 ccc C L .016 .028 .041 0.40 0.72 1.04 B L1 (.041) (1.04) 2X N/2 TIPS N 14 14 - - 01 0° 8° 0° 8° aaa .004 0.10 bbb .010 0.25 D ccc .008 0.20 aaa C A2 A h SEATING PLANE h C A1 H bxN bbb C A-B D c GAGE PLANE 0.25 L 01 (L1) SEE DETAIL A DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AN -A- D T -B- O BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AB. Land Pattern - S0-14 X DIMENSIONS DIM INCHES MILLIMETERS C (.205) (5.20) G .118 3.00 (C) G Z P .050 1.27 X .024 0.60 Y .087 2.20 Y Z .291 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 302A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2005 Semtech Corp. 14