SEMTECH SC2596

SC2596 Low Voltage Integrated DDR Termination Regulator POWER MANAGEMENT Description Features The SC2596 is an integrated linear DDR termination ‹ Sourcing or sinking 2.5A for DDR-I device, which provides a complete solution for DDR ‹ Sourcing or sinking 1.5A for DDR-II termination regulator designs; while meeting the JEDEC ‹ AV undervoltage lockout CC ‹ Reference output requirements of SSTL-2 and SSTL-18 specifications for DDR-SDRAM termination. ‹ Minimum number of external components ‹ Accurate internal voltage divider The SC2596 regulates up to +/- 2.5A for DDR-I and +/- ‹ Disable function, puts device into sleep mode 1.5A for DDR-II application requirements. ‹ Thermal shutdown ‹ Over current protection V is regulated to track the V voltage over the entire ‹ Available in SOIC8-EDP package TT REF current range with shoot through protection. ‹ Pb-free, Halogen free, and RoHS/WEEE compliant A V pin is incorporated to provide excellent load SENSE regulation, along with a buffered reference voltage for internal use. Applications ‹ DDR-I and DDR-II memory termination The SC2596 also features a disable function which is to ‹ SSTL-2 and SSTL-3 termination tri-state the output during Suspend To Ram (STR) states ‹ HSTL termination by pulling the EN pin low. ‹ PC motherboards ‹ Graphics boards ‹ Disk drives ‹ CD-ROM drives Typical Application Circuit AVCC SC2596 EN VTT EN VTT VDDQ VDDQ VSENSE VREF PVCC VREF 0 Septenber 24, 2009 1 www.semtech.com GND AVCC SC2596 POWER MANAGEMENT PRELIMINARY Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pr P PPr a a a ar r r ra a a am m m me e e et t t te e e er r SSlSm Sl y y y ym m m mb b b bo o o oll MMm MmMs a a a ax x x xiiiim m m mu u u um UUs Us Un n n niiiit t t ts Parameter Symbol Maximum Units PVCC, AVCC, VDDQ, EN to GND -V 0.3 to +6.0 O Thermal Resistance Junction to Case θ 5.5 C/W JC O Thermal Resistance Junction to Ambient θ 36.5 C/W JA O MT aximum Junction Temperature Range -40 to +125 C J O ST torage Temperature Range -65 to +150 C STG O PT eak IR Reflow Temperature 10-40S 260 C PKG ED SD Rating (Human Body Model) E2 S kV Electrical Characteristics (DDR-I) o o Unless otherwise specified: T = -40 C to +125 C, AV = PV = 2.5V, V = 2.5V. J CC CC DDQ P PPr PrPl a a a a ar r r r ra a a a am m m m me e e e et t t t te e e e er r r S SSl SlSs y y y y ym m m m mb b b b bo o o o oll TTs TTsTn e e e e es s s s st t t t t C C C C Co o o o on n n n nd d d d diiiiit t t t tiiiiio o o o on n n n ns s M M MnMp Mn iiiiin n Tp T TTx Tp y y y y yp p Mx M MMs Mx a a a a ax x U UUs Us Un n n n niiiiit t t t ts s RV eference Voltage I=Q 0mA0Q .49VDD0Q .5VDD0V .51VDD REF REF_OUT VOZ utput Impedance I=0 -30uA to +30uA 23 Ω REF VREF REF (1) VTT Output Regulation I = 0A OUT (V - V ) I = -1.5A -0 25 +V 25 m TT REF OUT I = +1.5A OUT QI uiescent Current I=0 0A 40 0 7A 0 u Q LOAD AV Enable Threshold 22 .1 2V . CC VZ DDQ Input Impedance 1k 00 Ω VDDQ QI uiescent Current in Shutdown E0 N = 0 10 5 2A 5 u SD EI N Pin Leakage Current E1 N = 0 uA Q_SD EH N Threshold Voltage V 2 V VL 0.8 VTT Leakage Current in I SD = 0V, VTT = 1.25V, 6A u VTT_L O Shutdown at 25 C © 2009 Semtech Corp. 2 www.semtech.com SC2596 POWER MANAGEMENT Electrical Characteristics (DDR-I Cont.) o o Unless otherwise specified: T = -40 C to +125 C, AV = PV = 2.5V, V = 2.5V. J CC CC DDQ Pr P PPl Pr a a a a ar r r r ra a a a am m m m me e e e et t t t te e e e er r r Sl S SSs Sl y y y y ym m m m mb b b b bo o o o oll T TTs TsTn e e e e es s s s st t t t t C C C C Co o o o on n n n nd d d d diiiiit t t t tiiiiio o o o on n n n ns s M M Mn MnMp iiiiin n T TTp TpTx y y y y yp p M MMx MxMs a a a a ax x U UUs Us Un n n n niiiiit t t t ts s VSENSE Current 50 0 2A 0 n I SENSE O TT hermal Shutdown 160 C SD O TT hermal Shutdown Hysteresis 10 C SD_HYS o Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, T = 25 C) A Electrical Characteristics (DDR-II) o o Unless otherwise specified: T = -40 C to +125 C, AV = 3.3V, PV = V = 1.8V. J CC CC DDQ P PPr PrPl a a a a ar r r r ra a a a am m m m me e e e et t t t te e e e er r r S SSl SlSs y y y y ym m m m mb b b b bo o o o oll TTs TTsTn e e e e es s s s st t t t t C C C C Co o o o on n n n nd d d d diiiiit t t t tiiiiio o o o on n n n ns s M M MnMp Mn iiiiin n Tp T TTx Tp y y y y yp p Mx M MMs Mx a a a a ax x U UUs Us Un n n n niiiiit t t t ts s RV eference Voltage I=Q 0mA0Q .49VDD0Q .5VDD0V .51VDD REF REF_OUT VOZ utput Impedance I=0 -30uA to +30uA 23 Ω REF VREF REF (1) VTT Output Regulation I = 0A OUT (V - V ) I = -1.0A -0 25 +V 25 m TT REF OUT I = +1.0A OUT QI uiescent Current I=0 0A 40 0 7A 0 u Q LOAD AV Enable Threshold 22 .1 2V . CC VZ DDQ Input Impedance 1k 00 Ω VDDQ QI uiescent Current in Shutdown E0 N = 0 10 5 2A 5 u SD EI N Pin Leakage Current E5 N = 0 0A . u Q_SD EH N Threshold Voltage V 2 V VL 0.8 VTT Leakage Current in I SD = 0V, VTT = 0.9V, 6A u VTT_L O Shutdown at 25 C VSENSE Current 50 0 2A 0 n I SENSE O TT hermal Shutdown 160 C SD O TT hermal Shutdown Hysteresis 10 C SD_HYS o Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, T = 25 C) A © 2009 Semtech Corp. 3 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Waveforms AVCC AVCC AVC AVCC C VDD VDDQ Q////P PVC VCC C VD VDDQ DQ//PVC //PVCC C VR VREF EF Vr Vreeff VT VTT T VT VTT T Start up. Shut down. AV AVCC CC AVCC AVCC PVCC PVCC PVC PVCC C EN EN EN EN VTT VTT VTT VTT Shut down by EN. Start up by EN. AV AVCC CC AVC AVCC C PV PVCC CC//VD //VDD DQ Q PV PVCC CC VTT VTT VTT VTT IO IO IO IO 1A load Transient with +/- 1A load © 2009 Semtech Corp. 4 www.semtech.com SC2596 POWER MANAGEMENT Waveforms 4.0 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 22.5 33.544.5 55.5 22.5 3 3.544.5 55.5 AV CC (V ) AV CC (V ) Maximum Sourcing Current vs AVCC. Maximum Sinking Current vs AVCC. (VDDQ=1.8V, PVCC=2.5V) (VDDQ=1.8V, PVCC=2.5V) 3.0 4.0 2.5 3.5 2.0 3.0 1.5 2.5 2.0 1.0 22.5 33.544.5 55.5 22.5 33.5 44.5 55.5 AV C C (V) A V CC ( V ) Maximum Sinking Current vs AVCC. Maximum Sourcing Current vs AVCC. (VDDQ=1.8V, PVCC=1.8V) (VDDQ=1.8V, PVCC=1.8V) © 2009 Semtech Corp. 5 www.semtech.com Output Current (A) Output Current (A) Output Current (A) Output Current (A) SC2596 POWER MANAGEMENT PRELIMINARY Pin Configuration Ordering Information (3) Part Number Package Temp. Range (T ) A TOP VIEW (1) O SC2596SETRT SOIC8-EDP -40 to +105 C (2) SC2596EVB Evaluation Board VTT GND 1 8 Notes: EN 2 7 PVCC (1) Only available in tape and reel packaging. A reel contains 2500 devices for SOIC8-EDP. VSENSE 3 6 AVCC (2) EVB provided with SOIC8-EDP package. VREF 4 5 VDDQ (3) Pb-free, Halogen free, and RoHS/WEEE compliant. (SOIC8-EDP) © 2009 Semtech Corp. 6 www.semtech.com SC2596 POWER MANAGEMENT Pin Descriptions P PP# P#Pe iiiiin n n n n # # # P PPePn Pe iiiiin n n n n N N N N Na a a a am m m m me e Pn P PPn Piiiiin n n n n F F F F Fu u u u un n n n nc c c c ct t t t tiiiiio o o o on n 1DG. N Ground 2NE. Enable pin. SC2596 is disabled when EN pin is low 3E VSENS VSENSE pin is a feedback pin. Connect a 10nF to 100nF Ceramic capacitor between this pin to ground and place this capacitor close to VSENSE pin is required to avoid oscillation during transient condition. 4F VRE VREF pin is an output pin, which provides the buffered output of the internal reference voltage. A 100nF ceramic capacitor should be connected from VREF pin to ground with short trace. 5Q VDD The VDDQ pin is an input pin for creating internal reference voltage to regulate VTT. The VDDQ voltage is connected to an internal resistor divider. The central tap of resistor divider (VDDQ/2) is connected to the internal voltage buffer, which output is connected to VREF pin and the non-inverting input of the error amplifier as the reference voltage. With the feedback loop closed, the V TT output voltage will always track the VDDQ/2 precisely. It is recommended that a 1uF ceramic capacitor should be added next to the VDDQ pin to ground to increase the noise immunity. 6C AVC The AVCC pin is used to supply all of the internal control circuitry. The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2596 to be in normal operation. If AVCC voltage is lower than the UVLO threshold voltage, the VTT pin should be in high impedance status. 7C PVC The PVCC pin provides the rail voltage from where the VTT pin draws load current. There is a limitation between AVCC and PVCC. The PVCC voltage must be less or equal to AVCC voltage to ensure the correct output voltage regulation. The VTT source current capability is dependent on PVCC voltage. Higher the voltage on PVCC, higher the source current. 8T VT The VTT pin is the output of SC2596. It can sink and source continuous current while keeping excellent load regulation. It is recommended that one should use at least one 220uF low ESR capacitor and a 1uF ceramic capacitor or one 220uF high ESR electrolytic capacitor and a 6.8uF ceramic capacitor, which are placed on the VTT strip plane to ground reducing the voltage spike under load transient condition. THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias. PAD Not connected internally. © 2009 Semtech Corp. 7 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Block Diagram EN AVCC PVCC Anti- UVLO + VDDQ Shoot- Thermal thru Shutdown VTT + + Driver - Circuit Vref Buffer Error Am p. GND VREF Vsense Description Description Description Description Description ERROR AMP ERROR AMP ERROR AMP ERROR AMP ERROR AMP SC2596 is a low-voltage, low-dropout DDR termination Low input offset op-amp for the main linear regulator. It regulator with separate power supply to support both controls the VTT output voltage and which side of the DDR1 and DDR2 applications. AVCC and PVCC can be MOSFET to turn on (or turn off) to achieve zero shoot tied together for DDR1 and can also be separated for through current. DDR2. ANTI-Shoot Thought Driver ANTI-Shoot Thought Driver ANTI-Shoot Thought Driver ANTI-Shoot Thought Driver ANTI-Shoot Thought Driver SC2596 regulates VTT to the voltage of VREF. VTT will sink or source upto 2.5A. Internal shoot-through protec- Buffer stage takes the error voltage to control MOSFET. tion ensure both top and bottom MOSFET will not con- Internal current limit is incorporated to protect from duct while maintaining fast source-to-sink load transient. shorted load. Thermal shut-down and internal current limit protect SC2596 from shorted load or over-heated THERMAL SHUTDOWN & UVLO THERMAL SHUTDOWN & UVLO THERMAL SHUTDOWN & UVLO THERMAL SHUTDOWN & UVLO THERMAL SHUTDOWN & UVLO VREF BUFF VREF BUFF VREF BUFF VREF BUFF VREF BUFF The Thermal shutdown block prevent the junction tem- VREF is derived from VDDQ with an accurate divide by o perature exceed 165 C. UVLO circuit to ensure proper op-amps(VREF Buffer). It is capable to sink and source power is available for correct operation of the IC. 30uA. It is used as the reference voltage to the Error amp. A 100nF or higher capacitor is recommended for VREF pin to ground; To enhance the noise immunity from board, an additional pull-down resistor (1MΩ) is recomanded as well from VREF pin to ground. © 2009 Semtech Corp. 8 www.semtech.com + - SC2596 POWER MANAGEMENT Application Information Overview cause a large trace inductance and trace resistance. Consider the load transient condition, a fast load cur- Double Data Rate (DDR) SDRAM was defined by JEDEC rent going through VTT strip plane will create a voltage 1997. Its clock speed is the same as previous SDRAM spike on VTT plane and a DC voltage drop for load cur- but data transfer speed is twice than previous SDRAM. rent. It is recommanded the VSENSE pin should be con- By now, the requirement voltage range is changed from nected center of VTT plane to improve regulation and 3.3V to 2.5V or 1.8V; the power dissipation is smaller transient response. than SDRAM. For above reasons, it is very popular and widely used in M/B, N/B, Video-cards, CD ROM drives, A longer trace of VSENSE may pick up noise and cause Disk drives. the error of load regulation. Hence designer should avoid a longer trace between VSENSE to VTT plane. A 100nF Regarding the DDR power management solution, there ceramic capacitor close to VSENSE pin is required. are two topologies can be selected for system design- ers. One is switching mode regulator that has bigger sink/ VREF source current capability, but the cost is higher and needs more board space. Another solution is linear mode regu- VREF pin is an output pin to provid internal reference lator, which costs less, and needs less board space. For voltage. System designer can use the voltage for two DIMM motherboards, system designers usually Northbridge chipset and memory. It is necessary to add choose the linear mode regulator for DDR power man- a ceramic capacitor (100nF) from VREF pin to ground agement solution. with shortest trace. Thermal shutdown Typical Application Circuits & Waveforms The SC2596 has built-in thermal detected circuit to pre- Four different application circuits are shown below in Fig- vent this device from over temperature and damage. ure 1, Figure 2, Figure 3 and Figure 4. Each circuit is The SC2596 goes into shunt down mode when tem- designed for a specific condition. See Note a. and b. O perature is higher than 165 C. The protection condition below for recommended power up sequencing. will release when the temperature of device drop down O by 10 C. Application_1: Standard SSTL-2 Application AVCC and PVCC The AVCC pin, PVCC pin and the V pin can be tied DDQ together for SSTL-2 application (Figure 1). It only needs AVCC and PVCC are the input supply pins for the SC2596. a 2.5V power rail for normal operation. System designer AVCC is supply voltage for all the internal control circuitry. can save the PCB space and reduce the cost. The AVCC voltage has to be greater than its UVLO thresh- old voltage (2.1V typical) to allow the SC2596 to be nor- VDDQ/EN=2.5V mal operation. S SC C2596 2596 VTT/1.25V 1 8 The PVCC pin provides the rail voltage from where the GND VTT VTT pin draws load current. There is a limitation between 2 7 EN PVCC AVCC and PVCC. The PVCC voltage must be less or equal 3 6 VSENSE AVCC to AVCC voltage to ensure the correct VTT output voltage VREF/1.25V regulation. 4 5 VREF VDDQ Csen Csense se CREF CREF CIN1 CIN1 CIN2 CIN2 COUT COUT VSENSE 100nF 100nF 100nF 100nF 1uF 1uF 100u 100uF F 220u 220uF F VSENSE pin is a feedback pin from VTT plane. VTT plane 0 is always a narrow and long strip plane in most montherboard applications. This long strip plane will Figure 1: Standard SSTL-2 application. © 2009 Semtech Corp. 9 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Application Information (Cont.) Application_2: Lower Power Loss Configuration for Application_4: High Source Current Configuration SSTL-2 If power loss is a major concern, separating the PVCC If there is a need for VTT to source more current, espe- form AVCC and VDDQ will be a good choice (Figure 2). cially for DDR-II applications, the system designer can tie The PVCC can operate at lower voltage (1.8V to 2.5V) if the AVCC and PVCC to 3.3V while has the VDDQ tie to 2.5V voltage is applied on AVCC and the VDDQ, the source 1.8V. This configuration can ensure more than 2A source current is lower due to the lower operating voltage ap- and sink capability from the VTT rail. plied on the PVCC. SC SC2596 2596 S SC C2596 2596 VTT/0.9V VTT/1.25V 1 8 1 8 GND VTT GND VTT EN AVCC/PVCC=3.3V EN/2.5V PVCC=2.5V 2 7 2 7 EN PVCC EN PVCC VDDQ/AVCC=2.5V 3 6 3 6 VSENSE AVCC VSENSE AVCC VREF/1.25V VREF/0.9V VDDQ=1.8V 4 5 4 5 VREF VDDQ VREF VDDQ CIN2 CIN2 CO COUT UT COUT COUT CI CIN2 N2 COUT COUT Csen Csense se CREF CREF CIN1 CIN1 Csen Csense se CREF CREF CIN1 CIN1 100nF 100nF 100nF 100nF 100nF 100nF 1M 1M 100nF 100nF 1u 1uF F 1M 1M 1u 1uF F 100u 100uF F 10u 10uF F 220u 220uF F 100u 100uF F 220u 220uF F 0 0 Figure 4: High current set up for SSTL-18(DDR-II). Figure 2: Lower power loss for SSTL-2(DDR-I). Application_5: All Ceramic Capacitor Configuration Application_3: Low Power Loss Configuration for SSTL-18(DDR-II) For some pure ceramic output capacitor designs, one If power loss is a major concern, setting the PVCC to be needs to add small ESR in series with the output capaci- 2.5V will be a good choice (Figure 3). The PVCC can op- erate at lower voltage. if 2.5V voltage is applied on AVCC tor in order to enhance stability margin. For example, an 100mohm external ESR is suggested to help improve and PVCC, the source current is lower due to the lower the phase margin for the circuit in Figure 5. Figure 6 operating voltage applied on the PVCC. shows the corresponding Bode plot. S SC C2596 2596 VTT/0.9V SC2596 SC2596 1 8 VTT/0.9V GND VTT 1 8 GND VTT EN AVCC/PVCC=2.5V EN 2 7 VDDQ/PVCC=1.8V EN PVCC 2 7 EN PVCC CO COUT UT 3 6 AVCC=3.3V VSENSE AVCC 3 6 VSENSE AVCC 10uF 10uF VREF/0.9V VDDQ=1.8V VREF/0.9V 4 5 VREF VDDQ 4 5 VREF VDDQ CIN2 CIN2 CIN3 CIN3 Ex Exter ternal nal R R CIN2 CIN2 COUT COUT CIN1 CIN1 Csen Csense se CREF CREF CIN1 CIN1 Csen Csense se CRE CREF F 100mO 100mOh hm m 100nF 100nF 100nF 100nF 1M 1M 1u 1uF F 100u 100uF F 220u 220uF F 1M 1M 100nF 100nF 1uF 1uF 1uF 1uF 100nF 100nF 10uF 10uF 0 0 Figure 5: All ceramic capacitor configuration. Figure 3: Lower power loss for SSTL-18(DDR-II). Notes: (a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V. (b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC. © 2009 Semtech Corp. 10 www.semtech.com SC2596 POWER MANAGEMENT Application Information (Cont.) Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5. Figure 6: Bode Plot of an all ceramic capacitor application The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V, IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase margins for different output capacitor values and ESR values at designed sourcing and sinking currents in Figure 7. Phase Margin vs External ESR IO=380mA_SINK IO=380mA_Soure 90.00 120.00 80.00 100.00 70.00 80.00 60.00 Cout=4.7uF Cout=4.7uF 60.00 50.00 Cout=10uF 40.00 Cout=10uF 40.00 20.00 30.00 Cout=22uF Cout=22uF 0.00 20.00 10.00 -20.00 0.00 -40.00 10mR 50mR 100mR 200mohm 10mR 50mR 100mR 200mohm Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values Layout guidelines 1) The SOIC8-EDP package of SC2596 can improve the thermal impedance (θ ) significantly. A suitable thermal JC pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern. 2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the V pin with the REF shortest connection trace. 3) To reduce the noise on input power rail for standard SSTL-2 application, a 100µF low ESR capacitor and a 1µF ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection. 4) VTT output copper plane should be as large as possible. A 4.7uF to 10µF capacitor have to be used to decouple the VTT pin. 5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor close this vsense pin. © 2009 Semtech Corp. 11 www.semtech.com Phase Magnitude Phase Magnitude SC2596 POWER MANAGEMENT PRELIMINARY Typical Application Circuit VDDQ 1.8V U1 SC2596 1 8 VTT GND VTT 0.9V EN 2 7 EN PVCC 3.3V 3 6 VSENSE AVCC 4 5 VREF VDDQ VREF R1 C1 C2 C7 0.9V C4 C5 C3 C6 1uF 1uF 1M 0 DDR-II VTT Solution Bill of Material R RRf RfRy e e e e ef f f Q QQy QyQe t t t t ty y Re R RRe Re e e e e ef f f f fe e e e er r r r re e e e en n n n nc c c c ce e PPe PPr Pe a a a a ar r r r rt t t t t N N N N Nu u u u um m m m mb b b b be e e e er r r r r/ / / / /V V V V Va a a a alllllu u u u ue e M MMr Mr Ma a a a an n n n nu u u u uf f f f fa a a a ac c c c ct t t t tu u u u ur r r r re e e e er r 11C3 1 1o 00nF, 25V, X5R,Ceramic, 060 Yage 21C3 2 1o 0nF, 16V, X5R, Ceramic , 060 Yage 31C3 3 1o uF, 16V, X5R, Ceramic , 060 Yage 41C3 6 1o uF, 16V, X5R, Ceramic , 060 Yage 51C3 7 1o uF, 16V, X5R, Ceramic , 060 Yage 61Cm 4 1o 00uF, 6.3V, Aluminu Yage 71Cm 5 2n 20uF, 6.3V, Aluminu Rubyco 81RM 1 1o M OH Yage 91U6 1 Sh C259 Semtec © 2009 Semtech Corp. 12 www.semtech.com 100nF 10nF 100uF 220uF 1uF SC2596 POWER MANAGEMENT Outline Drawing - SOIC8-EDP © 2009 Semtech Corp. 13 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Land Pattern - SOIC8-EDP Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2009 Semtech Corp. 14 www.semtech.com