SEMTECH SC2595

SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination ‹ Regulates while sourcing or sinking 1.5A device, which provides a complete solution for DDR ‹ AV range is from 2.5V to 5V CC termination designs; while meeting the JEDEC require- ‹ Reference output ments of SSTL-2 specifications for DDR-SDRAM termi- ‹ Minimum number of external components nation. ‹ Accurate internal voltage divider ‹ SOIC8-EDP package.Pb-free,Halogen free, and RoHS/ The SC2595 can source and sink 1.5A current at the WEEE compliant output V while maintaining excellent load regulation. TT Applications V is designed to track the V voltage with a tight ‹ DDR memory termination TT REF tolerance over the entire current range while preventing ‹ High speed data line termination shoot through on the output stage. ‹ PC motherboards ‹ Graphics boards A V pin is incorporated to provide excellent load SENSE ‹ Disk drives regulation, along with a buffered reference voltage. ‹ CD-ROM drives The SC2595 incorporates a disable function built into the AV pin to tri-state the output during Suspend To CC Ram (STR) states. (Multiple patents pending.) Typical Application Circuit VDD SC2595 1 8 VTT NC VTT 2 7 GND PVCC 3 6 VSENSE AVCC 4 5 VREF VREF VDDQ September 24, 2009 1 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pr P P PPr a a a a ar r r r ra a a a am m m m me e e e et t t t te e e e er r r S SSlSm Sl y y y y ym m m m mb b b b bo o o o olll M MMm MmMs a a a a ax x x x xiiiiim m m m mu u u u um m U UUs Us Un n n n niiiiit t t t ts s PV VCC, AVCC, VDDQ to GND -V 0.3 to +6.0 CC Thermal Resistance Junction to Case θ °C/W SOIC8-EDP 5.5 JC Thermal Resistance Junction to Ambient θ °C/W JA SOIC8-EDP 36.5 OT perating Temperature Range -C 40 to +105 ° A OT perating Junction Temperature Range -C 40 to +150 ° J ST torage Temperature Range -C 65 to +150 ° STG PT eak IR Reflow Temperature 10 - 40s 2C 40 ° LEAD PT eak IR Reflow Temperature 10 - 40s 2C 60 ° LEAD ED SD Rating (Human Body Model) E2 S KV Operating Range Pr P PPr a a a ar r r ra a a am m m me e e et t t te e e er r SSlSm Sl y y y ym m m mb b b bo o o oll MMm MmMs a a a ax x x xiiiim m m mu u u um UUs Us Un n n niiiit t t ts Parameter Symbol Maximum Units JT unction Temperature Range -C 40 to +150 ° J AV VCC to GND A 2V .3 to 5.5 CC PV VCC to GND P 2V .3 to A V CC CC Electrical Characteristics o Specifications with standard typeface are for T = 25 C and limits in boldface type apply over the full Operating Temperature Range J o o (T = -40 C to +150 C). Unless otherwise specified, AV = PV = 2.5V, V = 2.5V. J CC CC DDQ Pr P PPl Pr a a a a ar r r r ra a a a am m m m me e e e et t t t te e e e er r r Sl S SSs Sl y y y y ym m m m mb b b b bo o o o oll T TTs TsTn e e e e es s s s st t t t t C C C C Co o o o on n n n nd d d d diiiiit t t t tiiiiio o o o on n n n ns s M M Mn MnMp iiiiin n T TTp TpTx y y y y yp p M MMx MxMs a a a a ax x U UUs Us Un n n n niiiiit t t t ts s RV eference Voltage I=2 0mA VDDQ/12 .25 VDDQ/ V REF REF_OUT - 40mV + 40mV (1) Load Regulation REG I : 0 to +1.5A -0.5 % LOAD LOAD I : 0 to -1.5A +0.5 LOAD VS TT Output Voltage Offset VO I =0A, V - V -0 20 +V 20 m VTT OUT TT REF QI uiescent Current I=0 0A 4A 0 μ Q LOAD AVCC Enable Threshold 2V .1 VZ DDQ Input Impedance 1k 00 Ω VDDQ Note: Note: Note: Note: Note: (1) For Load Regulation, use a 10ms current pulse width when measuring V . TT ©2009 Semtech Corp. 2 www.semtech.com SC2595 POWER MANAGEMENT Pin Configuration Ordering Information Part Number Package Temp. Range (T ) A TOP VIEW (1)(2) O SC2595STRT SOIC8-EDP -40 to +105 C SC2595EVB Evaluation Board VTT NC 1 8 Notes: (1) Only available in tape and reel packaging. A reel contains GND 2 7 PVCC 2500 devices for SOIC8-EDP package. (2) Pb-free,Halogen free, and RoHS and WEEE compliant. VSENSE 3 6 AVCC VREF 4 5 VDDQ (SOIC8-EDP) ©2009 Semtech Corp. 3 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Pin Descriptions S SSP SP SO O O O OIIIIIC C C C C-----8 8 8 8 8L L L L L E E E E ED D D D DP P P P PPe PePn iiiiin n n n n N N N N Na a a a am m m m me e e Pn P P PPn iiiiin n n n n F F F F Fu u u u un n n n nc c c c ct t t t tiiiiio o o o on n P PP# P# Piiiiin n n n n # # # (1) 1CN. No internal connection 2DG. N Ground 3EVV SENS is a feedback pin. V plane is always a narrow and long strip plane in most SENSE TT motherboard applications. This long strip plane will cause a large trace inductance and trace resistance. Consider the load transient condition; a fast load current going through V strip plane can create voltage spikes on the V TT TT plane. The load current can also cause a DC voltage drop on the V plane. It is TT recommended that V should be connected to the center of V plane to SENSE TT improve the load regulation and the noise immunity. In case that one can't connect the V pin to the center of the V plane, one should connect it to the SENSE TT SC2595 V pin directly. A longer trace of V may pick up noise and cause the TT SENSE error of load regulation; hence the longer trace must be avoided. A 10nF to 100nF ceramic capacitor close to the V pin is required to avoid SENSE oscillation during transient condition. 4FVV RE is an output pin, which provides the buffered output of the internal reference REF voltage. System designer can use the V output voltage for Northbridge chipset REF and memory. Because these input pins are typically high impedance, there should be a small amount of current drawn from the V pin [figure 9, 10]. To REF improve the noise immunity, a ceramic capacitor (10nF - 100nF) should be added from the V pin to ground with short distance. REF (2) 5Q VDD The V pin is an input for creating internal reference voltage to regulate V The DDQ TT. V voltage is connected to internal 100Kohm resistor divider. The central tap DDQ of resistor divider (V /2) is connected to the internal voltage buffer, which DDQ output is connected to V pin and the non-inverting input of the error amplifier REF as the reference voltage. With the feedback loop closed, the V output voltage TT will always track the V /2 precisely. It is recommended to use 5.1 ohm + a DDQ 1uF ceramic capacitor for V pin's filter to increase the noise immunity. DDQ (2) 6C AVC The AV pin is used to supply all of the internal control circuitry. AV voltage CC CC has to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2595 be in normal operation. If AV voltage is lower than the UVLO threshold CC voltage, the V output voltage will remain at 0V. TT (2) 7C PVC The PV pin provides the rail voltage from where the V pin draws load current. CC TT There is a limitation between AV and PV . The PV voltage must be less or CC CC CC equal to AV voltage to ensure the correct output voltage regulation. The V CC TT source current capability is dependent on PV voltage. Higher the voltage on CC PV , higher the source current; however, it will cause more power loss and higher CC temperature rise [figure 5, 11, 12]. 8TVV T The pin is the output of SC2595. It can sink and source 1.5A continuous TT current and 3A peak current while keeping excellent load regulation. It is recommended that one should use at least 220uF low ESR capacitors (ESR should be lower than 250m ohm) and 10uF ceramic capacitors, which are uniformly spread on the V strip plane to reduce the voltage spike under load TT transient condition. Thermal Thermal pad should be connected to GND. Pad ©2009 Semtech Corp. 4 www.semtech.com SC2595 POWER MANAGEMENT Notes: Notes: Notes: Notes: Notes: (1) Can be used for vias. (2) Power up of AV , PV and V supplies. CC CC DDQ (a) The preferred mode of operation is when the AV , PV and V pins are tied together to a single supply. CC CC DDQ (b) If and when AV , PV pins are tied to a supply separate to that of the V supply pin; then the V supply should CC CC DDQ DDQ lead AV , PV supply or the V supply and the AV , PV supply should rise simultaneously. CC CC DDQ CC CC (c) If the AV , PV and V supply pins are connected in a way such that, AV , PV supplies precedes V supply; CC CC DDQ CC CC DDQ then V output precedes V . This can cause the SDRAM device to latch-up, which may cause permanent TT DDQ damage to the SDRAM. Block Diagram AVCC PVCC UVLO VDDQ - OUT + Driver + OUT VTT Circuit - VREF GND VSENSE NC ©2009 Semtech Corp. 5 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Application Information Overview Overview Overview Overview Overview Application_2: Lower Power Loss Configuration Application_2: Lower Power Loss Configuration Application_2: Lower Power Loss Configuration Application_2: Lower Power Loss Configuration Application_2: Lower Power Loss Configuration f f f f for SS or SS or SS or SS or SSTL TL TL TL TL-2 -2 -2 -2 -2 Double Data Rate (DDR) SDRAM was defined by JEDEC If power loss is a major concern, separated the PV form 1997. Its clock speed is the same as previous SDRAM CC but data transfers speed is twice than previous SDRAM. the AV and the V will be a good choice. The PV can CC DDQ CC By now, the requirement voltage range is changed from operate at lower voltage (1.8V to 2.5V). If 2.5V voltage 3.3V to 2.5V; the power dissipation is smaller than is applied on AV and the V , but the source current is CC DDQ lower due to the lower operating voltage applied on the SDRAM. For above reasons, it is very popular and widely PV . Please find the relative test result in Figures 5, 11 used in M/B, N/B, Video-cards, CD ROM drives, Disk CC drives. and 12. Regarding the DDR power management solution, there SC2595 are two topologies can be selected for system design- 1 8 NC VTT VTT 1.8V to 2.5V ers. One is switching mode regulator that has bigger sink/ 2 7 1.25V GND PVCC 2.5V VDD Vin source current capability, but the cost is higher and the 3 6 VSENSE AVCC board space needed is bigger. Another solution is linear 4 5 VREF VDDQ R2 Cin1 Cout1 mode regulator, which costs less, and needs the less Cin2 Cin2 R Csense Cref 68uF 220uF 1uF 10uF board space. For two DIMM motherboards, system de- 2.2uF 10nF signers usually choose the linear mode for DDR power Cddq management solution. 1uF Applications T T Typical Application Cir ypical Application Cir ypical Application Circuits & W cuits & W cuits & Wa a av v vef ef eforms orms orms T Typical Application Cir ypical Application Circuits & W cuits & Wa av vef eforms orms Figure 2: Lower power loss for SSTL-2 application Two different application circuits are shown below in Fig- ure 1 to Figure 2. Each circuit is designed for specific Notes: Notes: Notes: Notes: Notes: condition. More details are described below. See Note (1) Power up of AV , PV and V supplies. CC CC DDQ 1. Below for recommended power up sequencing. (a) The preferred mode of operation is when the AV , PV and V pins are tied together to a CC CC DDQ single supply. Application_1: Standar Application_1: Standar Application_1: Standar Application_1: Standar Application_1: Standard SS d SS d SS d SS d SSTL TL TL TL TL-2 Application -2 Application -2 Application -2 Application -2 Application (b) If and when AV , PV pins are tied to a supply CC CC The AV pins, the PV pin, and the V pin can be tied separate to that of the V supply pin; then CC CC DDQ DDQ together for SSTL-2 application. It only needs a 2.5V the V supply should lead AV , PV supply or DDQ CC CC the V supply and the AV , PV supply should power rail for normal operation. System designer can DDQ CC CC rise simultaneously. save the PCB space and reduce the cost. Please refer to figures 3 to 4 for test waveforms. (c) If the AV , PV and V supply pins are con CC CC DDQ nected in a way such that, AV , PV supplies CC CC precedes V supply; then V output precedes DDQ TT SC2595 V . This can cause the SDRAM device to latch- 1 8 DDQ VTT NC VTT up, which may cause permanent damage to the 1.25V 2 7 VDD GND PVCC SDRAM. 3 6 2.5V VSENSE AVCC R1 4 5 5.1 VREF VDDQ Cout1 Cin1 Cout2 68uF Csence Cref 220uF 10uF Cin2 10nF 2.2uF 1uF Figure 1: Standard SSTL-2 application ©2009 Semtech Corp. 6 www.semtech.com SC2595 POWER MANAGEMENT Application Information (Cont.) Layout guidelines Layout guidelines Layout guidelines Layout guidelines Layout guidelines 1)The SC2595 has a SOIC8-EDP package. It can improve the thermal impedance (θ ) significantly. A suitable ther- JC mal pad should be added when PCB layout. Some ther- mal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal perfor- mance . 2)To increase the noise immunity, a ceramic capacitor of 10nf to 100nf is required to decouple the V pin with REF the shortest connection trace, also A 10nF to 100nF ceramic capacitor close to the V pin is required to SENSE avoid oscillation during transient condition. 3)To reduce the noise on the input power rail for stan- dard SSTL-2 application, a 68μF low ESR capacitor and a 1μF ceramic capacitor have to be used on the input power rail with shortest possible connection. 4)For lower power loss SSTL-2 application, a 220μF AL. capacitor (ESR should be lower than 250m ohm) and a 10μF ceramic has to be added on the PV pin and a 1μF CC ceramic capacitor +5.1 ohm filter has to be added on the V pin with shortest possible connection. DDQ 5)V output copper plane should be as large as possible. TT 6)V trace should be as short as possible. SENSE ©2009 Semtech Corp. 7 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Test Waveforms Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Cout1=220uF, Cout2=10uF, Source 2A. Cout1=220uF, Cout2=10uF, Sink 2A. VDDQ VDDQ AVcc AVcc PVcc PVcc VTT VTT VREF VREF Figure 3 Figure 4 Typical Characteristics AVCC=VDDQ=2.5V AVcc vs IQ 600 3.00 550 2.75 500 450 2.50 400 2.25 350 VDDQ MAX 300 2.00 =2.5V SOURCE VDDQ CURRENT 250 =1.8V 1.75 200 150 1.50 100 1.25 50 0 1.00 2.53.0 3.54.0 4.55.0 5.56.0 1.81.9 2 2.1 2.22.3 2.42.5 AVcc(V) PVCC(V) Figure 6 Figure 5 ©2009 Semtech Corp. 8 www.semtech.com OUTPUT CURRENT(A) Quiescent current(uA) SC2595 POWER MANAGEMENT Typical Characteristics (Cont.) Temp vs UVLO Quiescent Current(AVCC= 2.5V) 800 2.00 1.99 700 1.98 1.97 600 1.96 2.5V UVLO 500 1.8V 1.95 (Typical) 1.94 400 1.93 1.92 300 1.91 200 1.90 0 2040 6080 100120140 20 30 40 50 60 70 80 90 100 110 Temperature ( ) ℃ Temperature( ) ℃ Figure 8 Figure 7 VDDQ=PVCC=AVCC=2.5V VREF_max vs IREF(VDDQ=2.5V) 1.250 1.250 1.245 1.245 1.240 1.240 -40℃ 1.235 1.235 0 ℃ 25℃ 1.230 1.230 75 ℃ 1.225 150℃ 1.225 1.220 1.220 1.215 1.215 1.210 1.210 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 IREF(uA) IREF(uA) Figure 10 Figure 9 ©2009 Semtech Corp. 9 www.semtech.com VREF(V) Current(uA) VREF(V) Voltage(V) SC2595 POWER MANAGEMENT PRELIMINARY Typical Characteristics (Cont.) VDDQ=2.5V VDDQ=1.8V 6.0 6.5 6.0 5.5 5.5 5.0 5.0 4.5 4.5 MAX 4.0 MAX SOURCE 4.0 SOURCE CURRE NT CURRENT 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVCC=PVCC(V) AVCC=PVCC(V) Figure 12 Figure 11 AVCC=PVCC=VDDQ=2.5V 140 120 100 80 SOURCE 60 SINK 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 DC CURRENT (A) Figure 13 ©2009 Semtech Corp. 10 www.semtech.com ℃ Temperature( ) Current(A) Current(A) SC2595 POWER MANAGEMENT Outline Drawing - SOIC8-EDP ©2009 Semtech Corp. 11 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Land Pattern - SOIC8-EDP Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 ©2009 Semtech Corp. 12 www.semtech.com