Name: SEMTECH SC2544
Brand: SEMTECH
SKU: SC2544

Description

Semtech SC2544 High Performance Wide Input Range Dual Synchronous Buck Controller

Part Number

SC2544

Price

Request Quote

Manufacturer

SEMTECH

Lead Time

Request Quote

Category

PRODUCTS - S

Specifications

Iout Max

Operating Frequency

100-300 kHz

Package

TSSOP-24; MLPQ-24

Vin(V) max

Vin(V) min

4.5

Vout Min

.75

Features

“Peel off “start up tracking Independent dual-outputs
10V internal regulator for gate driver to deliver high efficiency
24 lead TSSOP and MLPQ packages
Adjustable output voltage down to 0.75V
Flexible power sequencing with enable and power good output
Full protection: UVLO, OVP and programmable OCP
Fully WEEE and RoHS Compliant
Independent dual-outputs
Low shutdown current (100nA typical)
No need for current sense resistor
Out of phase operation to reduce cost of input capacitor
Programmable switching frequency: 100kHz~300kHz
Synchronous Buck topology with voltage mode control
Wide input voltage range: 4.5V~28V

Datasheet

SC2544-126637975.pdf

1502 KiB

Download

Extracted Text

SC2544 High Performance Wide Input Range Dual Synchronous Buck Controller POWER MANAGEMENT Description Features The SC2544 is a high performance dual PWM controller. Independent dual-outputs It is designed to convert a wide ranged input voltage down Wide input voltage range: 4.5V~28V to two independent output rails. The PWM operations of Adjustable output voltage down to 0.75V the two channels are 180 degree out of phase which Sequential and ratiometric start-up can greatly reduce the size and the cost of the input Power good output capacitors. Synchronous Buck PWM topology and volt- Synchronous Buck topology with voltage mode age mode control allow high efficiency operation, fast control transient responses, and flexible component selection Out of phase operation to reduce cost of input for easy designs. A 10V internal linear regulator pro- capacitor vides the bias for the controller, and this voltage is opti- 10V internal regulator for gate driver to deliver high mized for gate drivers to deliver high efficiency. The power efficiency sequencing is fully supported including independent start Programmable switching frequency: up, and power good output. In the shut down mode the 100kHz~300kHz controller only draws 100nA from the supply. The con- Full protection: UVLO, OVP and programmable troller also offers full protection features for the condi- tions of under voltage, over voltage, and the over current. OCP There is no need for a current sensing resistor because No need for current sense resistor the MOSFET on resistance is used for the sensing Low shutdown current (100nA typical) element. The switching frequency is adjustable from 100 24 lead TSSOP and MLPQ packages kHz to 300 kHz. Two packages TSSOP-24 and MLPQ-24 Fully WEEE and RoHS Compliant are offered. Applications Systems with 4.5V~28V input LCDTV and PDPTV Network and telecom systems Portable devices Typical Application Circuit SC2544 VO1 VIN+ 1 24 VIN AGND VCC 2 23 VCC ROSC 3 22 ENABLE EN PWRGD PWGRD 4 21 FB1 FB2 FB1 FB2 5 20 ERROUT1 ERROUT2 6 19 VIN+ SS1 SS2 VIN+ 7 18 ILIM1 ILIM2 8 17 BST1 BST2 9 16 VO2 VO1 DRVH1 DRVH2 10 15 PHASE1 PHASE2 11 14 DRVL1 DRVL2 FB1 VCC FB2 12 13 PGND PVCC Pinout shown as TSSOP-24. Revision: August 10, 2005 1 www.semtech.com SC2544 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Sm ymbol Ms aximu Unit BV ST1,BST2 to PGND 3V 8 bst VV IN to PGND 2V 8 in ILIM1,ILIM2 and ENto PGND VV IN VCC and PVCC to PGND 1V 4 PGND to AGND +V /-0.3 BST1 to PH1, BST2 to PH2,DRVH1 to PH1,DRVH2 to PH2 -V 0.3 to 14 DRVL1,DRVL2 to PGND -V 0.3 to VCC PHASE,DRVLto AGND pulse (100nS),peak voltage -V 3 AllOtherPins to AGND -V 0.3 to VCC o ST torage Temperature Range -60 to +150 C STG o JunctionTemperature T -40 to +150 C J Lead Temperature (Soldering)10 Sec forTSSOP-24 o LT ead Temperature (IRReflow)forMLPQ-24 260 C LEAD ThermalResistance Junctionto Case o TSSOP-24 θ 23 C/W JC MLP-24 2 ThermalResistance Junctionto Ambient o TSSOP-24 θ 78 C/W JA MLP-24 25 Note: This device is ESD sensitive. Use of standard ESD handling precautions is required. Electrical Characteristics o Unless specified: T = 25 C, V =16V, Fs=200KHz . A IN Ps arameter Tn estCondition Mp i Tx y Mt a Uni Undervoltage Lockout Sg tartThreshold V5 cc risin 4V . Ug VLOHysteresis V0 cc fallin 2V 0 m PowerSupply Operating Current(I -I )F SS1/SS2/EN=High, =0 200kHz 60 . 1A m IN PVCC S VV cc Regulated V0 IN>12 1V VA cc Load RegulationLevel I2 _load=0~20m % VV cc Line Regulation V2 in=12~24 % PG Vcc Operating Current 24 00KHz,1nF onHG,1nF onL 1A m Dw isable QuiescentCurrent E1 N=lo 00 . 1A u Main Switcheroutput LV ine Regulation 55 V4.5V or during recovery from a fault condition ( OCP, OVP, or UVLO). versus oscillation resistor is shown in Figure 1. The period of start up can be programed by the soft The advantages of using constant frequency operation start capacitor: are simple passive component selection and ease of Css× 2.5V Tss= feedback compensation. Before setting the operating 84μA frequency, the following trade-offs should be considered. By connecting different capacitors at SS1 and SS2 1) Passive component size pins, VO1 and VO2 will start at different time, achieving 2) Circuitry efficiency sequential start-up for the outputs. Connecting SS1 3) EMI condition and SS2 together would make the 2 outputs start and 4) Minimum switch on time reach steady state values at the same time, achieving 5) Maximum duty ratio ratiometric start-up. For a given output power, the sizes of the passive components are inversely proportional to the switching Shutdown Shutdown Shutdown Shutdown Shutdown frequency, whereas MOSFETs/Diodes switching losses When the EN pin is pulled low, an internal 15uA current are proportional to the operating frequency. Other issues source discharges the soft-start capacitor and DRVH/ such as heat dissipation, packaging and cost issues are DRVL signals stop pulsing. The output voltage ramps also to be considered. The frequency bands for signal down at a rate determined by the load condition. transmission should be avoided because of EM interference. The SC2544 can also be shutdown by pulling down directly on the SS pin. The designer needs to consider 350 the slope of the SS pin voltage and choose a suitable pull down resistor to prevent the output from 300 undershooting. 250 200 Shutdown can also be triggered when an OCP condition occurs. When an OCP condition is detected, DRVH and 150 DRVL will stop pulsing and enter a “tri-state shutdown” 100 with the output voltage ramping down at a rate deter- 50 mined by the load condition. The internal 15uA current source will begin discharging the soft-start capacitor Rosc(KOHM) and when the soft-start voltage reaches 0.65V, DRVL will go high. Figure 1. Switching frequency versus Rosc. © 2005 Semtech Corp. 8 www.semtech.com Fsw(KHz) SC2544 POWER MANAGEMENT Applications Information (Cont.) Over Current Protection (OCP) Over Current Protection (OCP) Over Current Protection (OCP) Over Current Protection (OCP) Over Current Protection (OCP) The inductor current is sensed by using the low side TG TG MOSFET R . After low side MOSFET is turned ds(on) on, the OCP comparator starts monitoring the II voltage drop across the MOSFET. The OCP trip LL level is programmed by the resistor from the ILIM pin to the phase node. There is an internal current source that flows out of the ILIM pin which will 10 100n 0nSS OC OCPP Ac Acttiivvee generate a voltage drop on the setting resistor. Bl Blaannkkiinngg When the sum of the setting resistor voltage and the MOSFET drain to source voltage is less then Figure 3. OCP comparator timing chart. zero, the OCP condition will be flagged. This functionality is depicted in Figure 2. U Under V nder Voltage Lock Out (UVL oltage Lock Out (UVLO) O) U U Under V nder V nder Voltage Lock Out (UVL oltage Lock Out (UVL oltage Lock Out (UVLO) O) O) The following formula is used to set the OCP level 10µAR×= I ×R The UVLO circuitry monitors Vcc and the soft start ILIM L_( PEAK DS ON) begins once Vcc ramps up above 4.5V. There is a When OCP is tripped, both high side and low side built in 200mV hysteresis for the UVLO ramp down MOSFETs will be turned off and this condition is threshold. The gate driver output will be in “tri- latched. At the same time, the soft start cap will state” (both high side and low side MOSFET off) be discharged by the internal current source of once Vcc ramps down bellow 4.2V (typical), and the 15uA. When the Vss drops bellow 0.65V, the DRVL soft start cap will be discharged by internal 15uA pin will go high again. current sink. Ov Ov Ov Ov Over V er V er V er V er Voltage Pr oltage Pr oltage Pr oltage Pr oltage Pro o o o ot t t t tection (O ection (O ection (O ection (O ection (OVP) VP) VP) VP) VP) To avoid switching noise during the phase node commutation, a 100nS blanking time is built in The OVP circuitry monitors the feedback voltages, after the low side MOSFET is turned on, as shown in If either feedback voltage exceeds 0.89V, the OVP Fig. 3. condition is registered. Under this condition, the DRVH pins will be pulled low, and the DRVL pins will be pulled high. This will create a “crow bar” condi- VCC tion for the input power rail in case the high side 10uA MOSFET is failed short. The crow bar operation DRVH may trip the input supply to prevent the load from OUTPUT seeing more voltage. ILIM + OCP Out P P P P Po o o o ow w w w wer Good Output er Good Output er Good Output er Good Output er Good Output - DRVL The power good is an open collector output. The PWRGD pin is pulled low at start up if any of the two feedback voltages below 90% of its regulation level. The ramp down threshold of the signal is 80% Figure 2. Block diagram of over current of the regulation target. External pull up is re- protection. quired for the PWRGD pin, and the pull up resistor should be chosen such that the pin does not sink more than 2mA when PWRGD is low.  2005 Semtech Corp. 9 www.semtech.com SC2544 POWER MANAGEMENT Applications Information (Cont.) 2 δ I = I 1+ . General Design Pr General Design Pr General Design Pr General Design Pr General Design Procedure f ocedure f ocedure f ocedure f ocedure for a St or a St or a St or a St or a Step-do ep-do ep-do ep-do ep-down P wn P wn P wn P wn Po o o o ow w w w wer er er er er L,rms o 12 Converter Converter Converter Converter Converter The followings are to be considered when choosing Selection criterias and design procedures for the fol- inductors. lowing parameters are described: a) Inductor core material: For higher efficiency 1) Output inductor (L) type and value applications above 300 KHz, ferrite, Kool-Mu and 2) Output capacitor (C ) type and value o polypermalloy materials should be used. Low-cost 3) Input capacitor (C ) type and value in powdered iron cores can be used for cost sensitive- 4) Power MOSFETs applications below 300 KHz but with attendant higher 5) Current sensing and limiting circuit 6) Voltage sensing circuit core losses. 7) Loop compensation network b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The The following step-down converter specifications are designer can choose the adjacent (larger) standard needed: inductance value. The inductance varies with Input voltage range: V and V in,min in,max temperature and DC current. It is a good engineering Input voltage ripple (peak-to-peak): DV in practice to re-evaluate the resultant current ripple Output voltage: V o at the rated DC output current. Output voltage accuracy: e c) Current rating: The saturation current of the Output voltage ripple (peak-to-peak): DV o inductor should be at least 1.5 times of the peak Nominal output (load) current: I o Maximum output current limit: I inductor current under all conditions. o,max Output (load) current transient slew rate: dI (A/ s) o η Circuit efficiency: Output Capacit Output Capacit Output Capacit Output Capacit Output Capacitor (C or (C or (C or (C or (C ) and V ) and V ) and V ) and V ) and V Ripple Ripple Ripple Ripple Ripple o o o o o out out out out out Inductor (L) and Ripple Current Inductor (L) and Ripple Current Inductor (L) and Ripple Current Inductor (L) and Ripple Current Inductor (L) and Ripple Current The output capacitor provides output current filtering Both step-down controllers in the SC2544 operate in in steady state and serves as a reservoir during load synchronous continuous-conduction mode (CCM) transient. The output capacitor can be modeled as regardless of the output load level. The output an ideal capacitor in series with its parasitic ESR and inductor selection/design is based on the output DC ESL as shown in Figure 4. and transient requirements. Both output current and voltage ripples are reduced with larger inductance but it takes longer to change the inductor current during load transients. Conversely smaller inductance Co Lesl Resr results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Figure 4. An equivalent circuit of output. Assuming that the inductor current ripple (peak-to- peak) value is *I , the inductance value will then δ o If the current through the branch is i (t), the voltage b be across the terminals will then be V (1− D) o L = . δI f t o s di (t) 1 b v (t) = V + i (t)dt+L +R i (t). o o b esl esr b ∫ C dt o 0 The peak current in the inductor becomes This basic equation illustrates the effects of ESR, (1+ /2)*Io δ ESL, and C on the output voltage. o and the RMS current is  2005 Semtech Corp. 10 www.semtech.com �� #�$� �� %�� &�� ’�� (�� !� "� �� "� �� )�� "� �� ’�� *�� "� �� 8�� ’�� )�� /�� "� �� 9�� +�� ,�� -� �� :��"� �� #; 9"� <� � �� =:#$;; 9"� >;� � �� )�� "� �� .�� /�� <=4� �� /� �/0"� 1/��+1"� �� ’�� )� � ��#;; 9"� =� �� "� �� 2�� "� �� <�= �� 2�� #;; 9"� =� � �� "� �� "� �� ?�3�� )�� ( �� ,�� 34-� �� "� �� ’�� ’�� @�� )�� "� �� ’�� 5� ��6� "� 7� �� (��)�� *+��,� �� -� �� %��&’� �� &�� -��,�� !�� #��0�� "#$�� $� � �� *+��,��1�� ,�� *�� ,�� 2�� !�� .��/�� (� ,�� 1 �� 2�� "3 � ��*�� 2��%.�*�’�� ,�� (��.�� SC2544 POWER MANAGEMENT Applications Information (Cont.) Choosing P Choosing P Choosing Po o ow w wer MOSFET er MOSFET er MOSFETs s s Choosing P Choosing Po ow wer MOSFET er MOSFETs s Sometimes meeting tight input voltage ripple Main considerations in selecting the MOSFET’s are specifications may require the use of larger input power dissipation, MOSFETs cost, and packaging. capacitance. At full load, the peak-to-peak input Switching losses and conduction losses of the MOSFET’s voltage ripple due to the ESR is are directly related to the total gate charge (C ) and g δ Δv = R (1+ )I . channel on-resistance (R ). In order to judge the ESR esr o ds(on) 2 performance of MOSFET’s, the product of the total The peak-to-peak input voltage ripple due to the gate charge and on-resistance is used as a figure of capacitor is merit (FOM). Transistors with the same FOM follow DI o Δv ≈ , C the same curve in Figure 8. C f in s From these two expressions, C can be found to meet IN the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce 50 ripple. The two step-down channels of the SC2544 40 Cg() 100 Rds operate at 180 degrees from each other. If both step- , down channels in the SC2544 are connected to the Cg() 200, Rds 20 same input rail, the input RMS currents will be reduced. Cg() 500, Rds Ripple cancellation effect of interleaving allows the use of smaller input capacitors. 1 0 0 5 10 15 20 When two channels with a common input are 1 Rds 20 On-resistance (mOhm) interleaved, the total DC input current is simply the FOM:100*10^{-12} sum of the individual DC input currents. The combined FOM:200*10^{-12} FOM:500*10^{-12} input current waveform depends on duty ratio and the output current waveform. Assuming that the Figure 8. Figure of Merit curves. output current ripple is small, the following formula can be used to estimate the RMS value of the ripple The closer the curve is to the origin, the lower is the current in the input capacitor. FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find Let the duty ratio and output current of Channel 1 and MOSFET’s with both low C and low R . Usually a g ds(on Channel 2 be D , D and I , I , respectively. 1 2 o1 o2 trade-off between R and C has to be made. ds(on g MOSFET selection also depends on applications. In If D <0.5 and D <0.5, then 1 2 many applications, either switching loss or conduction loss dominates for a particular MOSFET. For 2 2 I ≈ D I + D I . Cin 1 o1 2 o2 synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low duty cycle. The bottom switch If D >0.5 and (D -0.5) < D <0.5, then 1 1 2 conducts at high duty cycle but switches at near zero voltage. For such applications, MOSFET’s with low C 2 2 g 2 I ≈ 0.5I + (D − 0.5)(I + I ) + (D − D + 0.5)I . Cin o1 1 o1 o2 2 1 o2 are used for the top switch and MOSFET’s with low R are used for the bottom switch. ds(on) If D >0.5 and D < (D -0.5) < 0.5, then 1 2 1 MOSFET power dissipation consists of a) conduction loss due to the channel resistance R ; ds(on) 2 2 2 b) switching loss due to the switch rise time t and I ≈ 0.5I + D (I + I ) + (D − D − 0.5)I . r Cin o1 2 o1 o2 1 2 o2 fall time t ; and If D >0.5 and D > 0.5, then f 1 2 c) the gate loss due to the gate resistance R . G 2 2 2 I ≈ (D + D −1)(I + I ) + (1− D )I + (1− D )I . Cin 1 2 o1 o2 2 o1 1 o2  2005 Semtech Corp. 13 www.semtech.com Gate Charge (nC) SC2544 POWER MANAGEMENT Applications Information (Cont.) In Figure 9, Q is the gate charge needed to bring T T T T Top Switc op Switc op Switc op Switc op Switch h h h h gs1 the gate-to-source voltage V to the threshold voltage The RMS value of the top switch current is calculated gs V . as gs_th 2 δ Q is the additional gate charge required for the I = I D(1+ ). Q1,rms o gs2 12 switch current to reach its full-scale value I , and Q ds gd . is the charge needed to charge gate-to-drain (Miller) The conduction losses are then capacitance when V is falling. ds 2 P = I R . Switching losses occur during the time interval [t , tc Q1,rms ds(on) 1 t ]. Defining t = t -t and t can be approximated as 3 r 3 1 r R varies with temperature and gate-source ds(on) (Q + Q )R gs2 gd gt voltage. Curves showing R variations can be found t = . r ds(on) V − V cc gsp in manufacturers’ data sheet. From the Si4860 datasheet, R is less than 8m when V is greater Ω where R is the total resistance from the driver supply ds(on) gs gt than 10V. However R increases by 50% as the rail to the gate of the MOSFET. It includes the gate ds(on) o o junction temperature increases from 25 C to 110 C. driver internal impedance R , external resistance R gi ge and the gate resistance R within the MOSFET : g The switching losses can be estimated using the simple formula R = R +R +R . gt gi ge g V is the Miller plateau voltage shown in Figure 9. 1 δ gsp = + + P (t t )(1 )I V f . ts r f o in s 2 2 Similarly an approximate expression for t is f where t is the rise time and t is the fall time of the r f (Q + Q )R switching process. Different manufactures have gs2 gd gt t = . f different definitions and test conditions for t and V gsp r t . To clarify these, we sketch the typical MOSFET f switching characteristics under clamped inductive Only a portion of the total losses P = Q V f is g g cc s mode in Figure 9. dissipated in the MOSFET package. Here Q is the g total gate charge specified in the datasheet. The Vd Vdss power dissipated within the MOSFET package is V V o olts lts Id Ids s M M i il ll ler er p pl la at teau eau R g P = Q V f . tg g cc s Vg Vgss R gt Vg Vgs s t th h The total power loss of the top switch is then P = P +P +P . t tc ts tg Qg Qgss11 Qg Qgss22 Qg Qgdd If the input supply of the power converter varies G G a at te e ch char arg ge e t0 t0 t1 t1 t2 t2 t3 t3 over a wide range, then it will be necessary to weigh the relative importance of conduction and Figure 9. MOSFET switching characteristics switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design.  2005 Semtech Corp. 14 www.semtech.com SC2544 POWER MANAGEMENT Applications Information (Cont.) Bottom Switch Bottom Switch Bottom Switch Bottom Switch Bottom Switch Main Control Loop Design Main Control Loop Design Main Control Loop Design Main Control Loop Design Main Control Loop Design The goal of compensation is to shape the frequency The RMS current in bottom switch is given by response charatericstics of the buck converter to 2 achieve a better DC accuracy and a faster transient δ I =I (1−D)(1+ ). Q2,rms o 12 response for the output voltage, while maintaining the loop stability. The conduction losses are then The block diagram in Figure 10 represents the control 2 P =I R . bc Q2,rms ds(on) loop of a buck converter designed with the SC2544. The control loop consists of a compensator, a PWM modula- where R is the channel resistance of bottom ds(on) tor, and an LC filter. MOSFET. If the input voltage to output voltage ratio is high (e.g. V =12V, V =1.5V), the duty ratio D will in o The LC filter and PWM modulator represent the small be small. Since the bottom switch conducts with duty signal model of the buck converter operating at fixed ratio (1-D), the corresponding conduction losses can switching frequency. The transfer function of the be quite high. model is given by: Due to non-overlapping conduction between the top and V V 1+sR C O IN ESR = ⋅ the bottom MOSFET’s, the internal body diode or the 2 V V 1+sL/R+s LC C m external Schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with REF PWM + L Vo only a diode voltage between its drain and source EA MODULATOR REF terminals. The switching loss is negligible due to near zero- - voltage switching. Co ERROUT The gate losses are estimated as Zf Resr R g P = Q V f . bg g cc s Zs R gt The total bottom switch losses are then P =P +P . b bc bg Fig. 10. Block diagram of the control loop. Once the power losses for the top and bottom where V is the input voltage, Vm is the amplitude of MOSFET’s are known, thermal and package design IN the internal ramp, and R is the equivalent load. at component and system level should be done to verify that the maximum die junction temperature o The model is a second order system with a finite DC (T , usually 125 C) is not exceeded under the j,max gain, a complex pole pair at Fo, and an ESR zero at worst-case condition. The equivalent thermal Fz, as shown in Figure 11. The locations of the poles impedance from junction to ambient ( ) should θ ja and zero are determined by: satisfy T − T j,max a,max θ ≤ . ja P loss 1 FO = depends on the die to substrate bonding, θ ja 2π LCO packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area, and the air flow condition (natual or 1 FZ = forced convection). Actual temperature measurement 2π ResrCO of the prototype should be carried out to verify the thermal design.  2005 Semtech Corp. 15 www.semtech.com L LOOP OOP GA GA I IN N CO CO NV NV E E R R T TE E R G R G A A I IN N SC2544 POWER MANAGEMENT Applications Information (Cont.) The compensator in Figure 10 includes an error am- A resistive divider is used to program the output volt- plifier and impedance networks Zf and Zs. It is imple- age. The top resistor Rtop of the divider in Fig. 12 mented by the circuit in Figure 12. The compensator can be chosen from 20k to 30k . Then the bot- Ω Ω provides an integrator, double poles, and double ze- tom resistor Rbot is found from: ros. As shown in Figure 11, the integrator is used to boost the gain at low frequency. Two zeros are intro- 0.75V Rbot = ∗Rtop duced to compensate excessive phase lag at the Vo − 0.75V loop gain crossover due to the integrator (-90deg) and the complex pole pair (-180deg). Two high fre- quency poles are designed to compensate the ESR where 0.75V is the internal reference voltage of the zero and to attenuate high frequency noise. SC2544. The other components of the compensator can be calculated using following design procedure: (1). Plot the converter gain, including LC filter and Fp Fp11 FFpp22 CCOOMM PEN PENSA SATTOORR GA GAIINN PWM modulator. (2). Select the open loop crossover frequency Fc lo- Fz Fz11 Fz Fz22 cated at 10% to 20% of the switching frequency. At Fo Fo Fc, find the required DC gain. Fc Fc (3). Use the first compensator pole Fp1 to cancel the Fz Fz ESR zero Fz. (4). Have the second compensator pole Fp2 at half the switching frequency to attenuate the switching ripple and high frequency noise. (5). Place the first compensator zero Fz1 at or below FR FR E E Q Q U U E E N N C C Y Y ( (H H z z) ) 50% of the power stage resonant frequency Fo. (6). Place the second compensator zero Fz2 at or Fig. 11. Bode plots for control loop design. below the power stage resonant frequency Fo. A MathCAD program is available upon request for the calculation of the compensation parameters. C2 C1 R2 C3 R3 Rtop Vo - Vc Out + E/A Rbot 0.75V Fig. 12. Compensation network.  2005 Semtech Corp. 16 www.semtech.com G G A A IN IN ( (d d B B ) ) SC2544 POWER MANAGEMENT Applications Information (Cont.) PC Board Layout Issues PC Board Layout Issues PC Board Layout Issues PC Board Layout Issues PC Board Layout Issues Control Section Control Section Control Section Control Section Control Section Circuit board layout is very important for the proper 6) The frequency-setting resistor Rosc should be placed operation of high frequency switching power con- close to Pin 23. Trace length from this resistor to the verters. A power ground plane is required to reduce analog ground should be minimized. ground bounces. The followings are suggested for proper layout. 7) Place the bias decoupling capacitor right across the VCC and analog ground AGND. P P P P Po o o o ow w w w wer Stage er Stage er Stage er Stage er Stage 1) Separate the power ground from the signal ground. In SC2544 design, use an isolated local ground plane for the controller and tie it to power grand. 2) Minimize the size of the high pulse current loop. Keep the top MOSFET, the bottom MOSFET and the input capacitors within a small area with short and wide traces. In addition to the aluminum energy storage capacitors, add multi-layer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. 3) Reduce high frequency voltage ringing. Widen and shorten the drain and source traces of the MOSFETs to reduce stray inductances. Add a small RC snubber if necessary to reduce the high frequency ringing at the phase node. Sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node if the EMI is a concern for the system. 4) Shorten the gate drive trace. Integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efficiency. Short and wide gate drive traces reduce trace inductances. Bond wire inductance is about 2~3nH. If the length of the PCB trace from the gate driver to the MOSFET gate is 1 inch, the trace inductance will be about 25nH. If the gate drive current is 2A with 10ns rise and falling times, the voltage drops across the bond wire and the PCB trace will be 0.6V and 5V respectively. This may slow down the switching transient of the MOSFET’s. These inductances may also ring with the gate capacitance. 5) Put the decoupling capacitor for the gate drive power supplies (BST and PVCC) close to the IC and power ground.  2005 Semtech Corp. 17 www.semtech.com SC2544 POWER MANAGEMENT Typical Application Circuit SC2544MLTRT VO2 U1 SC2544 VIN+ R2 10K C1 1uF/25V 1 24 VIN AGND VCC C2 1uF/16V 2 23 R3 73.2K VCC ROSC 3 22 EN EN PWRGD PWGRD 4 21 FB1 FB2 FB1 FB2 SS1 SS2 1n C4 C3 1n 5 20 ERROUT1 ERROUT2 C9 4.7n 470nF 18k C12 4.7n R4 C11 C10 220nF 6 19 R5 18k SS1 SS2 R6 R7 4.7K 7 18 4.7K ILIM1 ILIM2 C17 1uF/16V C32 N.P. 8 17 C18 1uF/16V C33 N.P. BST1 BST2 0 R8 9 16 R9 0 DRVH1 DRVH2 2.2 R10 10 15 R11 2.2 PHASE1 PHASE2 11 14 DRVL1 DRVL2 VIN+ VCC VIN+ 12 13 PGND PVCC C31 C5 C6 C7 C8 C13 C14 C15 C16 R24 Q1 N.P. 10uF/25V 10uF/25V 0.1uF/25V 0.1uF/25V 10uF/25V 10uF/25V N.P. Q2 0R VO1 VO2 7.6uH L1 L2 7.6uH R12 28K R14 28K Q3 Q4 R13 499 R15 499 C35 C20 C21 C22 C23 C34 C24 C25 C26 C27 FB1 N.P. FB2 C19 3.9nF N.P. C29 C28 3.3nF C30 N.P. R17 4.9K N.P. N.P. N.P. R25 N.P. R18 8.25K N.P. R25 N.P. N.P. Vin: 4.5V ~ 28V Vout: 3.3V/6A and 5V/6A © 2005 Semtech Corp. 18 www.semtech.com 330uF /6.3V 330uF /6.3V IR F 7811A IR F7811A 1uF /16V IR F7811A IR 7811A 330uF /6.3V 330uF /6.3V SC2544 POWER MANAGEMENT Evaluation Board - Bill of Material SC2544MLTRT Ry ef Qe t Re eferenc Pr artNumber/Valu Manufacture 11 C5 1 1y uF,25V, X5R,Ceramic,080 An 23 C5 2,C18,C31 1y uF,16V,X5R,Ceramic ,080 An 34 C5 3,C4,C34,C35 1y nF,Ceramic 080 An 44 1, L1,L2,C5,C16,C20 N.P. C21,C24,C24, C29,C30,C32, C33,R25 54 C6 6,C7,C14,C15 1M 0uF,25V,X5R, Ceramic 120 Panasonic,ECJ3YB1E106 62 C3 8,C13 0y .1uF,25V, 060 An 72 C3 12,C9 4y .7nF,Ceramic,060 An 81 C3 10, 2y 20nF,Ceramic,060 An 91 C3 11 4y 70nF,Ceramic, 060 An 11 0 C3 17 1y nF,Ceramic,060 An 12 1 C3 28,C19 3y .3nF,Ceramic,060 An 12 2 Cp 22,C23,C26,C27 3L 3uF,6.3V,18mohm,PosCa Sanyo,6TPE330MI 12 3 Lm 1,L2 77 .6uH,6.8A,16moh Sumida,CDRH12 14 4 QA 1,Q2,A3,Q4 IR RF7811 I 11 5 R3 2 1y 0K,060 An 11 6 R3 3 7y 3.2K,060 An 12 7 R3 5,R4 1y 8K,060 An 11 8 R3 6 6y .8K,060 An 11 9 R3 7 4y .7K,060 An 21 0 R3 10 4y .7,060 An 21 1 R3 25,R11 4y .7,060 An 22 2 R3 14,R12 2y .2,060 An 22 3 R3 15,R13 4y 99,060 An 22 4 R3 18,R17 4y .9K,060 An 21 5 R3 24 0y ,060 An 21 6 U4 1 Sh C254 Semtec © 2005 Semtech Corp. 19 www.semtech.com SC2544 POWER MANAGEMENT Typical Characteristics CH1:Vi CH1: TG1 CH2: BG1 CH2:Ven CH3: TG2 CH3:VSS CH4: BG2 CH4:Vo Shut down by pulling down EN pin Gate waveform voltage. CH1: CH1: EN EN CH2: CH2: VO1 VO1 CH3:Vo CH3: CH3: VO2 VO2 CH4:Io Ratiometric start up(connect Transient response(0-5A). SS1,SS2 together). CH1 CH1: : E EN N CH1:TG CH2 CH2: : V VO O1 1 CH2:BG CH3 CH3: : V VO O2 2 CH3:TG CH4:BG Over current protection (5A/10mV) Sequential start up (Seperate SS1,SS2). © 2005 Semtech Corp. 20 www.semtech.com 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 SC2544 POWER MANAGEMENT Typical Characteristics (Cont.) Vin=8V Vin=16V 190 100% 188 80% 186 60% 184 182 40% 180 20% 178 0% -40 -10 20 50 80 110 0 1234 567 89 10 Temperature (Degree C) Io(A ) Efficiency Curve for Freq. vs. Temp. ( Rosc=75kohm, Vout=3.3V. Vin=16V). 350 10.5 300 10.3 250 10.1 200 9.9 150 9.7 100 9.5 50 10 12 14 16 18 20 22 24 26 28 30 Vin (V) Rosc(KOHM) Operating frequency vs. Rosc. Vcc vs. Vin ( Ta=25 Degree C). 9 10.13 8 10.11 7 10.09 6 10.07 5 10.05 10.03 4 -40 -20 0 20406080 100 120 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 Tj (Degree C) RILIM(KOHM) RILIM vs. OCP (Vi=12V). Vcc vs. Temp.  2005 Semtech Corp. 21 www.semtech.com Efficient Fsw(KHz) Io(A) Vcc (V) Vcc (V) Fs (khz) SC2544 POWER MANAGEMENT Typical Characteristics (Cont.) 7.0 6.5 6.0 5.5 5.0 8 10 12 1416 1820 2224 2628 Vin(V) Icc vs. Vin (25 DegreeC). 500 480 460 440 420 400 -40 -20 0 2040 6080 100 120 Tj (Degree C) DL min Ton vs. Tj (Vin=16V). 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Tj (Degree C) Dead time vs. Tj (Vin=16V, DH falling to DL rising).  2005 Semtech Corp. 22 www.semtech.com Dead time (nS) DRVL min Ton(nS) Icc (mA) SC2544 POWER MANAGEMENT Outline Drawing - TSSOP-24 DIMENSIONS A INCHES MILLIMETERS DIM D e MIN NOM MAX MIN NOM MAX - - - - N A .047 1.20 A1 .002 - .006 0.05 - 0.15 A2 .031 - .042 0.80 - 1.05 2X E/2 b .007 - .012 0.19 - 0.30 c .003 - .007 0.09 - 0.20 E1 D .303 .307 .311 7.70 7.80 7.90 E E1 .169 .173 .177 4.30 4.40 4.50 PIN 1 INDICATOR E .252 BSC 6.40 BSC e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 (.039) (1.0) ccc C 1 2 3 L1 e/2 N 24 24 2X N/2 TIPS 01 0° - 8° 0° - 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A - AND -B - TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AD. Land Pattern - TSSOP-24 X DIMENSIONS DIM INCHES MILLIMETERS C (.222) (5.65) G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 23 www.semtech.com SC2544 POWER MANAGEMENT Outline Drawing - MLPQ-24 (4 x 4mm) A D B DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A .031 .035 .040 0.80 0.90 1.00 A1 .000 .001 .002 0.00 0.02 0.05 - - - - A2 (.008) (0.20) PIN 1 b .007 .010 .012 0.18 0.25 0.30 E INDICATOR D .151 .157 .163 3.85 4.00 4.15 Top View (LASER MARK) D1 .100 .106 .110 2.55 2.70 2.80 E .151 .157 .163 3.85 4.00 4.15 E1 .100 2.70 2.80 .106 .110 2.55 e .020 BSC 0.50 BSC L .011 .016 .020 0.30 0.40 0.50 N 24 24 aaa .004 0.10 A2 bbb .004 0.10 A SEATING aaa C PLANE A1 C D1 LxN E/2 E1 Bottom View 2 1 N bxN bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2. Land Pattern - MLPQ-24 (4 x 4mm) K DIMENSIONS DIM INCHES MILLIMETERS (.155) (3.95) C G .122 3.10 H .106 2.70 G Z (C) H K .106 2.70 P .021 0.50 X .010 0.25 Y .033 0.85 Z .189 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 24 www.semtech.com

Frequently asked questions

At GID Industrial (Elite.Parts' parent company), we specialize in procuring industrial parts. We know where to find the rare and obsolete equipment that our customers need in order to get back to business. There are other companies who claim to do what we do, but we're confident that our commitment to quality and value is unparalleled in our field.

Warranties differ by part and by which suppliers we use to procure it for you. Sometimes, a part will be sold as-is and without a warranty. Our specialty, single board computers, tend to receive a one-year warranty.

Elite.Parts can ship via FedEx, UPS, DHL, and USPS. We have accounts with each of them and generally ship using one of those, but we can also ship using your account if you would prefer. However, we can use other carriers if it will be more convenient for you.

Absolutely! We are happy to serve customers regardless of location. We work with international clients all the time, and we are familiar with shipping to destinations all across the globe.

All major credit cards are accepted: Visa, MasterCard, Discover, and American Express. We will also accept payment made with wire transfer or PayPal. Checks will only be accepted from customers in the USA. Terms may available for larger orders, upon approval.

What they say about us

FANTASTIC RESOURCE

One of our top priorities is maintaining our business with precision, and we are constantly looking for affiliates that can help us achieve our goal. With the aid of GID Industrial, our obsolete product management has never been more efficient. They have been a great resource to our company, and have quickly become a go-to supplier on our list!

Bucher Emhart Glass

EXCELLENT SERVICE

With our strict fundamentals and high expectations, we were surprised when we came across GID Industrial and their competitive pricing. When we approached them with our issue, they were incredibly confident in being able to provide us with a seamless solution at the best price for us. GID Industrial quickly understood our needs and provided us with excellent service, as well as fully tested product to ensure what we received would be the right fit for our company.

Fuji

HARD TO FIND A BETTER PROVIDER

Our company provides services to aid in the manufacture of technological products, such as semiconductors and flat panel displays, and often searching for distributors of obsolete product we require can waste time and money. Finding GID Industrial proved to be a great asset to our company, with cost effective solutions and superior knowledge on all of their materials, it’d be hard to find a better provider of obsolete or hard to find products.

Applied Materials

CONSISTENTLY DELIVERS QUALITY SOLUTIONS

Over the years, the equipment used in our company becomes discontinued, but they’re still of great use to us and our customers. Once these products are no longer available through the manufacturer, finding a reliable, quick supplier is a necessity, and luckily for us, GID Industrial has provided the most trustworthy, quality solutions to our obsolete component needs.

Nidec Vamco

TERRIFIC RESOURCE

This company has been a terrific help to us (I work for Trican Well Service) in sourcing the Micron Ram Memory we needed for our Siemens computers. Great service! And great pricing! I know when the product is shipping and when it will arrive, all the way through the ordering process.

Trican Well Service

GO TO SOURCE

When I can't find an obsolete part, I first call GID and they'll come up with my parts every time. Great customer service and follow up as well. Scott emails me from time to time to touch base and see if we're having trouble finding something.....which is often with our 25 yr old equipment.

ConAgra Foods

SEMTECH SC2544

Why buy from GID?

What they say about us

Related Products